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1

Planarizing dielectrics for VLSI technology  

Microsoft Academic Search

In this paper we describe the first reported blanket removal properties of various dielectric films. Based on material selectivity, We deposited thin PEOX, thick BPSG and a hard dielectric film with lower removal rate on top of a patterned wafer. Initial polishing removed the top hard dielectric level completely, exposing the BPSG, but the lower hard material remains less polished,

Chi-Wen Liu; Bau-Tong Dai; Ching-Fa Yeh; Chien-Hung Liu; Po-Tsun Wang

1994-01-01

2

MEMS Wafer-level Packaging Technology Using LTCC Wafer  

NASA Astrophysics Data System (ADS)

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

3

Applying digital VLSI technology to radar signal processing  

Microsoft Academic Search

In spite of great advances in radar signal processing related to technological progress, the present digital signal processing (DSP) capability, still falls well short of what could be specified by a radar designer. It is, therefore, necessary to pay attention to the special characteristics of VLSI circuits in order to be able to exploit silicon as fully as possible as

J. B. G. Roberts; P. Simpson; B. C. Merrifield

1986-01-01

4

A Specialized Graduate Program in VLSI Design Tools and Technology  

Microsoft Academic Search

This paper describes the features of an interdisciplinary industry-sponsored graduate program in VLSI design tools and technology. An active participation of industry in finalizing the course curriculum by interacting with academia on a graduate project with predefined goals and objectives has popularized this program with the students and sponsoring agencies. The customized course curriculum, with the option of selecting specialized

M. Balakrishnan; B. S. Panwar

2005-01-01

5

A wafer scale fail bit analysis system for VLSI memory yield improvement  

Microsoft Academic Search

A wafer-scale fail bit analysis system which outputs an entire wafer fail bit map (FBM) by using a data compaction technique and testing structure is developed. With this system, process defect locations on a wafer can easily be electrically recognized quickly. The processing time of wafer-scale fail bit analysis is reduced to only 2% of that required by the conventional

Y. Sakai; J. Sawada; W. Sakamoto; J. Murato; H. Kawamoto; K. Sakai; K. Nakamuta

1990-01-01

6

VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.  

ERIC Educational Resources Information Center

As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

Bayoumi, Magdy

7

VLSI technology for smaller, cheaper, faster return link systems  

NASA Technical Reports Server (NTRS)

Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

1994-01-01

8

GaAs VLSI technology and circuit elements for DSP  

NASA Astrophysics Data System (ADS)

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Mikkelson, James M.

1990-10-01

9

Using software technology to specify abstract interfaces in VLSI design  

SciTech Connect

Good techniques for VLSI design change management do not now exist. A principal reason is the absence of effective methods for the specification of abstract interfaces for VLSI designs. This dissertation presents a new approach to such specification, an approach that extends to the VLSI domain D.L. Parna's techniques for precise specification of abstract software design interfaces to the VLSI domain. The proposed approach provides important new features including scalability to VLSI design levels, integration into the design life-cycle, and a uniform treatment of functional, electrical, and geometric design information. A technique is also introduced for attaching a value to the degree of specification adherence of a candidate module. To illustrate and evaluate the proposed approach, an example specification method using it is described and evaluated experimentally.

Gross, R.R.

1985-01-01

10

Optoelectronic-VLSI: photonics integrated with VLSI circuits  

Microsoft Academic Search

Optoelectronic-VLSI (OE-VLSI) technology represents the intimate integration of photonic devices with silicon VLSI electronics. We review the motivations and status of emerging OE-VLSI technologies and examine the performance of OE-VLSI technology versus conventional wire-bonded OE packaging. The results suggest that OE-VLSI integration offers substantial power and speed improvements even when relatively small numbers of photonic devices are driven with commodity

Ashok V. Krishnamoorthy; Keith W. Goossen

1998-01-01

11

A Tunable Photonic RF Notch Filter Based on Opto-VLSI Technology  

Microsoft Academic Search

In this paper, we propose a novel tunable transversal photonic RF notch filter based on opto-VLSI technology. By using an array of fiber Bragg gratings (FBGs) in conjunction with an opto-VLSI processor, the broadband light source can be spectrally sliced and attenuated, hence realizing a two-tap RF notch filter with stepwise truetime delays and variable weights. In addition, the free

Rong Zheng; Kamal E. Alameh; Zhenglin Wang

2006-01-01

12

Dynamic optical filter using Opto-VLSI technology  

Microsoft Academic Search

Reconfigurable multi-channel optical filters are presented in this paper. The operation principle of the reconfigurable filter is based on the dynamic beam steering capacity of Opto-VLSI processor in conjunction with a high dispersion free space grating. The dispersion grating separates the input signal spectrum while the Opto-VLSI processor is driven by optimised phase holograms to dynamically select the wavelengths to

Zhenglin Wang; Kamal Alameh; Rong Zheng; KiakChung Poh

2006-01-01

13

Optical I/O technology for digital VLSI  

NASA Astrophysics Data System (ADS)

We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scale integration (VLSI) circuits. However, for implementation of optical systems in high performance computing applications, the cost of components and packaging has to come down significantly from the traditional optical communication distances. In the current work we attempted to realize such a system by using power efficient optical and electronic components together with a potentially low cost packaging solution compatible with the electronics industry. Vertical Cavity Surface Emitting Lasers (VCSEL), positive-intrinsic-negative (PIN) photodetectors, polymer waveguide arrays as well as CMOS transceiver chip were heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0.18?m processing technology contains VCSEL drivers, transimpedance and limiting amplifiers and on-chip self-testing circuits. A self-test circuit in such high-speed systems will be highly beneficial to reduce the testing cost in real products. For fully assembled packages we measured a 3 Gb/s optical eye for the transmitter (24Gb/s aggregate data rate) and a transmission over the complete link was achieved at 1 Gb/s (8Gb/s aggregate data rate).

Mohammed, Edris M.; Thomas, Thomas P.; Lu, Daoqiang; Braunisch, Henning; Towle, Steven; Barnett, Brandon C.; Young, Ian A.; Vandentop, Gilroy

2004-06-01

14

Wafer-level vacuum/hermetic packaging technologies for MEMS  

NASA Astrophysics Data System (ADS)

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

15

Assessment of Silicon-on-Insulator Technologies for VLSI (Very Large Scale Integration).  

National Technical Information Service (NTIS)

A high-performance, cost-effective silicon-on-insulator (SOI) technology would have important near-term applications in radiation-hardened electronics and longer term applications in submicrometer VLSI. The advantages of SOI over bulk Si technology for th...

B. Y. Tsaur

1986-01-01

16

ELTRAN® (SOI-Epi Wafer™) Technology  

Microsoft Academic Search

\\u000a ELTRAN® (Epitaxial Layer TRANsfer), which is the first manufacturable and commercially available product using Porous Si,\\u000a has been originated, developed and produced in Canon Inc., Japan. The last established technique is highly reproducible splitting\\u000a in the Porous Si layer by Water Jet and reuse the seed wafer several times. The thicknesses of both SOI and the buried oxide\\u000a layers are

Takao Yonehara; Kifofumi Sakaguchi

17

A Monolithic Hough Transform Processor Based on Restructurable VLSI  

Microsoft Academic Search

The implementation of a Hough transform processor using a wafer-scale-integration technology, restructurable VLSI circuit is described. The Hough transform is typically used as a grouping operation in an image processing sequence. The transform discussed here groups pixels in order to extract linear features. This calculation is realized with a wafer-scale processor that allows a complete line extraction system to be

F. Matthew Rhodes; Joseph J. Dituri; Glenn H. Chapman; Bruce E. Emerson; Antonio M. Soares; Jack I. Raffel

1988-01-01

18

Wafer and piece-wise Si tip transfer technologies for applications in scanning probe microscopy  

Microsoft Academic Search

A novel tip transfer technology is proposed for applications in scanning probe microscopy (SPM). The technology is based on the concept of fabricating tips on an independent wafer and transferring them onto the target wafer. The transfer is also feasible on a full 4-in wafer scale. This is especially attractive for postprocessing CMOS wafers, e.g., for atomic force microscopy chips

Terunobu Akiyama; Urs Staufer; Nicolaas F. de Rooij

1999-01-01

19

Advanced FTIR technology for the chemical characterization of product wafers  

NASA Astrophysics Data System (ADS)

Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers. .

Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

2001-01-01

20

Fabricating capacitive micromachined ultrasonic transducers with wafer-bonding technology  

Microsoft Academic Search

Introduces a new method for fabricating capacitive micromachined ultrasonic transducers (CMUTs) that uses a wafer bonding technique. The transducer membrane and cavity are defined on an SOI (silicon-on-insulator) wafer and on a prime wafer, respectively. Then, using silicon direct bonding in a vacuum environment, the two wafers are bonded together to form a transducer. This new technique, capable of fabricating

Yongli Huang; A. Sanli Ergun; E. Haeggstrom; Mohammed H. Badi; B. T. Khuri-Yakub

2003-01-01

21

Material and process limits in silicon VLSI technology  

Microsoft Academic Search

The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely believed that this process will continue for at least another ten years. However there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur, and beyond ten years

JAMES D. PLUMMER; PETER B. GRIFFIN

2001-01-01

22

Product assurance technology for custom LSI/VLSI electronics  

NASA Technical Reports Server (NTRS)

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

1985-01-01

23

Wafer level packaging technology development for CMOS image sensors using Through Silicon Vias  

Microsoft Academic Search

In this paper a low temperature dasiavia-lastrdquo technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the steps of the through silicon vias (TSV) technology will be presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like

J. Charbonnier; D. Henry; F. Jacquet; B. Aventurier; C. Brunet-Manquat; G. Enyedi; N. Bouzaida; V. Lapras; N. Sillon

2008-01-01

24

Laser technology for wafer dicing and microvia drilling for next generation wafers (Invited Paper)  

NASA Astrophysics Data System (ADS)

Laser micromaching systems are being used in mainstream high-volume semiconductor applications. Two of those processes, via drilling and thin wafer dicing, are discussed in this paper. Via drilling has been proven viable for forming through chip and blind vias. The inherent flexibility of the laser process makes it possible to control via depth, diameter and sidewall slope. As a mask-less process, laser via drilling can be cost affective and highly flexible in its application. Thin wafer dicing reduces the breakage and damage to thin silicon wafers. A new process has been developed that improves the die strength of laser singulated devices beyond that obtained using conventional sawing techniques.

Toftness, Richard F.; Boyle, Adrian; Gillen, David

2005-04-01

25

Laser technology for wafer dicing and microvia drilling for next generation wafers (Invited Paper)  

Microsoft Academic Search

Laser micromaching systems are being used in mainstream high-volume semiconductor applications. Two of those processes, via drilling and thin wafer dicing, are discussed in this paper. Via drilling has been proven viable for forming through chip and blind vias. The inherent flexibility of the laser process makes it possible to control via depth, diameter and sidewall slope. As a mask-less

Richard F. Toftness; Adrian Boyle; David Gillen

2005-01-01

26

VLSI electronics: Microstructure science. Volume 9  

NASA Astrophysics Data System (ADS)

Various topics concerning VLSI electronics are discussed. The topics considered include: MOS/bipolar technology tradeoffs for VLSI, critique of refractory gate applications for MOS VLSI, VLSI design tools and environments, VLSI standard part manufacturer as a full-service vendor, VLSIC assembly and packaging, high-speed transport in ultrasmall dimensions, and applications of thermal-wave physics to microelectronics. Also discussed are: surface acoustic wave devices, VLSI and single-chip software-oriented computer architecture, microelectronics for the intelligent building, the next generation of integrated circuits, transport in submicrometer devices, and fabrication and performance of very high-frequency devices.

Einspruch, N. G.

27

VLSI neuroprocessors  

NASA Technical Reports Server (NTRS)

Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional techniques and enables multiple assignments, (many to many), not achievable with standard statistical approaches. Tactical movement planning (finding the best path from A to B) is accomplished with a digital two-dimensional concurrent processor array. By exploiting the natural parallel decomposition of the problem in silicon, a four order of magnitude speed-up over optimized software approaches has been demonstrated.

Kemeny, Sabrina E.

1994-01-01

28

17.5um thin Cu wire bonding for fragile low-K wafer technology  

Microsoft Academic Search

This paper describes the challenges of a 17.5um thin bare Cu wire bonding on aluminum bond pads for a fragile low-k wafer technology, on a BGA package. Previous evaluations have so far focused on 20um and 25um bare Cu wires as a suitable low cost replacement for Au wires. To improve performance, more fragile low-k wafer technology is being developed.

Teo Chen; Kim Jude

2010-01-01

29

SCREEN PRINTABLE POLYMERS FOR WAFER LEVEL PACKAGING: A TECHNOLOGY ASSESSMENT  

Microsoft Academic Search

Screen print patterning is an attractive alternative to traditional semiconductor photo-lithography. Our work compared the pattern resolution and mechanical resistance of screen-printed polymers versus spin-on methods. Optical microscopy of screen-printed coatings reveal sharp edge features as well as masked off saw streets and I\\/Os across the wafer. Thickness comparisons are made between the 2 methodologies. Design rules for screen fabrication,

James Clayton; Michael J. Hodgin

30

Fast integral rigorous modeling applied to wafer topography effect prediction on 2x nm bulk technologies  

NASA Astrophysics Data System (ADS)

Reflection by wafer topography and underlying layers during optical lithography can cause unwanted overexposure in the resist [1]. In most cases, the use of bottom anti reflective coating limits this effect. However, this solution is not always suitable because of process complexity, cost and cycle time penalty, as for ionic implantation lithography process in 28nm bulk technology. As a consequence, computational lithography solutions are currently under development to simulate and correct wafer topographical effects [2], [3]. For ionic implantation source drain (SD) photolithography step, wafer topography influences resulting in implant pattern variation are various: active silicon areas, Poly patterns, Shallow Trench Isolation (STI) and topographical transitions between these areas. In 28nm bulk SD process step, the large number of wafer stack variations involved in implant pattern modulation implies a complex modeling of optical proximity effects. Furthermore, those topography effects are expected to increase with wafer stack complexity through technology node downscaling evolution. In this context, rigorous simulation can bring significant value for wafer topography modeling evolution in R and D process development environment. Unfortunately, classical rigorous simulation engines are rapidly run time and memory limited with pattern complexity for multiple under layer wafer topography simulation. A presentation of a fast rigorous Maxwell's equation solving algorithm integrated into a photolithography proximity effects simulation flow is detailed in this paper. Accuracy, run time and memory consumption of this fast rigorous modeling engine is presented through the simulation of wafer topography effects during ionic implantation SD lithography step in 28nm bulk technology. Also, run time and memory consumption comparison is shown between presented fast rigorous modeling and classical rigorous RCWA method through simulation of design of interest. Finally, integration opportunity of such fast rigorous modeling method into OPC flow is discussed in this paper.

Michel, J.-C.; Le Denmat, J.-C.; Tishchenko, A.; Jourlin, Y.

2014-03-01

31

3D micro-optical lens scanner made by multi-wafer bonding technology  

NASA Astrophysics Data System (ADS)

We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

Bargiel, S.; Gorecki, C.; Bara?ski, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frömel, J.

2013-03-01

32

Through Silicon Via and 3-D Wafer\\/Chip Stacking Technology  

Microsoft Academic Search

Through silicon via and 3D wafer\\/chip stacking technology is thought to be the essential technology of the next generation high-end semiconductors such as high-speed microprocessors and high-speed memories. However, there are many issues regarding LSI design, process integration, thermal management, and cost are under development. Cost is one of the most critical issues to apply this technology to products. We

Kenji Takahashi; Masahiro Sekiguchi

2006-01-01

33

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics  

NASA Technical Reports Server (NTRS)

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

34

Exploring the Silicon Design Limits of Thin Wafer IGBT Technology: The Controlled Punch Through (CPT) IGBT  

Microsoft Academic Search

The paper introduces a new controlled punch through (CPT) IGBT buffer for next generation devices, which utilise thin wafers technology. The new concept is based on very shallow buffers with optimized doping profiles enabling minimum silicon design thicknesses close to the theoretical limit for a given voltage class. The advanced shaping of the buffer doping profile brings additional degree of

J. Vobecky; M. Rahimo; A. Kopta; S. Linder

2008-01-01

35

Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology  

NASA Astrophysics Data System (ADS)

Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

Shi, Fang Frank

36

Wafer-Level Transfer Technologies for PZT-Based RF MEMS Switches  

Microsoft Academic Search

We report on wafer-level transfer technologies to integrate PZT-based radio frequency (RF) microelectromechanical-systems switches on CMOS. Such heterogeneous integration can overcome the incompatibility of PZT material with back-end-of-the-line (BEOL) CMOS technology. The PZT stack and the transfer process have been optimized to avoid degradation of the PZT actuators during the transfer. In particular, we have optimized the seed layer for

Roland Guerre; Ute Drechsler; Debabrata Bhattacharyya; Pekka Rantakari; Richard Stutz; Robert V. Wright; Zlatoljub D. Milosavljevic; Tauno Vaha-Heikkila; Paul B. Kirby; Michel Despont

2010-01-01

37

Riscy approach to VLSI  

SciTech Connect

A general trend in computers today is to increase the complexity of architectures along with the increasing potential of implementation technologies. The consequences of this complexity are increased design time, more design errors, inconsistent implementations, and the delay of single chip implementation. The reduced instruction set computer (RISC) project investigates a VLSI alternative to this trend. The initial design is called RISC I. The authors discuss this project. 9 references.

Fitzpatrick, D.T.; Foderaro, J.K.; Katevenis, M.G.H.; Landman, H.A.; Patterson, D.A.; Peek, J.B.; Peshkess, Z.; Sequin, C.H.; Sherburne, R.W.; Van Dyke, K.S.

1982-03-01

38

Recent Development on the Production Technology of Silicon Carbide Wafers  

NASA Astrophysics Data System (ADS)

Recent development and current status on the growth technology of silicon carbide (SiC) single crystals, long-known as a promising wide bandgap semiconductor material applicable to electronic devices of higher performance, are briefly described. The micropipe defect density, which is known to cause fatal problems in SiC devices, has been reduced significantly, and up to date no longer cited as the most harmful defect for device applications. In addition, such technological advance has led to the increase of the crystal diameters up to 100mm, evoking acceleration of SiC device productions.

Fujimoto, Tatsuo

39

Self-adaptive phosphor coating technology for wafer-level scale chip packaging  

NASA Astrophysics Data System (ADS)

A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

2013-05-01

40

Evaluation of wafer bonding and etch back for SOI technology  

Microsoft Academic Search

Film quality and crystalline perfection of SOI layers obtained by bonding and etch back silicon-on-insulator (BESOI) technology have been studied. In particular, the various mechanisms of defect generation that contribute to a degradation of the original bulk Si quality in the superficial Si layer of such SOI structures have been investigated. Utilizing transmission x-ray topography combined with transmission electron microscopy

Helmut Baumgart; Theodore J. Letavic; Richard Egloff

1995-01-01

41

VLSI Architecture: Past, Present, and Future  

Microsoft Academic Search

This paper examines the impact of VLSI technology on the evolution of computer architecture and projects the future of this evolution. We see that over the past 20 years, the increased den- sity of VLSI chips was applied to close the gap between microprocessors and high-end CPUs. Today this gap is fully closed and adding devices to uniprocessors is well

William J. Dally; Steve Lacy

1999-01-01

42

Cubic millimeter power inductor fabricated in batch-type wafer technology  

Microsoft Academic Search

A hybrid technology for the realization of three-dimensional (3-D) miniaturized power inductors is presented. Our devices consist of planar Cu coils on polyimide substrates, and mm-size ferrite magnetic cores, obtained by three-dimensional micro-patterning of ferrite wafers using powder blasting. The coils are realized using an in-house developed high-resolution polyimide spinning and Cu electroplating process. Winding widths down to 5 ?m

Menouer Saidani; Martin A. M. Gijs

2003-01-01

43

Impact of an LPT(II) concept with Thin Wafer Process Technology for IGBT's vertical structure  

Microsoft Academic Search

In this paper, for the first time, 600 ~ 6500 V IGBTs utilizing a new vertical structure of ldquoLight Punch-Through (LPT) (II)rdquo with Thin Wafer Process Technology demonstrate high total performance with low overall loss and high safety operating area (SOA) capability. This collector structure enables a wide position in the trade-off characteristics between on-state voltage (VCE(sat)) and turn-off loss

Katsumi Nakamura; Daisuke Oya; Shoji Saito; Hiroaki Okabe; Kazunari Hatade

2009-01-01

44

Wafer-Level Packaging for RF Applications Using High-Resistivity Polycrystalline Silicon Substrate Technology  

Microsoft Academic Search

High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate in Wafer-Level Chip-Size Packaging (WLCSP) for RF applications. The WLCSP solution we demonstrate is based on adhesive bonding of a HRPS wafer to a silicon wafer with active devices. After bonding, the IC wafer is thinned below 50 µm and selectively removed to expose its front-side

A. Polyakov; S. Sinaga; P. M. Mendes; M. Bartek; J. H. Correia; J. N. Burghartz

45

Optical interconnections for VLSI systems  

Microsoft Academic Search

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The

S.-Y. Kung; R. A. Athale; Sun-Yuan Kung

1984-01-01

46

Hotspot management for spacer patterning technology with die-to-database wafer inspection system  

NASA Astrophysics Data System (ADS)

We have constructed hotspot management flow with a die-to-database (D2DB) inspection system for spacer patterning technologies (SPTs) which are among the strongest candidates in double patterning technologies below 3x nm half-pitch generations. At SPIE 2006[1], we reported in "Hotspot management" that extracted hotspot by full-chip lithography simulation could be quickly fed back to OPC, mask making, etc. Since the SPT includes process complexity from resist patterning to final device patterning, however, it is difficult to exactly estimate hotspots on final patterned features on wafers by full-chip lithography simulation. Therefore, experimental full-chip inspection methodologies for hotspots extraction are necessary in order to construct hotspot management for SPTs. In this work, we applied the D2DB inspection system with electron beam (EB) to SPTs in hotspot management flow. For the D2DB inspection system, the NGR-2100 has remarkable features for the full-chip inspection within reasonable operating time. This system provides accurate hotspot extraction by EB with wider field of view (FOV) than that of SEMs. With the constructed hotspot management flow, extracted hotspots for SPT involving errors of around 10nm could easily be fed back to fix the wafer processes and mask data.

Hagio, Yoshinori; Nagahama, Ichirota; Matsuoka, Yasuo; Mukai, Hidefumi; Hashimoto, Koji

2009-03-01

47

Ultra thin-wafer technology for a new 600 V-NPT-IGBT  

Microsoft Academic Search

In this paper the method of manufacturing 100 ?m thin IGBT wafers is described. The key topic of new deposition processes reducing the bow of very thin wafers is discussed as well as improvements in equipment and wafer handling. These measurements are the basis to realize for the first time 600 V Non-Punch-Through IGBTs with their advantages of cost effective

T. Laska; M. Matschitsch; W. Scholz

1997-01-01

48

A monolithic active pixel sensor for charged particle tracking and imaging using standard VLSI CMOS technology  

Microsoft Academic Search

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode, which is readily available in a CMOS technology. The diode has a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive

R. Turchetta; J. D. Berst; B. Casadei; G. Claus; C. Colledani; W. Dulinski; Y. Hu; D. Husson; J. P. Le Normand; J. L. Riester; G. Deptuch; U. Goerlach; S. Higueret; M. Winter

2001-01-01

49

Product assurance technology for procuring reliable, radiation-hard, custom LSI\\/VLSI electronics  

Microsoft Academic Search

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS\\/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip,

M. G. Buehler; R. A. Allen; B. R. Blaes; K. A. Hicks; G. A. Jennings; Y.-S. Lin; C. A. Pina; H. R. Sayah; N. Zamani

1989-01-01

50

Sensitivity analysis of add-on price estimate for select silicon wafering technologies  

NASA Technical Reports Server (NTRS)

The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

Mokashi, A. R.

1982-01-01

51

Thin-film encapsulation technology for above-IC MEMS wafer-level packaging  

NASA Astrophysics Data System (ADS)

This work presents a low-cost and low-temperature wafer-level packaging solution for microelectromechanical systems (MEMS) devices. Heat-sensitive polymer poly(propylene carbonate) is used as the sacrificial material to release the capping layer in a clean and fast manner. Free-standing caps made of amorphous silicon carbide films and as large as 450 µm in diameter are successfully fabricated. To demonstrate the validity of this technology, surface-micromachined Pirani vacuum gauges are fabricated as an example of MEMS devices and encapsulated. Capped Pirani gauges respond to pressure between 1 mTorr and 1 atm. The Pirani gauges are sealed with Parylene C films that exhibit near-hermetic properties and the initial sealing pressure for 300 µm diameter cavities is characterized to be in the range of tens of torr.

Zhang, Qing; Cicek, Paul-Vahé; Nabki, Frederic; El-Gamal, Mourad

2013-12-01

52

Symbolic Layout for Bipolar and MOS VLSI  

Microsoft Academic Search

VLSI design requires design methodologies which are tailored to the implementation technology. Symbolic layout has been addressed in the past for MOS technology, while bipolar technology has largely been ignored. This paper describes a novel symbolic design technique which addresses both bipolar and MOS technologies. The technique allows the designer to symbolically layout nMOS, CMOS, and bipolar circuit structures. The

Kevin S. B. Szabo; James M. Leask; Mohamed I. Elmasry

1987-01-01

53

Single-wafer-processed nano-positioning XY-stages with trench-sidewall micromachining technology  

NASA Astrophysics Data System (ADS)

For operation and manipulation with nanometric positioning precision, a single crystalline silicon micro XY-stage is developed by using double-sided bulk-micromachining technology. Front-side deep reactive ion etching combined with backside anisotropic etching constructs the high-aspect-ratio comb-driven XY-stage in a single standard silicon wafer (i.e., no silicon on insulator wafer is used). For integrating several electrostatic actuators in one silicon chip, different actuators are electrically isolated from each other using a trench-sidewall insulating technique. SiO2-refilled trench bars are formed on vertical trench sidewalls to isolate adjacent comb-drive elements. Combined with the reverse-biased p-n junction along the boron-diffused trench sidewall for comb driving, individual actuators can be operated independently. The developed XY-stage of 1600 × 1600 µm2 is suspended by four sets of folded-beam and bending-flexure composite springs. To maximize the moving distance, a two-segment comb finger with a gently curved transition is used for both improving the actuation efficiency and avoiding side instability of the stage. The experimental results verify the stage design including the gentle transition of a two-segment comb-drive scheme. Under 23 V driving voltage, a 10 µm moving stroke is measured in each of the four directions. Compared with a conventional comb structure, the two-segment comb fingers contribute 70% improvement in actuating amplitude. The positioning precision of the stage is evaluated with a nano-mechanical indenting experiment. A scanning probe microscopy probe with an electrical-heated nano tip is put in contact with the surface of a polymethyl methacrylate film that is coated on the stage surface. Along with the movement of the stage, pulsed heating on the nano tip produces serial nano-pitches. With the nano-indenting experiment, better than 18 nm positioning precision is obtained for the XY-stage.

Gu, Lei; Li, Xinxin; Bao, Haifei; Liu, Bin; Wang, Yuelin; Liu, Min; Yang, Zunxian; Cheng, Baoluo

2006-07-01

54

Smart power approaches VLSI complexity  

Microsoft Academic Search

This paper reviews the latest trends in the mixed power process field driven by the need to integrate increasing numbers of functions on the same chip. The more recent BCD (bipolar-CMOS-DMOS) examples are a demonstration of how smart power technology evolves following, with some delay, the road maps of VLSI CMOS and BiCMOS. The issues behind the trend to converge

C. Contiero; P. Galbiati; M. Palmieri; G. Ricotti; R. Stella

1998-01-01

55

Across wafer focus mapping and its applications in advanced technology nodes  

Microsoft Academic Search

The understanding of focus variation across a wafer is crucial to CD control (both ACLV and AWLV) and pattern fidelity on the wafer and chip levels. This is particularly true for the 65nm node and beyond, where focus margin is shrinking with the design rules, and is turning out to be one of the key process variables that directly impact

Gary Zhang; Stephen DeMoor; Scott Jessen; Qizhi He; Winston Yan; Sopa Chevacharoenkul; Venugopal Vellanki; Patrick Reynolds; Joe Ganeshan; Jan Hauschild; Marco Pieters

2006-01-01

56

Supercomputers and VLSI: the effect of large scale integration on computer architecture. Interim report  

SciTech Connect

The use of VLSI technology to build supercomputers is analyzed in depth. The benefits of VLSI are reviewed, and the liabilities are explored thoroughly. The perimeter problem and the planarity problem are identified as being critical limits on architectural design. The CHiP architecture, a highly parallel computer designed with VLSI implementation in mind, is scrutinized in terms of how well it exploits the benefit fo VLSI and how well it avoids the liabilities. Not surprisingly, it does pretty well.

Snyder, L.

1984-08-01

57

Laser Wafering for Silicon Solar.  

National Technical Information Service (NTIS)

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire s...

B. Jared B. Sweatt T. A. Friedman

2011-01-01

58

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories  

NASA Astrophysics Data System (ADS)

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

59

Ultra-high heat flux cooling characteristics of cryogenic micro-solid nitrogen particles and its application to semiconductor wafer cleaning technology  

NASA Astrophysics Data System (ADS)

The ultra-high heat flux cooling characteristics and impingement behavior of cryogenic micro-solid nitrogen (SN2) particles in relation to a heated wafer substrate were investigated for application to next generation semiconductor wafer cleaning technology. The fundamental characteristics of cooling heat transfer and photoresist removal-cleaning performance using micro-solid nitrogen particulate spray impinging on a heated substrate were numerically investigated and experimentally measured by a new type of integrated computational-experimental technique. This study contributes not only advanced cryogenic cooling technology for high thermal emission devices, but also to the field of nano device engineering including the semiconductor wafer cleaning technology.

Ishimoto, Jun; Oh, U.; Guanghan, Zhao; Koike, Tomoki; Ochiai, Naoya

2014-01-01

60

High Energy IED measurements with MEMs based Si grid technology inside a 300mm Si wafer  

NASA Astrophysics Data System (ADS)

The measurement of ion energy at the wafer surface for commercial equipment and process development without extensive modification of the reactor geometry has been an industry challenge. High energy, wide frequency range, process gases tolerant, contamination free and accurate ion energy measurements are the base requirements. In this work we will report on the complete system developed to achieve the base requirements. The system includes: a reusable silicon ion energy analyzer (IEA) wafer, signal feed through, RF confinement, and high voltage measurement and control. The IEA wafer design required carful understanding of the relationships between the plasma Debye length, the number of grids, intergrid charge exchange (spacing), capacitive coupling, materials, and dielectric flash over constraints. RF confinement with measurement transparency was addressed so as not to disturb the chamber plasma, wafer sheath and DC self-bias as well as to achieve spectral accuracy The experimental results were collected using a commercial parallel plate etcher powered by a dual frequency (VHF + LF). Modeling and Simulations also confirmed the details captured in the IED.

Funk, Merritt

2012-10-01

61

VLSI Signal Processing for Wireless Communication  

Microsoft Academic Search

Wireless communication system is a heavy dense composition of signal processing techniques with semiconductor technologies. With the ever increasing system capacity and data rate, VLSI design and implementation method for wireless communications becomes more challenging, which urges researchers in signal processing to provide new architectures and efficient algorithms to meet low power and high performance requirements. This paper presents a

Xinming Huang

62

High-Brightness GaN-Based Light-Emitting Diodes on Si Using Wafer Bonding Technology  

NASA Astrophysics Data System (ADS)

GaN-based light-emitting diodes (LEDs) grown on Si(111) substrates were fabricated with a vertical electrode method by using wafer bonding technology. The fabricated vertical LEDs showed a lower operating voltage and larger light output power than conventional LEDs due to enhancement in current spreading and reduction in tensile strain. The light output power of the vertical structured LEDs was 2.6 times higher than that of conventional LEDs, with an operating voltage at 20 mA reduced from 3.5 to 3.2 V.

Lee, Seung-Jae; Kim, Kang Ho; Ju, Jin-Woo; Jeong, Tak; Lee, Cheul-Ro; Baek, Jong Hyeob

2011-06-01

63

Uniform and High-Power Characteristics of AlGaInP-based Laser Diodes by 4-inch Wafer Process Technology for DVD-R\\/RW\\/RAM  

Microsoft Academic Search

In this study, we demonstrate the high-power (over 400 mW) at 75 degC single-lateral-mode operation of a 650-nm band LD, and we present the excellent uniformity of LD characteristics in 4-inch wafer. In summary, we have successfully fabricated high-power and single-lateral-mode 650-nm band AlGaInP LDs by using the 4-inch wafer process technology for the first time. The results confer the

H. Sumitomo; S. Kajiyama; H. Oguri; T. Sakashita; S. Domoto; K. Nakao; T. Yamamoto; T. Kita; T. Komatani; H. Kawakubo; M. Ono; S. Izumi

2006-01-01

64

The 1992 4th NASA SERC Symposium on VLSI Design  

NASA Technical Reports Server (NTRS)

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

Whitaker, Sterling R.

1992-01-01

65

An opto-VLSI reconfigurable broad-band optical splitter  

Microsoft Academic Search

A reconfigurable broad-band optical splitter is presented, which uses the multicasting capability of opto-very-large-scale-integrated (Opto-VLSI) technology to adaptively split an optical signal to N fiber ports. We demonstrate the proof-of-principle of a three-port structure that uses a reconfigurable Opto-VLSI processor to adaptively multicast an input optical signal with dynamic attenuation range of more than 25 dB over 55-nm bandwidth.

Rong Zheng; Zhenglin Wang; Kamal E. Alameh; William A. Crossland

2005-01-01

66

NASA Space Engineering Research Center for VLSI System Design  

NASA Technical Reports Server (NTRS)

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

1993-01-01

67

Parallel VLSI Architecture  

NASA Technical Reports Server (NTRS)

Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

1985-01-01

68

VLSI Circuit Functionality Tester.  

National Technical Information Service (NTIS)

An integrated system that assists a user in testing the functional specification of a very large scale integration (VLSI) circuit is described. The system is based on a NEC 8001 microcomputer that communicates with a NASCOM 1 microcomputer to drive the de...

P. H. Jesty

1986-01-01

69

Research in VLSI Systems.  

National Technical Information Service (NTIS)

This report summarizes progress on Research in VLSI Systems, from March 1981 to May 1982. The major areas under investigation are design description and synthesis, testing, and algorithms and architectures. In each area, our aim is to anticipate and to so...

J. Hennessy J. Newkirk R. Mattews T. Kailath

1982-01-01

70

Wafer bonding for MEMS and CMOS integration  

NASA Astrophysics Data System (ADS)

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.

Dragoi, V.; Pabo, E.; Burggraf, J.; Mittendorfer, G.

2011-05-01

71

Wafer scale nano-membranes supported on a silicon microsieve using thin-film transfer technology  

NASA Astrophysics Data System (ADS)

A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independent of the thin film, which is later transferred onto it by fusion bonding, thus providing flexibility in design and processing steps. Using this thin-film transfer technique, nano-membranes down to 50 nm thickness are fabricated. The fabrication of different kinds of membranes made of inorganic, metallic and polymer materials is presented here. Apart from dense nano-membranes, perforated membranes are fabricated using this modular approach. One of the main areas of interest for such membranes is in fluidics, where the low thickness and high strength of the supported nano-membranes are a big advantage.

Unnikrishnan, Sandeep; Jansen, Henri; Berenschot, Erwin; Elwenspoek, Miko

2008-06-01

72

Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies  

NASA Astrophysics Data System (ADS)

We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of InP/Si substrates for bulk InP in the fabrication of such a four-junction solar cell could significantly reduce the substrate cost since the current prices for commercial InP substrates are much higher than those for Si substrates by two orders of magnitude. Direct heteroepitaxial growth of InP thin films on Si substrates has not produced the low dislocation-density high quality layers required for active InGaAs/InP in optoelectronic devices due to the ˜8% lattice mismatch between InP and Si. We successfully fabricated InP/Si substrates by He implantation of InP prior to bonding to a thermally oxidized Si substrate and annealing to exfoliate an InP thin film. The thickness of the exfoliated InP films was only 900 nm, which means hundreds of the InP/Si substrates could be prepared from a single InP wafer in principle. The photovoltaic current-voltage characteristics of the In0.53Ga0.47As cells fabricated on the wafer-bonded InP/Si substrates were comparable to those synthesized on commercially available epi-ready InP substrates, and had a ˜20% higher short-circuit current which we attribute to the high reflectivity of the InP/SiO2/Si bonding interface. This work provides an initial demonstration of wafer-bonded InP/Si substrates as an alternative to bulk InP substrates for solar cell applications. We have observed photocurrent enhancements up to 260% at 900 nm for a GaAs cell with a dense array of Ag nanoparticles with 150 nm diameter and 20 nm height deposited through porous alumina membranes by thermal evaporation on top of the cell, relative to reference GaAs cells with no metal nanoparticle array. This dramatic photocurrent enhancement is attributed to the effect of metal nanoparticles to scatter the incident light into photovoltaic layers with a wide range of angles to increase the optical path length in the absorber layer. GaAs solar cells with metallic structures at the bottom of the photovoltaic active layers, not only at the top, using semiconductor-metal direct bonding have been fabricated. These metallic back structures could incouple the incident

Tanake, Katsuaki

73

Large array VLSI filter  

SciTech Connect

A 35-by-35-element pipelined convolutional kernel is being fabricated using VLSI chips, each containing a 5-by-1 segment of the kernel. Three levels of printed circuitry are used: the first is used for the VLSI chips; the second connects seven chips on one platform; and the third connects seven platforms with associated delay lines fitting on one board. Therefore, on each board there are seven rows of the kernel containing 245 multipliers and adders, and five such boards complete the kernel array. Each multiplier accepts an 8-bit picture element which is multiplied by a 16-bit weight. A truncated 22-bit product is added to a previously stored product sum and the results are shifted to the following multiplier as the next picture element is read. The multiplier uses a modified booth algorithm to reduce the number of shift add operations nearly in half. The filter box can be connected to any CPU. 3 references.

Nathan, R.

1983-10-01

74

Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits  

Microsoft Academic Search

In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.

Wojciech Maly

1985-01-01

75

Exploring the VLSI Scalability of Stream Processors  

Microsoft Academic Search

Stream processors are high-performance programmable processors optimized to run media applications. Recent work has shown these processors to be more area- and energy-efficient than conventional programmable architec- tures. This paper explores the scalability of stream archi- tectures to future VLSI technologies where over a thousand floating-point units on a single chip will be feasible. Two techniques for increasing the number

Brucek Khailany; William J. Dally; Scott Rixner; Ujval J. Kapasi; John D. Owens; Brian Towles

2003-01-01

76

VLSI implementation of digital fourier transforms  

SciTech Connect

The construction of Fast Fourier Transform (FFT) processors is discussed. Pipeline and parallel-pipeline organizations are developed and are shown to meet the constraints imposed by VLSI. Various circuit technologies for the construction of these processors are compared, and the description of a set of NMOS chips are given. A technique for reducing the latency of the adders internal to the chips is also presented. Finally, a broad set of possible FFT organizations is discussed.

Despain, A.; Sequin, C.; Thompson, C.; Wold, E.; Lioupis, D.

1982-11-01

77

Verification of VLSI designs  

NASA Technical Reports Server (NTRS)

In this paper we explore the specification and verification of VLSI designs. The paper focuses on abstract specification and verification of functionality using mathematical logic as opposed to low-level boolean equivalence verification such as that done using BDD's and Model Checking. Specification and verification, sometimes called formal methods, is one tool for increasing computer dependability in the face of an exponentially increasing testing effort.

Windley, P. J.

1991-01-01

78

Low temperature full wafer adhesive bonding of structured wafers  

Microsoft Academic Search

In this paper, we present a technology for void free low temperature full wafer adhesive bonding of structured wafers. Benzocyclobutene (BCB) is used as the intermediate bonding material. BCB bonds well with various materials and does not release significant amounts of by-products during the curing process. Thus void-free bond interfaces can be achieved. Cured BCB coatings have an excellent resistance

F. Niklaus; H. Andersson; P. Enoksson; G. Stemme

2001-01-01

79

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology  

NASA Astrophysics Data System (ADS)

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

80

Very Large Scale Integration (VLSI).  

ERIC Educational Resources Information Center

Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

Yeaman, Andrew R. J.

81

Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review  

Microsoft Academic Search

This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an im- portant manufacturing technique for advanced microelectronics and microelectromechanical systems, including 3-D integrated circuits, advanced wafer-level packaging, and microfluidics. Commercially available alignment tools provide prebonding wafer-to-wafer misalignment tolerances on the order of 0.25 µm. However, better alignment accuracy is required for increasing demands

Sang Hwui Lee; Kuan-Neng Chen; James Jian-Qiang Lu

2011-01-01

82

HMIC wafer level packaging  

Microsoft Academic Search

HMIC, an acronym for Heterolithic Microwave Integrated Circuits, is fundamentally a wafer level substrate which combines low, RF loss tangent glass with micromachined silicon to produce three dimensional circuitry with the capability to make RF, DC, and thermal vias as the device input and output. Using this technology both active and passive RF devices have been produced which have demonstrated

T. Boles; D. Hoag; M. Barter; R. Giacchino; P. Hogan; J. Goodrich

2009-01-01

83

HMIC wafer level packaging  

Microsoft Academic Search

HMIC, an acronym for heterolithic microwave integrated circuits, is fundamentally a wafer level substrate which combines low, RF loss tangent glass with micromachined silicon to produce three dimensional circuitry with the capability to make RF, DC, and thermal vias as the device input and output. Using this technology both active and passive RF devices have been produced which have demonstrated

T. Boles; D. Hoag; M. Barter; R. Giacchino; P. Hogan; J. Goodrich

2009-01-01

84

System-on-Wafer: 2-D and 3-D Technologies for Heterogeneous Systems  

Microsoft Academic Search

System integration, performance, cost and enhanced product functionality form the major driving forces behind contemporary innovations in packaging. The need for minia- turization has led to new architectures which combine a whole range of different technologies. The ultimate miniaturization goal is to incorporate all of the elements necessary to build the system in the same package. This approach of system-in-package

Jean-Charles Souriau; Nicolas Sillon; Jean Brun; Hervé Boutry; Thierry Hilt; David Henry; Gilles Poupon

2011-01-01

85

Mixed voltage VLSI design  

NASA Technical Reports Server (NTRS)

A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

Panwar, Ramesh; Rennels, David; Alkalaj, Leon

1993-01-01

86

Large array VLSI filter  

NASA Technical Reports Server (NTRS)

A 35 by 35 element pipelined convolutional kernel is being fabricated using VLSI chips, each containing a 5 by 1 segment of the kernel. Three levels of printed circuitry are used: the first level is used for the VLSI chips, the second level connects seven chips together on one platform, and the third level connects seven platforms with associated delay lines, all fitting on one board. Therefore, on each board there are seven rows of the kernel containing 245 multipliers and adders, and five such boards complete the kernel array. Each multiplier accepts an 8 bit picture element which is multiplied by a 16 bit weight. A truncated 22 bit product is added to a previously stored product sum and the results are shifted to the following multiplier as the next picture element is read in. The multiplier uses a modified Booth algorithm to reduce the number of shift add operations nearly in half. The filter box is presently configured as an ancillary box to a VAX 11/780, but can be connected to essentially any CPU. The I/O bandwidth is easily compatible with most CPU devices.

Nathan, R.

1983-01-01

87

Algorithms for VLSI layout  

SciTech Connect

This thesis considers several problems arising during VLSI layout and presents new techniques for solving them efficiently. A linear-time algorithm is proposed for generating a planar layout of a planar graph with n vertices. The vertices are represented by horizontal line segments and the edges by vertical line segments. This layout occupies an area at most n by 2n - 4 and contains no bends. Next, the author investigates two variants of this representation and presents characterizations of the classes of graphs that admit such representations. Furthermore, he presents linear time algorithms for testing the existence of and for constructing visibility representations. He also considers planar embeddings, where vertices are mapped to grid points and edges are mapped to pair-wise nonintersecting grid paths. The problem of wiring a given layout in a uniform grid is a fundamental problem in VLSI layout. A systematic approach to wiring layouts in the octo-square grid is presented. This approach is based on the concept of two-colorable maps. Algorithms for obtaining the wiring of a layout run in time linear with respect to the area occupied by the layout were developed.

Tollis, I.G.

1988-01-01

88

VLSI Chip for AI Workstations.  

National Technical Information Service (NTIS)

A VLSI chip (AI chip) has been developed for artificial intelligence (AI) workstations to support both AI and other procedural languages. The chip is based on the former AI processor (AIP), which combines RISC (reduced instruction set computer) architectu...

T. Aikawa Y. Bandai T. Kinoshita

1989-01-01

89

Analog VLSI for Neural Networks  

Microsoft Academic Search

IntroductionOne of the most promising strategies for implementing neural networks is through the use of electronicanalog VLSI #very large scale integration# circuits. An analog circuit is one that processes a continuum ofreal-valued signals of continuous time, in contrast to a digital circuit which processes integer-valued #mostoften binary# signals in discretized time. VLSI refers to an integrated circuit design and manufacturingtechnology

Robert W. Newcomb; Jason D. Lohn

1995-01-01

90

VLSI Architectures for Computing DFT's  

NASA Technical Reports Server (NTRS)

Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

1986-01-01

91

Double metalization for VLSI  

NASA Technical Reports Server (NTRS)

Postsintering process increases yield of double-layer metal conductors to almost 100 percent. When wafers containing double-metalized chips are sintered, metal layers react with oxide film remaining in insulation layer holes, breaking it up so that it no longer impedes electric current. Cooling also mechanically disrupts oxide film.

Trotter, J. D.; Wade, T. E.

1980-01-01

92

VLSI/LSI components  

NASA Astrophysics Data System (ADS)

Higher IC densities, improvements in static and dynamic RAMs, new program memories, and new manufacturing processes for chips were achieved in 1981. X-ray lithography was used to fabricate submicron MOSFETs, a 64 kbit NMOS entered mass production, and redundancy of ICs on chips became a reality. VLSI design reached a level of 430,000 transistors on a chip with a throughput rate of six trillion gate-Hz/sq cm. The first delivery of 64 kbit dynamic RAMs were made by four companies, with MTBF rates of the better chips of 100,000 hours. Electrically eraseable programmable ROMs with 16 kbit capacity were introduced, as was a 32 bit microprocessor with domino logic CMOS circuits. Finally, gate arrays, single metal layer interconnections, and circuits for CAD are discussed.

Bernhard, R.

1982-01-01

93

High-speed VLSI vision chip and its application  

NASA Astrophysics Data System (ADS)

With the progress of silicon integration technologies, visual information processing architecture has greatly been changed and eventually it can be integrated into a compact and yet high performance integrated circuits. In other words, the image processor is no longer considered as a desktop size bulky equipment but rather as one chip information processing module where photodetector and processing circuits are integrated, which is the VLSI vision chip. This paper discusses the architecture of the VLSI vision chip and some examples of high-speed image processing application are shown.

Ishikawa, Masatoshi

2001-04-01

94

ARPA/CSTO rapid VLSI implementation  

NASA Astrophysics Data System (ADS)

The task objective was to provide rapid access to cost effective, state-of-the-art U.S. microelectronics industry fabrication technology for DoD customers and the educational community. This access was provided through the establishment of a prototyping service for use by the DARPA and NSF research communities which offered access to a variety of technologies unobtainable from a single fabrication source. The Defense Advanced Research Projects Agency (DARPA) had the goal of providing state-of-the-art VLSI fabrication services and electronic systems assembly technology to DoD customers and the educational community to ensure that DoD has access to low-cost, advanced electronic assemblies and to ensure that the country's newly emerging engineers will be able to support military needs in the area of electronics. The first task was to provide VLSI fabrication to DoD and DARPA supported contractors who have need of custom chips and assemblies. The second task was to provide this same technology to NSF-sponsored activities, under DARPA guidance.

Pina, Cesar A.

1993-07-01

95

VLSI workshop and project: February - November 1982  

NASA Astrophysics Data System (ADS)

At regular intervals, the CSIRO VLSI Program coordinates the production of multiproject very large scale integrated circuit chips, in n-mos technology, using the Mead-Conway design method. The author attended the first Workshop conducted in support this activity, and designed a successful digital circuit project which became part of the first such chip. The Workshop, the project, the circuit design, the performance estimation and measured performance are described. Also covered the difficulties encountered in transfering the computer software design tools, supplied by the Program in a form suitable for the VAX computer operating system, to the main-frame IBM 3033 system in use at DRCS.

Hayward, J.

1984-09-01

96

MOS VLSI reliability and yield trends  

Microsoft Academic Search

The yield and reliability capability of an MOS technology are shown to be the product of at least six different technological trends; namely those towards: 1) more complex device structures, 2) scaled down feature sizes, 3) increased wafer sizes, 4) factory automation, 5) increased die size and package lead counts, and 6) increasingly sophisticated computer-aided design tools. The capabilities of

M. H. Woods

1986-01-01

97

Research into Self-Timed VLSI Circuits.  

National Technical Information Service (NTIS)

ALLENDE is a simple and powerful layout language, associated with a structured design methodology for VLSI. It has a combination of features that set it apart from the existing VLSI layout tools. These features include the procedural language approach, th...

R. J. Lipton

1984-01-01

98

Performance analysis of carbon nanotube interconnects for VLSI applications  

Microsoft Academic Search

The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this technology. A model is developed to calculate equivalent circuit parameters for a CNT-bundle interconnect based on interconnect geometry. Us- ing this model, the performance of CNT-bundle interconnects (at local, intermediate and global levels)

Navin Srivastava; Kaustav Banerjee

2005-01-01

99

Are carbon nanotubes the future of VLSI interconnections?  

Microsoft Academic Search

Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper and thereby extend the lifetime of electrical interconnects. This paper examines the state-of-the-art in CNT interconnect

Kaustav Banerjee; Navin Srivastava

2006-01-01

100

Firehose Architectures for Free-Space Optically Interconnected VLSI Circuits  

Microsoft Academic Search

Abstract Free-space optical interconnects will soon be able ,to provide ,input\\/output bandwidths ,to a VLSI chip in excess of a terabit per second. The successful application of this technology to parallel distributed processing systems depends ,on the ,need for high-bandwidth interconnects and

Ashok V. Krishnamoorthy; David A. B. Miller

1997-01-01

101

CCD wafer scale integration  

Microsoft Academic Search

Wafer scale CCD photodetector arrays of 26 million pixels or more are being fabricated on a limited production basis today. This paper provides an introduction to CCD wafer scale integration with an emphasis on common wafer scale CCD design architectures, applications and fabrication processes. Examples of wafer scale CCD products are reviewed, and a triple poly, double metal wafer scale

Paul P. Suni

1995-01-01

102

Wafer Manufacturing and Slicing Using Wiresaw  

NASA Astrophysics Data System (ADS)

Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer quality are presented. Summary and further reading are also provided.

Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

103

Atomically Flat Silicon Surface and Silicon\\/Insulator Interface Formation Technologies for (100) Surface Orientation Large-Diameter Wafers Introducing High Performance and Low-Noise Metal–Insulator–Silicon FETs  

Microsoft Academic Search

Technology to atomically flatten the silicon surface on (100) orientation large-diameter wafer and the formation technology of an atomically flat insulator film\\/silicon interface are developed in this paper. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200-mm-diameter wafers by annealing in pure argon ambience at 1200degC for 30 min. Atomically flat surfaces with

Rihito Kuroda; Tomoyuki Suwa; Akinobu Teramoto; Rui Hasebe; Shigetoshi Sugawa; Tadahiro Ohmi

2009-01-01

104

Laser wafering for silicon solar.  

SciTech Connect

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

105

Novel spin-coating technology for 248-nm/193-nm DUV lithography and low-k spin on dielectrics of 200-mm/300-mm wafers  

NASA Astrophysics Data System (ADS)

An alternative coating technology was developed for 248 nm/193 nm DUV lithography and low-k spin on dielectric (SOD) materials used in the interconnect area. This is a 300 mm enabling technology which overcomes turbulent flow limitations above 2000 rpm and it prevents 40 - 60% reduction on the process latitudes of evaporation-related variables, common to 300 mm conventional coaters. Our new coating technology is fully enclosed and it is capable of controlling the solvent concentration above the resist film dynamically in the gas phase. This feature allows a direct control of the evaporation mass transfer which determines the quality of the final resist profiles. Following process advantages are reported in this paper: (1) Demonstrated that final resist film thickness can be routinely varied by 4000 angstrom at a fixed drying spin speed, thus minimizing the impact of turbulence wall for 300 mm wafers. (2) Evaporation control allows wider range of useful thickness from a fixed viscosity material. (3) Latitudes of evaporation-related process variables is about 40% larger than that of a conventional coater. (4) Highly uniform films of 0.05% were obtained for 8800 angstrom target thickness with tighter wafer-wafer profile control because of the enclosed nature of the technology. (5) Dynamic evaporation control facilitates resist consumption minimization. Preliminary results indicate feasibility of a 0.4 cc process of record (POR) for a 200 mm substrate. (6) Lower COO due to demonstrated relative insensitivity to environmental variables, robust resist consumption minimization and superior process capabilities. (7) Improved planarization and gap fill properties for the new generation photoresist/low-k SOD materials deposited using this enclosed coating technology.

Gurer, Emir; Zhong, Tom X.; Lewellen, John W.; Lee, Ed C.

2000-06-01

106

SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface  

NASA Astrophysics Data System (ADS)

This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

2010-10-01

107

SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface  

Microsoft Academic Search

This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a

Gao Baohong; Liu Yuling; Wang Chenwei; Zhu Yadong; Wang Shengli; Zhou Qiang; Tan Baimei

2010-01-01

108

Clay VLSI layout language  

SciTech Connect

Clay is a procedural language based on C for nMOS VLSI layout. The primitive objects in Clay are wires and symbols. Wires are line segments of a given mask layer. Symbols are small rigid pieces of a layout, such as contact cuts or transistors. Wires and symbols are created and placed in a layout using programming language constructs. Composite structures, such as routing networks, inverters, registers, and PLAs can be written as functions that call lower-level functions or place the necessary wires and symbols directly. The programming language nature of Clay make it convenient to parameterize local and global features of a design, such as the size of a certain pullup transistor or the number of registers in an array. A key property of Clay layouts is that they are flexible. A section of a layout may be stretched as necessary to satisfy constraints on interface wires (those that have connections outside the cell's boundary.) This simplifies cell assembly by eliminating the need for exact pitch matching. All layout in Clay takes place within ordered contexts. Objects placed inside ordered contexts are separated horizontally or vertically, according to the sequential execution of program. There are two steps in the translation of a Clay program. The execution of the user's code wires a system of constraints as a side-effect. The layout constraint solver reads these constraints and outputs a rigid layout mask.

North, S.C.

1986-01-01

109

An interconnect structure for wafer scale neurocomputers  

Microsoft Academic Search

Silicon technology has two limitations: fabrication defects and limited interconnect. The authors believe the fault-tolerance of neural network models can compensate for fabrication defects. In this paper the authors present the design of an interconnect structure for wafer scale neural network emulation based on CMOS silicon technology that solves the interconnect problem. Thus, massively parallel, wafer scale neurocomputer architectures are

M. Rudnick; D. Hammerstrom

1988-01-01

110

SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers  

NASA Astrophysics Data System (ADS)

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

2010-02-01

111

A rule-based VLSI process flow validation system with macroscopic process simulation  

Microsoft Academic Search

As the integration scale of very large-scale integration (VLSI) circuits increases, it is becoming increasingly difficult to design long and complex process flows because there is a great amount of knowledge required in VLSI process technology. To assist in process-flow design, a rule-based validation system has been developed. This system checks designed process flows by using process knowledge related to

KIYOHIKO FUNAKOSHI; KAZUSHI MIZUNO

1990-01-01

112

Implementation studies for a VLSI Prolog coprocessor  

SciTech Connect

Prolog, like other declarative languages, requires the development of new execution models that are more complex than the ones supporting imperative languages. New primitives related to the management of the search strategy and the unification process must be identified. Moreover, to achieve better performance, time-critical primitives must be moved into hardware. Adding a specialized coprocessor to a standard CPU obtains one of the most effective implementations; this method also allows a modular upgrade of existing systems. A Prolog coprocessor behaves differently than numerical coprocessors. It does not execute single instructions; it executes complete segments of Prolog code. The approach the authors describe here refers to a 32-bit coprocessor designed as one VLSI (very large scale integrated) circuit based on microprogrammed architecture. The most innovative aspect of this project is the fully dedicated microarchitecture of the execution unit. The authors performed a detailed analysis and simulated the computational model and its implementation for data to support their final design decisions. They developed the analysis considering two execution techniques: interpreted and compiled. They describe compiled execution selected for the final design. Their simulations trace the actual behavior of the execution model and point out the performance that can be obtained using different architectural solutions. These results permit the selection of an optimal architecture within the technological constraints of VLSI implementation.

Appiani, E.; Conterno, B.; Luperini, V.; Roncarolo, L.

1989-02-01

113

MIPS: A VLSI Processor Architecture  

Microsoft Academic Search

Abstract MIPS is a new single chip VLSIprocessor,architecture. it attempts to achievehigh,performance,with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to severaltraditional hardware problems, such as providing pipeline interlocks, are used. . Key Words and Phrases: Instruction set design, VLSI, computer architecture, pipelining,

John Hennessy; Norman Jouppi; John Gill

114

Fundamentals of Microelectronics Processing (VLSI).  

ERIC Educational Resources Information Center

Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

Takoudis, Christos G.

1987-01-01

115

VLSI Mixed Signal Processing System.  

National Technical Information Service (NTIS)

An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are d...

A. Alvarez A. B. Premkumar

1993-01-01

116

VLSI mixed signal processing system  

NASA Technical Reports Server (NTRS)

An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

Alvarez, A.; Premkumar, A. B.

1993-01-01

117

VLSI architecture for stack filters  

Microsoft Academic Search

A new approach to implementation of stack filtering has been suggested in the work of Astola et al. (see Proceedings of Int. Conf. on Digital Signal Processing, Limassol, Cyprus, 1995). Based on this approach, efficient algorithms and a new VLSI architecture are developed. They are fast and programmable, thus supporting adaptive stack filtering in real time. An arbitrary stack filter

D. Gevorkian; M. Hu; O. Vainio; J. Astola

1997-01-01

118

Wafer-Level ANA Calibrations at NIST  

Microsoft Academic Search

The National Institute of Standards and Technology has begun a program supporting on-wafer scattering parameter measurements. In contrast to many previous NIST endeavors, this program seeks to transfer methodology into industrial measurement laboratories. The subject of this paper is the development of calibration techniques and algorithms, rather than physical standards, for the measurement of on-wafer scattering parameters. In particular, we

Roger Marks; Kurt Phillips

1989-01-01

119

The Fifth NASA Symposium on VLSI Design  

SciTech Connect

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design. Separate abstracts have been prepared for articles from this report.

Not Available

1993-01-01

120

The Fifth NASA Symposium on VLSI Design  

NASA Technical Reports Server (NTRS)

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

1993-01-01

121

Stanford Telecom VLSI design of a convolutional decoder  

Microsoft Academic Search

The authors describe the novel hardware and speed-efficient architectural features of a recent Stanford Telecom VLSI implementation of a 20-Mb\\/s convolutional decoder using 1.5-?m CMOS technology. The chip offers a selection of convolutional codes, including the (2,1) K=7 code commonly used in satellite communications, high-rate punctured versions of the code, and a (2,1) K=6 code included for requirements of backward

H. A. Bustamante; I. Kang; C. Nguyen; R. E. Peile

1989-01-01

122

Silicon Wafer Polishing  

NSDL National Science Digital Library

This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

2009-10-21

123

Opto-VLSI multiband tunable optical filter  

Microsoft Academic Search

A novel Opto-VLSI multiband tunable optical filter structure is proposed and demonstrated. Filter tunability is achieved by reconfiguring the holographic diffraction grating of an Opto-VLSI processor, allowing multiple passbands to be independently synthesised. A proof-of-principle three-passband tunable filter of 2 4;nm bandwidth is experimentally verified.

Mehrdad Raisi; Selam Ahderom; Kamal Alameh; Kamran Eshraghian

2003-01-01

124

Teaching processor architecture with a VLSI perspective  

Microsoft Academic Search

This paper proposes a new approach to teaching computer architecture by placing an explicit emphasis on circuit and VLSI aspects. This approach has the potential to enhance the teaching of both architecture and VLSI classes, to improve collaboration between CS and ECE departments and to lead to a better understanding of the current difficulties faced by microprocessor designers in industry.

Mircea R. Stan; Kevin Skadron

2002-01-01

125

Fast area-efficient VLSI adders  

Microsoft Academic Search

In this paper, we study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results we obtain lead to the design of area-time efficient VLSI adders. This is a major goal of our work: to design very low latency addition circuitry that is also area efficient.

Tackdon Han; David A. Carlson; Tack-don Han

1987-01-01

126

Model Reduction for VLSI Physical Verification  

Microsoft Academic Search

In this paper, we will first introduce physical verification of Very Large Scale Integration (VLSI) circuits and put the challenges in perspective from a computational electro-magnetics point of view. We argue that any models obtained from electromagnetic (electrostatic) analysis should be as simple as possible for a given accuracy. We will then focus on two aspects of VLSI physical verification,

N. P. van der Meijs

127

Silicon Wafer Lapping  

NSDL National Science Digital Library

This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

2010-02-08

128

Low temperature IC-compatible wafer-to-wafer bonding with embedded micro channels for integrated sensing systems  

Microsoft Academic Search

In this work, a low temperature wafer-to-wafer bonding technique is demonstrated. The technology can be implemented on a variety of materials serving as planar substrates in the microelectronics industry. As an integral part of this technique, one of the wafers to be bonded contains a patterned micro molded layer on the surface with a thickness range of 2 ?m to

A. Bruno Frazier

1995-01-01

129

An interconnect structure for wafer scale neurocomputers  

SciTech Connect

Silicon technology has two limitations: fabrication defects and limited interconnect. The authors believe the fault-tolerance of neural network models can compensate for fabrication defects. In this paper the authors present the design of an interconnect structure for wafer scale neural network emulation based on CMOS silicon technology that solves the interconnect problem. Thus, massively parallel, wafer scale neurocomputer architectures are feasible. Their design is part of the Cognitive Architecture Project (CAP) at the Oregon Graduate Center. The CAP architecture is a hybrid using analog computation and multiplexed digital interconnect. The long term goal is to emulate a million nodes, each with a thousand connections, on a single wafer.

Rudnick, M.; Hammerstrom, D.

1988-09-01

130

Focal-plane VLSI processing for multiresolution edge extraction  

NASA Astrophysics Data System (ADS)

The challenge of information extraction in robot vision and automated inspection requires the development of efficient and dedicated hardware systems. A specific requirement relates to the hierarchical description of a scene, which is difficult to implement in real-time on conventional computers. Hardware solutions may exploit parallel computing capabilities in order to provide intelligent sensing of visual information. A promising strategy seeks to exploit VLSI solutions in novel architectures for optical sensing and processing. The Multi- port Array photo-Receptor system (MAR) discussed in this paper combines optical transduction with integrated focal-plane processing. The central element of the MAR system is a full custom VLSI photo-sensor array with hexagonal tessellation which provides parallel analog read-out from groups of pixels over prescribed areas. The overall capability of the sensor is enhanced by the addition of external analog computation which performs real-time spatial convolution at multiple resolutions and uses feedback control for automatic edge tracking. Current VLSI technology allows the fabrication of a CMOS sensor array with dimensions of up to 500 X 500 pixels on a 1.5 cm die using CMOS 1.2 micron technology. VLSI also provides means to integrate analog computing modules and microcontrol capabilities. A set of chips required by the system has been fabricated and a first prototype which integrates an array of 128 X 128 pixels with zero-crossing detection at seven different spatial resolutions runs at a rate of 1 M pixel/sec. Edge data at multiple resolutions are computed in real-time. Parallel edge extraction at 16 different resolutions will be available from a forthcoming unit. The sensor includes arbitrary pixel displacement and non-linear dark current compensation. This type of integrated sensor is a good candidate for advanced applications which require small weight and size.

Tremblay, Marc; Poussart, Denis

1992-10-01

131

VLSI Array processors  

Microsoft Academic Search

High speed signal processing depends critically on parallel processor technology. In most applications, general-purpose parallel computers cannot offer satisfactory real-time processing speed due to severe system overhead. Therefore, for real-time digital signal processing (DSP) systems, special-purpose array processors have become the only appealing alternative. In designing or using such array Processors, most signal processing algorithms share the critical attributes of

S. Kung

1985-01-01

132

Systolic VLSI for Kalman filters  

NASA Technical Reports Server (NTRS)

A novel two-dimensional parallel computing method for real-time Kalman filtering is presented. The mathematical formulation of a Kalman filter algorithm is rearranged to be the type of Faddeev algorithm for generalizing signal processing. The data flow mapping from the Faddeev algorithm to a two-dimensional concurrent computing structure is developed. The architecture of the resulting processor cells is regular, simple, expandable, and therefore naturally suitable for VLSI chip implementation. The computing methodology and the two-dimensional systolic arrays are useful for Kalman filter applications as well as other matrix/vector based algebraic computations.

Yeh, H.-G.; Chang, J. J.

1986-01-01

133

Fast and area-efficient VLSI adders  

SciTech Connect

Area-time tradeoffs have been an important topic in VLSI research. This is because the cost of fabricating a circuit is an exponential function of its area. As a result, optimizing the area of a VLSI design is much more important than optimizing the speed of an algorithm. This dissertation examines area-time tradeoffs in VLSI for prefix computation using graph representations of the problem. Since the problem is intimately related to binary addition, results obtained lead to design of area-time efficient VLSI adders. This is a major goal of the work: to design very low latency-addition circuitry that is also area-efficient. To this end, a new graph representation is presented for prefix computation that leads to the design of a fast, area-efficient binary adder. The new graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, the author designed VLSI adders having area A = O(n log n) whose delay time is the lowest possible value, i.e., the fastest possible area-efficient VLSI adder. For the large number of inputs, the pipelined model of prefix circuit is presented. Also presented is a fault-tolerant model for the developed prefix circuit, based on the partitioning of the network.

Han, T.D.

1987-01-01

134

Computer-aided design of integrated circuit fabrication processes for VLSI (Very Large Scale Integration) devices  

Microsoft Academic Search

Efficient design of high performance VLSI process requires accurate models for the physical processes used for fabrication. This is particularly true as device geometries shrink and fabrication technologies become inherently 2D. First order models for thermal oxidation, ion implantation, diffusion, chemical vapor deposition and other processes cannot accurately predict device structures from modern IC technologies. The fundamental objective of this

J. D. Plummer; R. W. Dutton; J. F. Gibbons; C. R. Helms; J. D. Meindl; W. A. Tiller; C. P. Ho; K. C. Saraswat; B. E. Deal

1983-01-01

135

Fully-depleted silicon-on-sapphire and its application to advanced VLSI design  

NASA Technical Reports Server (NTRS)

In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

Offord, Bruce W.

1992-01-01

136

Extremely long life and low-cost 193nm excimer laser chamber technology for 450mm wafer multipatterning lithography  

NASA Astrophysics Data System (ADS)

193nm ArF excimer lasers are widely used as light sources for the lithography process of semiconductor production. 193nm ArF exicmer lasers are expected to continue to be the main solution in photolithography, since advanced lithography technologies such as multiple patterning and Self-Aligned Double Patterning (SADP) are being developed. In order to apply these technologies to high-volume semiconductor manufacturing, the key is to reduce the total operating cost. To reduce the total operating cost, life extension of consumable part and reduction of power consumption are an important factor. The chamber life time and power consumption are a main factor to decide the total operating cost. Therefore, we have developed the new technology for extension of the chamber life time and low electricity consumption. In this paper, we will report the new technology to extend the life time of the laser chamber and to reduce the electricity consumption.

Tsushima, Hiroaki; Katsuumi, Hisakazu; Ikeda, Hiroyuki; Asayama, Takeshi; Kumazaki, Takahito; Kurosu, Akihiko; Ohta, Takeshi; Kakizaki, Kouji; Matsunaga, Takashi; Mizoguchi, Hakaru

2014-04-01

137

A second generation 50 Mbps VLSI level zero processing system prototype  

NASA Technical Reports Server (NTRS)

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

1994-01-01

138

Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics  

SciTech Connect

Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

None

2010-01-15

139

Case for Digit Serial VLSI Signal Processors.  

National Technical Information Service (NTIS)

Digit serial architectures, which have digit serial data transmission combined with digit serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit serial input are overcome if the input is overlapp...

M. J. Irwin R. M. Owens

1990-01-01

140

Data Structure for VLSI Synthesis and Verification.  

National Technical Information Service (NTIS)

This document describes a VLSI design representation developed at USC as part of the USC Expert Synthesis System project. The data structure is implementation-independent and can be regarded as a general hardware design representation schema. It is charac...

D. W. Knapp A. C. Parker

1983-01-01

141

Statistical Process Control System for VLSI Fabrication.  

National Technical Information Service (NTIS)

The CMU-CAM system for statistical process control of VLSI (very large scale integration) manufacturing is described. It is a software system which can perform statistical quality control and feed-forward control rescheduling on line, and process diagnosi...

A. J. Strojwas

1989-01-01

142

Wafer LMC accuracy improvement by adding mask model  

NASA Astrophysics Data System (ADS)

Mask effect will be more sensitive for wafer printing in high-end technology. For advance only using current wafer model can not predict real wafer behavior accurately because it do not concern real mask performance (CD error, corner rounding..). Generally, we use wafer model to check whether our OPC results can satisfy our requirements (CD target). Through simulation on post-OPC patterns by using wafer model, we can check whether these post-OPC patterns can meet our target. Hence, accuracy model can help us to predict real wafer printing results and avoid OPC verification error. To Improve simulation verification accuracy at wafer level and decrease false alarm. We must consider mask effect like corner rounding and line-end shortening...etc in high-end mask. UMC (United Microelectronics Corporation) has cooperated with Brion and DNP to evaluate whether the wafer LMC (Lithography Manufacturability Check) (Brion hot spots prediction by simulation contour) accuracy can be improved by adding mask model into LMC verification procedure. We combine mask model (DNP provide 45nm node Poly mask model) and wafer model (UMC provide 45nm node Poly wafer model) then build up a new model that called M-FEM (Mask Focus Energy Matrix model) (Brion fitting M-FEM model). We compare the hotspots prediction between M-FEM model and baseline wafer model by LMC verification. Some different hotspots between two models were found. We evaluate whether the hotspots of M-FEM is more close to wafer printing results.

Lo, Wei Cyuan; Cheng, Yung Feng; Chen, Ming Jui; Haung, Peter; Chang, Stephen; Tsujimoto, Eiji

2010-03-01

143

Designing of Low-Power VLSI Circuits using Non-Clocked Logic Style  

NASA Astrophysics Data System (ADS)

Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the vlsi circuits with the performance upto the acceptable level. The dominant term in a well designed vlsi circuit is the switching power and low-power design thus becomes the task of minimizing this switching power. So, to design a low-power vlsi circuit, it is preferable to use Nonclocked logic styles as they have less switching power. In this work various Non-clocked logic styles are compared by performing transistor level simulations for half adder circuit using TSMC 0.18 µm Technology and Eldo simulator of Mentor graphics.

Sharma, Vishal; Srivastava, Jitendra Kaushal

2012-08-01

144

Convolving optically addressed VLSI liquid crystal SLM  

NASA Astrophysics Data System (ADS)

We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

Jared, David A.; Stirk, Charles W.

1994-03-01

145

VLSI processor for high-performance arithmetic computations  

NASA Astrophysics Data System (ADS)

A high performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform one or more of these operations. The throughput rate for each operation is the same and is wordlength independent. This is achieved using redundant arithmetic. With current CMOS technology, throughput rates in excess of 80 million operations per second are expected.

McQuillan, S. E.; McCanny, J. V.

1991-12-01

146

Forming electrical interconnections through semiconductor wafers  

NASA Technical Reports Server (NTRS)

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Anthony, T. R.

1981-01-01

147

The VLSI design of error-trellis syndrome decoding for convolutional codes  

NASA Technical Reports Server (NTRS)

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

1985-01-01

148

The VLSI design of an error-trellis syndrome decoder for certain convolutional codes  

NASA Technical Reports Server (NTRS)

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

1986-01-01

149

A study on fine pitch Au and Cu WB integrity vs. Ni thickness of Ni\\/Pd\\/Au bond pad on C90 low k wafer technology for high temperature automotive  

Microsoft Academic Search

For high temperature automotive application, IC products are required to pass stringent high temperature storage stress test (e.g. 5000hrs at 150 deg C), hence requires reliable wire bonds. Such requirement is especially challenging with fine pitch Au & Cu wire bond (e.g. bond pad pitch >; 70um and bonded ball diameter <; 58um), more-so on low k wafer technology with

Eu Poh Leng; Poh Zi Song; Au Yin Kheng; C. C. Yong; Anh Tran Tu; J. Arthur; H. Downey; V. Mathew; Chee Yit Yin

2010-01-01

150

High temperature automotive application: A study on fine pitch Au and Cu WB integrity vs. Ni thickness of Ni\\/Pd\\/Au bond pad on C90 low k wafer technology  

Microsoft Academic Search

For high temperature automotive application, IC products are required to pass stringent high temperature storage stress test (e.g. 5000hrs at 150 deg C), hence requires reliable wire bonds. Such requirement is especially challenging with fine pitch Au & Cu wire bond (e.g. bond pad pitch <; 70um and bonded ball diameter <; 58um), more-so on low k wafer technology with

Eu Poh Leng; Poh Zi Song; Au Yin Kheng; C. C. Yong; Tran Tu Anh; J. Arthur; H. Downey; V. Mathew; Chee Yit Yin

2010-01-01

151

Wafer characteristics via reflectometry  

DOEpatents

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

152

A database management system for a VLSI design system  

Microsoft Academic Search

A special purpose database management system for VLSI design environment is presented. Besides supporting design data management and tools integration, the system provides lots of facilities for supporting fast development of efficient and powerful VLSI CAD tools. This system could simplify the task and reduce efforts of implementing an integrated VLSI design system.

Gwo-Dong Chen; Tai-Ming Parng

1988-01-01

153

Reciprocating Saw for Silicon Wafers  

NASA Technical Reports Server (NTRS)

Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

Morrison, A. D.; Collins, E. R., Jr.

1985-01-01

154

Parallel architectures for optoelectronic VLSI processing  

NASA Astrophysics Data System (ADS)

Limited bandwidth because of too few and too slow external pins is one of the major problems in current VLSI systems. Increasing clock rates and the growing transistor density in future microprocessor will enlarge the imbalance between satisfying computing power and insufficient communication performance. Optoelectronic VLSI (OE-VLSI) circuits using highly dense 3D optical interconnections offer the potential to overcome these problems. To lead OE-VLSI processing to success it is necessary to point out a diversity of architectures that profit extremely from a 2D optical input/output interface. Such architectures have to be developed especially for an optoelectronic solution. We demonstrate this for various architectures like binary neural associative memories and fine-grain 3D processor cores for integer and digital signal processing. We specify the electronic circuits and the optical interconnection schemes. We found out that an optoelectronic approach for the associative memory offers two orders of magnitude more performance than all-electronic solutions. The stacked 3D integer processor offers a performance increase of about 10 to 50 over current RISC processors. For the realization of the OE-VLSI circuits we developed a CMOS-SEED chip and a smart detector test chip consisting of CMOS circuitry monolithically integrated with a silicon based array of photo diodes.

Fey, Dietmar; Grimm, Guido; Erhard, Werner

1999-04-01

155

Improvement in WL-CSP reliability by wafer thinning  

Microsoft Academic Search

WL-CSP is a low profile, true chip sue package that is entirely built on a wafer using front-end and back end processing. The wafers can be batch-processed in a fab, which reduces the number of materials and packaging steps, reduces inventory, and allows for wafer level burn in and test. This technology is driven by cost, sue, and ease of

Li Wetz; Jeny White; Beth Keser

2003-01-01

156

Wafer level reliability testing: An idea whose time has come  

NASA Technical Reports Server (NTRS)

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Trapp, O. D.

1987-01-01

157

CMOS wafer bonding for back-side illuminated image sensors fabrication  

Microsoft Academic Search

Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area. The process flows of the two main competing wafer bonding technologies used for this manufacturing

V. Dragoi; A. Filbert; S. Zhu; G. Mittendorfer

2010-01-01

158

MIL-STD-1553 VLSI components  

NASA Astrophysics Data System (ADS)

The performance, physical and electrical characteristics of novel VLSI components which will support all MIL-STD-1553 terminals are described. A transceiver, protocol, and computer interface set of chips supports remote terminal unit, bus controller, and bus monitor modes of operation. A discussion of these VLSI components is given, and their special features are explored. These features include size and packaging options, radiation hardness, power, and reliability considerations. The special capabilities of these devices are highlighted, along with programming options that facilitate a broad array of applications.

Friedman, Steven N.

159

Ion implantation technology and ion sources.  

PubMed

Ion implantation (I/I) technology has been developed with a great economic success of industries of VLSI (Very Large-Scale Integrated circuit) devices. Due to its large flexibility and good controllability, the I/I technology has been assuming various challenging requirements of VLSI evolutions, especially in advanced evolutional characteristics of CMOSFET. Here, reviewing the demands of VLSI manufacturing to the I/I technology, required characteristics of ion implanters, and their ion sources are discussed. PMID:24593652

Sugitani, Michiro

2014-02-01

160

RF W-band wafer-to-wafer transition  

Microsoft Academic Search

Multiwafer silicon designs must provide an avenue for electrical signals to flow from wafer to wafer. For this purpose, a two-layer electrical bond is proposed to provide electrical connection between two coplanar waveguides printed on the adjacent faces of two vertically stacked silicon wafers. In addition to serving as a versatile low-temperature thermocompression wafer bond, loss of approximately 0.1 dB

Katherine J. Herrick; Linda P. B. Katehi

2001-01-01

161

Upper and lower bounds on switching energy in VLSI  

NASA Astrophysics Data System (ADS)

A technology independent framework is established for measuring the 'switching energy' consumed by Very Large Scale Integrated (VLSI) circuits. Techniques are developed for analyzing functional energy consumption, and for designing energy efficient VLSI circuits. A wire (or gate) in a circuit uses switching energy when it changes state from 1 to 0 or vice versa. The 'Uniswitch Model' (USM) of energy consumption, which measures the differences between pairs of states of an embedded circuit, is developed. The following worst case lower bounds are obtained in USM. Monotone circuits require switching energy proportional to the circuit's area. A class of n-input, boolean valued functions, including addition and multiplication, uses Omega (n log(2)n) switching energy, when computed by a shallow depth circuit. A special case of the parity function is shown to require switching energy proportional to the area. Upper bounds in USM are derived. Novel circuits and layouts are obtained for n-bit OR and compare functions that have shallow depth and use only linear energy, in the worst case. A shallow depth n-bit addition circuit is laid out in a manner that uses linear energy, on the average. This is a log factor better than the worst case lower bound for addition.

Kissin, Gloria

1990-09-01

162

VLSI design in the 3rd dimension  

Microsoft Academic Search

Recently, the need for increased circuit complexity has outpaced our ability to perform efficient routing and placement, while still maintaining small die sizes. Part of this problem can be attributed to the limits imposed by designing in two dimensions. Three-dimensional VLSI circuits, obtainable through using a transferred thin-film process, can provide a path for realizing complete structures, while reducing route

Stephen Strickland; Erhan Ergin; David R. Kaeli; Paul M. Zavracky

1998-01-01

163

Reconfigurable architectures for VLSI processing arrays  

Microsoft Academic Search

The paper presents the problem of fault tolerance in VLSI array structures: its aim is to discuss architectures capable of surviving a number of random faults while keeping costs (in terms of added silicon area and of increased processing time) as low as possible. Two different approaches are presented, both based upon introduction of simple patterns of faults and by

M. Sami; R. Stefanelli

1986-01-01

164

Delay and power optimization in VLSI circuits  

Microsoft Academic Search

The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macromodels are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.

Lance A. Glasser; Lennox P. J. Hoyte

1984-01-01

165

The VLSI package - An analytical review  

NASA Astrophysics Data System (ADS)

Current very large-scale integrated (VLSI) chip packaging options, with a special emphasis on the various size and chip I/O complexity issues are reviewed, quantitatively. The two basic packaging options reviewed are the hermetic chip carrier (HCC) and the pin grid array (PGA). The impact that chip input/output (I/O) has on the 'size' growth of packages as single chip enclosures, as well as that of the chips themselves, is considered. It is shown that the HCC is inherently more area-efficient for almost any high I/O configured VLSI chip, especially if the chip size growth that must be anticipated is considered as I/O's of 400 are entertained. After quantitative considerations of discrete packaging options are exhausted, it is finally recommended that a multichip VLSI module should be seriously considered as a more efficient packaging concept. This, however, requires some innovation directed toward the development of adequate prepackaged chip testing. This could be facilitated through the incorporation of physically testable I/O ports on the 'passivated' VLSI chip; e.g., flip chip 'bumps', tape-automated bonding (TAB), or beam lead chip interconnects.

Lewis, E. T.

1984-06-01

166

Modeling concepts for VLSI CAD objects  

Microsoft Academic Search

VLSI CAD applications deal with design objects that have an interface description and an implementation description. Versions of design objects have a common interface but differ in their implementations. A molecular object is a modeling construct which enables a database entity to be represented by two sets of heterogeneous records, one set describes the object's interface and the other describes

Don S. Batory; Won Kim

1985-01-01

167

Scanning holographic scatterometer for wafer surface inspection  

NASA Astrophysics Data System (ADS)

The semiconductor industry requires ever smaller semiconductor structures with faster response times and more function per unit area of each chip. In addition, the industry is changing from 200 mm to 300 mm diameter wafers with fewer defects and rapid detection at all processing stages. To meet these needs, defect data must be processed in near-real-time to expedite correction of processing problems at the earliest possible stage. Under a Small Business Innovation Research (SBIR) program, sponsored by the Air Force Manufacturing Technology Division at Wright Laboratory, Dayton, Ohio, Sentec Corporation has developed a revolutionary technology for contaminant particle detection on unpatterned semiconductor wafers. A key to the Sentec technology is detection, not of the intensity of backscattered energy from particles or defects, but of the amplitude of the electro-magneitc field of this backscattered energy. This new technology will allow the detection of particles that are significantly smaller than those which can be reliably located using current scatterometers. The technical concepts for a stand-alone particle detection tool have been created. It uses a continuous scanning mechanism to perform high-speed examinations of target wafers. This tool, also, has the capability of quantifying the microroughness or background haze of a subject wafer and presenting that information separate from the contamination particle data. During the course of this project, three patent applications were filed.

Klooster, Alex; Marks, James; Hanson, Kael; Sawatari, Takeo

2004-05-01

168

Wafer-level package interconnect options  

Microsoft Academic Search

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare

Jayaprakash Balachandran; Steven Brebels; Geert Carchon; Maarten Kuijk; Walter De Raedt; Bart K. J. C. Nauwelaers; Eric Beyne

2006-01-01

169

Etching Of Semiconductor Wafer Edges  

DOEpatents

A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

2003-12-09

170

30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology  

NASA Technical Reports Server (NTRS)

An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

1986-01-01

171

Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter  

NASA Technical Reports Server (NTRS)

The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

Chen, C. P.; Leipold, M. H.

1984-01-01

172

Wafer plane inspection for advanced reticle defects  

NASA Astrophysics Data System (ADS)

Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

2008-06-01

173

VLSI impact on RAMS strategies in avionics design  

NASA Astrophysics Data System (ADS)

Although VLSI will improve the reliability of electronics-dominated avionics, off-chip interconnections will still limit reliability. The reliability of a VLSI chip is expected to be nearly 20 times that of LSI chips. The control over the system MTBF by the MTBF of the interconnections can be lessened by increasing the complexity of the VLSI devices, thus decreasing the number of interconnections on a board.

Webster, L. R.; Mader, J. M.

174

Proceedings of the Low-Cost Solar Array Wafering Workshop  

NASA Technical Reports Server (NTRS)

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

Morrison, A. D.

1982-01-01

175

Interconnect-limited VLSI architecture  

Microsoft Academic Search

As semiconductor technology scales, wires are becoming the dominant factor in determining system performance and power dissipation. By 2008, it is expected that chip traversal will require 16 clocks. Modern superscalar architectures that depend on global register files, global bypass structures, and global instruction issue logic are poorly matched to future semiconductor technology. This technology demands architectures that exploit locality

William J. Dally

1999-01-01

176

?-Device fabrication and packaging below 300°C utilizing plasma-assisted wafer-to-wafer bonding  

NASA Astrophysics Data System (ADS)

Wafer-to-wafer bonding techniques, such as anodic bonding or high temperature silicon direct fusion bonding, have been in development since the late 1960's and became key technologies for MEMS manufacturing. Plasma assisted wafer bonding is an emerging method offering several advantages over traditional bonding techniques. This technology was first discovered and patented in the early 1990's and has been used in SOI production for the past five years. Now plasma activation benefits are being used to enable 3D integration and advanced MEMS device fabrication and packaging. The main advantage of plasma assisted bonding is that high strength direct bonds between substrates, like Si, glass or polymers, can be achieved already below 300°C.

Kirchberger, Herwig; Pelzer, Rainer; Farrens, Sharon

2006-12-01

177

1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics  

SciTech Connect

The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

Lorenz, Adam [1366 Technologies] [1366 Technologies

2013-08-30

178

Cascaded VLSI Chips Help Neural Network To Learn  

NASA Technical Reports Server (NTRS)

Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

1993-01-01

179

A 16-channel analog VLSI processor for bionic ears and speech-recognition front ends  

Microsoft Academic Search

We describe a 470 ?W 16-channel analog VLSI processor for bionic ears (cochlear implants) and portable speech-recognition front ends. The power consumption of the processor is kept at low levels through the use of subthreshold CMOS technology. Each channel is composed of a programmable bandpass filter, an envelope detector, and a logarithmic dual-slope analog-to-digital converter that currently operate over 51

Michael W. Baker; T. K.-T. Lu; C. D. Salthouse; J.-J. Sit; S. Zhak; R. Sarpeshkar

2003-01-01

180

Low-power system-level design of VLSI packet switching fabrics  

Microsoft Academic Search

System-level design of packet switching fabrics focuses on performance metrics and rarely considers the physical requirements that are usually addressed later at the circuit-level. However, low-power dissipation has become a major requirement in such fabrics dictated by the requirements of emerging applications and by the recent advances in fabrication and VLSI technologies. This paper proposes a framework for system-level design

Amr G. Wassal; M. Anwar Hasan

2001-01-01

181

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI  

Microsoft Academic Search

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (Vt) drops

Fariborz Assaderaghi; Dennis Sinitsky; Stephen A. Parke; Jeffrey Bokor; Ping K. Ko; Chenming Hu

1997-01-01

182

VLSI recursive motion estimator chip set  

Microsoft Academic Search

The design of a VLSI chip set implementing a recursive motion estimator (ME) for video applications is described. This chip set can be used to compress the information of a full-motion video source for applications where low-bit-rate or very-low-bit-rate coding is required. The ME block provides for a set of motion vectors describing the displacement of two consecutive frames. The

S. Brofferio; M. Monti; V. Rampa; M. Taliercio

1990-01-01

183

Decoding the Golden Code: A VLSI Design  

Microsoft Academic Search

The recently proposed Golden code is an optimal space-time block code for 2 times 2 multiple-input-multiple-output (MIMO) systems. The aim of this work is the design of a VLSI decoder for a MIMO system coded with the Golden code. The architecture is based on a rearrangement of the sphere decoding algorithm that achieves maximum-likelihood (ML) decoding performance. Compared to other

Barbara Cerato; Guido Masera; Emanuele Viterbo

2009-01-01

184

Leak detection utilizing analog binaural (VLSI) techniques  

NASA Technical Reports Server (NTRS)

A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

Hartley, Frank T. (inventor)

1995-01-01

185

VLSI Microsystem for Rapid Bioinformatic Pattern Recognition  

NASA Technical Reports Server (NTRS)

A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

Fang, Wai-Chi; Lue, Jaw-Chyng

2009-01-01

186

Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications  

Microsoft Academic Search

Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and provides the highest density for 3D interconnects to date. One approach for IC stacking pursued by imec is the integration of Through Silicon Vias with extreme wafer thinning and backside processing on full CMOS wafers. This

Anne Jourdain; Thibault Buisson; Alain Phommahaxay; Augusto Redolfi; Sarasvathi Thangaraju; Youssef Travaly; Eric Beyne; Bart Swinnen

2011-01-01

187

A VLSI implementation of CAVLC for H.264/AVC  

NASA Astrophysics Data System (ADS)

H.264 is the newest video coding standard and is currently one of the hot subjects of video processing technologies. Coding quality and compression ratio have been greatly improved in the new standard compared with the previous standards. The context-based adaptive technology is introduced into the new standard, which can be said to be a technology renovation of the video coding. The main entropy coding technologies of H.264 include VLC (Variable- Length Coding) and CABAC (Context-based Adaptive Binary Arithmetic Coding). CAVLC is VLC and adopts the context-based adaptive technology, therefore the coding efficiency is greatly improved. Currently, the design of the CAVLC encoder is mainly in software method, but with the development of real-time video processing technology, it is difficult for software to meet the demands. As a result, the hardware method in designing of CAVLC coder becomes a good choice. In the paper a CAVLC entropy encoder architecture based VLSI is proposed and implemented on an Altera FPGA device. As the results of simulation and synthesis, it can process 4×4 or 2×2 blocks per 16 clock periods with pipelined architecture and can achieve the real-time processing requirement of 30 frames per second for a 720×480 video at 100 MHz operation frequency.

Luo, Li; Li, Zheying; Yu, Qinmei

2009-10-01

188

Wafer thinning for high-density, through-wafer interconnects  

NASA Astrophysics Data System (ADS)

Thinning of micromachined wafers containing trenches and cavities to realize through-chip interconnects is presented. Successful thinning of wafers by lapping and polishing until the cavities previously etched by deep reactive ion etching are reached is demonstrated. The possible causes of damage to the etched structures are investigated. The trapping of particles in the cavities and suitable cleaning procedures to address this issue are studied. The results achieved so far allow further processing of the thinned wafers to form through wafer interconnections by copper electroplating. Further improvement of the quality of thinned surfaces can be achieved by alternative cleaning procedures.

Wang, Lianwei; Visser, Cassan C. G.; de Boer, Charles R.; Laros, M.; van der Vlist, W.; Groeneweg, J.; Craciun, G.; Sarro, Pasqualina M.

2003-01-01

189

Wafer-scale micro-optics fabrication  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Voelkel, Reinhard

2012-07-01

190

Parallel optimization algorithms and their implementation in VLSI design  

NASA Technical Reports Server (NTRS)

Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

Lee, G.; Feeley, J. J.

1991-01-01

191

Modeling of interconnect capacitance, delay, and crosstalk in VLSI  

Microsoft Academic Search

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form

Shyh-Chyi Wong; Gwo-Yann Lee; Dye-Jyun Ma

2000-01-01

192

Image Compression on a VLSI Neural-Based Vector Quantizer.  

ERIC Educational Resources Information Center

Describes a modified frequency-sensitive self-organization (FSO) algorithm for image data compression and the associated VLSI architecture. Topics discussed include vector quantization; VLSI neural processor architecture; detailed circuit implementation; and a neural network vector quantization prototype chip. Examples of images using the FSO…

Chen, Oscal T.-C.; And Others

1992-01-01

193

A VLSI Design Framework with Freeware CAD Tools  

Microsoft Academic Search

This work presents a PC-based freeware CAD environment to design and tape out VLSI microelectronic circuits, starting from schematic capture all the way to a foundry compatible GDS II database. These free tools will help more Malaysian universities to set up low cost VLSI CAD laboratories and tape out circuits using Silterra's University Program. This will help grow local IC

Y. K. Teh; F. Mohd-Yasin; M. B. I. Reaz; A. Kordesch

2006-01-01

194

Augmented reality for wafer prober  

NASA Astrophysics Data System (ADS)

The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

Gilgenkrantz, Pascal

2011-02-01

195

Optima XE Single Wafer High Energy Ion Implanter  

SciTech Connect

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny [Axcelis Technologies, Inc. 108 Cherry Hill Drive, Beverly, MA 01915 (United States)

2008-11-03

196

On-wafer level packaging of RF MEMS devices for Ka-band applications  

Microsoft Academic Search

In this paper, on-wafer level packaging technology for RF MEMS is described, and then a novel packaging design for RF MEMS devices with different fabrication technology at millimeter-wave band is presented. The discussed RF MEMS devices on naked wafer includes a MEMS filter and a distributed MEMS transmission line (DMTL) phase shifter, which are fabricated using LIGA and micromachined technology,

Qun Wu; Bo-Shi Jin; Xun-Jun He; Kai Tang; Fang Zhang; Jong-Chul Lee

2006-01-01

197

Accelerating litho technology development for advanced design node flash memory FEOL by next-generation wafer inspection and SEM review platforms  

NASA Astrophysics Data System (ADS)

Development of an advanced design node for NAND flash memory devices in semiconductor manufacturing requires accelerated identification and characterization of yield-limiting defect types at critical front-end of line (FEOL) process steps. This enables a shorter development cycle time and a faster production ramp to meet market demand. This paper presents a methodology for detecting defects that have a substantial yield impact on a FEOL after-develop inspection (ADI) layer using an advanced broadband optical wafer defect inspector and a scanning electron microscope (SEM) review tool. In addition, this paper presents experimental data that demonstrates defect migration from an ADI layer to an after-clean inspection (ACI) layer, and provides clear differentiation between yield-impacting critical defects and noncritical defects on the layers. The goal of these studies is to determine the feasibility of implementing an inspection point at ADI. The advantage of capturing yield-limiting defects on an ADI layer is that wafers can be reworked when an excursion occurs, an option that is not always possible for ACI layers. Our investigation is divided into two parts: (1) Inspection of an ADI layer with high sensitivity to find an accurate representation of the defect population and to gain understanding on the propagation of defects from the ADI layer to the ACI layer; and, (2) Inspection of an ACI layer to develop an understanding of unique defects generated by the ACI process step. Overall, this paper discusses the advantages of baselining defectivity at ADI process levels for accelerated development of advanced design node memory devices.

Lee, Byoung Ho; Ahn, Jeongho; Ihm, Dongchul; Chin, Soobok; Lee, Dong-Ryul; Choi, Seongchae; Lee, Junbum; Kang, Ho-Kyu; Sivaraman, Gangadharan; Yamamoto, Tetsuya; Lakhawat, Rahul; Sanapala, Ravikumar; Lee, Chang Ho; Lobo, Arun

2012-03-01

198

Encapsulation challenges for wafer level packaging  

Microsoft Academic Search

The interest of user for WLP has been raised because of benefits such as reduced package thickness, fan-out capability, high I\\/O, substrate-less process, integration of passives into structure, good thermal and electrical performance. The objective of this paper is to delineate technical challenges and issues that potential adopter of wafer level molding will face, technological solution availability and the broad

E. K. Th; J. Y. Hao; J. P. Ding; Q. F. Li; W. L. Chan; S. C. Ho; H. M. Huang; Y. J. Jiang

2009-01-01

199

Partitioning and mapping B-spline surface fitting algorithm into fixed-size VLSI arrays  

NASA Astrophysics Data System (ADS)

A method of solving the uniform bicubic B-spline surface fitting algorithm is proposed which introduces parallelism in a way that may be effectively exploited by a suitable parallel architecture. This method is based on the observation that a tensor product spline surface fitting problem can be split into two spline curve fitting problems and each of these problems can be realized by a macropipeline of fixed size VLSI arrays. In fact, the heart of curve fitting problem consists of a block tridiagonal linear system. Based on the state-of-art electronic and packaging technologies, the size of VLSI arithmetic devices is limited due to the bounded chip area and I/O packaging constraints. A modular approach to achieve VLSI matrix arithmetic solution for the block tridiagonal linear system is amenable from the viewpoints of feasibility and applicability. A matrix partitioning approach is presented to overcome those technological constraints imposed by the number of I/O pins. A block tridiagonal linear system of size mn is then divided into m simple tridiagonal systems of size n and n simple tridiagonal systems of size m by the Dc Boor partitioning theorem. Each of the simple tridiagonal linear systems could be partitioned and mappied into a series of two fixed size primitive VLSI matrix arithmetic arrays including L-U decomposer and triangular system solver. The L-U decomposer and triangular system solver could be realized by a hex-connected processor array and an inverse perfect shuffle machine respectively. It would be shown that a B-spline surface fitting problem for a grid of mn points can be solved by m hex-connected processor arrays having 4 processors, m inverse perfect shuffle machines having n processors and n inverse perfect shuffle machines having m processors in (3(m+n)+2({logzn1 +flog2n)+4J units of time.

Chang, Po-Rong; Lee, Share-Young

1990-08-01

200

A silicon wafer packaging solution for HB-LEDs  

Microsoft Academic Search

In this paper we present HyLED, a silicon wafer packaging solution for high-brightness LEDs. The associated technology is batch micro-machining\\/metallisation processing of silicon wafers allowing significant reduction of the final device size. The presented package is multi-functional where the micro-machined cavity acts as reflector, thermal conductor and reservoir for the silicone\\/colour conversion substance. The base material, silicon, has excellent mechanical

Tom Murphy; Steen Weichel; Steven Isaacs; Jochen Kuhmann

2007-01-01

201

Gettering Silicon Wafers with Phosphorus  

NASA Technical Reports Server (NTRS)

Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

Daiello, R. V.

1983-01-01

202

High throughput wafer defect monitor for integrated metrology applications in photolithography  

NASA Astrophysics Data System (ADS)

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

2008-04-01

203

Reconfigurable architectures for VLSI processing arrays  

SciTech Connect

The paper presents the problem of fault tolerance in VLSI array structures: its aim is to discuss architectures capable of surviving a number of random faults while keeping costs (in terms of added silicon area and of increased processing time) as low as possible. Two different approaches are presented, both based upon introduction of simple patterns of faults and by global reconfiguration techniques (rather than one-to-one substitution of faulty elements by spare ones). Various solutions are compared, and relative performances are discussed in order to determine criteria for selecting the one most suitable to particular applications.

Sami, M.; Stefanelli, R.

1986-05-01

204

ORGANIZATION AND VLSI IMPLEMENTATION OF MIPS  

Microsoft Academic Search

Abstract MlPS is an 32-bit, high pcrformancc processor architecture implcmcntcd as an nMOS VLSI Gp. I’hc processor uses a low 1~~1, strcamlincd instruction set coupled \\\\vit!l a fast pipeline to achicvcan instruction rateof two million instructions persecond. Close interaction bctwccn,the processor dcsiglland,car-npilzrsfor the machine,yields cfficicnt execution of,programs,on the chip. Simplifyin g the instruction,set and,the rcquircmcnts placed on the hardware by

Steven A. Przybylski; Thomas R. Gross; John L. Hennessy; Norman Jouppi; Christopher Rowen

205

High performance VLSI telemetry data systems  

NASA Astrophysics Data System (ADS)

NASA-Goddard has over the last five years developed generic ground telemetry data system elements addressing the budget limitations-driven demand for greater modularity, flexibility, and interchangeability. These design solutions, which may be characterized as a 'functional components approach', encompasses both hardware and software components; the former involve telemetry application-specific ICs for data rate requirements of up to 300 Mbps, while the latter extend to embedded local software intelligence. Attention is given to the consequences of the functional components approach for VLSI components.

Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

1990-09-01

206

VLSI Reed-Solomon Encoder With Interleaver  

NASA Technical Reports Server (NTRS)

Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).

Hsu, In-Shek; Deutsch, L. J.; Truong, Trieu-Kie; Reed, I. S.

1990-01-01

207

VLED for Si wafer-level packaging  

NASA Astrophysics Data System (ADS)

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-02-01

208

Development of a monolithic, multi-MEMS microsystem on a chip demonstrating iMEMS{trademark} VLSI technology. R and D status report number 10, January 1--March 31, 1996  

SciTech Connect

This quarter saw the first silicon from the iMEMS{reg_sign} test chip, with complete circuits and beam structures. The wafers looked fine cosmetically and the circuits functioned as designed, but the beams suffered an anomaly that the authors have never seen before. Diagnostic work is under way to sort out the root cause, and other wafers are coming out this quarter to see if it was a one-time anomaly. Work on the process-development front has slowed because of the construction of a dedicated fabrication line for the last-generation process. With the current robust market place for ADI`s business, the existing fabrication line has been operating at 100% capacity. On the device front, great progress has been made by both Berkeley and ADI in the area of gyroscopes. Measurements of close to a degree per second or better have been made for gyros of all three axes and of both single- (linear) and double- (rotary) axis devices. In addition, ADI has designed a gyro that can be packaged in air that very well might meet some of the low-precision needs. Accelerometers of several new formats have been designed and several have been implemented in silicon. First samples of the ADXL 181 designed especially for the fuzing, safe and arming application have been assembled and are in characterization by ADI and others. In addition, 2-axis, Z-axis and digital output designs have been demonstrated. A 3-axis micro-watt accelerometer has been designed and is in fabrication. A 2-axis design for tilt applications is also nearing silicon realization. This portfolio of linear accelerometers, and even angular versions of the same provide, an arsenal of capability for specialized needs as they arise in both commercial and military applications.

NONE

1996-04-17

209

Prediction of thermo-mechanical integrity of wafer backend processes  

Microsoft Academic Search

More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function\\/product integration will increase the importance of thermomechanical reliability, as confirmed by the ITRS (International technology roadmap for semiconductors; [1]). Since most of the

V. Gonda; J. M. J. Den Toonder; J. Beijer; G. Q. Zhang; W. D. van Driel; R. J. O. M. Hoofman; L. J. Ernst

2004-01-01

210

Edge Sorter Implemented by Hardware for VLSI Verification.  

National Technical Information Service (NTIS)

This paper investigates a new architecture to accelerate very large scale integration (VLSI) mask checking and presents an edge sorting operation used in the edge-based scanline algorithm for hardware implementation. The logic is deliberately designed wit...

F. Yun S. Zhang K. Zhang

1994-01-01

211

Notation for Describing Multiple Views of VLSI Circuits.  

National Technical Information Service (NTIS)

A declarative hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the nation in a way that emphasizes common elements. ...

J. L. Baer L. McMurchie L. Snyder M. C. Liem R. Nottrott

1988-01-01

212

VLSI (Very Large Scale Integration) Floating Point Chip Design Study.  

National Technical Information Service (NTIS)

This report describes techniques for very large scale integration (VLSI) implementation of arithmetic algorithms. The report describes an algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and...

J. G. Nash

1985-01-01

213

Wafer Replacement Cluster Tool (Presentation);  

SciTech Connect

This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

Branz, H. M.

2008-04-01

214

Dynamic WDM equalizer using opto-VLSI beam processing  

Microsoft Academic Search

We demonstrate an efficient wavelength-division-multiplexed (WDM) equalizer structure that uses a reconfigurable opto-very large scale integrated processor to steer\\/reshape many optical beams simultaneously, thus, achieving channel-by-channel equalization. The opto-VLSI processor consists of an array of liquid crystal (LC) cells independently addressed by a VLSI circuit to generate a reconfigurable reflective digital hologram. More than 30-dB dynamic range is demonstrated with

Selam Ahderom; Mehrdad Raisi; Kamal E. Alameh; Kamran Eshraghian

2003-01-01

215

Opto-VLSI-based tunable single-mode fiber laser  

Microsoft Academic Search

A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05

Feng Xiao; Kamal Alameh; Tongtak Lee

2009-01-01

216

Wavelength-encoded OCDMA system using opto-VLSI processors  

Microsoft Academic Search

We propose and experimentally demonstrate a 2.5 Gbits\\/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and

Muhsen Aljada; Kamal Alameh

2007-01-01

217

A Regular VLSI Array for an Irregular Algorithm  

Microsoft Academic Search

We present an application speciflc, asynchronous VLSI pro- cessor array for the dynamic programming algorithm for the 0\\/1 knap- sack problem. The array is derived systematically, using correctness- preservingtransformations,intwosteps:thestandard(dense)algorithm is flrst transformed into an irregular (sparse) functional program which has better e-ciency. This program is then implemented as a modular VLSI architecture with nearest neighbor connections. Proving bounds onbufiersizesyieldsalineararrayofidenticalasynchronousprocessors, each

Florent De Dinechin; Doran K. Wilde; Sanjay V. Rajopadhye; Rumen Andonov

1996-01-01

218

A High Speed VLSI Architecture for Handwriting Recognition  

Microsoft Academic Search

This article presents PAPRICA-3, a VLSI-oriented architecture for real-time processing of images and its implementation on HACRE, a high-speed, cascadable, 32-processors VLSI slice. The architecture is based on an array of programmable processing elements with the instruction set tailored to image processing, mathematical morphology, and neural networks emulation. Dedicated hardware features allow simultaneous image acquisition, processing, neural network emulation, and

Francesco Gregoretti; Roberto Passerone; Leonardo Maria Reyneri; Claudio Sansoč

2001-01-01

219

Image sharpness and beam focus VLSI sensors for adaptive optics  

Microsoft Academic Search

High-resolution wavefront control for adaptive optics requires accurate sensing of a measure of optical quality. We present two analog very-large-scale-integration (VLSI) image-plane sensors that supply real-time metrics of image and beam quality, for applications in imaging and line-of-sight laser communication. The image metric VLSI sensor quantifies sharpness of the received image in terms of average rectified spatial gradients. The beam

Michael Cohen; Gert Cauwenberghs; Mikhail A. Vorontsov

2002-01-01

220

IGBT scaling principle toward CMOS compatible wafer processes  

NASA Astrophysics Data System (ADS)

A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

Tanaka, Masahiro; Omura, Ichiro

2013-02-01

221

Design and Reliability in Wafer Level Packaging  

Microsoft Academic Search

Wafer Level Packaging (WLP) has the highest potential for future single chip packages because the WLP is intrinsically a chip size package. The package is completed directly on the wafer then singulated by dicing for the assembly. All packaging and testing operations of the dice are replaced by whole wafer fabrication and wafer level testing. Therefore, it becomes more cost-effective

Xuejun Fan; Qiang Han

2008-01-01

222

Spinner For Etching Of Semiconductor Wafers  

NASA Technical Reports Server (NTRS)

Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

Lombardi, Frank

1989-01-01

223

Synthesis algorithm of VLSI multipliers for ASIC  

NASA Technical Reports Server (NTRS)

Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

Chua, O. H.; Eldin, A. G.

1993-01-01

224

VLSI processors for signal detection in SETI.  

PubMed

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features. PMID:11537749

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

225

VLSI processors for signal detection in SETI  

NASA Technical Reports Server (NTRS)

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

226

PLA realizations for VLSI state machines  

NASA Technical Reports Server (NTRS)

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

1990-01-01

227

Implementation of optical interconnections for VLSI  

NASA Technical Reports Server (NTRS)

This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: (1) the holographic optical element (HOE), (2) the laser sources, (3) the detectors and associated circuits forming an optically addressed gate, and (4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 x 20 microns has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity, and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five holograms.

Wu, Wennie H.; Bergman, Larry A.; Johnston, Alan R.; Guest, Clark C.; Esener, Sadik C.

1987-01-01

228

Plasma-assisted InP-to-Si low temperature wafer bonding  

Microsoft Academic Search

The applicability of wafer bonding as a tool to integrate the dissimilar material system InP-to-Si is presented and discussed with recent examples of InP-based optoelectronic devices on Si. From there, the lowering of annealing temperature in wafer bonding by plasma-assisted bonding is the essence of this review paper. Lower annealing temperatures would further launch wafer bonding as a competitive technology

Donato Pasquariello; Klas Hjort

2002-01-01

229

Thermomechanical global response of the EUVL wafer during exposure  

NASA Astrophysics Data System (ADS)

Extreme ultraviolet lithography (EUVL) is one of the leading technologies for Next-Generation Lithography. Continued progress in its development will be facilitated by characterizing all sources of distortion in the chip fabrication process. These include the thermal distortions of the wafer caused by deposited EUVL energy during scanning exposure. Absorbed energy from the beam produces temperature increases and structural displacements in the wafer, which directly contribute to pattern placement errors and image blur. Because of the vacuum conditions of EUVL systems, wafer chucking will be electrostatic, which has a number of advantages over mechanical clamping systems. The goals of this research are to predict the transient temperature increases and corresponding displacements (locally and globally) consistent with the thermomechanical boundary conditions of the wafer. Both thermal and structural finite element models were constructed to numerically simulate wafer exposure. The response of the wafer is relatively sensitive to the interface conditions between the substrate and electrostatic chuck. Thus, parametric studies of the response to changes in the contact conductance and the friction coefficient were performed and are presented in this paper.

Chang, Jaehyuk; Martin, Carl J.; Engelstad, Roxann L.; Lovell, Edward G.

2002-07-01

230

Ultra short pulse laser meeting the requirements for high speed and high quality dicing of low-k wafers  

Microsoft Academic Search

Commercially available sawing technologies don't seem to be capable of meeting the challenging task of wafer dicing process. This paper presents a novel technology and procedure that eliminate the issues related to dicing of low-k wafers. Our tests demonstrate that Corelase's ultra short pulse laser technology, X-LASE, can be used in conjunction with traditional diamond sawing to dice low-k wafers

Jari Sillanpää; Jarno Kangastupa; Arto Salokatve; Harry Asonen

2005-01-01

231

A VLSI architecture of a decoder for trellis coded modulation using constellations designed for the Rayleigh channel  

Microsoft Academic Search

New N-dimensional constellations for the Rayleigh fading channel have been described previously. These constellations provide a diversity of order N and a gain of 10 dB to 14.5 dB at a BER of 10-3 when compared to 16-QAM modulations. The decoding of a 4-dimensional 4096 points constellation seems unrealistic, even with today's VLSI technology. This paper proposes algorithmic simplifications, which

E. Boutillon; J.-C. Belfiore; N. Demassieux

1994-01-01

232

Sub-micron, planarized, Nb-AlO(x)-Nb Josephson process for 125 mm wafers developed in partnership with Si technology  

NASA Astrophysics Data System (ADS)

A new planarized all-refractory technology was demonstrated for low-Tc superconductivity (PARTS). With the exception of the Nb-AlO(x)-Nb trilayer preparation, the processing is done almost exclusively within an advanced Si technology fabrication facility. This approach made it possible to leverage highly off of existing state-of-the-art lithography, metal etching, materials deposition, and planarization capabilities. Using chemical-mechanical polish as the planarization technique Josephson junctions ranging in size from 0.5-100 sq microns were fabricated. Junction quality is excellent with the figure of merit Vm typically exceeding 70 mV. PARTS has yielded fully functional integrated Josephson devices including magnetometers, gradiometers, and soliton oscillators.

Ketchen, M. B.; Pearson, D.; Kleinsasser, A. W.; Hu, C.-K.; Smyth, M.; Logan, J.; Stawiasz, K.; Baran, E.; Jaso, M.; Ross, T.

1991-11-01

233

Wafer characteristics via reflectometry and wafer processing apparatus and method  

DOEpatents

An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

Sopori, Bhushan L. (Denver, CO)

2007-07-03

234

Multi-objective optimization of laser scribing for the isolation process of solar cell wafers using grey relational analysis  

Microsoft Academic Search

A novel method is presented for optimizing laser scribing of solar cell wafers for the isolation process. Multiple performance characteristics are optimized using grey relational analysis (GRA). Laser scribing technology is a useful solution for solar cell isolation processes. Solar energy is available worldwide and useful to everybody. Most solar cell technology is currently based on silicon wafer technology. Two

Chun-Hao Li; Ming-Jong Tsai

2009-01-01

235

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

236

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?  

NASA Astrophysics Data System (ADS)

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Green, Martin A.

2014-03-01

237

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.  

PubMed

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

2014-08-15

238

Wafer Scale Distributed Radio.  

National Technical Information Service (NTIS)

Modem silicon technology offers ultrafast transistors, with fT > 200 GHz in today's 45nm CMOS and fT > 300 GHz in SiGe. While extremely fast, these transistors suffer from several limitations which affect the performance of high dynamic range analog and R...

A. M. Niknejad B. Nikolic E. Alon J. Rabaey

2009-01-01

239

VLSI structures and iterative analysis for large-scale computation  

SciTech Connect

Problems of computation and development of VLSI structures are considered in relation to each other. In particular, two issues are addressed: (a) development of components and algorithms for standard operations, suitable for VLSI implementation; (b) large-scale computation, in this case the iterative solution of large least-square problems in a limited-size VLSI architecture. On standard operations, improved and new adders are presented that can be implemented in VLSI. The adders so designed are shown to be superior when compared to other existing ones. Moreover, an iterative multiplier that uses carry save adders is also presented. On large-scale computation, analysis of iterative techniques for least-squares problems is first addressed. New convergence results are obtained and explicit expressions, for the optimal parameters as well as for their corresponding optimal asymptotic rate of convergence are derived for the family of iterative schemes known as Accelerated Overrelaxation (AOR). Moreover, partitioning of the iterative algorithm and time-space expansion are used so that a parallel implementation of the iterative scheme is obtained, in a way that computation can be performed, in a fixed-size VLSI architecture, independent of the size of the problem.

Papadopoulou, E.P.

1986-01-01

240

High-order wafer alignment in manufacturing  

NASA Astrophysics Data System (ADS)

Requirements for ever tightening overlay control are driving improvements in tool set up and matching procedures, APC processes, and wafer alignment techniques in an attempt to address both systematic and non systematic sources of overlay error. Thermal processes used in semiconductor manufacturing have been shown to have drastic and unpredictable impacts on lithography overlay control. Traditional linear alignment can accommodate symmetric and linearly uniform wafer distortions even if these defects vary in magnitude wafer to wafer. However linear alignment cannot accommodate asymmetric wafer distortions caused by variations in film stresses and rapid thermal processes. Overlay improvement techniques such as Corrections per Exposure can be used to compensate for known systematic errors. However, systematic corrections applied on a lot by lot basis cannot account for variations in wafer to wafer grid distortions caused by semiconductor processing. With High Order Wafer Alignment, the sample size of wafer alignment data is significantly increased and modeled to correct for process induced grid distortions. HOWA grid corrections are calculated and applied for each wafer. Improved wafer to wafer overlay performance was demonstrated. How HOWA corrections propagate level to level in a typical alignment tree as well as the interaction of mixing and matching high order wafer alignment with traditional linear alignment used on less overlay critical levels. This evaluation included the evaluating the impact of overlay offsets added by systematic tool matching corrections, product specific corrections per exposure and 10 term APC process control.

Pike, Michael; Felix, Nelson; Menon, Vinayan; Ausschnitt, Christopher; Wiltshire, Timothy; Meyers, Sheldon; Kim, Won; Minghetti, Blandine

2012-03-01

241

450mm wafer patterning with jet and flash imprint lithography  

NASA Astrophysics Data System (ADS)

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

242

Thermomechanical Design of Resilient Contact Systems for Wafer Level Packaging  

Microsoft Academic Search

Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased

Rainer Dudek; Hans Walter; Ralf Doering; Bernd Michel; Thorsten Meyer; Joerg Zapf; Harry Hedler

2006-01-01

243

Platinum-coated probes sliding at up to 100 mm s-1 against coated silicon wafers for AFM probe-based recording technology  

NASA Astrophysics Data System (ADS)

One of the new alternative information storage technologies being researched is based on the probe-based recording technique. In one technique, a phase-change medium is used, and the phase change is accomplished by applying either a high or low magnitude of current which heats the interface to different temperatures. Tip wear is a serious concern. For wear protection of the phase-change chalcogenide medium with a silicon substrate, diamond-like carbon (DLC) film with various lubricant overcoats was deposited on the recording layer surface. Nanowear properties of platinum (Pt)-coated probes with high electrical conductivity have been investigated in sliding against the coated medium using an atomic force microscope (AFM). A silicon grating sample and software to deconvolute tip shape were used to characterize the change in the tip shape and evaluate the tip radius and its wear volume. The nanowear experiments were performed at sliding velocities ranging from 0.1 to 100 mm s-1. Pt-coated tips on the lubricant-coated DLC film surfaces showed less sensitivity to the velocity and the load as compared to the unlubricated DLC film surfaces. In wear life threshold experiments, the threshold reaches a smaller sliding distance at higher loads. In high-temperature experiments at 80 °C, the wear rate is higher compared to that at 20 °C. The results suggest that the wear mechanism at low velocity appears to be primarily adhesive and abrasive. At high velocity, an additional wear mechanism of the tribochemical reaction is important.

Bhushan, Bharat; Kwak, Kwang Joo

2007-08-01

244

Performance optimization of digital VLSI circuits  

SciTech Connect

Designers of digital VLSI circuits have virtually no computer tools available for the optimization of circuit performance. Instead, a designer relies extensively on circuit-analysis tools, such as circuit simulation (SPICE) and/or critical-delay-path analysis. A circuit-analysis approach to digital design is very labor-intensive and seldom produces a circuit with optimum area/delay or power/delay trade off. The goal of this research is to provide a synthesis approach to the design of digital circuits by finding the sizes of transistors that optimize circuits by finding the sizes of transistors that optimize circuit performance (delay, area, power). Solutions are found that are optimum for all possible delay paths of a given circuit and not for just a single path. The approach of this research is to formulate the problem of area/delay or power/delay optimization as a nonlinear program. Conditions for optimality are then established using graph theory and Kuhn-Tucker conditions. Finally, the use of augmented-Lagrangian and projected-Lagrangian algorithms are reviewed for the solution of the nonlinear programs. Two computer programs, PLATO and COP, were developed by the author to optimize CMOS PLA's (PLATO) and general CMOS circuits (COP). These tools provably find the globally optimum transistor sizes for a given circuit. Results are presented for PLA's and small- to medium-sized cells.

Marple, D.P.

1987-01-01

245

Development of Magnesium Wafer Cells.  

National Technical Information Service (NTIS)

The purpose of this development contract is to design a practical magnesium wafer battery which performs satisfactorily after storage for various periods at ambient temperatures up to 160F. The initial phase of development includes the design of a cell an...

T. S. Hungate

1966-01-01

246

Development of Magnesium Wafer Cells.  

National Technical Information Service (NTIS)

This paper discusses the development of magnesium wafer cells. The principal physical condition causing constructional difficulties in both the 1-3/4 X 3-1/4 inch and 1-1/8 X 1-1/8 inch cell size batteries was the evolution of gas during storage and disch...

L. W. Eaton

1968-01-01

247

Wafer level packaging of MEMS  

Microsoft Academic Search

Wafer level packaging methods of MEMS are described. These play important roles to reduce cost and to improve reliability. MEMS structures on silicon chips are encapsulated with bonded caps or with shells fabricated by surface micromachining, and electrical interconnections are made from the cavity. Vacuum packaging methods are also described.

M. Esashi

2009-01-01

248

Dynamic wafer handling process in semiconductor manufacturing  

Microsoft Academic Search

In semiconductor manufacturing, wafers are transferred using wafer handling robots. Typically a pick-measure-place method is used to transfer wafers accurately between stations. The measurement step is performed using an aligner, which is time-consuming. To increase wafer transfer efficiency, it is desirable to speed up the measurement or place it in parallel with other operations. Hence two optic sensors are installed

Heping Chen; Ben Mooring; Harold Stern

2011-01-01

249

Interferometric and confocal techniques for testing of silicon wafers  

NASA Astrophysics Data System (ADS)

The paper provides new insights into Silicon wafer measurements in context of technological problems of developing a sophisticated measurement technique, which harnesses helium atom beam as a probe. Nano-resolution imaging techniques such as scanning tunnelling microscopy (STM) and atomic force microscopy (AFM) are well-know in surface science. A scanning helium atom microscope, where a focused beam of low energy, neutral helium atoms is used as an imaging probe is a new concept creating non-destructive and non-invasive surface investigation tool in science and industry. This paper is focused on measurements of flatness and thickness of the wafer, which is used as a deflecting mirror of the helium beam. Two -optics based- measurement techniques are presented: scanning confocal system and the Fizeau interferometer. The latter is applied as a quick reference device placed close to the production line whereas the former offers high accuracy flatness and thickness maps of the wafers.

Galas, J.; Litwin, D.; Sitarek, S.; Surma, B.; Piatkowski, B.; Miros, A.

2006-05-01

250

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

251

NASA Space Engineering Research Center for VLSI systems design  

NASA Technical Reports Server (NTRS)

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

1991-01-01

252

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Technical Reports Server (NTRS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

253

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Astrophysics Data System (ADS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-02-01

254

Yield and equipment utilization improvements achieved through fab conversion to carbon fiber\\/PEEK wafer carriers and carbon fiber\\/polypropylene storage boxes  

Microsoft Academic Search

Many semiconductor fabs using outdated wafer carrier technology are facing problems with carrier dimensional variation over time and particle generation. Carrier dimensional variation leads to excessive tool failures and wafer damage. This results in decreased throughput and yield loss. In addition, carrier particulation directly causes wafer defects, also negatively affecting yield. IBM-Burlington was encountering these problems and put a great

Ed Merrill; Jim Bostwick; Chad Gilhoi; Kirk Mikkelsen

2000-01-01

255

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress  

NASA Astrophysics Data System (ADS)

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Brunner, Timothy A.; Menon, Vinayan C.; Wong, Cheuk Wun; Gluschenkov, Oleg; Belyansky, Michael P.; Felix, Nelson M.; Ausschnitt, Christopher P.; Vukkadala, Pradeep; Veeraraghavan, Sathish; Sinha, Jaydeep K.

2013-10-01

256

Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001  

SciTech Connect

The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.

Beetz, C.P.; Steinbeck, J.; Hsueh, K.L.

2001-03-31

257

Peak crosstalk noise estimation in CMOS VLSI circuits  

Microsoft Academic Search

Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time of flight delay of the signal through the interconnect. In this paper, a linear resistor model is used to approximate the CMOS driver stage, and the CMOS receiver

Kevin T. Tang; Eby G. Friedman

1999-01-01

258

Common-mode failures in redundant VLSI systems: a survey  

Microsoft Academic Search

This paper presents a survey of CMF (common-mode failures) in redundant systems with emphasis on VLSI (very large scale integration) systems. The paper discusses CMF in redundant systems, their possible causes, and techniques to analyze reliability of redundant systems in the presence of CMF. Current practice and results on the use of design diversity techniques for CMF are reviewed. By

Subhasish Mitra; Nirmal R. Saxena; Edward J. McCluskey

2000-01-01

259

Macromodeling and Optimization of Digital MOS VLSI Circuits  

Microsoft Academic Search

Power consumption and signal delay are crucial to the design of high-performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based

Mark Douglas Matson; Lance A. Glasser

1986-01-01

260

VLSI implementation of a reduced symmetric fuzzy singleton set  

NASA Astrophysics Data System (ADS)

A fuzzy logic controller (FLC) has been proposed and implemented in many control systems to deliver smooth and more reliable outputs than the traditional control systems. In most of the existing VLSI FLC chips, the architectures are based on general purpose microcontroller structure tailored to fuzzy logic implementation. The drawbacks in these types of FLC VLSI chips are low speed, high cost, and long design time. Moreover, an expensive development system is also needed to program a general purpose microcontroller for a specific fuzzy logic control system. In order to alleviate the drawbacks in existing VLSI fuzzy logic circuits, a reduced symmetric fuzzy singleton set (RSFSS) is proposed in this paper. The proposed RSFSS system can handle three input variables, nine rules for each input variable, and produces two output values. Each rule is based on a symmetric triangular membership function. The triangular membership functions of each state variable are defined symmetrically with respect to the centroid of the universe of discourse. Since the hardware complexity is greatly reduced, the entire FLC based on the RSFS structure can be implemented on a VLSI chip with a dimension of 2.22 mm X 2.22 mm.

Chang, Yi-Chieh; Wu, Kung C.

1993-08-01

261

SPIDER -- A CAD System for Modeling VLSI Metallization Patterns  

Microsoft Academic Search

A system of CAD programs, called SPIDER, for ensuring adequate current-carrying capacity in VLSI circuits has been developed. The approach is hierarchical, and it automates and simplifies many of the tasks previously performed by the circuit designer. The system converts transient current waveforms into dc electromigration equivalent values, and includes an algorithm for determining the line width adjustments necessary for

Joseph E. Hall; Dale E. Hocevar; Ping Yang; Michael J. Mcgraw

1987-01-01

262

An Interactive Multimedia Learning Environment for VLSI Built with COSMOS  

ERIC Educational Resources Information Center

This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

Angelides, Marios C.; Agius, Harry W.

2002-01-01

263

Mixed mode VLSI implementation of a neural associative memory  

Microsoft Academic Search

A mixed mode digital\\/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a n×m matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. Although analog circuits suffer from device mismatch

Arne Heittmann; U. Ruckert

1999-01-01

264

VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications  

Microsoft Academic Search

The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is

Rozita Teymourzadeh; Masuri Othman

265

Hybrid VLSI/QCA Architecture for Computing FFTs  

NASA Technical Reports Server (NTRS)

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

266

VLSI implementations of image and video multimedia processing systems  

Microsoft Academic Search

An overview of very large scale integrated (VLSI) implementations of multimedia processing systems is given with particular emphasis on architectures for image and video processing. Alternative design approaches are discussed for dedicated image and video processing circuits and for programmable multimedia processors. Current design examples of dedicated and programmable architectures are reviewed, and the techniques employed to improve the performance

Peter Pirsch; Hans-Joachim Stolberg

1998-01-01

267

GEORG: VLSI circuit partitioner with a new genetic algorithm framework  

Microsoft Academic Search

This paper suggests a new framework of multidimensional genetic algorithm and applies it to the real-world problem of very large scale integration (VLSI) partitioning. The framework consists of a new multidimensional genetic operator, called geographic crossover, and a new genetic encoding scheme. Geographic crossover enables more powerful creation of new solutions by allowing a diverse mixture of parent solutions. Its

Byung-Ro Moon; Yun-Sik Lee; Chun-Kyung Kim

1998-01-01

268

CMOS VLSI Layout and Verification of a SIMD Computer  

NASA Technical Reports Server (NTRS)

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

Zheng, Jianqing

1996-01-01

269

Why VLSI implementations of associative VLCNs require connection multiplexing  

Microsoft Academic Search

A discussion is presented of some of the implementation constraints imposed on VLSI architectures for emulations of very large connectionist\\/neural networks (VLCNs). Specifically, the authors show that multiplexing of interconnections is necessary for networks exhibiting poor locality. They show that it is more feasible to build a VLCN system with sharing or multiplexing of interconnections than to build one with

Jim Bailey; Dan Hammerstrom

1988-01-01

270

A special purpose silicon compiler for designing supercomputing VLSI systems  

NASA Technical Reports Server (NTRS)

Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

1991-01-01

271

A VLSI architecture for arithmetic coding of multilevel images  

Microsoft Academic Search

We describe a VLSI architecture of an arithmetic coder for a multilevel alphabet (256 symbols) that includes the storing and updating of probabilities, the updating of the interval, and the correction of the codeword. The architecture is based on the utilization of redundant arithmetic, and the development of new schemes for storing and updating the cumulative probabilities and updating the

M. Boo; J. D. Bruguera; T. Lang

1998-01-01

272

Power estimation tool for sub-micron CMOS VLSI circuits  

Microsoft Academic Search

Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. Previous approaches for switch level current simulations used simple current models that did not match accurately the supply current. In this paper, we present a detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by

F. Rouatbi; Baher Haroun; Asim J. Al-Khalili

1992-01-01

273

Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits  

Microsoft Academic Search

This brief introduces a partitioning algorithm, which facilitates pseudoexhaustive testing, to detect and locate faults in digital VLSI circuits. The algorithm is based on an analysis of circuit's primary input cones and fanout (PIFAN) values. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to

Bassam Shaer; David L. Landis; Sami A. Al-arian

2000-01-01

274

A VLSI architecture for bicubic surface patch image generation  

Microsoft Academic Search

A VLSI architecture is presented for generating ray-tracing images of bicubic surface in Bezier form by using the subdivision algorithm. It uses a set of tree transverse operators to find the nearest intersection between a surface patch and a ray by traversing the entire subdivision tree in preorder. This scheme retains the advantage of subdivision and substantially reduces the circuit

P. C. Chao; M.-Y. Chern

1989-01-01

275

Germanium on sapphire by wafer bonding  

NASA Astrophysics Data System (ADS)

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 × 10 -6 K -1) and sapphire (5 × 10 -6 K -1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm 2/V s have been fabricated onto the thick germanium on sapphire layer.

Baine, P. T.; Gamble, H. S.; Armstrong, B. M.; M cNeill, D. W.; Mitchell, S. J. N.; Low, Y. H.; Rainey, P. V.

2008-12-01

276

Wafer Inspection in the Photolithography Process  

NSDL National Science Digital Library

This is a description for a learning module from Maricopa Advanced Technology Education Center. This PDF describes the module; access may be purchased by visiting the MATEC website. In this module, your learners begin to master the sensitive after develop inspection (ADI) methods that follow photolithography. MATEC describes macro- and micro-inspection techniques and distinguishes qualitative (inspection) from quantitative (metrology) methods. The chief focus is on teaching learners to examine wafers under an optical microscope; a simulated microscope is also provided in a computer-based training (CBT) format. The module covers edge bead inspection and provides extensive practice in flash boundary inspection, including evaluating Nikon crosses, overlay boxes, scanning electronic microscope features, resolution bars, Verniers, and product identification numbers.

2012-12-03

277

Low temperature, high strength, wafer-to-wafer bonding  

SciTech Connect

This paper reports on high strength bonds which can be formed between portions of silicon wafer coated with reflowed BPSG at temperatures as low as 160[degrees]C. Both a novel modified cantilever beam analysis, and crude physical methods attest to the strength of the bonds formed. Strong bonds between thermal oxides also have been observed, indicating that neither boron nor phosphorous are essential to the process. Preparation cleanliness may be the key to low temperature, high strength bonding,. Recent work in the glass sol-gel area supports the hypothesis that this process is the result of a low temperature condensation reaction.reaction.

Fleming, J.G.; Roherty-Osmun, E.; Godshall, N.A. (Sandia National Labs., Albuquerque, NM (United States))

1992-11-01

278

Fast-ramp rapid vertical processor for 300-mm Si wafer processing  

NASA Astrophysics Data System (ADS)

Fast-ramp vertical furnace technology has been established on the 200-nm wafer platform providing higher capacity production, decreased cycle time and lower thermal budgets. Fast-ramp furnaces are capable of instantaneous temperature ramp rates up to 100 degrees C/min. This fast-ramp technology is now applied to 300-nm wafer processing on the SVG/Thermco Rapid Vertical Processor Vertical Furnace. 300- mm fast-ramp capability using the latest in real-time adaptive model based temperature control technology, Clairvoyant Control, is reported. Atmospheric Thermal Oxidation, LPCVD Nitride and Polysilicon Deposition, and LPCVD TEOS-based SiO2 Deposition results are discussed. 300- mm wafer Radial Delta Temperature dependence on temperature ramp rate, wafer pitch, and wafer support fixtures are discussed. Wafer throughput is calculated and reported. The Clairvoyant Control methodology of combining thermal, direct and virtually-sensed parameters to produce real-tim e estimation of wafer temperatures, thermal trajectory optimization, and feedback to minimize variations in film thickness and electrical properties is presented.

Porter, Cole; Laser, Allan; Herring, Robert; Pandey, Pradeep

1998-09-01

279

Smart stackingTM technology: An industrial solution for 3D layer stacking  

Microsoft Academic Search

Smart Stacking™ is a wafer-to-wafer stacking technology of partially or fully processed wafers. This technology enables transferring very thin layers in a high volume manufacturing environment. The core technologies are surface conditioning, low temperature direct bonding and wafer thinning (figure 1). This technology is adapted for advanced semiconductor applications such as Back Side Illumination (BSI) CMOS Image Sensors (CIS) as

C. Lagahe Blanchard; I. Radu; M. Sadaka; K. Landry

2011-01-01

280

Wafer CD variation for random units of track and polarization  

NASA Astrophysics Data System (ADS)

After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

2012-03-01

281

Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis  

SciTech Connect

This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

Tobin, K.W.

2003-05-22

282

Thin film effects in ultrasonic wafer thermometry  

Microsoft Academic Search

We use an ultrasonic technique where the temperature dependence of lowest order anti-symmetric Lamb wave velocity in the silicon wafer is utilized for in-situ temperature measurement in the 20-1000°C range. In almost all wafer processing steps, one or more layers of thin films are present on the wafers. The effects of these films on temperature sensitivity is investigated. A theoretical

F. L. Degertekin; J. Pei; B. V. Honein; B. T. Khuri-Yakub; K. C. Saraswat

1994-01-01

283

Metal Enhanced Fluorescence on Silicon Wafer Substrates  

PubMed Central

We report on the fluorescence enhancement induced by silver island film (SIF) deposited on a silicon wafer. The model immunoassay was studied on silvered and unsilvered wafers. The fluorescence brightness of Rhodamine Red X increased about 300% on the SIF, while the lifetime was reduced by several fold and the photostability increased substantially. We discuss potential uses of silicon wafer substrates in multiplex assays in which the fluorescence is enhanced due to the SIF, and the multiplexing is achieved by using micro transponders.

Gryczynski, I.; Matveeva, E.G.; Sarkar, P.; Bharill, S.; Borejdo, J.; Mandecki, W.; Akopova, I.; Gryczynski, Z.

2008-01-01

284

Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm  

Microsoft Academic Search

In this paper, we present efficient VLSI architectures for full-search block-matching motion estimation (BMME) algorithm. Given a search range, we partition it into sub-search arrays called tiles. By fully exploiting data dependency within a tile, efficient VLSI architectures can be obtained. Using the proposed VLSI architectures, all the block-matchings in a tile can be processed in parallel. All the tiles

Zhong-li He; Ming Lei Liou

1997-01-01

285

A reclaiming process for solar cell silicon wafer surfaces.  

PubMed

The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost. PMID:21446525

Pa, P S

2011-01-01

286

Efficient simulation and optimization of wafer topographies in double patterning  

NASA Astrophysics Data System (ADS)

As the technology marches towards the 32nm node and beyond in semiconductor manufacturing, double patterning and double exposure techniques are currently regarded as the potential candidates to produce lines and spaces (L&S) and contact holes (C/H), respectively. In this paper, the Waveguide method, a rigorous electromagnetic field (EMF) solver, is employed to investigate the impact of wafer topographies on two specific double patterning techniques. At first, the topography effects induced by the first patterning on the second lithography process in a lithography-etch-lithographyetch (LELE) process are demonstrated. A new methodology of the bottom anti-reflective coating (BARC) optimization is proposed to reduce the impact of wafer topography on resist profiles. Additionally, an optical proximity correction (OPC) of the second lithography mask is demonstrated to compensate the wafer topography induced asymmetric deformations of line ends. Rigorous EMF simulations of lithographic exposures are also applied to investigate wafer topography effects in a freezing process. The difference between the optical properties of the frozen (first) resist and the second resist potentially causes linewidth variations. Quantitative criteria for tolerable refractive index and extinction differences between the two resist materials are given. The described studies can be used for the optimizations of topographic waferstacks, the OPC of the second litho mask, and for the development of resist materials with appropriate optical properties.

Shao, Feng; Evanschitzky, Peter; Fühner, Tim; Erdmann, Andreas

2009-03-01

287

Performance Evaluations of Ceramic Wafer Seals  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

288

The hardness assurance wafer probe - HAWP  

NASA Astrophysics Data System (ADS)

Complete radiation sensitivity assessments of integrated circuits can now be performed at the wafer level using a new system, the Hardness Assurance Wafer Probe, HAWP. This system utilizes a pulsed Nd:YAG infrared laser impinging on the backside of the wafer to evaluate the transient behavior of the circuits. A low energy X ray source collimated to a single die site actually performs total dose irradiations. Finally, special electrical measurements are used to enable a prediction of the neutron sensitivity of bipolar devices. The HAWP System is described and correlations of wafer probe results to conventional radiation tests for a digital part type are provided.

King, E. E.; Tettemer, G. L.; Linderman, P. B.; Micheletti, P. E.

1983-12-01

289

Designing DWDM multiplexers on SiON wafers  

NASA Astrophysics Data System (ADS)

I propose an integrated multiplexer/demultiplexer that use a concave blazed diffraction grating on SiON wafer. The paper presents a technology that overcome existing issues regarding implementation of such a microoptic device. Two types of similar integrated systems were developed but both of them have not minimized chromatic, astigmatism and spherical aberrations. Both systems use gold coating for vertical walls of diffraction grating that has reflection index lower than aluminum for wavelength used. Technology proposed in this paper minimizes the chromatic, astigmatism and spherical aberrations. Also is used aluminum for coating of vertical walls of diffraction grating. SiON wafer is etched with Argon plasma through photoresist mask with thickness of 0,8 ?m for grating configuration allowing reusing of the photoresist in next stage of coating. This makes possible that coating through liftoff to be aligned to vertical walls of concave diffraction grating, eliminating positioning errors due to coating mask.

Dragnea, Laurentiu

2010-09-01

290

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads  

DOEpatents

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

2013-12-03

291

Across-wafer CD uniformity control through lithography and etch process: experimental verification  

NASA Astrophysics Data System (ADS)

Process variation on lot-to-lot and wafer-to-wafer level has been well addressed using R2R control in advanced process control, however, to tackle the ever increasing die-to-die (i.e. across-wafer) level process variation at the 65nm technology node and beyond, the process control must be extended into finer domain: across-wafer level. A novel model based process control approach [2] was proposed to reduce the critical dimension (CD) variation on across-wafer level. The central idea of the proposed approach is to compensate for upstream and downstream systematic CD variation by adjusting the across-wafer Post-Exposure Bake (PEB) temperature profile of a multi-zone bake plate. A temperature-to-offset model relating the PEB temperature profile of multi-zone bake plate to its heater zone offsets was constructed experimentally using wireless temperature sensors from OnWafer Technologies. The baseline post-etch CD signature and plasma etch bias signature were extracted to characterize the lithography and etch processes. And a post-etch CD variation reduction of 40% was realized in the verification experiment, which validated the efficacy of the proposed approach.

Zhang, Qiaolin; Tang, Cherry; Cain, Jason; Hui, Angela; Hsieh, Tony; Maccrae, Nick; Singh, Bhanwar; Poolla, Kameshwar; Spanos, Costas J.

2007-03-01

292

Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010  

SciTech Connect

1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

Lorenz, A.

2011-06-01

293

Wafer management between coat/developer track and immersion lithography tool  

NASA Astrophysics Data System (ADS)

The ArF immersion lithography is a probable technique for the application below 65 nm hp generation. The first immersion lithography scanner, the engineering evaluation tool (EET) being connected inline with a coat/developer (C/D) ACT12 (Tokyo Electron Ltd.), was completed in the end of 2004 and showed that a bit of residual water might make a watermark on the wafer. Tokyo Electron Ltd. and Nikon Corp. have challenged to resolve this problem from a point of view of improvements on the system components for production tools. Nikon improves on local water filling nozzle, wafer table and wafer loader. The nozzle and the wafer table in the exposure tool are optimized to diminish the residual water, while the wafer stage is driven at high speed for high throughput of the production tool. However a bit of water, the amount of which also depends on a topcoat material, may remain. The wafer loader should carry the wafer to the C/D before drying up it. Before post exposure bake (PEB), C/D rinses and dries the wafer immediately to prevent it from the generation of watermark by remaining water. The wafer handling condition including rinse of which is optimized using the ACT12 connected to the EET and have applied to the new C/D LITHIUSi+ connected to S609B, the first Nikon's immersion scanner for mass production. In this report, we present the latest immersion technology, including the wafer contamination control, which is developed through the collaboration between Tokyo Electron Ltd. and Nikon Corp.

Fujiwara, Tomoharu; Shiraishi, Kenichi; Tanizaki, Hirokazu; Ishii, Yuuki; Kyoda, Hideharu; Yamamoto, Taro; Ishida, Seiki

2006-04-01

294

Strength of Si wafers with microcracks: A theoretical model  

Microsoft Academic Search

Wafer breakage is a major problem in the photovoltaic industry and becomes more serious as the industry attempts to use thinner wafers. It is well established that the poor strength of PV wafers is primarily due to the presence of residual microcracks, which are generated by cutting and wafering procedures and are not removed by subsequent etching of the wafers.

Przemyslaw Rupnowski; Bhushan Sopori

2008-01-01

295

Characterization of 300 mm silicon-polished and EPI wafers  

Microsoft Academic Search

Maturity of 300 mm polished wafers and early epi wafers were evaluated in respects of particles, flatness, metal contamination, and epitaxy thickness. Data of 300 mm polished wafers showed encouraging characteristics comparable to state-of-the-art 200 mm prime wafers. Preliminary characterization of 300 mm epi wafers revealed that dominant localized light scatterers (LLS) with sizes more than 1 ?m were epitaxy

Steven Shih; Chi Au; Zach Yang; Troy Messina; Randal K. Goodall; Howard R. Huff

1999-01-01

296

Design and performance of VLSI based parallel multiplier  

SciTech Connect

The VLSI design and layout of a (log /sup 2/n) time n-bit binary parallel multiplier for two unsigned operands is introduced. The proposed design consists of partitioning the multiplier and multiplicand bits into four groups of n/4 bits each and then reducing the matrix of sixteen product terms using three to two parallel counters and a brent-kung (log n) time parallel adder. Area-time performance of the present scheme has been compared with the existing schemes for parallel multipliers. Regular and recursive design of the multiplier is shown to be suitable for vlsi implementation and an improved table lookup multiplier has been used to form the basis of the recursive design scheme. 17 references.

Agrawal, D.P.; Pathak, G.C.; Swain, N.K.; Agrawal, B.K.

1983-01-01

297

Wafer-Scale Flexible Surface Acoustic Wave Devices Based on an AlN/Si Structure  

NASA Astrophysics Data System (ADS)

Wafer-scale flexible surface acoustic wave (SAW) devices based on AlN/silicon structure are demonstrated. The final fabricated devices with a 50?m-thickness silicon wafer exhibit good flexibility with a bending curvature radius of 8 mm. Measurements under free and bending conditions are carried out, showing that the central frequency shifts little as the curvature changes. SAW devices with central frequency about 191.9MHz and Q-factor up to 600 are obtained. The flexible technology proposed is directly applied to the wafer silicon substrate in the last step, providing the potential of high performance flexible wafer-scale devices by direct integration with mature CMOS and MEMS technology.

Zhang, Cang-Hai; Yang, Yi; Zhou, Chang-Jian; Shu, Yi; Tian, He; Wang, Zhe; Xue, Qing-Tang; Ren, Tian-Ling

2013-07-01

298

VLSI Design and Verification of the Imagine Processor  

Microsoft Academic Search

The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford Un- versity and Texas Instruments in a 1.5V 0.15µ mp rocess with five layers of aluminum metal. The VLSI design, clock- ing, and verification methodologies for the Imagine proces- sor are presented. These methodologies enabled a small team of graduate students with limited resources

Brucek Khailany; William J. Dally; Andrew Chang; Ujval J. Kapasi; Jinyung Namkoong; Brian Towles

2002-01-01

299

Timing Analysis and Performance Improvement of MOS VLSI Designs  

Microsoft Academic Search

TV is a MOS VLSI switch-level timing verifier. It has built-in direction-finding through pass transistors to minimize the number of false paths found, and has knowledge of clocking disciplines to increase the usefulness of timing analysis for chips with several clock phases. TV can find several distinct critical paths at once by using a modified breadth-first search, so that the

Norman P. Jouppi

1987-01-01

300

A Nanosensor Array-Based VLSI Gas Discriminator  

Microsoft Academic Search

Chemiresistive nanowires can be organized as cross-reactive sensor arrays to mimic the human olfactory system in terms of sensing and discriminating various gases and odors. This paper presents a single chip gas discrimination system that integrates a cross-reactive array of chemiresistive nanosensors with an underlying VLSI pattern classifier to accurately and efficiently identify the gas\\/odor to which the system is

Kevin M. Irick; Wei Xu; Narayanan Vijaykrishnan; Mary Jane Irwin

2005-01-01

301

VLSI implementation of shape-adaptive discrete wavelet transform  

Microsoft Academic Search

In this paper, several VLSI architectures and implementations of Shape-Adaptive Discrete Wavelet Transform (SA- DWT) with odd symmetric biorthogonal filters are presented. The hardware implementation issues of SA-DWT algorithm are first addressed, and one lifting scheme together with some appropriate shape information processing units is introduced for the 1-D SA-DWT architectures. These architectures can efficiently perform 1-D length-adaptive DWT on

Po-Chih Tseng; Chao-Tseng Huang; Liang-Gee Chen

2002-01-01

302

Scanners for visualizing activity of analog VLSI circuitry  

Microsoft Academic Search

This paper tutorially describes mixed digital-analog serial multiplexers (scanners) that we use to visualize the activity of one- and two-dimensional arrays of analog VLSI elements. These scanners range from simple one-dimensional devices designed to scan a one-dimensional array onto an oscilloscope, to complete video scanners with integrated sync and blank computation and on-chip video amplifiers. We discuss practical details of

Carver A. Mead; Tobias Delbrück

1991-01-01

303

Computing perspectives: the rise of the VLSI processor  

Microsoft Academic Search

Around 1970 Intel discovered it could put 2,000 transistors—or perhaps a few more—on a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), an event which had been long heralded, but had been seemingly slow to come. At the time, it went almost unnoticed in the computer industry. This was partly

Maurice V. Wilkes

1990-01-01

304

Parallel Random Number Generation for VLSI Systems Using Cellular Automata  

Microsoft Academic Search

A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in parallel from various cells in the cellular automaton on each

Peter D. Hortensius; Robert D. Mcleod; Howard C. Card

1989-01-01

305

A parametric VLSI architecture for video motion estimation  

Microsoft Academic Search

This paper presents a VLSI macro-cell for the implementation of full-search (FS) motion estimation that is a key issue of various video processing and compression standards such as MPEG and H.263. Beyond the usual algorithm, advanced-prediction and static-priority options are supported to improve the SNR\\/bit-rate efficiency. The architecture is fully parametric in terms of block size and maximum search area

Luca Fanucci; Sergio Saponara; Lorenzo Bertini

2001-01-01

306

VLSI architecture for hierarchical mesh-based motion estimation  

Microsoft Academic Search

Methods for object-based compression and composition of natural and synthetic video content are currently emerging in standards such as MPEG-4 and VRML. This paper shows a novel VLSI architecture for generating content-based video object representation. The architecture uses a novel technique, borrowed from the 3D modeling, to optimize the mesh coding. The architecture generates the mesh nodes location as well

Wael Badawy; Guoqing Zhang; Magdy Bayoumi

1999-01-01

307

Power estimation tool for sub-micron CMOS VLSI circuits  

Microsoft Academic Search

Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. A detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by SPICE LEVEL 3 at peak values and 5% at the average current is presented. The current model accounts for short-channel effects, input risetimes, short-circuit

F. Rouatbi; B. Haroun; A. J. Al-Khalili

1992-01-01

308

Motion detection with a view toward VLSI implementation  

NASA Astrophysics Data System (ADS)

A small low-cost motion detector would have widespread applications in visual control systems such as miniature unmanned aerial vehicles and collision avoidance systems. In the last 20 years a number of analog VLSI chips have been developed which incorporate both photodetection and motion computation on the same chip. Nevertheless, artificial real-time vision and simple seeing systems remain a massive challenge mainly because the environment greatly impacts on their performance. On the other hand, biological systems have, through years of evolution, come up with a number of simple but clever solutions. The Reichardt Correlator is a biologically inspired model for motion detection. However, the basic model is not a robust estimator of velocity. The accuracy and reliability of this model can be significantly improved through various elaborations. VLSI is ideally suited to the parallel processing seen in nature because it allows for high device integration density and complex implementation of complex functions. Howsoever, VLSI poses some serious bounds on the types of elaborations that can be implemented. We have explored this problem and will present a number of improved models with robust outputs that are practical in terms of real time implementation in microchips.

Tan, Xu Jiang; Chong, Stephanie; Rainsford, Tamath; Al-Sarawi, Said

2007-01-01

309

New Results in the Use of Piezoelectric Wafer Active Sensors for Structural Health Monitoring  

Microsoft Academic Search

Piezoelectric-wafer active sensors (PWAS) are small, inexpensive, non-invasive, elastic wave generators\\/receptors that can be easily affixed to a structure. Piezoelectric-wafer active sensors are wide- band non-resonant devices. They can be wired into sensor arrays and connected to data concentrators and wireless communicators. However, the development of PWAS technology is not yet complete, and a number of issues have still to

Victor Giurgiutiu

310

Endpoint detectable plating through femtosecond laser drilled glass wafers for electrical interconnections  

Microsoft Academic Search

An endpoint detectable plating process to avoid over-electroplating was proposed and performed in this work. The technology was developed for fabrication of Pyrex glass wafer with electrical feed-throughs. Thin film of gold was deposited on the glass wafer prior to the femtosecond laser drilling. When the growing metal in the through-holes was contacted to the metal, a resistance between the

Takashi Abe; Xinghua Li; Masayoshi Esashi

2003-01-01

311

Fabrication and characterization of hybrid silicon-on-silicon carbide wafers  

Microsoft Academic Search

Multiple 50 and 75 mm hybrid Si-on-SiC substrates consisting of thin film [100] Si (1 mum) on bulk 6H and 4H SiC wafers were fabricated using novel low-temperature (150°C) wafer bonding and slicing techniques. These substrates were developed to be competitive with Si and SOI technology for the fabrication of Si electronics. A set of samples was prepared comparing various

Steven G. Whipple

2006-01-01

312

Preparation and Characterization of PZT Wafers  

NASA Astrophysics Data System (ADS)

Piezoelectric materials have recently attracted a lot of attention for ultrasonic structural health monitoring (shm) in aerospace, defence and civilian sectors, where they can act as both actuators and sensors. Incidentally, piezoelectric materials in the form of wafers (pwas-piezoelectric wafer active sensor, approx. 5-10 mm square and 0.2-0.3 mm thickness) are inexpensive, non intrusive and non-resonant wide band devices that can be surface-mounted on existing structures, inserted between the layers of lap joints or embedded inside composite materials. The material of choice for piezoelectric wafers is lead zirconate titanate (PZT) of composition close to morphotropic phase boundary [pb(zr0.52 ti0.48)o3]. However, an excess pbo is normally added to pzt as a densification aid and also to make up for the lead loss during high temperature sintering. Hence, it is of paramount importance to know how the shift of the lead content from the morphotropic composition affects the piezoelectric and mechanical properties of the sintered wafers, keeping in view the importance of mechanical properties of wafers in shm. In the present study, we observed that with the increase in the lead content of the sintered wafers, the dielectric and piezoelectric constants decreased. However, the elastic modulus, hardness and fracture toughness of the wafers increased with increasing lead content in the composition. Hence, the lead content in the sintered wafers should be optimized to get acceptable piezoelectric and mechanical

Seal, A.; Rao, B. S. S. Chandra; Kamath, S. V.; Sen, A.; Maiti, H. S.

2008-07-01

313

Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards. [Very Large Scale Integration (VLSI)  

SciTech Connect

This paper discusses the sensor-based driving of a car in a-priori unknown environments using human-like'' reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver's aid using the new fuzzy inferencing VLSI hardware and human-like'' reasoning schemes.

Pin, F.G.; Watanabe, Y.

1992-01-01

314

A self-priming, high performance, check valve diaphragm micropump made from SOI wafers  

NASA Astrophysics Data System (ADS)

In this paper, we describe a self-priming high performance piezoelectrically actuated check valve diaphragm micropump. The micropump was fabricated from three wafers: two silicon-on-insulator (SOI) wafers and one silicon wafer. A process named 'SOI/SOI wafer bonding and etching back followed by a second wafer bonding' was developed in order to make the core components of this device which included an inlet check valve, an outlet check valve, a diaphragm and a chamber. The movable structures of this device, i.e. the check valves and the diaphragm, were fabricated from the device layers of the two bonded SOI wafers. Taking advantages of SOI wafer technology and etch-stop layers, the vertical parameters of the movable structures were precisely controlled in fabrication. The micropump was self-priming without any pre-filling process. The pumping rate of the micropump was linearly adjustable from 0 to 650l µm min-1 by adjusting frequency. The maximum pumping rate was 860 µl min-1 and the maximum pumping pressure was approximately 10.5 psi. The power consumption of the device was less than 1.2 mW.

Kang, Jianke; Mantese, Joseph V.; Auner, Gregory W.

2008-12-01

315

Reconfigurable multi-passband optical filter using Opto-VLSI processor  

Microsoft Academic Search

A reconfigurable multi-passband optical filter of 0.5 nm linewidth and a tuning range of 8 nm is demonstrated using an opto-VLSI processor. The wavelength tunability is performed using digital phase holograms uploaded on the opto-VLSI processor.

Muhsen Aljada; Kamal Alameh

2008-01-01

316

Demonstration of tunable optical notch filter using 1-D opto-VLSI processor  

Microsoft Academic Search

An opto-very-large-scale-integrated (opto-VLSI)-based tunable optical filter structure is demonstrated. Filter tunability is achieved by reconfiguring the holographic diffraction grating of an opto-VLSI processor, allowing virtually any type of filter response to be synthesized. A proof-of-concept tunable notch filter with wavelength span of 7 nm is experimentally verified

Chung-Kiak Poh; Kamal Alameh; Zhenglin Wang

2006-01-01

317

Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks  

Microsoft Academic Search

This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior

David Blair Kirk

1993-01-01

318

Parallel algorithms and VLSI architectures for stack filtering using Fibonacci p-codes  

Microsoft Academic Search

A parallel decompositional algorithm and VLSI architecture is proposed for computation of the output of a stack filter over a single window of input samples using Fibonacci p-codes. For a subclass of positive Boolean functions, a more efficient parallel algorithm and VLSI architecture for running stack filtering is also presented. The area-time complexities of the proposed designs are estimated

David Z. Gevorkian; K. O. Egiazarian; S. S. Agaian; J. T. Astola; O. Vainio

1995-01-01

319

High Speed Image Processing System Based on the Custom VLSI for Digital Signal Processing (DSP).  

National Technical Information Service (NTIS)

A 16 bit VLSI including a 32 bit multiplier was designed for a SAR image processing system to minimize the error of the summing of the products. The image processing system consists of the data memories, interface circuits, the VLSI's, and the vision proc...

M. Kubo K. Horiguchi Y. Kuniyasu S. Horii E. Osaki

1986-01-01

320

The efficient VLSI design of BICUBIC convolution interpolation for digital image processing  

Microsoft Academic Search

This paper presents an efficient VLSI design of bicubic convolution interpolation for digital image processing. The architecture of reducing the computational complexity of generating coefficients as well as decreasing number of memory access times is proposed. Our proposed method provides a simple hardware architecture design, low computation cost and is easy to implement. Based on our technique, the high-speed VLSI

Chung-chi Lin; Ming-hwa Sheu; Huann-keng Chiang; Chishyan Liaw; Zeng-chuan Wu

2008-01-01

321

On the Complexity of VLSI-Friendly Neural Networks for Classification Problems  

Microsoft Academic Search

This paper presents some complexity results for the specific case of a VLSI friendly neural network used in classification problems. A VLSI-friendly neural network is a neural network using exclusively integer weights in a narrow interval. The results presented here give updated worst-case lower bounds for the number of weights used by the network. It is shown that the number

Sorin Draghici

1998-01-01

322

Implications of wafer design for manufacturing practices on photomask manufacturing  

NASA Astrophysics Data System (ADS)

Focus on Design for Manufacturing (DFM) in semiconductor device design has increased as semiconductor manufacturing technology has become more complex. Many of the techniques developed to improve wafer yield and manufacturability can also be applied to the photomask manufacturing process. For example, for the last several technology nodes, semiconductor manufacturers have known that pattern density and uniformity can have significant impact on wafer processes such as etching and chemical mechanical polishing. Photomask manufacturing can also be impacted by pattern density and its uniformity. Some of these DFM practices can be beneficial if applied directly to photomask manufacturing while some of them can make photomask manufacturing significantly more difficult. Optical proximity correction (OPC), which involves convoluting the design shape to account for optical, physical and chemical processes, is increasingly required to support advanced lithography; some of the operational parameters of the OPC, such as the fragmentation run length, challenge mask resolution capability, image fidelity, defect inspection, mask repair, and dimensional metrology of photomasks. Sub-resolution assist features (SRAFs), which are utilized to create robust wafer lithography are often the most challenging mask features to create. The size and placement of SRAFs on photomasks are factors that impact photomask manufacturability in terms of image resolution, inspection, and dispositioning criteria. As OPC and other DFM processes become more widely deployed in an effort to make robust wafer manufacturing processes, the photomask maker needs to be involved to evaluate the implications to photomask manufacturing and assist in optimizing these DFM procedures to maximally benefit both the photomask and semiconductor manufacturing processes.

Watts, Andrew; Rankin, Jed; Magg, Christopher

2005-11-01

323

Development of megasonic cleaning for silicon wafers  

NASA Technical Reports Server (NTRS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-01-01

324

Full wafer macro-CD imaging for excursion control of fast patterning processes  

NASA Astrophysics Data System (ADS)

A powerful new inspection technology enables the excursion control of fast patterning processes. Full images of 300mm wafers are captured and processed to extract CD uniformity information of contact hole and line-space patterns. Suitable masking filters are applied to process and analyze the information from active logic and/or memory areas separately. Characteristic process tool signatures can then be detected based on die, exposure field and wafer-level pattern variations. Based on inspection times of a few seconds per wafer, rapid monitoring of 100% of processed wafers at full surface is feasible. CD-imaging is demonstrated for the monitoring of key patterning process steps in gate formation. Use cases for stand-alone, integrated and smart sampling strategies are discussed.

Markwort, Lars; Kappel, Christoph; Kharrazian, Reza; Guittet, Pierre-Yves

2010-03-01

325

Multiproject wafers: not just for million-dollar mask sets  

NASA Astrophysics Data System (ADS)

With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task dictates careful consideration of the alternative methods.

Morse, Richard D.

2003-06-01

326

Mask CD uniformity metrology for logic patterning and its correlation to wafer data  

NASA Astrophysics Data System (ADS)

With the next technology nodes 193nm lithography is pushed to its utmost limits. The industry is forced to print at low k1 factor which goes along with a high MEEF. Additionally, new blank materials are being introduced for smaller nodes. From 4x node and beyond, global CD uniformity on wafer is getting more critical and becomes key factor to ensure a high yield in chip production. Advanced process control is required and correction strategies are applied to maintain tight wafer CD uniformity. Beside other parameters, like scanner and etch process, mask CD uniformity is one main contributor to the intra-field CD on wafer. To enable effective CDU correction strategies it is necessary to establish a mask CD uniformity metrology which shows a good correlation to wafer prints. Especially for logic pattern mask uniformity measurements to control intra-field CD uniformity becomes challenging. In this paper we will focus on mask CD uniformity measurement for logic application utilizing WLCD, which is based on aerial image technology. We will investigate 40nm node and 28nm node gate masks using 6% MoSi phase shifting mask and MoSi binary mask respectively. Furthermore, we will correlate the mask CD uniformity data to wafer data to evaluate the capability of WLCD to predict the intra-field wafer CD uniformity correctly in order to support feedforward correction strategies. We will show that WLCD shows an excellent correlation to wafer data. Additionally, we will provide an outlook on logic contact-hole masks showing first CD uniformity data and wafer correlation data.

Le Gratiet, Bertrand; Zékri, Raphaėl.; Sundermann, Frank; Trautzsch, Thomas; Thaler, Thomas; Birkner, Robert; Buttgereit, Ute

2012-06-01

327

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

2012-11-29

328

Automatic classification of spatial signatures on semiconductor wafer maps  

NASA Astrophysics Data System (ADS)

This paper describes spatial signature analysis (SSA), a cooperative research project between SEMATECH and Oak Ridge National Laboratory for automatically analyzing and reducing semiconductor wafermap defect data to useful information. Trends towards larger wafer formats and smaller critical dimensions have caused an exponential increase in the volume of visual and parametric defect data which must be analyzed and stored, therefore necessitating the development of automated tools for wafer defect analysis. Contamination particles that did not create problems with 1 micron design rules can now be categorized as killer defects. SSA is an automated wafermap analysis procedure which performs a sophisticated defect clustering and signature classification of electronic wafermaps. This procedure has been realized in a software system that contains a signature classifier that is user-trainable. Known examples of historically problematic process signatures are added to a training database for the classifier. Once a suitable training set has been established, the software can automatically segment and classify multiple signatures from a standard electronic wafermap file into user-defined categories. It is anticipated that successful integration of this technology with other wafer monitoring strategies will result in reduced time-to-discovery and ultimately improved product yield.

Tobin, Kenneth W., Jr.; Gleason, Shaun S.; Karnowski, Thomas P.; Cohen, Susan L.; Lakhani, Fred

1997-07-01

329

An adaptive, lossless data compression algorithm and VLSI implementations  

NASA Technical Reports Server (NTRS)

This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

1993-01-01

330

A VLSI architecture for simplified arithmetic Fourier transform algorithm  

NASA Technical Reports Server (NTRS)

The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

1992-01-01

331

Image and Video Compression with VLSI Neural Networks  

NASA Technical Reports Server (NTRS)

An advanced motion-compensated predictive video compression system based on artificial neural networks has been developed to effectively eliminate the temporal and spatial redundancy of video image sequences and thus reduce the bandwidth and storage required for the transmission and recording of the video signal. The VLSI neuroprocessor for high-speed high-ratio image compression based upon a self-organization network and the conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results.

Fang, W.; Sheu, B.

1993-01-01

332

TOPICAL REVIEW: Wafer level packaging of MEMS  

Microsoft Academic Search

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in

Masayoshi Esashi

2008-01-01

333

Fabrication of wafer-level thermocompression bonds  

Microsoft Academic Search

Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding. The fabrication process for wafer bonding at 300°C via compressing gold under 7 MPa of pressure is described in detail. One of the issues encountered in the process development was e-beam source spitting, which resulted in micrometer diameter sized Au on the surfaces, and made bonding

Christine H. Tsau; S. M. Spearing; M. A. Schmidt

2002-01-01

334

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner  

NASA Technical Reports Server (NTRS)

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

335

Simultaneous double side grinding of silicon wafers: a literature review  

Microsoft Academic Search

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of

Z. C. Li; Z. J. Pei; Graham R. Fisher

2006-01-01

336

A Flip-Chip AlGaInP LED with GaN\\/Sapphire Transparent Substrate Fabricated by Direct Wafer Bonding  

Microsoft Academic Search

A red-light AlGaInP light emitting diode (LED) is fabricated by using direct wafer bonding technology. Taking N-GaN wafer as the transparent substrate, the red-light LED is flip-chiped onto a structured silicon submount. Electronic luminance (EL) test reveals that the luminance flux is 130% higher than that of the conventional LED made from the same LED wafer. Current-voltage (I-V) measurement indicates

Ting Liang; Xia Guo; Bao-Lu Guan; Jing Guo; Xiao-Ling Gu; Qiao-Ming Lin; Guang-Di Shen

2007-01-01

337

Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule  

SciTech Connect

The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the wafer. In addition, it was found to be suitable for growing very large crystals. The equipment used was simple and inexpensive to operate. Reasonable solar cells were fabricated on re-crystallized material.

Emanuel Sachs Tonio Buonassisi

2013-01-16

338

A GRINDING-BASED MANUFACTURING METHOD FOR SILICON WAFERS: GENERATION MECHANISMS OF CENTRAL BUMPS ON GROUND WAFERS  

Microsoft Academic Search

Most integrated circuits (IC) are fabricated using silicon wafers. The continuing shrinkage of the size of IC features has imposed more and more stringent requirements on the wafer flatness. Furthermore, wafer manufacturers are under constant pressure to reduce the wafer cost. The traditional lapping-based manufacturing method is unable to satisfy the ever-increasing demand for better flatness and lower cost. Previous

Wangping Sun; Z. J. Pei; Graham R. Fisher

2006-01-01

339

Measurements of the geometrical characteristics of the silicon wafer for helium microscope focusing mirror  

NASA Astrophysics Data System (ADS)

Nano-resolution imaging techniques such as scanning tunnelling microscopy (STM) and atomic force microscopy(AFM) are well-know in surface science. However, a scanning helium atom microscope, where a focused beam of low energy, neutral helium atoms is used as an imaging probe is a very new concept creating non-destructive and noninvasive surface investigation tool in science and industry. The He-beam is created by supersonic expansion from a high pressure reservoir through a nozzle. It is focused onto the sample by a mirror created from an electrostatically deformed single silicon wafer. The shape of the mirror is enforced by an electrode system controlled by a computer. The focusing mirror consists of a chemically-prepared silicon wafer placed between two aluminium discs and suspended above an electrode structure. The deflection of the mirror is controlled by an electric field between the wafer and the electrodes. The accuracy of the shape of the mirror is the most critical since it determines the resolution of the helium microscope. The required modeling of the mirror shape depends on initial quality of the wafer. Therefore it is planned to make various improvements to the mirror at both the macroscopic and atomic levels. This paper is focused on measurements of flatness and thickness of the wafer with high accuracy using specialized optics based techniques, so that the technological process of the wafers could be modified to obtain high quality material.

Litwin, D.; Galas, J.; Kozlowski, T.; Sitarek, S.

2005-09-01

340

Porous solid ion exchange wafer for immobilizing biomolecules  

DOEpatents

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

2007-12-11

341

Testing interconnected VLSI circuits in the Big Viterbi Decoder  

NASA Technical Reports Server (NTRS)

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.

1991-01-01

342

New VLSI complexity results for threshold gate comparison  

SciTech Connect

The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

Beiu, V.

1996-12-31

343

A front-end wafer-level microsystem packaging technique with micro-cap array  

NASA Astrophysics Data System (ADS)

The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

Chiang, Yuh-Min

2002-09-01

344

Tra.Q — Laser marking for single wafer identification — Production experience from 100 million wafers  

Microsoft Academic Search

Single wafer identification is a mandatory element of a modern solar cell production [1]. It accelerates the efficiency roadmap of the solar cell and fosters the cost reduction roadmap of the fabrication. The laser marking concept Tra.Q creates an individual code on each and every wafer. This makes process optimization and quality control easier and faster. The solar cells are

Sven Wanka; David Rychtarik; Jorg Muller; Steffen Geissler; Philip Kappe; Marco Spallek; Uli vom Bauer; Christoph Ludwig; Peter Wawer

2011-01-01

345

Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking  

Microsoft Academic Search

This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer alignment accuracy and electrical connectivity. Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers. A particular concern is related to the planarization (e.g. CMP) of Cu-SiO2 hybrid surfaces: copper dishing and erosion

I. Radu; D. Landru; G. Gaudin; G. Riou; C. Tempesta; F. Letertre; L. Di Cioccio; P. Gueguen; T. Signamarcheix; C. Euvrard; J. Dechamp; L. Clavelier; M. Sadaka

2010-01-01

346

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

347

Novel on chip-interconnection structures for giga-scale integration VLSI ICS  

NASA Astrophysics Data System (ADS)

Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

Nelakuditi, Usha R.; Reddy, S. N.

2013-01-01

348

Analog VLSI Implementations of Auditory Wavelet Transforms Using Switched-Capacitor Circuits.  

National Technical Information Service (NTIS)

A general scheme for the VLSI implementation of auditory wavelet transforms is proposed using switched capacitor (SC) circuits. SC circuits are well suited for this application since the dilation constant across different scales of the transform can be pr...

J. Lin Y. Pati T. Edwards S. Shamma

1992-01-01

349

The VLSI design of a single chip Reed-Solomon encoder  

NASA Technical Reports Server (NTRS)

A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

Truong, T. K.; Deutsch, L. J.; Reed, I. S.

1982-01-01

350

Dynamic Opto-VLSI lens and lens-let generation with programmable focal length  

Microsoft Academic Search

In this paper we present and demonstrate a dynamic lens and lens array generation method with programmable focal length based on an Opto-VLSI processor. The Opto-VLSI is driven by computer generated algorithm to generate a discrete Fresnel lens phase hologram. By optimizing the phase hologram, lenses and lens arrays of different focal lengths ranging from 300mm to infinity can be

Zhenglin Wang; Kamal Alameh; Rong Zheng; Salem Adherom

2005-01-01

351

Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers  

Microsoft Academic Search

A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber

Feng Xiao; Kamal Alameh; Yong Tak Lee

2009-01-01

352

Opto-VLSI-based reconfigurable free-space optical interconnects architecture  

Microsoft Academic Search

This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The

Muhsen Aljada; Kamal E. Alameh; Yong Tak Lee; Il Sug Chung

2007-01-01

353

Opto-VLSI-based correlator architecture for multiwavelength optical header recognition  

Microsoft Academic Search

A novel optical correlator employing an opto-very-large-scale-integration (VLSI) processor to construct the routing lookup table, in conjunction with an array of fiber Bragg gratings (FBGs) for multiwavelength optical header recognition is demonstrated. The FBG array provides wavelength-dependent time delays, whereas the opto-VLSI processor generates wavelength intensity profiles that match arbitrary bit patterns. The recognition of 4-b optical patterns is experimentally

Muhsen Aljada; Kamal E. Alameh; Khalid Al-Begain

2006-01-01

354

An Extensible Object-Oriented Approach to Databases for VLSI\\/CAD  

Microsoft Academic Search

This paper describes an approach to the specification and modeling of information associated with the design and evolution of VLSI components. The approach is characterized by combined structural and behavioral descriptions of a component. Database modeling requirements specific to the VLSI design domain are considered and techniques t.o address them are described. An extensible object-oriented information management framework, the 3DIS

Hamideh Afsarmanesh; Dennis Mcleod; David Knapp; Alice C. Parker

1985-01-01

355

VLSI Photonics: How Can We Approach Using Micro\\/NanoMaterials?  

Microsoft Academic Search

This paper presents our recent results on the materials science and engineering research that we are pursuing for what we call very large scale integrated (VLSI) micro\\/nano-photonic circuit applications and optical printed circuit board (O-PCB) applications. It discusses on the design and fabrication of optical waveguides and photonic devices to be part of the micro\\/nano-photonic integration for VLSI photonic integrated

El-Hang Lee; Hyun-Shik Lee; Yong Ku Kwon; Kyong-Hon Kim; Seung-Gol Lee; Beom-Hoan O

2010-01-01

356

Making Porous Luminescent Regions In Silicon Wafers  

NASA Technical Reports Server (NTRS)

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

357

LSI\\/VLSI ion implanted GaAs IC processing  

Microsoft Academic Search

During this reporting period, growth of low dislocation GaAs crystals by the horizontal Bridgman method is reported. LEC semi-insulating substrate material from a commercial supplier of 3 inch diameter wafers was evaluated finding that three out of four ingots passed the qualification tests. The major process activities centered on the testing of processing equipment before the start of the 3

R. Zucca; A. Fistenberg

1983-01-01

358

Event-driven neural integration and synchronicity in analog VLSI.  

PubMed

Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics. PMID:23366007

Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

2012-01-01

359

VLSI-based video event triggering for image data compression  

NASA Technical Reports Server (NTRS)

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

Williams, Glenn L.

1994-01-01

360

Efficient VLSI architecture for training radial basis function networks.  

PubMed

This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

Fan, Zhe-Cheng; Hwang, Wen-Jyi

2013-01-01

361

A laser plotting system for VLSI chip layouts  

NASA Technical Reports Server (NTRS)

One of the most time consuming facets of custom Very Large Scale Integration (VLSI) design is obtaining hardcopy plots of the mask geometries of cells and chips. The traditional method of generating these plots is to use a multicolor pen plotter. Pen plotters are inherently slow and the plotting speed increases linearly with the number of edges that must be plotted. A moderate custom chip design at the Jet Propulsion Laboratory (JPL) now consists of more than 200,000 such edges and can take as much as eight hours to plot using a pen plotter. Software is described that was written at JPL to produce similar plots using a laser printer. It is shown that, for rather small layouts, the laser printer can provide nearly instantaneous turnaround. For moderate to large chip designs, the laser printer provides a factor of five or more improvement is speed over pen plotting.

Deutsch, L. J.; Harding, J. A.

1985-01-01

362

Opto-VLSI-based reconfigurable photonic RF filter  

NASA Astrophysics Data System (ADS)

Radio frequency (RF) signal processors based on photonics have several advantages, such as broadband capability, immunity to electromagnetic interference, flexibility, and light weight in comparison to all-electronics RF filters. It still requires innovative research and development to achieve high-resolution reconfigurable photonic RF signal processors featuring high selectivity, resolution, wide tunability, and fast reconfigurability. In this paper, we propose and experimentally demonstrate the concept of a reconfigurable photonic RF filter structure integrating an Amplified Spontaneous Emission (ASE) source, an Opto-VLSI processor that generates arbitrary phase-only steering and multicasting holograms for wavelength selection and attenuation, arrayed waveguide gratings (AWGs) for waveband multiplexing and demultiplexing, high-dispersion fibres for RF delay synthesis, and a balanced photodetector for generating positive and negative processor weights. Independent control of the weights of a reconfigurable photonic RF filter is experimentally demonstrated.

Xiao, Feng; Shen, Mingya; Juswardy, Budi; Alameh, Kamal

2009-08-01

363

Efficient VLSI Architecture for Training Radial Basis Function Networks  

PubMed Central

This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

Fan, Zhe-Cheng; Hwang, Wen-Jyi

2013-01-01

364

Across wafer CD uniformity optimization by wafer film scheme at double patterning lithography process  

NASA Astrophysics Data System (ADS)

The Double Patterning lithography (DPL) process is a well known method to overcome the k1 limit below 0.25, but the pattern final performance (OVL/CD) get more sensitive with the initial core CD uniformity, one of the main factors is across wafer CD uniformity control. Previous improvements applying scanner dose or PEB temperature multi-zone control, the others use the vacuum PEB plate design. In this study, we adopt various DPL sacrificial layers to modify wafer warpage level, it can adjust a suitable wafer warpage profile. By this method, we can achieve 30% CD uniformity improvement without the scanner dose/ PEB multi-zone heating compensation,

Lin, Hsiao-Chiang; Li, Yang-Liang; Wang, Shiuan-Chuan; Liu, Chien-Hung; Wang, Zih-Song; Hsuh, Jhung-Yuin

2014-04-01

365

Bubble-Free Wafer Bonding of GaAs and InP on Silicon in a Microcleanroom  

NASA Astrophysics Data System (ADS)

A technology is presented that will allow the fabrication of thin III-V compound semiconductor layers of low dislocation density on silicon substrates. GaAs and InP wafers were successfully bonded to bare and oxidized silicon substrates in an experimental setup that produces a microcleanroom for bubble-free bonding in any environment. The bonding strength was found to be comparable to that of Si on oxidized Si and sufficient to subsequent grinding and polishing of the bonded wafers.

Lehmann, V.; Mitani, K.; Stengl, R.; Mii, T.; Gösele, U.

1989-12-01

366

Electroless Ni\\/Au Bump on a Copper Patterned Wafer for the CMOS Image Sensor Package in Mobile Phones  

Microsoft Academic Search

Wafer bumping technology using an electroless Ni\\/Au bump on a Cu patterned wafer is studied for the flip chip type CMOS image\\u000a sensor (CIS) package for the camera module in mobile phones. The effect of different pretreatment steps on surface roughness\\u000a and etching of Cu pads is investigated to improve the adherence between the Cu pad and the Ni\\/Au bump.

Joong-Do Kim

2007-01-01

367

Microcantilever Probe Cards With Silicon and Nickel Composite Micromachining Technique for Wafer-Level Burn-In Testing  

Microsoft Academic Search

A new type of probe card is designed and fabricated for wafer-level integrated circuit (IC) testing. Using micromachining technology, roughly 18000 cantilever-tip probes can be integrated in one 4-in wafer, with a minimum pitch of 90 mum for adjacent probing tips. The probe card employs a silicon-and-metal composite structure, in which the bulk-micromachined silicon cantilever arrays provide uniform probing height

Fei Wang; Xinxin Li; Songlin Feng

2009-01-01

368

Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias  

Microsoft Academic Search

Three-dimensional (3D) integration is emerging as an attractive technology to continue Moore’s law through the integration of multi-stacked chips interconnected with through-silicon-vias (TSVs). To address the challenge in filling high aspect-ratio TSVs with copper, this paper reports an improved bottom-up copper electroplating (BCE) technique by introducing a glass transfer wafer, which is temporarily bonded with the device wafer to provide

Chongshen Song; Zheyao Wang; Litian Liu

2010-01-01

369

An efficient electrical addressing method using through-wafer vias for two-dimensional ultrasonic arrays  

Microsoft Academic Search

This paper presents a technology for high density and low parasitic capacitance electrical interconnects to arrays of Capacitive Micromachined Ultrasonic Transducers (CMUTs) on a silicon chip. Vertical wafer feedthroughs (vias) connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the chip. A 20 to 1 high aspect ratio 20 ?m

Ching H. Cheng; Eugene M. Chow; Xuecheng Jin; Sanli Ergun; Butrus T. Khuri-Yakub

2000-01-01

370

Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging  

Microsoft Academic Search

This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be

Fan Ji; Seppo Leppävuori; Ismo Luusua; Kimmo Henttinen; Simo Eränen; Iiro Hietanen; Mikko Juntunen

2008-01-01

371

On-wafer calibration techniques for giga-hertz CMOS measurements  

Microsoft Academic Search

This paper presents five different methods for performing on-wafer calibration of RF CMOS measurements. All methods are compatible with standard CMOS technology. A comparison of method performance up to 12 GHz is made with measurements on RF CMOS devices. The results verify that substrate and metallization losses must be considered to obtain high accuracy. Fixture design issues are discussed and

Troels Emil Kolding; Fredrik Bajers Vej

1999-01-01

372

Radar technology in ITT  

Microsoft Academic Search

With the introduction in the late 1980s and 1990s of such technologies as VLSI, GaAs monolithic circuits, integrated electrooptics, coherent fiber optics, high-power solid-state millimeter-wave sources, and specialized materials, the performance, packaging, and cost of radar systems will undergo radical changes. It is noted by way of example that low-cost GaAs monolithic transmitter\\/receivers (employing integrated optics technology) coherently fed by

R. Palmer

1982-01-01

373

Apparatus for edge etching of semiconductor wafers  

NASA Technical Reports Server (NTRS)

A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

Casajus, A.

1986-01-01

374

Low-temperature full wafer adhesive bonding  

Microsoft Academic Search

We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 µm and 18 µm. The tested polymer materials were benzocyclobutene (BCB)

Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

2001-01-01

375

Compliant Wafer Level Package for Enhanced Reliability  

Microsoft Academic Search

Wafer level package (WLP) volumes are steadily increasing due to their small package size and low manufacturing cost. However, applications to date have been mostly limited to die smaller than 5mm x 5mm. Solder joint fatigue due to stresses generated by the CTE mismatch between the die and the printed circuit board (PCB) limits adoption of WLP for large dies.

Guilian Gao; Bel Haba; Vage Oganesian; Ken Honer; David Ovrutsky; Charles Rosenstein; Ekaterina Axelrod; Felix Hazanovich; Yulia Aksenton

2007-01-01

376

Contactless magnetically levitated silicon wafer transport system  

Microsoft Academic Search

A new magnetically levitated wafer transport system is developed for the semiconductor fabrication process to get rid of the particle and oil contaminations that normally exist in conventional transport systems. The transport system consists of levitation, stabilization tracks, and a propelling system. Stabilities needed for levitation in the transport system are achieved by an antagonistic property produced in the tracks

K. H. Park; S. K. Lee; J. H. Yi; S. H. Kim; Y. K. Kwak; I. A. Wang

1996-01-01

377

On the chemo-mechanical polishing for nano-scale surface finish of brittle wafers.  

PubMed

Chemo-mechanical polishing (CMP) has been a common method to produce nano-scale surface finish of brittle wafers. This paper provides a relatively comprehensive review on the CMP of silicon, silicon carbide and sapphire including both patents and papers. The discussion includes the limitations and further research directions of the CMP technology, the material removal mechanisms, and the control and optimization of the CMP for brittle wafers. The paper concluded that the usage of mix- or coated- abrasives may improve the CMP in terms of less subsurface damage and higher material removal rate. PMID:20415661

Wang, Y G; Zhang, L C

2010-06-01

378

Bubble-domain circuit wafer evaluation coil set  

NASA Technical Reports Server (NTRS)

Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

Chen, T. T.; Williams, J. L.

1975-01-01

379

Data-driven multiprocessor for switch-level simulation of VLSI circuits  

SciTech Connect

Algorithms, architecture, and performance are described of a computer called the Fast-1 - a special-purpose machine for switch-level simulation of VLSI circuits. The Fast-1 does not implement a previously existing simulation algorithm. Rather its simulation algorithm and its architecture were developed together. The Fast-1 is data-driven, which means that the flow of data determines which instructions to execute next. Data-driven execution has several important attributes: it implements event-driven simulation in a natural way, and it makes parallelism easier to exploit. Although the architecture described has yet to be implemented in hardware, it has itself been simulated using a software implementation that allows performance to be measured in terms of read-modify-write memory cycles. The software-implemented FAST-1 runs at speeds comparable to other software-implemented switch-level simulators. Thus it was possible to collect an extensive set of experimental performance results of the Fast-1 simulating actual circuits, including some with over twenty thousand transistors. These measurements indicate that a hardware-implemented, uniprocessor Fast-1 offers several orders of magnitude speedup over software-implemented simulators running on conventional computers built using similar technology.

Frank, E.H.

1985-01-01

380

Investigation of VLSI Bipolar Transistors Irradiated with Electrons, Ions and Neutrons for Space Application  

NASA Astrophysics Data System (ADS)

A systematic investigation of radiation effects on a BICMOS technology manufactured by STM has been undertaken. Bipolar transistors were irradiated by neutrons, C, Ar and Kr ions, and recently by electrons. Fast neutrons, as well as other types of particles, produce defects mainly by displacing silicon atoms from their lattice positions to interstitial locations, i.e. generating vacancy-interstitial pairs (the so-called Frenkel pairs). Although imparted doses differ largely, the experimental results indicate that the gain (?) variation is mostly related to the non-ionizing energy-loss (NIEL) deposition for neutrons, ions and electrons. The variation of the inverse of the gain degradation, ?(1/?), is found to be linearly related (as predicted by the Messenger-Spratt equation for neutron irradiations) to the concentrations of the Frenkel pairs generated independently of the kind of incoming particle. For space applications, this linear dependence on the concentration of Frenkel pairs allows to evaluate the total amount of the gain degradation of VLSI components due to the flux of charged particles during the full life of operation of any pay-load. In fact, the total amount of expected Frenkel pairs can be estimated taking into account the isotopic spectra. It has to be point out that in cosmic rays there is relevant flux of electrons and isotopes up to Ni, which are within the range of particles presently investigated.

D'Angelo, P.; Fallica, G.; Galbiati, A.; Mangoni, R.; Modica, R.; Pensotti, S.; Rancoita, P. G.

2006-04-01

381

Evaluation of the damaged layers formed during the wafer processing of InP wafers  

Microsoft Academic Search

Double-crystal X-ray diffraction and X-ray topography were used to characterize InP wafers at various stages of polishing. InP Sn-doped single crystals were grown by the conventional LEC technique. The wafers cut from the single-crystal ingots were first lapped on both sides by alumina powders removing 80 microns from each face, etched by bromine-methanol, and then mirror-polished by Br-methanol removing 10

Y. Takahashi; T. Fukui; O. Oda

1987-01-01

382

A MEMS guide plate for a high temperature testing of a wafer level packaged die wafer  

Microsoft Academic Search

This paper describes the design and fabrication of a MEMS guide plate, which was used for a vertical probe card to test a\\u000a wafer level packaged die wafer. The size of the fabricated MEMS guide plate was 10.6 × 10.6 cm. The MEMS guide plate consisted\\u000a of 8,192 holes to insert pogo pins, and four holes for bolting between the guide plate and

Woo-Chang Choi; Jee-Youl Ryu

2011-01-01

383

Design, Process, and Reliability of Wafer Level Packaging  

Microsoft Academic Search

\\u000a Wafer level packaging (WLP) has been growing continuously in electronics packaging due to its low cost in batch manufacturing\\u000a and the potential of enabling wafer test and burn-in. A variety of wafer level packages have been devised, among which four\\u000a important categories are identified including thin film redistribution and bumping, encapsulated package, compliant interconnect,\\u000a and wafer level underfill. This chapter

Zhuqing Zhang; C. Wong

384

Study of Ag-In solder as low temperature wafer bonding intermediate layer  

NASA Astrophysics Data System (ADS)

Indium-silver as solder materials for low temperature bonding had been introduced earlier. In theory the final bonding interface composition is determined by the overall materials composition. Wafer bonding based multiple intermediate layers facilitates precise control of the formed alloy composition and the joint thickness. Thus the bonding temperature and post-bonding re-melting temperature could be easily designed by controlling the multilayer materials. In this paper, a more fundamental study of In-Ag solder materials is carried out in chip-to-chip level by using flip-chip based thermocompression bonding. Bonding at 180°C for various time duration under various bonding pressure is studied. Approaches of forming Ag IIIn with re-melting temperature higher than 400°C at the bonding interface are proposed and discussed. Knowledge learned in this process technology can support us to develop sophisticated wafer level packaging process based wafer bonding for applications of MEMS and IC packages.

Made, Riko I.; Gan, Chee Lip; Lee, Chengkuo; Yan, Li Ling; Yu, Aibin; Yoon, Seung Wook; Lau, John H.

2008-03-01

385

Wafer sub-layer impact in OPC/ORC models for advanced node implant layers  

NASA Astrophysics Data System (ADS)

From 28 nm technology node and below optical proximity correction (OPC) needs to take into account light scattering effects from prior layers when bottom anti-reflective coating (BARC) is not used, which is typical for ionic implantation layers. These effects are complex, especially when multiple sub layers have to be considered: for instance active and poly structures need to be accounted for. A new model form has been developed to address this wafer topography during model calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification (using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction and verification. This paper discusses an exploration of this new model results using extended wafer measurements (including SEM). Current results show good accuracy on various representative structures.

Le-Denmat, Jean-Christophe; Michel, Jean-Christophe; Sungauer, Elodie; Yesilada, Emek; Robert, Frederic; Lan, Song; Feng, Mu; Wang, Lei; Depre, Laurent; Kapasi, Sanjay

2014-03-01

386

First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies  

NASA Technical Reports Server (NTRS)

Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

2008-01-01

387

Development of ultra-low impedance Through-wafer Micro-vias  

NASA Astrophysics Data System (ADS)

Concurrent with our microcalorimeter array fabrication for Constellation-X technology development, we are developing ultra-low impedance Through-Wafer Micro-Vias (TWMV) as electrical interconnects for superconducting circuits. The TWMV will enable the electrical contacts of each detector to be routed to contacts on the backside of the array. There, they can be bump-bonded to a wiring fan-out board which interfaces with the front-end Superconducting Quantum Interference Device readout. We are concentrating our developmental efforts on ultra-low impedance copper and superconducting aluminum TWMV in 300-400 micron thick silicon wafers. For both schemes, a periodic pulse-reverse electroplating process is used to fill or coat micron-scale through-wafer holes of aspect ratios up to 20. Here we discuss the design, fabrication process, and recent electro-mechanical test results of Al and Cu TWMV at room and cryogenic temperatures.

Finkbeiner, F. M.; Adams, C.; Apodaca, E.; Chervenak, J. A.; Fischer, J.; Doan, N.; Li, M. J.; Stahle, C. K.; Brekosky, R. P.; Bandler, S. R.; Figueroa-Feliciano, E.; Lindeman, M. A.; Kelley, R. L.; Saab, T.; Talley, D. J.

2004-03-01

388

Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer  

SciTech Connect

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

1999-09-07

389

Characterization of Charging Control of a Single Wafer High Current Spot Beam Implanter  

SciTech Connect

This paper focuses on the characterization of charging control of an Axcelis Optima HD single wafer high current spot beam implanter using MOS capacitors with attached antennas of different size and shape. Resist patterns are implemented on Infineon Technologies own charging control wafers to investigate the influence of photo resist on charging damage. Compared to batch high current implanters the design of the beamline and the beam shape are comparable to single wafer high current spot beam implanters, however due to the different scanning architecture the dose rate of the single wafer high current spot beam implanters is significantly higher compared to the batch tools. Therefore, the risk of charging damage will be higher. The charging damage was studied as a function of the energy, the beam current and the most important plasma flood gun parameters. The results have shown that for very high antenna ratios the charging damage for single wafer implanters, even spot or ribbon beam implanters, is higher than for high current batch implanters.

Schmeide, Matthias; Bukethal, Christoph [Infineon Technologies Dresden GmbH and Co. OHG, Koenigsbruecker Str. 180, D-01099 Dresden (Germany)

2008-11-03

390

In-situ ultrasonic thermometry of semiconductor wafers  

Microsoft Academic Search

We report a temperature measurement technique based on the temperature dependence of acoustic wave velocity in silicon wafers. The zeroth order antisymmetric Lamb wave is excited in the wafer using the quartz pins which support the wafer during processing. Extensional waves are generated in the quartz pin by a PZT-SH transducer and the acoustic energy is coupled to the Lamb

F. L. Degertekin; J. Pei; Y. J. Lee; B. T. Khuri-Yakub; K. C. Saraswat

1993-01-01

391

Integrated optical waveguides in polyimide for wafer scale integration  

Microsoft Academic Search

Optical interconnections promise several key advantages over their electrical counterparts such as large bandwidth and reduced propagation delay. The limitations of electrical interconnections become even more significant for wafer scale integration (WSI), and wafer scale hybrid packaging (WSHP) because of the length of wafer scale interconnections. The authors investigate the possibility of using optically transparent organic dielectrics such as certain

R. Selvaraj; H. T. Lin; J. F. McDonald

1988-01-01

392

High density circuit technology, part 3  

NASA Technical Reports Server (NTRS)

Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations.

Wade, T. E.

1982-01-01

393

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force  

Microsoft Academic Search

This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of

Minoru Sudou; Hidekuni Takao; Kazuaki Sawada; Makoto Ishida

2007-01-01

394

Correlation between reticle- and wafer-CD difference of multiple 28nm reticle-sites  

NASA Astrophysics Data System (ADS)

Reticle critical dimension uniformity (CDU) is an important criterion for the qualification of mask layer processes. Normally, the smaller the three sigma value of reticle CDU is, the better is the reticle CDU performance. For qualification of mask processes, the mask layers to be qualified should have a comparable reticle CDU compared to the process of record (POR) mask layers. Because the reticle critical dimension (CD) measurement is based on algorithms like "middle side lobe measurement", evaluation of the reticle CD-values can not reflect aspects like the sidewall angle of the reticle and variation in corner rounding which may be critical for 45nm technology nodes (and below). All involved tools and processes contribute to the wafer intra-field CDU (scanner, track, reticle, metrology). Normally, the reticle contribution to the wafer CDU should be as small as possible. In order to reduce the process contributions to the wafer intra-field CDU during the mask qualification process, the same toolset (exposure tool, metrology tool) should be applied as for the POR. Out of the results of these investigations the correlation between wafer measurement to target (MTT) and reticle MTT can be obtained in order to accurately qualify the CDU performance of the mask processes. We will demonstrate the correlation between reticle MTT and wafer MTT by use of multiple mask processes and alternative mask blank materials. We will investigate the results of four process-layers looking at advanced binary maskblank material from two different suppliers (moreover the results of a 2X-via layer as an example for a phase-shift maskblank is discussed). Objective of this article is to demonstrate the distribution between reticle MTT and wafer MTT as a qualification criterion for mask processes. The correlation between wafer CD-difference and reticle CD-difference of these mask processes are demonstrated by having performed investigations of dense features of different 28nmtechnology process layers (poly-, active-, contact-, 1X-metal-, 2X-via layers). Referring to the correlation between wafer and reticle MTT, the contribution of the reticle CD-difference to the wafer CD-difference can be used as an evaluation method for the transfer-process of different mask sites.

Ning, Guoxiang; Richter, Frank; Thamm, Thomas; Ackmann, Paul; Staples, Marc; Weisbuch, Francois; Kurth, Karin; Schenker, Joerg; Leschok, Andre; GN, Fang Hong

2012-11-01

395

TOPICAL REVIEW: Wafer level packaging of MEMS  

NASA Astrophysics Data System (ADS)

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

Esashi, Masayoshi

2008-07-01

396

Devices using resin wafers and applications thereof  

SciTech Connect

Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

2009-03-24

397

Precipitating Chromium Impurities in Silicon Wafers  

NASA Technical Reports Server (NTRS)

Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

Salama, A. M.

1982-01-01

398

Advanced Modelling of Silicon Wafer Solar Cells  

NASA Astrophysics Data System (ADS)

Modelling of solar cells today is general practice in research and widely-used in industry. Established modelling software is typically limited to one dimension and/or to small scales. Additionally, novel effects, like, e.g., the use of diffractive structures or luminescent materials, are not established. In this paper we discuss how the combination of different modelling techniques can be used to overcome these limitations. In this context two examples are presented. The first example concerns the combination of the open source simulation software PC1D with circuit modelling to investigate the effect of local shunts on the global characteristics of a silicon wafer solar cell. For the investigated example (4.5 cm2 cell area) we find that a local point shunt reduces the solar cell efficiency by 4% relative. The second example concerns the modelling of diffractive gratings for thin silicon wafer solar cells. For this purpose, we use the rigorous coupled wave analysis to simulate Sentaurus technical computer-aided design (TCAD) is combined with the rigorous coupled wave analysis, a method to solve Maxwell's equations for periodic structures. Here we show that a grating can be used to improve the absorption in a thin silicon wafer solar cell considerably.

Peters, Marius; Fajun, Ma; Siyu, Guo; Hoex, Bram; Blaesi, Benedikt; Glunz, Stefan; Aberle, Armin; Luther, Joachim

2012-10-01

399

Evaluation of the damaged layers formed during the wafer processing of InP wafers  

NASA Astrophysics Data System (ADS)

Double-crystal X-ray diffraction and X-ray topography were used to characterize InP wafers at various stages of polishing. InP Sn-doped single crystals were grown by the conventional LEC technique. The wafers cut from the single-crystal ingots were first lapped on both sides by alumina powders removing 80 microns from each face, etched by bromine-methanol, and then mirror-polished by Br-methanol removing 10 microns from one side. The wafers were evaluated after each wafering process and then evaluated after etching for various times to reveal the depth of damaged layers. The diffraction technique revealed high levels of damage in both as-cut and as-lapped samples but no damage in the polished samples. However, the technique of X-ray topography was more sensitive than the diffraction technique, revealing microcracks (in the as-cut and the lapped wafers) at the etch depths insensitive to the diffraction technique; the mirror-polished samples were again shown to be free from damage.

Takahashi, Y.; Fukui, T.; Oda, O.

1987-04-01

400

Field-programmable smart-pixel arrays: design, VLSI implementation, and applications.  

PubMed

A smart-pixel array is a two-dimensional array of optoelectronic devices that combine optical inputs and outputs with electronic processing circuitry. A field-programmable smart-pixel array (FP-SPA) is a smart-pixel array capable of having its electronic functionality dynamically programmed in the field. Such devices could be used in a diverse range of applications, including optical switching, optical digital signal processing, and optical image processing. We describe the design, VLSI implementation, and applications of a first-generation FP-SPA implemented with the 0.8-microm complementary metal-oxide semiconductor-self-electro-optic effect device technology made available through the Lucent Technologies-Advanced Research Projects Agency Cooperative (Lucent/ARPA/COOP) program. We report spice simulations and experimental results of two sample applications: In the first application, we configure this FP-SPA as an array of free-space optical binary switches that can be used in optical multistage networks. In the second, we configure the device as an optoelectronic transceiver for a dynamically reconfigurable free-space intelligent optical backplane called the hyperplane. We also describe the testing setup and the electrical and the optical tests that demonstrate the correct functionality of the fabricated device. Such devices have the potential to reduce significantly the need for custom design and fabrication of application-specific optoelectronic devices in the same manner that field-programmable gate arrays have largely eliminated the need for custom design and fabrication of application-specific gate arrays, except in the most demanding applications. PMID:18305683

Sherif, S S; Griebel, S K; Au, A; Hui, D; Szymanski, T H; Hinton, H S

1999-02-10

401

Routing the power and ground wires on a VLSI chip  

NASA Astrophysics Data System (ADS)

This thesis presents four new algorithms to route noncrossing power and ground trees in one metal layer of a VLSI chip. The implementation of the best algorithm forms MIT's Placement-Interconnect (PI) Projects power-ground routing phase. The input of this power-ground algorithm is a set of rectangular modules on a rectangular chip. Because of bonding limitations, the pads are placed along the chip's perimeter, while the logic modules are placed in the interior. In constructing the power-ground layout, the algorithm first lays a ground ring between the pads and the chip's perimeter, then a power ring between the logic modules and the pads. Next, a tree of wires connects the ground pad with the logic modules' ground connection points. Then, starting at various points on the power ring, several branches of wires connect the power ring to the logic modules' power connection points. A tree-traversal algorithm then uses the modules' current requirements to determine how much current will flow through each power-ground wire during the chip's operation. An algorithm then widens each wire to the width appropriate for carrying that current.

Moulton, A. S.

1984-07-01

402

A VLSI decomposition of the deBruijn graph  

NASA Technical Reports Server (NTRS)

A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

Collins, O.; Dolinar, S.; Mceliece, R.; Pollara, F.

1990-01-01

403

Discounts for dynamic programming with applications in VLSI processor arrays  

SciTech Connect

This dissertation introduces a method for transforming certain dynamic programming problems into ones that require less space and time to solve under the logarithmic cost criterion, an appropriate complexity measure for flexible word-length machines. The mapping is based on discounts that change the costs but not the identities of optimal policies. Under the proper circumstances, the structure present in the original problem is preserved in the image so that the functional equations of dynamic programming still apply. Practical value of the theory is illustrated by demonstrating that a previously published VLSI processor array can be made asymptotically smaller and faster. The second half of this work addresses issues that arise in parallel sequence comparison. The paradigm here is deoxyribonucleic acid (DNA) which maybe considered a string over a four-character alphabet. It is shown how a number of popular sequence matching algorithms can be mapped onto linear arrays of processors. One of these, the Princeton Nucleic Acid Comparator (P-NAC), has been fabricated, tested, and found to work perfectly. Its efficient implementation is due entirely to an application of discounts; benchmark results prove that it is several hundred times faster than a minicomputer.

Lopresti, D.P.

1987-01-01

404

Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process  

NASA Astrophysics Data System (ADS)

Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements™) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

2013-09-01

405

Wafer surface pre-treatment study for micro bubble free of lithography process  

NASA Astrophysics Data System (ADS)

Photo resist micro bubble and void defect is reported as a typical and very puzzle defect type in photo lithography process, it becomes more and more significantly and severely with the IC technology drive towards 2× node. Introduced in this paper, we have studied the mechanism of photo resist micro bubble at different in-coming wafer surface condition and tested a series of pre treatment optimization method to resolve photo resist micro bubble defect on different wafer substrate, including in the standard flat and smooth wafer surface and also in special wafer surface with high density line/space micro-structure substrate as is in logic process FinFET tri-gate structure and Nor type flash memory cell area Floating Gate/ONO/Control Gate structure. As is discovered in our paper, in general flat and smooth wafer surface, the photo resist micro bubble is formed during resist RRC coating process (resist reduction coating) and will easy lead to Si concave defect after etch; while in the high density line/space micro-structure substrate as FinFET tri-gate, the photo resist void defect is always formed after lithography pattern formation and will final cause the gate line broken after the etching process or localized over dose effect at Ion IMP layers. The 2nd type of photo resist micro bubble is much more complicated and hard to be eliminated. We try to figure out the interfacial mechanism between different type of photo resist (ArF, KrF and I-line) and pre-wet solvent by systematic methods and DOE splits. And finally, we succeeded to dig out the best solution to eliminate the micro bubble defect in different wafer surface condition and implement in the photolithography process.

Yang, Xiaosong; Zhu, XiaoZheng; Cai, Spencer

2014-04-01

406

Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size  

NASA Astrophysics Data System (ADS)

For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

2013-06-01

407

Characterization of semiconductor surface-emitting laser wafers  

SciTech Connect

The development of epitaxial semiconductor surface-emitting lasers has begun in recent years. These lasers are ultra-short (few {mu}m) Fabry-Perot resonators comprising epitaxial multilayer semiconductor mirrors and quantum well active regions. The resonators are single crystals grown along the lasing axis by molecular beam epitaxy (MBE) or chemical vapor deposition (CVD). They offer significant advances over conventional cleaved, edge-emitting lasers for creating lasers with single elements of 2 dimensional arrays, low beam divergence, engineered active regions, single longitudinal modes, and improved temperature characteristics. To realize the high potential of these new laser structures, techniques for characterizing the laser wafer after growth and between fabrication steps must be developed. In this paper we discuss several optical techniques that we have developed for this emerging surface-emitting laser technology.

Gourley, P.L.; Vawter, G.A.; Brennan, T.M.; Hammons, B.E.

1990-01-01

408

Product assurance technology efforts: Technical accomplishments  

NASA Technical Reports Server (NTRS)

Product assurance technology topics addressed include: wafer acceptance procedures, test chips, test structures, test chip methodology, fault models, and the Combined Release and Radiation Effects Satellite test chip.

1985-01-01

409

High-speed VLSI networks for computing the discrete fourier transform  

SciTech Connect

The authors propose a VLSI design for computing the discrete Fourier transform that can be used to implement the general Winograd algorithm or Good's algorithm when it is based on the Winograd type small n DFTs. The design is simple and makes extensive use of parallelism and pipelining. The corresponding network has two basic memory units: a ROM is used to store the small n algorithms, and a two-dimensional memory of shift registers is used to store the intermediate results. The processing part consists basically of two units: a two-dimensional mesh of adders and a set of multipliers. The control can be implemented in VLSI and it is only slightly more complicated than the one required by FFT. It is shown that the performance of the design is the best possible in a certain sense and that Winograd's algorithm will offer an advantage over FFT in VLSI. 21 references.

Ja'ja', J.

1984-01-01

410

Thinning of PLZT ceramic wafers for sensor integration  

NASA Astrophysics Data System (ADS)

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300?m. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10?m, the surface roughness was below 1nm in rms, and the flatness was better than ?/5.

Jin, Na; Liu, Weiguo

2010-08-01

411

Evaluation of the damaged layers formed during the wafer processing of InP wafers  

SciTech Connect

InP is now becoming a very promising material for substrates in the application of laser diodes, light emitting diodes, and high speed FET's. In this context, high quality polishing is desired in such a way that no damaged layer is detected. However, very little attention has been paid to the quantitative characterization of the polishing process. There is only a report concerned with the characterization of mirror-polished InP wafers. In the present work, the authors applied double-crystal x-ray diffraction and x-ray topography for the evaluation of InP wafers in various polishing stages.

Takahashi, Y.; Fukui, T.; Oda, O.

1987-04-01

412

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging  

NASA Astrophysics Data System (ADS)

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

2014-07-01

413

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.  

PubMed

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-01

414

Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins  

NASA Astrophysics Data System (ADS)

Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

Müller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

2014-04-01

415

Wafer bonding of gallium arsenide on sapphire  

Microsoft Academic Search

\\u000a $1\\\\overline{1} 02$  ) sapphire in a micro-cleanroom at room temperature under hydrophilic or hydrophobic surface conditions. Subsequent heating\\u000a up to 500 °C increased the bond energy of the GaAs-on-sapphire (GOS) wafer pair close to the fracture energy of the bulk material.\\u000a The bond energy was measured as a function of the temperature. Since the thermal expansion coefficients of GaAs and sapphire\\u000a are close to

P. Kopperschmidt; G. Kästner; S. Senz; D. Hesse; U. Gösele

1997-01-01

416

A fast lightstripe rangefinding system with smart VLSI sensor  

NASA Technical Reports Server (NTRS)

The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

1989-01-01

417

Recent Advances in Machining of Silicon Wafers for Semiconductor Applications  

Microsoft Academic Search

Silicon wafers are used world-wide for the production of microchips. Silicon is a hard and brittle material. Conversion of\\u000a silicon ingots into polished wafers requires much processing including machining and chemical processing. The machining is\\u000a critical to high-quality standards. With the development of new components, the eletronic industries require hgher standards\\u000a for total thickness variation and also wafer warp. This

P. S. Sreejith; G. Udupa; Y. B. M. Noor; B. K. A. Ngoi

2001-01-01

418

Through-wafer copper electroplating for three-dimensional interconnects  

Microsoft Academic Search

Through-wafer electrical connections are becoming increasingly important for three-dimensional integrated circuits, microelectromechanical systems packaging and radio-frequency components. In this paper, we report our current results on the formation of through-wafer metal plugs using the copper electroplating technique. Several approaches for via filling are investigated, such as filling before or after wafer thinning. Among the methods experimented, the one-side Cu plating

N T Nguyen; E Boellaard; N P Pham; V G Kutchoukov; G Craciun; P M Sarro

2002-01-01

419

Scalability potential in ELTRAN(R) SOI-epi wafer  

Microsoft Academic Search

For coming device applications, advanced requirements for silicon-on-insulator (SOI) wafers are increasing. One of the most important items is scalability that includes scaling up of the wafer diameter and scaling down of the SOI layer thickness (tSOI). 300 mm wafers and ultra thin SOI with tSOI less than 100 nm will be required according to the ITRS (SIA, 1999). 300

M. Ito; K. Yamagata; H. Miyabayashi; T. Yonehara

2000-01-01

420

Direct To Digital Holography For High Aspect Ratio Inspection of Semiconductor Wafers  

NASA Astrophysics Data System (ADS)

Direct to Digital Holography (DDH) has been developed as a semiconductor wafer inspection tool and in particular as a tool for seeing defects in high aspect ratio (HAR) structures on semiconductor wafers and also for seeing partial-height defects. While the tool works very well for general wafer inspection, it has unusual capabilities for high aspect ratio inspection (HARI) and for detecting thin residual film defects (partial height defects). Inspection of HAR structures is rated as one of the highest unmet priorities of the member companies of International SEMATECH, and finding residual thin film defects (in some cases called ``stringers'') is also a very difficult challenge. The capabilities that make DDH unusually sensitive include: 1) the capture of the whole wave-both the classical amplitude captured by traditional optical systems, and the phase of the wave, with phase potentially measured to ~1/1000'th of a wavelength or ~2 to 3 Angstroms for a deep ultra-violet (DUV) laser; 2) heterodyne detection-this allows it to capture very low signal levels; and 3) a head-on geometry using a collimated laser beam that allows best penetration of HAR structures. The basic features and methods of this patented technology are presented, along with simple calculations of signal strength and expected noise levels for various circumstances. Full-wave numerical calculations of electromagnetic field penetration into HAR contacts and experimental results from various wafer types and structures are also presented.

Thomas, C. E. (Tommy); Hunt, Martin A.; Bahm, Tracy M.; Baylor, Larry R.; Bingham, Philip R.; Chidley, Matthew D.; Dai, Xiaolong; Delahanty, Robert J.; El-Khashab, Ayman; Gilbert, Judd M.; Goddard, James S.; Hanson, Gregory R.; Hickson, Joel D.; Hylton, Kathy W.; John, George C.; Jones, Michael L.; Mayo, Michael W.; Marek, Christopher; Price, John H.; Rasmussen, David A.; Schaefer, Louis J.; Schulze, Mark A.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin, Kenneth W.; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Owen, Robert W.

2003-09-01

421

6W/25mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing  

NASA Astrophysics Data System (ADS)

Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6W/25mm2 power transfer density over a distance of up to 0.32mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits.

Radecki, Andrzej; Chung, Hayun; Yoshida, Yoichi; Miura, Noriyuki; Shidei, Tsunaaki; Ishikuro, Hiroki; Kuroda, Tadahiro

422

Micro-miniature gas chromatograph column disposed in silicon wafers  

DOEpatents

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, Conrad M. (Antioch, CA)

2000-01-01

423

Neutron guidance by internal reflections in thin silicon wafers  

NASA Astrophysics Data System (ADS)

We have performed cold neutron longitudinal transmission measurements through single crystal silicon wafers of 200 ?m thickness and 50 mm length which have been coated on both sides with nickel to form microguides. Rocking curve measurements with neutrons of a wavelength of 7 Å have been conducted on assemblies of straight wafers placed end-to-end for neutron pathways in silicon from 50 to 200 mm, and on curved wafers. In addition, transmission measurements have been carried out on a straight wafer as a function of wavelength. We find that the reflectivity for the internal silicon-nickel interface is 0.988±0.005.

Grüning, U.; Magerl, A.; Mildner, D. F. R.

1992-04-01

424

Micro-miniature gas chromatograph column disposed in silicon wafers  

SciTech Connect

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, C.M.

2000-05-30

425

Novel wafer stepper with violet LED light source  

NASA Astrophysics Data System (ADS)

Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

Ting, Yung-Chiang; Shy, Shyi-Long

2014-03-01

426

Improved near surface heavy impurity detection by a novel charged particle energy filter technique.  

National Technical Information Service (NTIS)

As the typical feature size of silicon integrated circuits, such as in VLSI technology, has become smaller, the surface cleanliness of silicon wafers has become more important. Hence, detection of trace impurities introduced during the processing steps is...

K. Ishibashi B. K. Patnaik N. R. Parikh H. Tateno J. D. Hunn

1994-01-01

427

TECHNICAL NOTE: Deep etching of glass wafers using sputtered molybdenum masks  

NASA Astrophysics Data System (ADS)

This note presents a simple, low-cost technology to fabricate very deep isotropically etched features in glass wafers. A process based on fast etching glass combined with a stress-optimized molybdenum mask layer and a photoresist was found to be very suitable for such purposes. The obtained performance, up to 1.2 mm deep etching, rivals the best existing techniques while being more cost-competitive and using widely available equipment.

Ceyssens, Frederik; Puers, Robert

2009-06-01

428

Electrostatic microactuators fabricated using deep RIE and wafer bonding for hard disk drives  

Microsoft Academic Search

A bulk micromachined three-dimensional electrostatic microactuator, used for a hard disk drive dual-stage positioning system, was developed using deep RIE and wafer bonding technologies. The actuators, arranged as vertical comb drives, thereby enhance the electrostatic driving force. By using the proper flexures, the secondary stage actuator drives the R\\/W magnetic head with a high frequency and accuracy. Micro fabrication of

Bangtao Chen; Jianmin Miao

2004-01-01

429

Development of ultra-low impedance Through-wafer Micro-vias  

Microsoft Academic Search

Concurrent with our microcalorimeter array fabrication for Constellation-X technology development, we are developing ultra-low impedance Through-Wafer Micro-Vias (TWMV) as electrical interconnects for superconducting circuits. The TWMV will enable the electrical contacts of each detector to be routed to contacts on the backside of the array. There, they can be bump-bonded to a wiring fan-out board which interfaces with the front-end

F. M. Finkbeiner; C. Adams; E. Apodaca; J. A. Chervenak; J. Fischer; N. Doan; M. J. Li; C. K. Stahle; R. P. Brekosky; S. R. Bandler; E. Figueroa-Feliciano; M. A. Lindeman; R. L. Kelley; T. Saab; D. J. Talley

2004-01-01

430

A VLSI implementation of PDF computations in HMM based speech recognition  

Microsoft Academic Search

We present an architecture and VLSI implementation of the computations of Gaussian observation probabilities in HMM based speech recognition. As opposed to the previous work of Sagayama and Takahashi (see IEEE International Conf. on Acoustics, Speech and Signal Proc., vol.1, p.213-16, 1995), reducing the number of arithmetic operations is not the major concern when these computations are implemented in a

J. Pihl; T. Svendsen; M. H. Johnsen

1996-01-01

431

VLSI chip-set for data compression using the Rice algorithm  

NASA Technical Reports Server (NTRS)

A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

Venbrux, J.; Liu, N.

1990-01-01

432

Designing VLSI network nodes to reduce memory traffic in a shared memory parallel computer  

Microsoft Academic Search

Serialization of memory access can be a critical bottleneck in shared memory parallel computers. The NYU Ultracomputer, a large-scale MIMD (multiple instruction stream, multiple data stream) shared memory architecture, may be viewed as a column of processors and a column of memory modules connected by a rectangular network of enhanced 2×2 buffered crossbars. These VLSI nodes enable the network to

Susan Dickey; Allan Gottlieb; Richard Kenner; Yue-Sheng Liu

1987-01-01

433

Designing VLSI Network Nodes to Reduce Memory Traffic in a Shared Memory Parallel Computer  

Microsoft Academic Search

Serialization of memory access can be a critical bottleneck in shared memory parallel computers. The NYU Ultracomputer, a large-scale MIMD (Multiple Instruction stream, Multiple Data stream) shared memory architec- ture, may be viewed as a column of processors and a column of memory modules connected by a rectangular net- work of enhanced two by two buffered crossbars. These VLSI nodes

Susan Dickey; Allan Gottlieb; Richard Kenner; Yue-Sheng Liu

1986-01-01

434

On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects  

Microsoft Academic Search

This paper presents a comprehensive study of the applicability of single-walled carbon nanotubes (SWCNTs) as interconnects in nanoscale integrated circuits. A detailed analysis of SWCNT interconnect resistance (considering its dependence on all physical parameters, as well as factors affecting the contact resistance), the first full 3-D capacitance simulations of SWCNT bundles for realistic very large scale integration (VLSI) interconnect dimensions,

Navin Srivastava; Hong Li; Franz Kreupl; Kaustav Banerjee

2009-01-01

435

Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor  

Microsoft Academic Search

In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on

Muhsen Aljada; Rong Zheng; Kamal Alameh; Yong-Tak Lee

2007-01-01

436

A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar  

NASA Technical Reports Server (NTRS)

For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

Fang, W.

1994-01-01

437

Realistic and efficient simulation of electro-thermal effects in VLSI circuits  

Microsoft Academic Search

Needs for electro-thermal simulation of VLSI circuits, as opposed to both the system and device levels, are analyzed. A system capable of modeling these effects in a realistic and sufficiently accurate way that uses a reasonable amount of CPU resources is presented. An innovative solver is also proposed. The system is used to study the importance of some three dimensional

Mohamed-Nabil Sabry; Anne Bontemps; Veronique Aubert; Reinhold Vahrmann

1997-01-01

438

VLSI module placement based on rectangle-packing by the sequence-pair  

Microsoft Academic Search

The earliest and the most critical stage in VLSI layout design is the placement. The background of which is the rectangle packing problem: Given set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is

Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani

1996-01-01

439

A Framework for High Level Estimations of Signal Processing VLSI Implementations  

Microsoft Academic Search

This paper deals with the presentation of a framework for the rapid prototyping of Digital Signal Processing applications. The BSS framework enables both synthesis of dedicated VLSI circuits and cost, performance estimation. The latter can be used at different accuracy levels and can help the designer in selecting a proper algorithm in order to improve the global performance of its

Jean-philippe Diguet; Daniel Chillet; Olivier Sentieys

2000-01-01

440

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform  

Microsoft Academic Search

Using the lifting scheme to construct VLSI architectures for discrete wavelet transforms outperforms using convolution in many aspects, such as computation complexity and boundary extension. Nevertheless, the critical path of the lifting scheme is potentially longer than that of convolution. Although pipelining can reduce the critical path, it will prolong the latency and require more registers for a 1D architecture

Chao-tsung Huang; Po-chih Tseng; Liang-gee Chen

2002-01-01

441

An algorithm to compact a VLSI symbolic layout with mixed constraints  

Microsoft Academic Search

A popular algorithm to compact a VLSI symbolic layout is to use a graph algorithm similar to finding the 'longest-path' in a network. The algorithm assumes that the spacing constraints on the mask elements are of the lower-bound type. However, to enable the user to have close control over the compaction result, a desired symbolic layout system should allow the

Yuh-Zen Liao; Chak-Kuen Wong

1983-01-01

442

Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical Constraints  

Microsoft Academic Search

Local Optimality paradigm is applicable to all combinatorial optimization problems. Its direct field of application are the constructive solution algorithm; its main advantage is the low computational cost for multiple high quality initial solutions for iterative improvement algorithms. The application of the paradigm to the VLSI channel routing has necessitated the creation of new knowledge represented by the theory of

Anthony D. Johnson

1998-01-01

443

ALLIANCE: A complete Set of CAD Tools for teaching VLSI Design  

Microsoft Academic Search

The ALLIANCE package is a complete set of CAD tools for teaching VLSIdesign. ALLIANCE aims at allowing universities to start and develop VLSI designactivities without too much time and money investments. Each ALLIANCE toolcan operate as a standalone program as well as a part of the complete designframework. The basic design flow is first presented, then each tool is reviewed.Experience

Alain Greiner

1992-01-01

444

Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI  

Microsoft Academic Search

In this paper, we obtain the lower bounds on total energy dissipation of deep submicron (DSM) VLSI circuits via an information-theoretic framework. This framework enables the derivation of lower bounds under the constraint of reliable operation in presence of DSM noise. We employ noise-tolerance via coding to approach the lower bounds on energy dissipation. It is shown that the lower

Rajamohana Hegde; Naresh R. Shanbhag

1999-01-01

445

Real-Time Analog VLSI Sensors for 2-D Direction of Motion  

Microsoft Academic Search

. Optical flow fields are a primary source of information aboutthe visual scene in technical and biological systems. In a step towards asystem for real time scene analysis we have developed two new algorithmsfor the parallel computation of the direction of motion field in 2-D. Wehave successfully implemented these algorithms in analog VLSI hardwaresuch that all processing is performed in

Rainer A. Deutschmann; Charles M. Higgins; Christof Koch

1997-01-01

446

A VLSI architecture for hierarchical mesh based motion compensation using scalable affine transformation core  

Microsoft Academic Search

This paper presents a VLSI architecture for hierarchical mesh based motion compensation. It uses a hierarchical adaptive structured mesh, which minimizes the number of bits describing the mesh. The mesh is constructed as triangular patches that describe the motion at different resolutions. Image warping is used to reconstruct the frame, whereas an affine transformation is used to texture map the

Wael Badawy; Guoqing Zhang; Mike Talley; Magdy Bayoumi

2000-01-01

447

The Feasibility of a VLSI Chip for Ray Tracing Bicublic Patches  

Microsoft Academic Search

In this article we explore the possibility of a VLSI chip for ray tracing bicubic patches in Bezier form. The purpose of the chip is to calculate the intersection point of a ray with the bicubic patch to a specified level of accuracy, returning parameter values (u,v) specifying the location of the intersection on the patch, and a parameter value,

Ron Pulleyblank; John Kapenga

1987-01-01

448

Low-temperature thin-film indium bonding for reliable wafer-level hermetic MEMS packaging  

NASA Astrophysics Data System (ADS)

This paper reports on low-temperature and hermetic thin-film indium bonding for wafer-level encapsulation and packaging of delicate and temperature sensitive devices. This indium-bonding technology enables bonding of surface materials commonly used in MEMS technology. The temperature is kept below 140?°C for all process steps and no surface treatment is applied before and during bonding. This bonding technology allows hermetic sealing at 140?°C with a leak rate below 4?×?10-12?mbar l s-1 at room temperature. The tensile strength of the bonds up to 25 MPa goes along with a very high yield.

Straessle, R.; Pétremand, Y.; Briand, D.; Dadras, M.; de Rooij, N. F.

2013-07-01

449

Foundations of software technology and theoretical computer science  

Microsoft Academic Search

The papers in this book report on foundations of software technology and theoretical computer science project research results. The authors report on algorithmics: design and analysis of graph, geometric, algebraic and VLSI algorithms; data structures; average analysis; complexity theory; parallel parsing; concurrency; algebraic semantics, event structures; logic programming; algebraic properties, semantics; and software technology: program transformations, algebraic methods. These results

Madhavan

1990-01-01

450

Through silicon vias technology for CMOS image sensors packaging  

Microsoft Academic Search

In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. The design rules of the vias will be briefly described and then, the steps of the technology will be presented : glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific

D. Henry; F. Jacquet; M. Neyret; X. Baillin; T. Enot; V. Lapras; C. Brunet-Manquat; J. Charbonnier; B. Aventurier; N. Sillon

2008-01-01

451

Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks.  

NASA Astrophysics Data System (ADS)

This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for quantitative computation, as well as qualitative.

Kirk, David Blair

452

CMOS VLSI Active-Pixel Sensor for Tracking  

NASA Technical Reports Server (NTRS)

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

453

MEMS-Based Probe Array for Wafer Level LSI Testing Transferred onto Low CTE LTCC Substrate by Au\\/Sn Eutectic Bonding  

Microsoft Academic Search

This paper describes the fabrication technology of a new MEMS-based probe card. The probe card is designed to satisfy requirements from advanced wafer-level, burn-in LSI tests. The problem of thermal expansion mismatch between the probe card and LSI wafers is solved by using a LTCC (low temperature cofired ceramics) substrate with a coefficient of thermal expansion of 3.4 ppm\\/degC. The

S.-H. Choe; S. Tanaka; M. Esashi

2007-01-01

454

Determination of bending stress of Si wafer using concentrated load  

Microsoft Academic Search

The technique of concentrated load with a simple O-ring supporter is used to measure the deflection of Si wafers. The load varies so that the ratio of the deflection to the wafer thickness changes from 0 to 1. For some samples, this ratio goes up to 1.4 at which the samples are fractured. It is observed in the experiment that

L. D. Chen; M. J. Zhang; S. Zhang

1994-01-01

455

Embedded PZT Wafer Sensors for Structural Health Monitoring  

Microsoft Academic Search

Recent advances in structural integrity evaluation have led to the development of PZT wafer sensors (PWAS) which can be embedded or surface mounted for both acoustic emission (AE) and ultrasonic (UT) modes, which forms an integrated approach for Structural Health Monitoring (SHM) of aerospace structures. For the fabrication of PWAS wafers, soft PZT formulation (SP-5H Grade containing dopants like BA,

R. Gangadharan; C. R. L. Murthy; M. R. Bhat; A. Sen; N. Das; A. Seal

2007-01-01

456

Sealing of adhesive bonded devices on wafer level  

Microsoft Academic Search

In this paper, we present a low temperature wafer-level encapsulation technique to hermetically seal adhesive bonded microsystem structures by cladding the adhesive with an additional diffusion barrier. Two wafers containing cavities for MEMS devices were bonded together using benzocyclobutene (BCB). The devices were sealed by a combined dicing and self-aligning etching technique and by finally coating the structures with evaporated

Joachim Oberhammer; Frank Niklaus; Göran Stemme

2004-01-01

457

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Selwyn, Gary S. (Los Alamos, NM)

1998-01-01

458

Soft Configurable Wafer Scale Integration: Design, Implementation and Yield Analysis.  

National Technical Information Service (NTIS)

Soft-Configurable Wafer Scale Integration uses software controlled switches to connect up the fault-free parts of a wafer. Compared to hard configuration, the soft configurable approach has the advantages of providing low-cost connections and runtime faul...

M. G. Blatt

1990-01-01

459

Height Inspection of Wafer Bumps Without Explicit 3-D Reconstruction  

Microsoft Academic Search

Die bonding in the semiconductor industry requires placement of solder bumps not on PCBs but on wafers. Such wafer bumps, which are much miniaturized from their counterparts on printed circuit boards (PCBs), require their heights meet rigid specifications. Yet the small size, the lack of texture, and the mirror-like nature of the bump surface make the inspection task a challenge.

Mei Dong; Ronald Chung; Edmund Y. Lam; Kenneth S. M. Fung

2010-01-01

460

Shift scheduling for steppers in the semiconductor wafer fabrication process  

Microsoft Academic Search

In this paper, an approach is proposed for scheduling stepper machines that are acting as bottleneck machines in the semiconductor wafer fabrication process. We consider the problem of scheduling the steppers for an 8 hour shift, determining which types of wafer lots to work on each machine. The scheduling objective is to find the optimal stepper allocations such that the

Sooyoung Kim; Seung-Hee Yea; Bokang Kim

2002-01-01

461

Room Temperature Si\\/Si Wafer Direct Bonding in Air  

Microsoft Academic Search

Wafer direct bonding technique offers flexible and inexpensive ways to fabricate novel semiconductor devices. But its application is much limited by high temperature process and void problem. In this study, room temperature Si\\/Si wafer direct bonding has been performed using sequential plasma pretreatment prior to bonding. A shorter O2 reactive ion etching (RIE) pretreatment (~10 s) and followed by N2

Chenxi Wang; Eiji Higurashi; T. Suga

2007-01-01

462

Alternative facility layouts for semiconductor wafer fabrication facilities  

Microsoft Academic Search

Semiconductor wafer fabrication facilities are widely acknowledged to be among the most complicated industrial systems from a production planning and control point of view. The design of most wafer fabrication facilities has followed the process layout, where similar machines are located together. This feeds to complex, reentrant product flows through the facility. In this paper, we examine the effects on

Christopher D. Geiger; Rieko Hase; Christos G. Takoudis; Reha Uzsoy

1997-01-01

463

P/N Inp Solar Cells on Ge Wafers.  

National Technical Information Service (NTIS)

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick ...

S. Wojtczuk S. Vernon E. A. Burke

1994-01-01

464

Infrared spectroscopy of wafer-scale graphene.  

PubMed

We report spectroscopy results from the mid- to far-infrared on wafer-scale graphene, grown either epitaxially on silicon carbide or by chemical vapor deposition. The free carrier absorption (Drude peak) is simultaneously obtained with the universal optical conductivity (due to interband transitions) and the wavelength at which Pauli blocking occurs due to band filling. From these, the graphene layer number, doping level, sheet resistivity, carrier mobility, and scattering rate can be inferred. The mid-IR absorption of epitaxial two-layer graphene shows a less pronounced peak at 0.37 ± 0.02 eV compared to that in exfoliated bilayer graphene. In heavily chemically doped single-layer graphene, a record high transmission reduction due to free carriers approaching 40% at 250 ?m (40 cm(-1)) is measured in this atomically thin material, supporting the great potential of graphene in far-infrared and terahertz optoelectronics. PMID:22077967

Yan, Hugen; Xia, Fengnian; Zhu, Wenjuan; Freitag, Marcus; Dimitrakopoulos, Christos; Bol, Ageeth A; Tulevski, George; Avouris, Phaedon

2011-12-27

465

The investigation on research opportunities for the applications of the Internet of Things in semiconductor wafer fabrication  

Microsoft Academic Search

Based on the state-of-the-art technologies of the Internet of Things (IOT) and Radio Frequency Identifier (RFID) this paper introduces the concepts of IOT\\/RFID and investigates its open research opportunity and potential applications in real-time monitoring and dispatch controls for semiconductor wafer fabrication (FAB).

Yong-Zai Lu

2010-01-01

466

Top-down fabricated silicon-nanowire-based field-effect transistor device on a (111) silicon wafer.  

PubMed

The unique anisotropic wet-etching mechanism of a (111) silicon wafer facilitates the highly controllable top-down fabrication of silicon nanowires (SiNWs) with conventional microfabrication technology. The fabrication process is compatible with the surface manufacturing technique, which is employed to build a nanowire-based field-effect transistor structure on the fabricated SiNW. PMID:23143874

Yu, Xiao; Wang, Yuchen; Zhou, Hong; Liu, Yanxiang; Wang, Yi; Li, Tie; Wang, Yuelin

2013-02-25

467

Microsystems and wafer processes for volume production of highly reliable fiber optic components for telecom and datacom-application  

Microsoft Academic Search

In realizing an efficient volume production of highly reliable active fiberoptic components the microsystem-technique was one of the most important factors. Micro-mechanical methods allow large scale fabrication of micro optical silicon lenses with methods, machines and materials using standard semiconductor wafer technology. With micromechanical processes, such as anodic bonding of optical components and special solder bonding techniques, it is possible

H. L. Althaus; W. Gramann; K. Panzer

1998-01-01

468

Investigations of Wafer Scale Etching with Xenon Difluoride  

NASA Astrophysics Data System (ADS)

A good and uniform bulk silicon wafer etching method can be applied to the wafer thinning process in MEMS and 3D applications. In this study, the use of a Xenon Difluoride (XeF2) gas-phase etching system, operating at room temperature, has been investigated for bulk silicon wafer thinning. We investigated the Si-wafer surface morphology and profile following each XeF2 etching process cycle. Theoretical results are used to compare with the experimental results as well. A clean wafer surface by proper surface treatments is significant to achieve a uniform surface profile and morphology for XeF2 etching. A proper design of etching cycle with nitrogen ambient during etching is necessary to achieve the fastest and uniform silicon etching rate. The silicon etching rate is reported as a function of etching pressure, nitrogen pressure, and etching duration.

Chen, K. N.; Hoivik, N.; Lin, C. Y.; Young, A.; Ieong, M.; Shahidi, G.

2006-03-01

469

Reduction of Thermal Conductivity in Wafer-Bonded Silicon  

SciTech Connect

Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

2006-11-27

470

A novel technique for cleaning semiconductor wafers using ultrasonic transducer  

NASA Astrophysics Data System (ADS)

An experiment was designed based on U.S. Patent no. 6,766,813 which describes a process that effectively cleans a semiconductor wafer with the help of ultrasonic vibrations. The semiconductor wafer was freely supported by a hollow cylindrical box made of foam. Two commonly occurring contaminants found on wafers in the industry are silicon and silicon dioxide. Micrometer sizes of these two materials were used to replicate contaminants that commonly occur in the industry. The wafer was then excited with the help of an ultrasonic transducer in the aim of knocking off these contaminants from the surface of the semiconductor wafer. Particle counts were taken with the help of a modified optical microscope before and after applying the ultrasonic vibration in order to determine the effectiveness of this technique.

Nakade, Rugved; Yow, Raylon; Sayka, Tony; Sardar, Dhiraj

2006-10-01

471

Methodology for Producing and Testing a Genesil Silicon Compiler Designed VLSI Chip Which Incorporates Design for Testability.  

National Technical Information Service (NTIS)

Testability issues concerning the need for including Design for Testability (DFT) techniques in VLSI (Very Large Scale Integration) designs are discussed. Types of fault models, the use of fault simulation and the DFT techniques of Scan Path and Built in ...

B. L. Pooler

1990-01-01

472

Rapid defect detections of bonded wafer using near infrared polariscope  

NASA Astrophysics Data System (ADS)

In modern field of microelectronics and MEMS, wafer bonding has emerged as an important processing step in wide range of manufacturing applications. During the manufacturing process, even in the modern clean room, small defects result from trapped particles and gas bubbles exist at bonded interface. Defects and trapped particles may exist on the top and bottom of the wafers, or at the interface of bonded wafer pair. These inclusions will generate high stress around debond region at the wafers bonded interface. In this paper, inspection at the bonded interface will be the interest of investigation. Since silicon wafer is opaque to visible light, defect detection at the bonded interface of silicon wafer is not possible. Due to the fact that silicon wafer is transparent to wavelength greater than 1150nm, an Near Infrared Polariscope which has showed some promises on residual stress measurement on silicon devices has been adapted and developed. This method is based on the well known photoelastic principles, where the stress variations are measured based on the changes of light propagation velocity in birefringence material. The results are compared and contrast with conventional Infrared Transmission Imaging tool (IRT) which is widely used to inspect the bonded silicon wafer. In this research, the trapped particles that are not visible via conventional infrared transmission method are identified via the generated residual stress pattern. The magnitude of the residual stress fields associated with each defect is examined qualitatively and quantitatively. The stress field generated at the wafers bonded interface will looks like a 'butterfly' pattern. Wafer pairs Pyrex-Si and Si-Si bonded interface will be examined.

Ng, Chi Seng; Asundi, Anand K.

2011-09-01

473

Direct Wafer Bonding of GaInAsP/InP Membrane Structure on Silicon-on-Insulator Substrate  

NASA Astrophysics Data System (ADS)

Wafer bonding technology was investigated to integrate active photonic devices on a silicon-on-insulator (SOI) substrate for highly compact photonic integrated circuits. A single-quantum-well (SQW) GaInAsP/InP membrane structure bonded onto an SOI substrate was successfully obtained by a direct bonding with thermal annealing at 300-450 °C in H2 atmosphere. The photoluminescence intensity of the SQW membrane structure did not degrade after this direct bonding and its spectral shape did not change. This wafer bonding technique can be applied to the realization of direct optical coupling using SOI passive waveguides from a membrane’s active region.

Maruyama, Takeo; Okumura, Tadashi; Arai, Shigehisa

2006-11-01

474

Novel broadband reconfigurable optical add-drop multiplexer employing custom fiber arrays and Opto-VLSI processors  

Microsoft Academic Search

A reconfigurable optical add\\/drop multiplexer (ROADM) structure based on using a custom-made fiber array and an Opto-VLSI processor is proposed and demonstrated. The fiber array consists of N pairs of angled fibers corresponding to N channels, each of which can independently perform add, drop, and thru functions through a reconfigurable Opto-VLSI beam steerer. Experimental results show that the ROADM structure

Feng Xiao; Budi Juswardy; Kamal Alameh; Yong Tak Lee

2008-01-01

475

Opto-VLSI-based photonic true-time delay architecture for broadband adaptive nulling in phased array antennas  

Microsoft Academic Search

This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RFmodulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which

Budi Juswardy; Feng Xiao; Kamal Alameh

2009-01-01

476

A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant  

Microsoft Academic Search

In this paper, we present a VLSI architecture for real-time image processing in quality control industrial applications: automation of the visual inspection phase of mechanical parts treated by the Fluorescent Magnetic Particle Inspection method for structural-defect detection. The VLSI architecture implements a highly constrained neural network tailored for this specific application: the multi-layer perceptron with strictly local connections. The learning

Maurizio Valle; Luigi Raffo; Daniele D. Caviglia; Giacomo M. Bisio

1996-01-01

477

Bubble-Free Silicon Wafer Bonding in a Non-Cleanroom Environment  

Microsoft Academic Search

Bubble-free bonding of 4-inch silicon wafers on either silicon or quartz wafers is achieved outside a cleanroom. Two wafers are stacked horizontally in a rack with the two mirror-polished surfaces facing each other. In order to avoid wafer contact during hydrophilization, cleaning, and drying, the wafers are separated in the rack by teflon spacers introduced at the wafer edges. After

R. Stengl; K.-Y. Ahn; U. Gösele

1988-01-01

478

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

479

Wafer-level vacuum packaging for an optical readout bi-material cantilever infrared FPA  

NASA Astrophysics Data System (ADS)

In this paper, we report the design and fabrication of an uncooled infrared (IR) focal plane array (FPA) on quartz substrate and the wafer-level vacuum packaging for the IR FPA in view of an optical readout method. This FPA is composed of bi-material cantilever array which fabricated by the Micro-Electro Mechanical System (MEMS) technology, and the wafer-level packaging of the IR FPA is realized based on AuSn solder bonding technique. The interface of soldering is observed by scan electron microscope (SEM), which indicates that bonding interface is smooth and with no bubbles. The air leakage rate of packaged FPA is measured to be 1.3×10-9 atm·cc/s.

Li, Shuyu; Zhou, Xiaoxiong; Yu, Xiaomei

2013-12-01

480

Separation of gallium and arsenic from the wafer grinding extraction solution.  

PubMed

This work investigates the separation of gallium and arsenic from the wafer grinding extraction solution. The wafer grinding extraction solution was generated using hot and concentrated nitric acid. In this study, adsorption technology was employed to remove the toxic arsenic from the extraction solution. Ferric hydroxide was the adsorbent employed to adsorb arsenic. The effects of pH value, contact time, absorbent dosage, and chloride ion concentration on the efficiency of adsorption of gallium and arsenic were investigated. The optimal conditions for recovering gallium and removing arsenic were a raw pH of 0.2, a contact time of 6min and a ferric hydroxide concentration of 30.4g/L. Additionally, adding chloric ions reduces the residual percentage of gallium (ReGa) and the percentage of arsenic removed (RAs). Under these optimal conditions, ReGa and RAs are 100 and 80%, respectively. PMID:15478937

Chen, Yi-Fu; Yang, Fong-Ru; Jean, Jeng-Shyong; Tsai, Chin-Ying

2004-01-01

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