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1

SOD wafer technology  

Microsoft Academic Search

Silicon-on-diamond (SOD) structured wafer with 4-inch diameter was fabricated by the technologies of CVD diamond deposition, Si wafer bonding and thinning. Diamond thin film with high quality and low interface state density was uniformly deposited on Silicon (001) substrate, continuous H+ ion bombardment to as-grown film surface under DC bias was performed to decrease the intrinsic tensile stress in the

C. Z. Gu; Y. Sun; J. K. Jia; Z. S. Jin

2003-01-01

2

Bipolar IC Wafer Process Technology,  

National Technical Information Service (NTIS)

The paper introduces Fuji Electric's wafer process technology for bipolar IC's. The processes are classified into two types of 8 micrometer rule characterized by high-current output and high voltage, and 4 micrometer rule characterized by high frequency a...

K. Meguro Y. Nagayasu O. Sasaki

1988-01-01

3

Planarizing dielectrics for VLSI technology  

Microsoft Academic Search

In this paper we describe the first reported blanket removal properties of various dielectric films. Based on material selectivity, We deposited thin PEOX, thick BPSG and a hard dielectric film with lower removal rate on top of a patterned wafer. Initial polishing removed the top hard dielectric level completely, exposing the BPSG, but the lower hard material remains less polished,

Chi-Wen Liu; Bau-Tong Dai; Ching-Fa Yeh; Chien-Hung Liu; Po-Tsun Wang

1994-01-01

4

MEMS Wafer-level Packaging Technology Using LTCC Wafer  

NASA Astrophysics Data System (ADS)

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

5

LSA project perspective of wafering technology  

NASA Astrophysics Data System (ADS)

The economics and techniques for eliminating wafering as a part of ingot technology in the production of silicon sheets for photovoltaic applications are considered. Technical progress in both ingot and non-ingot technologies for the low cost solar array project is described in the context of process economics. The critical areas of research in wafering are delineated and their payoff potential discussed.

Koliwad, K. M.

1982-02-01

6

A network flow approach to the wafer scale integration of VLSI arrays  

NASA Astrophysics Data System (ADS)

An algorithm is described for reconfiguring a 2-dimensional VLSI array on a silicon wafer that has some faulty cells. The functional cells of the array are interconnected in order to simulate a fault-free array of smaller size, where the interconnection wires are routed inside horizontal and vertical channels, according to the Manhattan model. The concept of simulation distance is introduced, and it is shown to be related to the length of the longest interconnection wire. The algorithm makes use of network flow techniques in order to find wiring with minimum simulation distance. This results in a practical heuristic for minimum simulation distance. This results in a practical heuristic for minimizing the maximum wire length. The complexity and performance of this algorithm are also discussed in the paper.

Codenotti, B.; Tamassia, R.

1985-06-01

7

Ag-Sn Fluxless Wafer Bonding Technology  

Microsoft Academic Search

Wafer bonding technology is important for most MEMS devices' packaging, especially for RF-MEMS devices. Different materials systems, such as Au-Sn, Au-In, have been developed for wafer bonding. A new bonding system, using Ag-Sn, is investigated in this paper. Comparing to well developed Au-Sn bonding (typically bonding temperature of 280degC ), Ag-Sn would provide a potentially lower temperature, lower cost wafer-level

XiaoGang Ji; Jian Cai; YoonChul Sohn; Qian Wang; Woonbae Kim

2006-01-01

8

RF-MEMS wafer-level packaging using through-wafer via technology  

Microsoft Academic Search

This paper presents wafer-level packaging (WLP) solution for RF-MEMS applications based on through-wafer via (TWV) technology in high-resistivity silicon (HRS). A pre-processed HRS capping wafer containing recesses and vertical Cu-plated TWV interconnect is, after alignment, bonded to the RF-MEMS wafer providing environmental protection and easy signal access. Optionally, cavities can be formed simultaneously with TWV in the capping wafer, which

J. Tian; J. Iannacci; S. Sosin; R. Gaddi; M. Bartek

2006-01-01

9

Multilevel-spiral inductors using VLSI interconnect technology  

Microsoft Academic Search

A multilevel-spiral (MLS) inductor structure for implementation in VLSI interconnect technology is presented. Inductances of 8.8 and 32 nH and maximum quality-factors (Q) of ~6.8 and 3.0, respectively, are achieved in a four-level metal BiCMOS technology, with four turns at each of the two or four stacked spiral coils and with an area of 226×226 ?m2. The comparison of the

J. N. Burghartz; K. A. Jenkins; M. Soyuer

1996-01-01

10

VLSI memory technology: Current status and future trends  

Microsoft Academic Search

In this paper, first, newly developed state-of-the-art VLSI memory chips, exemplified by DRAM, SRAM, and Flash memory, are discussed. Second, technology trends concerning standard DRAM's, embedded memories, and low-voltage memories are reviewed. For standard DRAM's, memory cells with high cell capacitance, high-speed subsystem technologies (such as synchronous operations, pipelining\\/prefetching, and use of packet protocols), and small-swing interfaces are investigated. And

Kiyoo Itoh; S. Kimura; T. Sakata

1999-01-01

11

VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.  

ERIC Educational Resources Information Center

As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

Bayoumi, Magdy

12

Wafer-level hermetic packaging technology for MEMS using anodically-bondable LTCC wafer  

Microsoft Academic Search

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature cofired ceramic (LTCC) wafer, in which electrical feedthroughs and passive components can be embedded. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of heat shock (?40 °C\\/+150 °C, 30 min\\/30 min) by diaphragm method. The width of seal rings necessary for hermetic

Shuji Tanaka; Sakae Matsuzaki; Mamoru Mohri; Atsushi Okada; Hideyuki Fukushi; Masayoshi Esashi

2011-01-01

13

The leading edge of production wafer probe test technology  

Microsoft Academic Search

Microelectronic wafer and die level testing have undergone significant changes in the past few years. This work's first section describes today's leading edge characteristics for numerous areas of this test technology including the minimum I\\/O pad pitch, advances in contactor technologies, maximum number of l\\/Os probed, maximum number of die tested in parallel, the largest prober and substrates, and the

W. R. Mann; Frederick L. Taber; Philip W. Seitzer; Jerry J. Broz

2004-01-01

14

The Leading Edge of Production Wafer Probe Test Technology  

Microsoft Academic Search

Microelectronic wafer and die level testing have undergone significant changes in the past few years. This paper's first section describes today's leading edge characteristics for numerous areas of this test technology including the minimum I\\/O pad pitch, advances in contactor technologies, maximum number of I\\/Os probed, maximum number of die tested in parallel, the largest prober and substrates, and the

William R. Mann; Frederick L. Taber; Philip W. Seitzer; Jerry J. Broz

2004-01-01

15

Three-dimensional shared memory fabricated using wafer stacking technology  

Microsoft Academic Search

We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the

K. W. Lee; T. Nakamura; T. Ono; Y. Yamada; T. Mizukusa; H. Hashimoto; K. T. Park; H. Kurino; M. Koyanagi

2000-01-01

16

The influence of VLSI technology evolution on radiation-induced latchup in space systems  

Microsoft Academic Search

Changes in technology and device scaling have generally increased the sensitivity of VLSI devices to latchup from single interactions of heavy particles in space. This paper discusses latchup mechanisms, comparing latchup from heavy particles in space with electrically induced latchup, which has been more widely studied. The effects of technology changes and device scaling on latchup susceptibility are discussed as

A. H. Johnston

1996-01-01

17

Advanced FTIR technology for the chemical characterization of product wafers  

NASA Astrophysics Data System (ADS)

Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers. .

Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

2001-01-01

18

A Test Methodology for VLSI Chips on Silicon  

Microsoft Academic Search

This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multichip silicon substrate. After a brief description of the package technology itself, the necessary elements of an ideal test methodology are provided, along with a description of the drawbacks of existing methods. The test strategy developed, covering test from the wafer

Thomas M. Storey

1993-01-01

19

Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies  

Microsoft Academic Search

The important method of bonding wafers to wafers or die to wafers has been discussed in an earlier chapter. In this chapter, we will examine the formation and filling of through-silicon vias (TSVs) and the post-bond process of thinning waferto-wafer pairs to further process TSVs and build metallization on the final exposed surface. In the section on wafer thinning, the

Sharath Hosali; Greg Smith; Larry Smith; Susan Vitkavage; Sitaram Arkalgud

20

Automotive SOI-BCD Technology Using Bonded Wafers  

SciTech Connect

The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N{sup +} layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

Himi, H.; Fujino, S. [DENSO CORPORATION, Ashinoya, Kota-cho, Nukata-gun, Aichi Pref., 444-0193 (Japan)

2008-11-03

21

Overview of complementary GaAs technology for high-speed VLSI circuits  

Microsoft Academic Search

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power

Richard B. Brown; Bruce Bernhardt; Mike LaMacchia; Jon Abrokwah; Phiroze N. Parakh; Todd D. Basso; Spencer M. Gold; Sean Stetson; Claude R. Gauthier; David Foster; Brian Crawforth; Timothy McQuire; Karem A. Sakallah; Ronald J. Lomax; Trevor N. Mudge

1998-01-01

22

A new wafer-level packaging technology for MEMS with hermetic micro-environment  

Microsoft Academic Search

We report a new wafer-level packaging technology for miniature MEMS in a hermetic micro-environment. The unique and new feature of this technology is that it only uses low cost wafer-level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning steps as compared to more expensive process steps that will be required in other alternative wafer-level technologies involving

Rajen Chanchani; Christopher D. Nordquist; Roy H. Olsson; Tracy Peterson; Randy Shul; Catalina Ahlers; Thomas A. Plut; Gary A. Patrizi

2011-01-01

23

Science and technology of plasma activated direct wafer bonding  

NASA Astrophysics Data System (ADS)

This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

Roberds, Brian Edward

24

Interconnection technologies for multichip assemblies (ITMA)-A UK Information Technology Engineering Directorate hybrid wafer scale project  

Microsoft Academic Search

The Interconnection technology for multichip assemblies (ITMA) project is addressing the application of a silicon-substrate-based multichip module (MCM) technology to the requirements of parallel computing applications in the UK. The program involves activities on MCM design methodology, silicon substrate process technology, device assembly, module packaging technology, the design of VLSI devices specifically for MCM applications, and the implementation of advanced

D. J. Pedder

1993-01-01

25

VLSI Memories,  

National Technical Information Service (NTIS)

The article, an update on Mitsubishi VLSI memory technology, discusses main products including dynamic RAMs, static RAMs, ROM, and application-specific memory devices. The Corporation has developed a 4Mb dynamic RAM with a submicron (0.8 micrometer) desig...

M. Yamada S. Kayano T. Yoshihara H. Harima H. Hamano

1988-01-01

26

Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap  

Microsoft Academic Search

Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs-AlGaAs multiple-quantum-well

Ashok V. Krishnamoorthy; David A. B. Miller

1996-01-01

27

The 300 mm silicon wafer — a cost and technology challenge  

Microsoft Academic Search

The conversion to 300 mm wafers is strictly cost driven. Cost, capability and timing are still the major challenges during this shaky transition phase. Looking back to 1995, industry consortia decided that the next wafer size would be 300 mm and all major Si manufacturers started to invest in costly 300 mm pilot lines. Even during the recent recession, they

Peter O. Hahn

2001-01-01

28

VLSI intelligent magnetic bubble memories  

SciTech Connect

This thesis presents a systematic exploration of VLSI possibilities for intelligent magnetic bubble memories in which back-end processors and memory elements could be incorporated in bubble VLSI chips. To provide the basis of system designs on bubble chips, a comprehensive library of magnetic bubble logic components was established, with emphasis on standardization in terms of dimensions and I/O to facilitate the chip composition task. These components were designed in current-access perforated-sheet configuration and fabricated on magnetic garnet wafers supporting 2-..mu..m bubbles. Operating margins were studied on 8-..mu..m period devices at 1 MHz by using a high speed magneto-optical sampling camera system. Bubble-to-bubble interaction force was found very reliable in producing successful logic operation with 12% bias field margins equal to 80% of the bubble propagation margin and about 60% of the free bubble bias field margin. An 8.5% overlapped bias margin was obtained for all of the logic components. The established library of bubble logic components was used to design intelligent bubble memories that support string-pattern matching and associative-searching functions. The intrinsic features of bubble logic technology were examined to indicate opportunities for VLSI bubble logic systems on memory chips.

Hwang, J.P.

1985-01-01

29

A low cost wafer-level MEMS packaging technology  

Microsoft Academic Search

This paper presents a low-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied to a wide variety of MEMS devices after their fabrication sequence is completed. Our technique utilizes thermal decomposition of a sacrificial polymeric material through a polymer overcoat

P. Monajemi; F. Ayazi; P. J. Joseph; P. A. Kohl

2005-01-01

30

Material and process limits in silicon VLSI technology  

Microsoft Academic Search

The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely believed that this process will continue for at least another ten years. However there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur, and beyond ten years

JAMES D. PLUMMER; PETER B. GRIFFIN

2001-01-01

31

Full-wafer technology for laser fabrication and testing  

Microsoft Academic Search

Summary Full-wafer fal~rication of A1GaAs lasers, which have mirrors etched by chemically assisted ion-beam etching and passivated by ion-beam sputtered AlzO3, is described. Full-wafer testing techniques for both laser parameters (P-l, far-field, spectrum, T0), as well as other test sites for process development and control (critical dimensions, overlay, etch depths, sheet resistances) have been developed, q'he lasers have excellent beam

D. J. Webb; M. K. Benedict; G. L. Bona; P. Buchman; N. Cahoon; K. Dätwyler; H. P. Dietrich; A. Moser; G. Sasso; H. K. Seitz; P. Vettiger; O. Voegeli; P. Wolf

1991-01-01

32

SEMICONDUCTOR TECHNOLOGY: Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology  

Microsoft Academic Search

A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are

Cao Yuhan; Luo Le

2009-01-01

33

Wafer bonding technology for silicon-on-lnsulator applications: A review  

NASA Astrophysics Data System (ADS)

School of Engineering, Duke University, Durham, North Carolina, 27706. The status of wafer bonding technology especially for silicon-on-insulator (SOI) materials is reviewed. General advantages of wafer bonding as well as specific problems of wafer bonding, such as interface bubble formation, and solutions for these problems are discussed. The specific requirements for SOI materials in terms of SOI layer thickness and the appropriate thinning procedures are dealt with. Interface properties such as bonding strength and electrical properties are also reviewed. Various device results are mentioned.

Mitani, Kiyoshi; Gösele, Ulrich M.

1992-07-01

34

Sea of leads ultra high-density compliant wafer-level packaging technology  

Microsoft Academic Search

Sea of leads (SoL) is a novel ultra high-density compliant wafer-level packaging technology. SoL extends wafer-level batch processing of multilayer on-chip interconnect networks to include x-y-z compliant chip input\\/output (I\\/O) interconnects with a density exceeding 104 leads per cm2. A package with 12×103 compliant leads distributed across a cm2 has been demonstrated. The compliance enables wafer-level testing as well as

Muhannad S. Bakir; Hollie A. Reed; Paul A. Kohl; Kevin P. Martin; James D. Meindl

2002-01-01

35

Development on integrated passive devices using wafer level package technologies  

Microsoft Academic Search

In recent years, as the demand for ever-smaller electronic systems grows, Industry trends are seeking ways to increase IC integration levels and to reduce the size and weight of IC packages. The explosive expansion of mobile electronic terminals generates strong demand for high-performance, cost-effective and miniaturized RF modules providing desired wireless connectivity. The chip scale package (CSP) and wafer-level packaging

Byeung-Gee Kim; Yun-Mook Park; Jun-Kyu Lee; In-Soo Kang

2010-01-01

36

Cool Plasma Activated Surface in Silicon Wafer Direct Bonding Technology  

Microsoft Academic Search

A novel cool plasma surface activation method has been developed for high quality SOI\\/SDB (Silicon wafer Direct Bonding) preparation. The activation effectiveness of different plasma gases, espetially of O2 plsma gases were investigated. The measurements of H. V-PMOS and L.V.-NMOS devices made on the SOI\\/SDB and on a bulk Silicon indicate that ratios of electron and hole mobility of SOI

G.-L. Sun; J. Zhan; Q.-Y. Tong; S.-J. Xie; Y.-M. Cai; S.-J. Lu

1988-01-01

37

3D micro-optical lens scanner made by multi-wafer bonding technology  

NASA Astrophysics Data System (ADS)

We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

Bargiel, S.; Gorecki, C.; Bara?ski, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frömel, J.

2013-03-01

38

New challenges for 300 mm Si technology: 3D interconnects at wafer scale by aligned wafer bonding  

Microsoft Academic Search

A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1?m. The method uses two top–bottom microscope pairs for observing the alignment keys and a minimal Z-axis travel during wafer alignment procedure. After the alignment procedure, the wafers

V. Dragoi; P. Lindner; M. Tischler; C. Schaefer

2002-01-01

39

An overview of Pb-free, flip-chip wafer-bumping technologies  

NASA Astrophysics Data System (ADS)

To meet the European Union Restriction of Hazardous Substances requirements and the continuing demand for lower costs, finer pitch, and high-reliability flip-chip packaging structures, considerable work is going on in the electronic industry to develop leadfree solutions for flip-chip technology. In this paper, various solder-bumping technologies developed for flip-chip applications are reviewed with an emphasis on a new wafer-bumping technology called C4NP (Controlled-Collapse-Chip-Connect New Process). Several inherent advantages of C4NP technology are discussed over other technologies. This paper will also discuss the recent development and implementation of lead-free C4 interconnections for 300 mm wafers demonstrated at IBM. In addition, some metallurgical considerations associated with C4NP technology are discussed.

Kang, Sung K.; Gruber, Peter; Shih, Da-Yuan

2008-06-01

40

Novel Hermetic Wafer-Level-Packaging Technology using Low-Temperature Passivation  

Microsoft Academic Search

In the past decade wafer level packaging (WLP) has been proven to be a very competitive solution regarding performance, miniaturization and costs for a wide range of applications. However, they are up to now not matching the performance of hermetically sealed Glass or Glass-to-MetalSeal packages, esp. when considering application in extreme environment. In this paper a novel packaging technology is

Jürgen Leib; Dietrich Mund; Michael Töpper

2005-01-01

41

Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology  

NASA Astrophysics Data System (ADS)

Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

Shi, Fang Frank

42

Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias  

NASA Astrophysics Data System (ADS)

The presented wafer-level packaging technology enables the direct integration of electrical interconnects during low-temperature wafer bonding of a cap substrate featuring through silicon vias (TSVs) onto a MEMS device wafer. The hybrid bonding process is based on hydrophilic direct bonding of plasma-activated Si/SiO2 surfaces and the simultaneous interconnection of the device metallization layers with Cu TSVs by transient liquid phase (TLP) bonding of ultra-thin AuSn connects. The direct bond enables precise geometry definition between device and cap substrate, whereas the TLP bonding does not require a planarization of the interconnect metallization before bonding. The complete process flow is successfully validated and the fabricated devices' characterization evidenced ohmic interconnects without interfacial voids in the TLP bond.

Kühne, Stéphane; Hierold, Christofer

2011-08-01

43

Robust hermetic wafer level thin-film encapsulation technology for stacked MEMS \\/ IC package  

Microsoft Academic Search

This paper reports a thin-film encapsulation technology for wafer level micro-electro-mechanical systems (MEMS) package, using poly-benzo-oxazole (PBO) sacrificial material and plasma enhanced chemical vapor deposited silicon oxide (PECVD SiO) cap layer. This technique, which is applicable for MEMS technologies, saves die size and enables conventional package processes such as dicing, picking, mounting and bonding. Besides the fabrication processes of the

Y. Shimooka; M. Inoue; M. Endo; S. Obata; A. Kojima; T. Miyagi; Y. Sugizaki; I. Mori; H. Shibata

2008-01-01

44

Implementing fiducial probe card alignment technology for production wafer probing  

Microsoft Academic Search

To match the ever-increasing density and performance of integrated circuits, new generations of probe cards are getting adopted in the main stream manufacturing process in a rapid pace. To match the product geometry and performance, probe tips are getting increasingly denser, product refined, and miniaturized. The appearances of these tips vary significantly between different technologies, wear and tear of the

Dominique Langlois; Michel Fardel; Karl R. Heiman; Fenglei Du

2003-01-01

45

A monolithic active pixel sensor for charged particle tracking and imaging using standard VLSI CMOS technology  

NASA Astrophysics Data System (ADS)

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode, which is readily available in a CMOS technology. The diode has a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. Semiconductor device simulation, using either ToSCA based or 3-D ISE-TCAD software packages shows that the charge collection is efficient, reasonably fast (order of 100ns), and the charge spreading limited to a few pixels only. A first prototype has been designed, fabricated and tested. It is made of four arrays each containing 64×64 pixels, with a readout pitch of 20?m in both directions. The device is fabricated using standard submicron 0.6?m CMOS process, which features twin-tub implanted in a p-type epitaxial layer, a characteristic common to many modern CMOS VLSI processes. Extensive tests made with soft X-ray source (55Fe) and minimum ionising particles (15GeV/c pions) fully demonstrate the predicted performances, with the individual pixel noise (ENC) below 20 electrons and the Signal-to-Noise ratio for both 5.9keV X-rays and Minimum Ionising Particles (MIP) of the order of 30. This novel device opens new perspectives in high-precision vertex detectors in Particle Physics experiments, as well as in other application, like low-energy beta particle imaging, visible light single photon imaging (using the Hybrid Photon Detector approach) and high-precision slow neutron imaging.

Turchetta, R.; Berst, J. D.; Casadei, B.; Claus, G.; Colledani, C.; Dulinski, W.; Hu, Y.; Husson, D.; Le Normand, J. P.; Riester, J. L.; Deptuch, G.; Goerlach, U.; Higueret, S.; Winter, M.

2001-02-01

46

Epitaxial liftoff technology onto processed silicon foundry wafers  

NASA Astrophysics Data System (ADS)

Technical objectives are to research the application of liftoff transfer of epitaxial material to foreign substrates including: surface chemistry and electrical, mechanical, thermal, and optical properties of Van der Waals bonded materials; III-V devices bonded to silicon circuitry and to other substrates with enhanced optical, electrical, or thermal properties; and integrated optical devices incorporating lifted-off material and/or devices with LiNbO3 glass or other substrates. This effort addresses the need for new technologies which can fully utilize the performance advantages of III-V (GaAs, InGaAs, InGaAsP, and InP) materials for electronic and optoelectronic applications. Specifically, the program is directed at demonstrating the potential of epitaxial liftoff as a technology to enable the realization of 'monolithic' optoelectronic devices with the characteristics of epitaxial material, that is, by transfer of epitaxial material to foreign substrates in a form that permits material processing and device fabrication to proceed as though the epitaxial material were grown directly on the substrate.

Yablonovitch, Eli

47

On-Chip High Variable Inductor Using Wafer-Level Chip-Scale Package Technology  

Microsoft Academic Search

In this paper, the authors propose an on-chip high-Q variable inductor embedded in wafer-level chip-scale package (WL-CSP). The variable inductor has a metal plate and a spiral inductor fabricated by the WL-CSP technology. The metal plate can be moved by a microelectromechanical systems (MEMS) actuator, and the inductance is varied according to the position of the metal plate. At the

Kenichi Okada; Hirotaka Sugawara; Hiroyuki Ito; Kazuhisa Itoi; Masakazu Sato; Hiroshi Abe; Tatsuya Ito; Kazuya Masu

2006-01-01

48

Silicon–glass wafer bonding with silicon hydrophilic fusion bonding technology  

Microsoft Academic Search

Silicon–glass wafer bonding is realized with silicon hydrophilic fusion bonding technology. Tensile strength testing shows that the bonding strength is large enough for most applications of integrated circuits and transducers. The bonding strengths of 4 in. 525 ?m thick #7740 glass–4 in. 525 ?m thick silicon and of 1.5 in. 1000 ?m thick #7740 glass–2 in. 380 ?m thick silicon

Zhi-Xiong Xiao; Guo-Ying Wu; Zhi-Hong Li; Guo-Bing Zhang; Yi-Long Hao; Yang-Yuan Wang

1999-01-01

49

An overview of Pb-free, flip-chip wafer-bumping technologies  

Microsoft Academic Search

To meet the European Union Restriction of Hazardous Substances requirements and the continuing demand for lower costs, finer\\u000a pitch, and high-reliability flip-chip packaging structures, considerable work is going on in the electronic industry to develop\\u000a leadfree solutions for flip-chip technology. In this paper, various solder-bumping technologies developed for flip-chip applications\\u000a are reviewed with an emphasis on a new wafer-bumping technology

Sung K. Kang; Peter Gruber; Da-Yuan Shih

2008-01-01

50

Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers  

Microsoft Academic Search

This paper presents an approach to build electronic systems with very high chip count. Instead of packing the chips laterally as it is done in multichip-modules (MCMs), individual dies, blocks of dies and ultimately entire wafers are stacked on top of each other. Electrical interconnection is accomplished using plated through-hole contacts through the silicon substrate. Proper thermal management is obtained

S. Linder; H. Baltes; F. Gnaedinger; E. Doering

1994-01-01

51

New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration  

Microsoft Academic Search

A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack

Takafumi Fukushima; Yusuke Yamada; Hirokazu Kikuchi; Mitsumasa Koyanagi

2006-01-01

52

Electroplated Metal Buried Interconnect and Through-Wafer Metal-Filled Via Technology for High-Power Integrated Electronics  

Microsoft Academic Search

In this paper, we present the design, fabrication process, and experimental results of an electroplated metal buried interconnect and through-wafer via technology suitable for extremely low resistance interconnection of microelectronic devices. The technology is demonstrated using a 3-D daisy-chain test structure comprised of electroplated through-wafer vias buried in the silicon substrate to form the respective interconnect. In contrast to the

Chang-Hyeon Ji; Florian Herrault; Peter Hopper; Peter Smeys; Peter Johnson; Mark G. Allen

2009-01-01

53

Characterization and control of microcontamination for advanced technology nodes and 300-mm wafer processing: overview and challenges  

Microsoft Academic Search

Advanced process technologies have been introducing many unseen problems on process yield and device reliability. Microcontamination, which enables defects causing electric faults, has also been hard to understand, detect, and control. In this paper, the requirements and methodologies for contamination control in advanced technologies such as at the 90-nm processing technology node and immersion lithography using 300-mm wafer processing were

B. H. J. Tseng; M. D. You; S. C. Hsin

2005-01-01

54

Hybrid wafer-level vacuum hermetic micropackaging technology for MOEMS-MEMS  

NASA Astrophysics Data System (ADS)

Packaging constitutes one of the most costly steps of MEMS/MOEMS manufacturing. The package protects the MEMS devices and, in the case of MOEMS, it also provides light access to the device. In many cases, MEMS require a specific atmosphere for their proper functioning. The atmosphere should be kept invariable during the lifetime of the package in order to not degrade the performance of the device. Maintaining a constant atmosphere inside the package becomes more challenging as the cavity volume is decreased to the microliter and nanoliter range. Other packaging requirements are compatibility with wafer-level microfabrication techniques (cost reduction) and low temperature assembly in cases where temperature sensitive devices are to be packaged. In recent years, INO has performed a great amount of work towards the development of uncooled IR microbolometer detectors using VOx technology. Different pixel designs have been optimized for different applications. The bolometer pixels require a vacuum atmosphere below 10 mTorr to be maintained during the lifetime of the device in order to operate at their highest sensitivity. INO's micropackaging technology has been demonstrated to provide base pressures below 5 mTorr. An equivalent flow rate of 2.5×10-14 Torr.l/sec has been obtained for a device packaged without any getter. The advantages of INO's micropackaging technology are the possibility of achieving very low base pressures, the low temperatures required for the assembly (the package device is never exposed to a temperature above 150 °C) and its compatibility with hybrid wafer-level packaging. The technology has been developed for the micropackaging of INO's 160×120 pixel uncooled microbolometer FPA, but it is compatible with any other kinds of MOEMS-MEMS devices requiring vacuum hermetic packaging. In order to increase the lifetime of the package, knowledge of the gases outgassing inside the package is crucial. A hybrid approach has been chosen as it permits packaging only known-good dies and saving considerable quantities of IR window material. In INO's hybrid wafer-level packaging, dicing is performed only through one of the wafers, therefore reducing the risk of perturbing the vacuum during the separation of the different dies.

Garcia-Blanco, Sonia; Topart, Patrice; Le Foulgoc, Karine; Caron, Jean-Sol; Desroches, Yan; Alain, Christine; Chateauneuf, Francois; Jerominek, Hubert

2009-02-01

55

Semiconductor thin film transfer by wafer bonding and advanced ion implantation layer splitting technologies  

NASA Astrophysics Data System (ADS)

Wafer bonding is an attractive technology for modern semiconductor and microelectronic industry due to its variability in allowing combination of materials. Initially, the bonding of wafers of the same material, such as silicon-silicon wafer bonding has been major interest. In the meantime, research interest has shifted to the bonding of dissimilar materials such as silicon to quartz or to sapphire. Thermal stress coming from the different expansion coefficients usually is a barrier to the success of dissimilar material bonding. Thermal stress may cause debonding, sliding, cracking, thermal misfit dislocations, or film wrinkle to impair the quality of the transferred layer. This dissertation presents several effective approaches to solve the thermal stress problem. These approaches concern bonding processes (low vacuum bonding and storage), thinning (advanced ion implantation layer splitting), and annealing processes (accumulative effect of blister generation) and are combined to design the best heat-treatment cycle. For this propose the concept of hot bonding is used in order to effectively minimize the thermal mismatch of dissimilar material bonding during the bonding and thinning procedures. During the initial bonding and bond strengthening phase, the difference in the temperature between bonding and annealing processes should be decreased as much as possible to avoid excessive thermal stresses. This concept can be realized either by increasing the bonding temperature or by decreasing the annealing temperature. A thinning technique has to employed that can thin the device wafer before debonding occurs due to the thermal stress generated either from the cooling-down process in the first case or by the annealing process itself in the late case. The ion implantation layer splitting method, also known as the Smart-cutsp°ler process, developed by Bruel at LEIT in France is a practical thinning technique which satisfies the above requirement. In the study, an advanced ion implantation layer splitting technique was developed to significantly decrease the splitting (annealing) temperature. It successfully solved the debonding and cracking problems because of thermal stress. Low vacuum bonding and storage process also was investigated in the dissertation because its enhanced bonding effect can render a way to increase sufficient high bonding energy at low annealing (splitting) temperature condition that can notably reduce thermal stress to successfully transfer a thin film onto substrate during splitting process.

Lee, Tien-Hsi

56

Plate-like structure health monitoring based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers  

NASA Astrophysics Data System (ADS)

Piezoelectric ceramic wafers are applied for the excitation and detection of ultrasonic guided waves to determine the health state of plate-like structures. Two PZT wafers, whose diameter is 11mm and thickness is 0.4mm respectively, are bonded permanently on the surface of a 1mm thick aluminum plate. One of these wafers is actuated by sinusoidal tone burst at various frequencies ranging from 100kHz to 500kHz, the other one is used as a receiver for acquiring ultrasonic guided wave signals. According to the amplitudes and shapes of these received signals, guided wave modes and their proper frequency range by using these wafers are determined. For the improvement of the signal-to-noise ratio, the Daubechies wavelet of order 40 is used for signal denoising as the mother wavelet. Furthermore, the detection of an artificial cylindrical through-hole defect is achieved by using S0 at 300kHz. Experimental results show that it is feasible and effective to detect defects in plate-like structures based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers.

Liu, Zenghua; Zhao, Jichen; He, Cunfu; Wu, Bin

2008-11-01

57

Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing  

NASA Astrophysics Data System (ADS)

The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore the capability of the tool for characterizing multiple geometric parameters associated with the manufacturing process that are important to the yield and performance of advanced bottle DRAM devices.

Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

2005-09-01

58

Advanced diffuser technology helps reduce vent-up times while maintaining wafer integrity on vacuum tools loadlock chambers  

NASA Astrophysics Data System (ADS)

Wafer throughput and particle counts are key metrics for any semiconductor manufacturer's yield enhancement programs. Recent advancements in diffuser technology have helped manufacturers enhance these metrics while improving the attributes for most vacuum processes. These processes include dry etch, chemical vapor deposition (CVD), physical vapor deposition (PVD), rapid thermal processing (RTP) and Epitaxial deposition (Epi). Execution of membrane diffuser technology dramatically decreases required vent time and has become a highly effective tool upgrade option. An early implementation of this technology was used on 200mm batch-style loadlocks that had an inherently large internal volume. The loadlock was prone to long vent cycles to prevent particle contamination. As the industry transitioned to a 300mm wafer platform, factories increased their development of single-wafer loadlocks (SWLL) in an effort to boost tool throughput. Gas diffusers with ultra fine filtration membranes solved these issues. Compared to the 200mm batch-style loadlocks, the SWLLs had extremely low internal volumes and were designed to cycle vacuum to atmosphere very quickly. With the low volumes inherent in the SWLL, the velocity of the incoming vent gas became critical, since any particles on the bottom of the loadlock chamber would easily sweep onto the wafer should they be hit with a high velocity gas. Particles are typically present in the loadlock due to mechanical wafer handling devices and environmental exposure. Gas diffusers allowed a large, uniform volumetric flowrate of gas into the loadlock chamber at low downstream gas velocities. While now standard on most 300mm loadlocks, the majority of 200mm tools in the field do not utilize membrane diffusers. Typically a screen, frit and/or soft vent procedure is used to control the flow into the loadlock. However, these tools can now be retrofitted with membrane diffuser technology. The result is a large reduction in particle count while maintaining throughput levels at a low cost with minimal downtime.

Vroman, Chris; Quartaro, Chris; Randolph, Marshall

2008-04-01

59

Application of a new laser scanning pattern wafer inspection tool to leading edge memory and logic applications at Infineon Technologies  

Microsoft Academic Search

A new patterned wafer laser-based inspection tool has been introduced to the market place, incorporating double darkfield laser scanning technology. Developed from a well-known production-proven platform, the new system is intended to provide the sensitivity required for 0.18 ?m design rules, with extendibility to 0.13 ?m. The inspection technology combines low angle laser illumination with dual darkfield scattered light collection

T. Reuter; U. Bohmler; S. Steck; M. McLaren; Siqun Xiao; R. Howland Pinto

1999-01-01

60

Thin hermetic passivation of semiconductors using low temperature borosilicate glass - benchmark of a new wafer-level packaging technology  

Microsoft Academic Search

A novel approach on wafer-level passivation using a thin, hermetic borosilicate glass layer replacing the polymers in redistribution is presented here. The technology will be benchmarked to those conventional technologies. The glass layer is deposited at low temperatures (T<100degC) using a plasma-enhanced e-beam deposition and can be structured by a lift-off process using a standard photoresist process for masking. The

Juergen Leib; Oliver Gyenge; Ulli Hansen; Simon Maus; Thorsten Fischer; Kai Zoschke; Michael Toepper

2009-01-01

61

Bonded wafer substrates for integrated detector arrays  

SciTech Connect

Bonded wafer substrates have been made which are optimized for integrating high energy particle detector arrays with their readout electronics. The detectors are processed in the handle wafer, which is a 300 [mu]m thick, high resistivity, <111> crystal orientation silicon wafer. This wafer is bonded to a primary wafer using a low temperature process that does not affect the detector material. The support electronics are processed in the remnant of the primary wafer, which is a submicron thick <100> crystal orientation silicon film formed by a bond-and-etchback procedure. These two device materials are isolated from each other by a radiation hardened dielectric film. The integrated process is based on a low temperature, radiation hardened VLSI CMOS process which is also shown not to seriously affect the detector material.

Wang, J.J.; King, E.E.; Leonov, P.; Huang, D.H. (Advanced Research and Applications Corp., Sunnyvale, CA (United States)); Thompson, P.; Godbey, D. (Naval Research Lab., Washington, DC (United States))

1993-10-01

62

A practical, flip-chip, multi-layer pre-encapsulation technology for wafer-scale underfill  

Microsoft Academic Search

This paper describes the conception, development, and application of a novel materials set and methodology for fabricating assembly-ready flip chips pre-encapsulated, at the wafer level, with a low coefficient of thermal expansion (CTE) underfill. This technology is unique in that it addresses a key challenge currently facing the high density interconnect (HDI) electronics industry-how to produce cost-effectively, in a streamlined

Robert V. Burress; M. Albert Capote; Yong-Joon Lee; Howard A. Lenos; Jeffrey F. Zamora

2001-01-01

63

Optical interconnections for VLSI systems  

Microsoft Academic Search

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The

S.-Y. Kung; R. A. Athale; Sun-Yuan Kung

1984-01-01

64

Thinning Technology for Lithium Niobate Wafer by Surface Activated Bonding and Chemical Mechanical Polishing  

NASA Astrophysics Data System (ADS)

A lithium niobate (LiNbO3) hybrid wafer was developed by a combination of wafer bonding and chemical mechanical polishing. In this study, various plasma ambients were applied to activate the surface of LiNbO3 and Si substrate to bond the wafers at room temperature. After the surface activated bonding process, the LiNbO3 substrate was lapped by chemical mechanical polishing. The thickness of the 10 cm diameter LiNbO3 substrate can be decreased from 400 to 10 ?m without generating serious cracks. Under the optimum lapping parameters, a 1.5 nm surface roughness of the LiNbO3 film can be obtained.

Wu, Chia?Cheng; Horng, Ray?Hua; Wuu, Dong?Sing; Chen, Tsai?Ning; Ho, Shih?Shian; Ting, Chia?Jen; Tsai, Hung?Yin

2006-04-01

65

Yield-driven multi-project reticle design and wafer dicing  

NASA Astrophysics Data System (ADS)

The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has lead to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.

Kahng, Andrew B.; Mandoiu, Ion; Xu, Xu; Zelikovsky, Alex

2005-11-01

66

Customizable VLSI artificial neural network chips based on a novel technology  

SciTech Connect

The human cerebral cortex contains approximately 10{sup 11} neurons and 10{sup 14} synapses. It thus seems logical that any technology intended to mimic human capabilities should have the ability to fabricate a very large number of neurons and even larger numbers of synapses. This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems.

Fu, C. Y.; Law, B.; Chapline, G. [Lawrence Livermore National Lab., CA (United States); Swenson, D. [Naval Air Warfare Center, China Lake, CA (United States)

1993-09-14

67

VLSI implementation of parallel Kalman filters  

NASA Astrophysics Data System (ADS)

This paper describes a top-down approach for implementing the Kalman filter with VLSI technology. The approach is based on: (1) uncorrelating the measurement data to the filter so that each measurement can be processed simultaneously, (2) decoupling the predictor and corrector in the filter so that these computations can be evaluated in separate processors, (3) mapping the Kalman filter equations directly onto a highly parallel/pipelined architecture, and (4) implementing each processor architecture with VLSI technology. The performance of the newly developed VLSI architectures have been simulated using a data flow language. In addition, a board level implementation of the Kalman filter processor has been constructed using state-of-the-art VLSI components. The Kalman filter processor can be applied to a wide-class of avionic signal processing applications such as target tracking, target prediction, on-board calibration of inertial systems and in-flight estimation of aircraft stability/control derivatives.

Travassos, R. H.; Andrews, A.

68

VLSI-circuit techniques technologies for ultrahigh-speed data-conversion interfaces. Final report, 28 Sep 87-28 Feb 91  

SciTech Connect

The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

Wooley, B.A.

1991-04-29

69

A novel technology for fabricating customizable VLSI artificial neural network chips  

SciTech Connect

This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems. These neural networks are programmed using precision laser cutting and deposition. The fast turnaround of laser-based customization allows us to explore different neural network architectures and to rapidly program the synaptic weights. Our customizable chip allows us to expand an artificial network laterally and vertically. This flexibility permits us to build very large neural network systems.

Fu, C.Y.; Law, B.; Chapline, G. [Lawrence Livermore National Lab., CA (United States); Swenson, D. [Naval Air Warfare Center, China Lake, CA (United States)

1992-02-05

70

Interferometry for wafer dimensional metrology  

NASA Astrophysics Data System (ADS)

Wafer shape and thickness variation are important parameters in the IC manufacturing process. The thickness variation, also called flatness, enters the depth-of-focus budget of microlithography, and also affects film thickness uniformity in the CMP processing. The shape mainly affects wafer handling, and may also require some depth-of-focus if the wafer shape is not perfectly flattened by chucking. In the progression of technology nodes to smaller feature sizes, and hence smaller depth-of-focus of the lithography tool, the requirement for the PV-flatness over stepper exposure sites is becoming progressively tighter, and has reached 45nm for the next technology node of 45nm half pitch. Consequently, in order to be gauge-capable the flatness metrology tool needs to provide a measurement precision of the order of 1nm. Future technology nodes will require wafers with even better flatness and metrology tools with better measurement precision. For the last several years the common capacitive tools for wafer dimensional metrology have been replaced by interferometric tools with higher sensitivity and resolution. In the interferometric tools the front and back surface figure of the wafer is measured simultaneously while the wafer is held vertically in its intrinsic shape. The thickness variation and shape are then calculated from these single-sided maps. The wafer shape, and hence each wafer surface figure, can be tens of microns, necessitating a huge dynamic range of the interferometer when considering the 1nm measurement precision. Furthermore, wafers are very flexible, and hence very prone to vibrations as well as bending. This presentation addresses these special requirements of interferometric wafer measurements, and discusses the system configuration and measurement performance of WaferSightTM, KLA-Tencor's interferometric dimensional metrology tool for 300mm wafers for current and future technology nodes.

Freischlad, Klaus; Tang, Shouhong; Grenfell, Jim

2007-09-01

71

Monolithic integration of waveguide polymer electrooptic modulators on VLSI circuitry  

Microsoft Academic Search

We demonstrated some of the critical technology that is needed for the monolithic integration of polymer electrooptic modulators and VLSI circuitry by fabricating and testing a phase slab modulator on nonplanar VLSI circuits. We demonstrated the survival of GaAs MESFET's to the high-voltage poling and polymer modulator fabrication procedures. We also implemented an electrical interconnect scheme between the electronics and

Srinath Kalluri; Mehrdad Ziari; Antao Chen; V. Chuyanov; W. H. Steier; Datong Chen; B. Jalali; H. Fetterman; L. R. Dalton

1996-01-01

72

Rad-tolerant flight VLSI from commercial foundries  

Microsoft Academic Search

This paper reviews techniques which have been used to protect CMOS circuits from the deleterious effects of the natural space radiation environment. Three custom flight VLSI processors have been designed and fabricated at commercial foundries. A program has been initiated to provide this radiation-tolerant VLSI technology to designers of Application Specific Integrated Circuits

J. W. Gambes; Gary K. Maki

1996-01-01

73

Wafer scale nano-membranes supported on a silicon microsieve using thin-film transfer technology  

NASA Astrophysics Data System (ADS)

A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independent of the thin film, which is later transferred onto it by fusion bonding, thus providing flexibility in design and processing steps. Using this thin-film transfer technique, nano-membranes down to 50 nm thickness are fabricated. The fabrication of different kinds of membranes made of inorganic, metallic and polymer materials is presented here. Apart from dense nano-membranes, perforated membranes are fabricated using this modular approach. One of the main areas of interest for such membranes is in fluidics, where the low thickness and high strength of the supported nano-membranes are a big advantage.

Unnikrishnan, Sandeep; Jansen, Henri; Berenschot, Erwin; Elwenspoek, Miko

2008-06-01

74

Wafer-scale processing technology for monolithically integrated GaSb thermophotovoltaic device array on semi-insulating GaAs substrate  

NASA Astrophysics Data System (ADS)

This paper presents the entire fabrication and processing steps necessary for wafer scale monolithic integration of series interconnected GaSb devices grown on semi-insulating GaAs substrates. A device array has been fabricated on complete 50 mm (2 inch) diameter wafer using standard photolithography, wet chemical selective etching, dielectric deposition and single-sided metallization. For proof of concept of the wafer-scale feasibility of this process, six large-area series interconnected GaSb p-n junction thermophotovoltaic cells with each cell consisting of 24 small-area devices have been fabricated and characterized for its electrical connectivity. The fabrication process presented in this paper can be used for optoelectronic and electronic device technologies based on GaSb and related antimonide based compound semiconductors.

Kim, Jung Min; Dutta, Partha S.; Brown, Eric; Borrego, Jose M.; Greiff, Paul

2013-06-01

75

Innovative design methodology for implementing heterogeneous multiprocessor architectures in VLSI  

SciTech Connect

Considering the design cost of today's VLSI systems, advanced VLSI technology may not be cost-effective for implementing complex computer systems. In the paper, an innovative design approach which can drastically reduce the cost of implementing heterogeneous multiprocessor architectures in VLSI is presented. The author introduces high-level architectural design tools for assisting the design of multiprocessor systems with distributed memory modules and communication networks, and presents a logic/firmware synthesis scheme for automatically implementing multitasking structures and system service functions for multiprocessor architectures. Furthermore, the importance of the firmware synthesis aspect of VLSI system design is emphasized. Most logic of complex VLSI systems can be implemented very easily in firmware using the design approach introduced here. 10 references.

Tientien Li

1983-01-01

76

A novel fabrication technology for anti-reflex wafer-level vacuum packaged microscanning mirrors  

Microsoft Academic Search

The use of microscanning mirrors in mobile laser projection systems demands for robust fabrication technologies. Dust, change in humidity and temperature can only be tolerated if the fragile devices are enclosed in a hermetic package. A novel fabrication process is presented based on two 30 micron thick epitaxially deposited silicon layers and a buried interconnection layer. This technology allows the

M. Oldsen; U. Hofmann; H. J. Quenzer; J. Janes; C. Stolte; K. Gruber; M. Ites; F. Sörensen; B. Wagner

2008-01-01

77

Adhesive wafer bonding for MEMS applications  

Microsoft Academic Search

Low temperature wafer bonding is a powerful technique for MEMS\\/MOEMS devices fabrication and packaging. Among the low temperature processes adhesive bonding focuses a high technological interest. Adhesive wafer bonding is a bonding approach using an intermediate layer for bonding (e.g. glass, polymers, resists, polyimides). The main advantages of this method are: surface planarization, encapsulation of structures on the wafer surface,

Viorel Dragoi; Thomas Glinsner; Gerald Mittendorfer; Bernhard Wieder; Paul Lindner

2003-01-01

78

Wafer Probing Issues at Millimeter Wave Frequencies  

Microsoft Academic Search

With increased wafer probing activity at millimeter wave frequencies, and the maturing of wafer probing technology itself, new issues have arisen. Many of these issues involve phenomena which, although present at lower frequencies, do not cause significant perturbation at measured data below 40 GHz. At higher frequencies wafer probe systems begin to experience the effects of phenomena such as surface

Edward M. Godshalk

1992-01-01

79

Development of wafer level packaged scanning micromirrors  

Microsoft Academic Search

This paper presents design, simulation and fabrication of a wafer level packaged Microelectromechanical Systems (MEMS) scanning mirror. In particular we emphasize on the process development and materials characterization of In- Ag solder for a new wafer level hermetic\\/vacuum package using low temperature wafer bonding technology. The micromirror is actuated with an electrostatic comb actuator and operates in resonant torsional mode.

Aibin Yu; Chengkuo Lee; Li Ling Yan; Qing Xin Zhang; Seung Uk Yoon; John H. Lau

2008-01-01

80

Mixed Voltage VLSI Design.  

National Technical Information Service (NTIS)

A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the ...

R. Panwar D. Rennels L. Alkalaj

1993-01-01

81

Area-time complexity for VLSI  

Microsoft Academic Search

The complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of computation appropriate to VLSI technology. This model focuses on two key parameters, the amount of silicon area and time required to implement a DFT on a single chip. Lower bounds on area (A) and time (T) are related to the number of points

Clark D. Thompson

1979-01-01

82

Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology  

NASA Astrophysics Data System (ADS)

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

Gagnard, Xavier; Bonnaud, Olivier

2000-08-01

83

Wafer Manufacturing and Slicing Using Wiresaw  

NASA Astrophysics Data System (ADS)

Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer quality are presented. Summary and further reading are also provided.

Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

84

Laser wafering for silicon solar.  

SciTech Connect

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

85

Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits  

Microsoft Academic Search

In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.

Wojciech Maly

1985-01-01

86

Novel spin-coating technology for 248-nm/193-nm DUV lithography and low-k spin on dielectrics of 200-mm/300-mm wafers  

NASA Astrophysics Data System (ADS)

An alternative coating technology was developed for 248 nm/193 nm DUV lithography and low-k spin on dielectric (SOD) materials used in the interconnect area. This is a 300 mm enabling technology which overcomes turbulent flow limitations above 2000 rpm and it prevents 40 - 60% reduction on the process latitudes of evaporation-related variables, common to 300 mm conventional coaters. Our new coating technology is fully enclosed and it is capable of controlling the solvent concentration above the resist film dynamically in the gas phase. This feature allows a direct control of the evaporation mass transfer which determines the quality of the final resist profiles. Following process advantages are reported in this paper: (1) Demonstrated that final resist film thickness can be routinely varied by 4000 angstrom at a fixed drying spin speed, thus minimizing the impact of turbulence wall for 300 mm wafers. (2) Evaporation control allows wider range of useful thickness from a fixed viscosity material. (3) Latitudes of evaporation-related process variables is about 40% larger than that of a conventional coater. (4) Highly uniform films of 0.05% were obtained for 8800 angstrom target thickness with tighter wafer-wafer profile control because of the enclosed nature of the technology. (5) Dynamic evaporation control facilitates resist consumption minimization. Preliminary results indicate feasibility of a 0.4 cc process of record (POR) for a 200 mm substrate. (6) Lower COO due to demonstrated relative insensitivity to environmental variables, robust resist consumption minimization and superior process capabilities. (7) Improved planarization and gap fill properties for the new generation photoresist/low-k SOD materials deposited using this enclosed coating technology.

Gurer, Emir; Zhong, Tom X.; Lewellen, John W.; Lee, Ed C.

2000-06-01

87

Design automation for wafer scale integration  

SciTech Connect

Wafer scale integration (WSI) is a technique for implementing large digital systems on a single wafer. This thesis describes a system of design automation tools developed to aid in the implementation of wafer scale integrated systems. An overview of wafer scale integration is given with fabrication details and yield considerations discussed. The Wafer architectural Design Language (WDL) used to describe and specify a system architecture to the development system is introduced along with a compiler that translates the high level WDL description into net lists and other internal data bases. Interactive placement tools used to map the system architecture onto the functional die sites on a wafer are described. A very fast line probe router was developed to perform the custom wafer level routing need to personalize each wafer. Router data structures, algorithms, techniques, and results are discussed in detail. Sample wafer scale architectures and the result of their WSI implementations are shown. Also presented is the Wafer Transmission Module (WTM) a packaging technology related to wafer scale integration.

Donlan, B.J.

1986-01-01

88

VLSI based implementation of PCM MUX encoder for range telemetry system  

Microsoft Academic Search

The development of highly efficient VLSI technology and rapid advancement of FPGA & CPLD architecture has created a revolution in the design approach of complex electronic systems. The discrete event driven system designs are gradually replaced with highly advanced integrated system design methodology. The present paper describes the VLSI based implementation of pulse code modulated (PCM) multiplexer and encoder schemes

G. Sadhukhan; M. Sandhu; R. P. Singh

2004-01-01

89

Analog VLSI Implementation of Artificial Neural Networks with Supervised On-Chip Learning  

Microsoft Academic Search

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and\\/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities

Maurizio Valle

2002-01-01

90

Silicon Wafer Epitaxy  

NSDL National Science Digital Library

This Quicktime animation shows an optional process for creating silicon epitaxial wafers. The animations shows a trichlorosilane gas being injected which creates a monocrystaline film atop the preexisting wafer. This is the seventh animation in a series of how silicon wafers are created. The previous animation showing silicon wafer polishing can be seen here.The next and final animation in this sequence about silicon wafer laser inspection can be seen here.

2009-10-19

91

SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers  

NASA Astrophysics Data System (ADS)

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

2010-02-01

92

Dictionary machine (for VLSI)  

SciTech Connect

The authors present the design of a dictionary machine that is suitable for VLSI implementation, and discusses how to realize this implementation efficiently. The machine supports the operations of search, insert, delete, and extractment on an arbitrary ordered set. Each of these operations takes time o(logn), where n is the number of entries present when the operation is performed. Moreover, arbitrary sequences of these instructions can be pipelined through the machine at a constant rate (i.e. independent of n and the capacity of the machine). The time o(logn) is an improvement over previous VLSI designs of dictionary machines which require time o(log n) per operation, where n is the maximum number of keys that can be stored. 10 references.

Ottmann, T.A.; Rosenberg, A.L.; Stockmeyer, L.J.

1982-09-01

93

Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects  

Microsoft Academic Search

We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after

G. Anelli; M. Campbell; M. Delmastro; F. Faccio; S. Floria; A. Giraldo; E. Heijne; P. Jarron; K. Kloukinas; A. Marchioro; P. Moreira; W. Snoeys

1999-01-01

94

Very Large Scale Integration (VLSI).  

ERIC Educational Resources Information Center

|Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must…

Yeaman, Andrew R. J.

95

Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections  

Microsoft Academic Search

Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling

Chiung-Wen Lin; Hsueh-An Yang; Wei Chung Wang; Weileun Fang

2007-01-01

96

Wafer-Level ANA Calibrations at NIST  

Microsoft Academic Search

The National Institute of Standards and Technology has begun a program supporting on-wafer scattering parameter measurements. In contrast to many previous NIST endeavors, this program seeks to transfer methodology into industrial measurement laboratories. The subject of this paper is the development of calibration techniques and algorithms, rather than physical standards, for the measurement of on-wafer scattering parameters. In particular, we

Roger Marks; Kurt Phillips

1989-01-01

97

Electron multi-beam technology for mask and wafer writing at 0.1nm address grid  

NASA Astrophysics Data System (ADS)

An overview of electron beam tool configurations is provided. The adoption of multi-beam writing is mandatory in order to fulfill industrial needs for 11nm HP nodes and below. IMS Nanofabrication realized a 50keV electron multibeam proof-of-concept (POC) tool confirming writing principles with 0.1nm address grid and lithography performance capability. The new architecture will be introduced for mask writing at first, but has also the potential for 1xmask (master template) and direct wafer writing. The POC system achieves the predicted 5nm 1sigma blur across the 82?m x 82?m array of 512 x 512 (262,144) programmable 20nm beams. 24nm HP has been demonstrated and complex patterns have been written in scanning stripe exposure mode. The first production worthy system for the 11nm HP mask node is scheduled for 2014 (Alpha), 2015 (Beta) and 1st generation HVM mask writer tools in 2016. Implementing a multi-axis column configuration, 50x / 100x productivity enhancements are possible for direct 300mm / 450mm wafer writing.

Platzgummer, Elmar; Klein, Christof; Loeschner, Hans

2013-03-01

98

Scheduling semiconductor wafer fabrication  

Microsoft Academic Search

The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

LAWRENCE M. WEIN

1988-01-01

99

Silicon Wafer Polishing  

NSDL National Science Digital Library

This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

2009-10-21

100

Hydrophobic silicon wafer bonding  

Microsoft Academic Search

Silicon wafers with hydrophilic surfaces can be bonded at room temperature (RT). This has been attributed to the presence of OH groups on the mating surfaces that form hydrogen bonds between the two wafers.19 Hydrophobic Si wafers prepared by a dip in diluted HF without subsequent water rinse have shown a similar RT bonding performance.3 Dispersion van der Waals forces

Q.-Y. Tong; E. Schmidt; U. Gösele; M. Reiche

1994-01-01

101

Silicon Wafer Lapping  

NSDL National Science Digital Library

This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

2010-02-08

102

Carbon Nanotubes for VLSI: Interconnect and Transistor Applications  

Microsoft Academic Search

Carbon nanotubes (CNTs) offer unique properties such as the highest current density, ballistic transport, ultrahigh thermal conductivity, and extremely high mechanical strength. Because of these remarkable properties, they have been expected for use as wiring materials and as alternate channel materials for extending complementary metal-oxide-semiconductor (CMOS) performance in future very large scale integration (VLSI) technologies. In this paper, we report

Yuji Awano; Shintaro Sato; Mizuhisa Nihei; Tadashi Sakai; Yutaka Ohno; Takashi Mizutani

2010-01-01

103

Performance analysis of carbon nanotube interconnects for VLSI applications  

Microsoft Academic Search

The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this technology. A model is developed to calculate equivalent circuit parameters for a CNT-bundle interconnect based on interconnect geometry. Us- ing this model, the performance of CNT-bundle interconnects (at local, intermediate and global levels)

Navin Srivastava; Kaustav Banerjee

2005-01-01

104

Are carbon nanotubes the future of VLSI interconnections?  

Microsoft Academic Search

Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper and thereby extend the lifetime of electrical interconnects. This paper examines the state-of-the-art in CNT interconnect

Kaustav Banerjee; Navin Srivastava

2006-01-01

105

Titanic: a VLSI based content addressable parallel array processor  

SciTech Connect

A design is presented for a content addressable parallel array processor (CAPAP) which is both practical and feasible. Its practicality stems from an extensive program of research into real applications of content addressability and parallelism. The feasibility of the design stems from development under a set of conservative engineering constraints tied to limitations of VLSI technology. 1 ref.

Weems, C.; Levitan, S.; Foster, C.

1982-01-01

106

A parallel algorithm for channel routing problems [VLSI  

Microsoft Academic Search

A parallel algorithm for channel routing problems is presented. The problem is to route the given interconnections between two rows of terminals on a multilayer channel where the channel area must be minimized. The current advancement of VLSI chip technology allows one to use four layers composed of two metal layers and two polysilicon layers for routing in a chip.

Nobuo Funabiki; Yoshiyasu Takefuji

1992-01-01

107

Wafer-scale microdevice transfer\\/interconnect: its application in an AFM-based data-storage system  

Microsoft Academic Search

We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer, and interconnect method for batch fabricating systems on chip that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 free-standing cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver wafer

Michel Despont; Ute Drechsler; R. Yu; H. B. Pogge; P. Vettiger

2004-01-01

108

Enabling 3DIC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking  

Microsoft Academic Search

High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of bulk CMOS devices with and

D. Y. Chen; W. C. Chiou; M. F. Chen; T. D. Wang; K. M. Ching; H. J. Tu; W. J. Wu; C. L. Yu; K. F. Yang; H. B. Chang; M. H. Tseng; C. W. Hsiao; Y. J. Lu; H. P. Hu; Y. C. Lin; C. S. Hsu; W. S. Shue; C. H. Yu

2009-01-01

109

Semiconductor Wafer Bonding  

Microsoft Academic Search

When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical

U. Gosele; Q.-Y. Tong

1998-01-01

110

Wafer level chip scale packaging (WL-CSP): an overview  

Microsoft Academic Search

Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when

Philip Garrou

2000-01-01

111

High temperature materials for thin-film thermocouples on silicon wafers  

Microsoft Academic Search

We have developed an instrumented calibration wafer for radiometric temperature measurements in rapid thermal processing (RTP) tools for semiconductor processing. The instrumented wafers have sputter deposited thin-film thermocouples to minimize the thermal disturbance of the wafer by the sensors. The National Institute of Standards and Technology (NIST) calibration wafer also employs platinum–palladium wire thermocouples to achieve a combined standard uncertainty

Kenneth G Kreider; Greg Gillen

2000-01-01

112

Electrical through-wafer interconnects with sub-picofarad parasitic capacitance [MEMS packaging  

Microsoft Academic Search

This paper presents a technology for high density and low parasitic capacitance electrical through-wafer interconnects to an array of capacitive micromachined ultrasonic transducers (CMUTs) on a silicon wafer. Vertical wafer feedthroughs (interconnects) connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the wafer. A 20 to 1 high aspect ratio

C. H. Cheng; A. S. Ergun; B. T. Khuri-Yakub

2001-01-01

113

Scribe characterization vehicle test chip for ultra fast product wafer yield monitoring  

Microsoft Academic Search

Sub 100nm technology nodes face more wafer to wafer and lot to lot variability. 300mm wafer manufacturing also faces larger within wafer spatial trends. Monitoring those issues on a per layer basis as well as correlating them to the product yield is key for significant yield improvements. A novel characterization vehicle® (CV®) has been developed, which is being used in

Christopher Hess; Anand Inani; Yun Lin; Michele Squicciarini; Ron Lindley; Nobuchika Akiya

2006-01-01

114

Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics  

SciTech Connect

Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

None

2010-01-15

115

Knowledge Based Approach to VLSI CAD.  

National Technical Information Service (NTIS)

Artificial Intelligence (AI) techniques offer one possible avenue toward new CAD tools to handle the complexities of VLSI. This paper summarizes the experience of the Rutgers AI/VLSI group in exploring applications of AI to VLSI design over the past few y...

L. I. Steinberg T. M. Mitchell

1983-01-01

116

VLSI design at the undergraduate level  

Microsoft Academic Search

An attempt has been made to introduce VLSI design education into the traditional undergraduate electrical engineering curriculum at the State University of New York, New Paltz, through an innovative one-semester digital VLSI design course sequence. The emphasis in VLSI education is on full custom design, thereby exposing undergraduate students to the lower levels of design. The course is compatible with

A. Srivastava; K. Audenaerde

1989-01-01

117

Three wafer stacking for 3D integration.  

SciTech Connect

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

2011-11-01

118

Reliable and low cost wafer level packaging. Process description and qualification testing results for wide area vertical expansion (WAVE TM) package technology  

Microsoft Academic Search

A number of companies around the world are developing or have begun offering devices processed and packaged in the wafer format. Most of these competing concepts involve the creation of a redistribution layer over the face of the chip, a method long employed by IBM in the development of its well known flip-chip C4 processes. Wafer level packaging has the

V. Solberg; D. Light; J. Fjelstad

2000-01-01

119

Image quality and wafer level optics  

NASA Astrophysics Data System (ADS)

Increasing demand from consumers to integrate camera modules into electronic devices, such as cell phones, has driven the cost of camera modules down very rapidly. Now that most cell phones include at least one camera, consumers are starting to ask for better image quality - without compromising on the cost. Wafer level optics has emerged over the past few years as an innovative technology enabling simultaneous manufacturing of thousands of lenses, at the wafer level. Using reflow-compatible materials to manufacture these lenses permits a reduction in the cost and size of camera module, thus answering the market demand for lowering the cost. But what about image quality? The author will present image quality analysis that was conducted for both VGA and megapixel camera resolutions. Comparison between conventional camera modules and wafer level camera modules shows wafer level technology brings equivalent, if not better, image quality performance compared to conventional camera modules.

Dagan, Y.; Humpston, G.

2010-04-01

120

Wafer LMC accuracy improvement by adding mask model  

NASA Astrophysics Data System (ADS)

Mask effect will be more sensitive for wafer printing in high-end technology. For advance only using current wafer model can not predict real wafer behavior accurately because it do not concern real mask performance (CD error, corner rounding..). Generally, we use wafer model to check whether our OPC results can satisfy our requirements (CD target). Through simulation on post-OPC patterns by using wafer model, we can check whether these post-OPC patterns can meet our target. Hence, accuracy model can help us to predict real wafer printing results and avoid OPC verification error. To Improve simulation verification accuracy at wafer level and decrease false alarm. We must consider mask effect like corner rounding and line-end shortening...etc in high-end mask. UMC (United Microelectronics Corporation) has cooperated with Brion and DNP to evaluate whether the wafer LMC (Lithography Manufacturability Check) (Brion hot spots prediction by simulation contour) accuracy can be improved by adding mask model into LMC verification procedure. We combine mask model (DNP provide 45nm node Poly mask model) and wafer model (UMC provide 45nm node Poly wafer model) then build up a new model that called M-FEM (Mask Focus Energy Matrix model) (Brion fitting M-FEM model). We compare the hotspots prediction between M-FEM model and baseline wafer model by LMC verification. Some different hotspots between two models were found. We evaluate whether the hotspots of M-FEM is more close to wafer printing results.

Lo, Wei Cyuan; Cheng, Yung Feng; Chen, Ming Jui; Haung, Peter; Chang, Stephen; Tsujimoto, Eiji

2010-03-01

121

Assembly and Hermetic Encapsulation of Wafer Level Secondary Batteries  

Microsoft Academic Search

A new technology was developed for the construction and hermetic encapsulation of chip-size secondary lithium-ion batteries on a wafer-level plane. To reduce the size of the package and improve the handling and assembly of miniature batteries, we established a wafer-level process that combines foil processing of Li batteries and wafer technologies for battery contacts and encapsulation. Parylene and thin-film metal

K. Marquardt; R. Hahn; T. Luger; H. Reichl

2006-01-01

122

Wafer Temperature Measurement and Control During Laser Spike Annealing  

Microsoft Academic Search

Sub-melt millisecond annealing technologies have been widely accepted for current and future IC fabrication. Real-time temperature control, both within wafer and from wafer-to-wafer, is one of the key challenges that must be addressed for the successful introduction of any millisecond annealing technology into a production environment. In this paper, we show results from a novel pyrometry approach that measures the

Shaoyin Chen; J. Hebb; A. Jain; S. Shetty; Yun Wang

2007-01-01

123

PERFORATED WAFER FUEL ELEMENTS  

Microsoft Academic Search

A method of compacting perforated wafers from a mixture of stainless ; steel and 30 wt.% UOâ its described. A die containing 68 core pins was ; constructed tc compact wafers 5\\/8 in. square, 1\\/4 in. thick containing 68 holes. ; These holes are 0.068 in. in diameter and the distance between adjacent holes is ; 0.012 in. From results

H. S. Kalish; E. N. Mazza; G. Zuromsky

1954-01-01

124

Semiconductor wafer bonding  

Microsoft Academic Search

When mirror-polished, flat, and clean wafers are brought into contact, they are locally attracted to each other and adhere or bond. This phenomenon is known as semiconductor wafer bonding. Different adhesion forces (van der Waals forces, hydrogen bonding) are the reason for the bonding effect at room temperature. The different bonding mechanisms acting in dependence on the surface conditions (hydrophilic,

M. Reiche

2006-01-01

125

Wafer-level membrane transfer bonding of polycrystalline silicon bolometers for use in infrared focal plane arrays  

Microsoft Academic Search

In this paper we present a new, innovative technology for fabrication and integration of free-hanging transducers. The transducer structures are processed on the original substrate wafer (sacrificial device wafer) and then transferred to a new substrate wafer (target wafer). The technology consists only of low-temperature processes, thus it is compatible with integrated circuits. We have applied the new membrane transfer

Frank Niklaus; Edvard Kälvesten; Göran Stemme

2001-01-01

126

New laser scanning techniques for wafer inspection  

NASA Astrophysics Data System (ADS)

A laser scanning system designed for inspection of patterned wafers is described. This system addresses the inspection needs for 64 Mb (0.35 micrometers ) and 256 Mb (0.25 micrometers ) DRAM process technologies. The system is capable of detecting contaminant particles and planar pattern defects on memory and logic devices. The throughput of the system is designed for 30 wafers (200 mm in diameter) per hour. The beam at 488 nm is brought to a focal spot and is scanned on the wafer surface using an acousto-optic deflector (AOD). The entire wafer is scanned under oblique illumination in narrow strips in a serpentine fashion. The specular beam is collected and processed in, what we have named, the autoposition sensor (APS) to servo- lock the height position of the wafer during the scan. The system utilizes multiple independent collection channels positioned around the scan line and it is possible to select the polarization of the collected light for enhanced signal-to-background ratio. The engineering tradeoffs for realizing a system with high throughput and sensitivity are formulated and discussed. Calculations ilustrating scattering from submicron size particles under various polarization conditions are shown. These results lead to optimum design for collection optics. The APS channel is described and illustrated by results indicating that it is possible to keep the surface height of the wafer constant to within 0.4 micrometers in the presence of large changes in topography and wafer reflectivity. Results obtained from a range of production wafers demonstrating detection of 0.1 micrometers anomalies on bare wafer, 0.3 micrometers on memory devices, and 0.4 micrometers on random logic structures are presented.

Nikoonahad, Mehrdad; Leslie, Brian C.; Stokowski, Stanley E.; Trafas, Brian M.; Wells, Keith B.

1995-09-01

127

Cost effective, mass productive Wafer-Level Chip Size Package (WLCSP) technology applied to Ku-band frequency converters  

Microsoft Academic Search

Cost effective, mass productive Ku-band up- and down-converter MMIC's for wireless communication are presented. These MMIC's are designed by using a three-dimensional MMIC technology that optimized for flip-chip solder reflow-compatible implementation; hence, that removes necessity of packaging. The MMIC structure incorporates inverse TFMS lines so that a ground metal can be applied to cover the whole chip surface except for

S. Fujita; M. Imagawa; T. Satoh; T. Tokumitsu; Y. Hasegawa

2010-01-01

128

A parallel processing VLSI BAM engine.  

PubMed

In this paper emerging parallel/distributed architectures are explored for the digital VLSI implementation of adaptive bidirectional associative memory (BAM) neural network. A single instruction stream many data stream (SIMD)-based parallel processing architecture, is developed for the adaptive BAM neural network, taking advantage of the inherent parallelism in BAM. This novel neural processor architecture is named the sliding feeder BAM array processor (SLiFBAM). The SLiFBAM processor can be viewed as a two-stroke neural processing engine, It has four operating modes: learn pattern, evaluate pattern, read weight, and write weight. Design of a SLiFBAM VLSI processor chip is also described. By using 2-mum scalable CMOS technology, a SLiFBAM processor chip with 4+4 neurons and eight modules of 256x5 bit local weight-storage SRAM, was integrated on a 6.9x7.4 mm(2) prototype die. The system architecture is highly flexible and modular, enabling the construction of larger BAM networks of up to 252 neurons using multiple SLiFBAM chips. PMID:18255644

Hasan, S R; Siong, N K

1997-01-01

129

Algorithms for VLSI artwork  

SciTech Connect

The specific problems that the author studies in this thesis are painting and drawing of rectilinear polygons, covering rectilinear polygons by rectangles, and partitioning rectilinear polygons into rectangles. These problems have application to VLSI design, computer graphics, etc. He considers three display devices, one-dimensional and two dimensional pen plotters, and video screens, for the problem of painting and covering. An 0 (n log n) time algorithm to obtain an optimal drawing strategy on one-dimensional plotters is obtained (n is the number of the vertices of the polygons). Fore the case of a two-dimensional plotter, the strategy to optimally draw the contour of a rectilinear polygon can be found in linear time. However, for a collection of rectilinear polygons, this problem is NP-hard. For screen type displays, he formulates three strategies to paint a rectilinear polygon using a rectangle as a primitive. For two of these, he shows the problem NP-hard. Performance bounds for these strategies are also obtained. Three approximation algorithms to cover a rectilinear polygon that is neither horizontally nor vertically convex by rectangles are developed. All three guarantee covers that have at most twice as many rectangles as in an optimal cover. The complexities of those algorithms are O (n log n), O(n{sup 2}), and O(n{sup 4}), respectively. Finally, he develops two algorithms to obtain the optimal partition of simple rectilinear polygons. Their time complexities are {approximately} O (kn) and O (n log k), where k is the number of the inversions of the polygon. Both are significantly faster than the existing best algorithm on polygons whose size is large relative to k.

Wu, San-Yuan.

1989-01-01

130

A study on fine pitch Au and Cu WB integrity vs. Ni thickness of Ni\\/Pd\\/Au bond pad on C90 low k wafer technology for high temperature automotive  

Microsoft Academic Search

For high temperature automotive application, IC products are required to pass stringent high temperature storage stress test (e.g. 5000hrs at 150 deg C), hence requires reliable wire bonds. Such requirement is especially challenging with fine pitch Au & Cu wire bond (e.g. bond pad pitch >; 70um and bonded ball diameter <; 58um), more-so on low k wafer technology with

Eu Poh Leng; Poh Zi Song; Au Yin Kheng; C. C. Yong; Anh Tran Tu; J. Arthur; H. Downey; V. Mathew; Chee Yit Yin

2010-01-01

131

High temperature automotive application: A study on fine pitch Au and Cu WB integrity vs. Ni thickness of Ni\\/Pd\\/Au bond pad on C90 low k wafer technology  

Microsoft Academic Search

For high temperature automotive application, IC products are required to pass stringent high temperature storage stress test (e.g. 5000hrs at 150 deg C), hence requires reliable wire bonds. Such requirement is especially challenging with fine pitch Au & Cu wire bond (e.g. bond pad pitch <; 70um and bonded ball diameter <; 58um), more-so on low k wafer technology with

Eu Poh Leng; Poh Zi Song; Au Yin Kheng; C. C. Yong; Tran Tu Anh; J. Arthur; H. Downey; V. Mathew; Chee Yit Yin

2010-01-01

132

Wafer characteristics via reflectometry  

SciTech Connect

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

133

Interface study of bonded wafers by digitized linear frequency modulated thermal wave imaging  

Microsoft Academic Search

Thermography is a whole field, non-contact and non-destructive characterization technique that is widely used for the investigation of sub-surface features in various kinds of solid materials (conductors, semiconductors, insulators and polymers). In this work, a new method is proposed and demonstrated for the interface study of the bonded wafers that are frequently used in MEMS and VLSI. For the demonstration,

Ravibabu Mulaveesala; Prem Pal; Suneet Tuli

2006-01-01

134

From Wafer to Package  

NSDL National Science Digital Library

This website includes an animation of finished wafer to packaged integrated Circuits. Objective: Describe the wafer to packaged device process steps. This simulation is from Module 075 of the Process & Equipment III Cluster of the MATEC Module Library (MML). You will find the animation under the heading "Process & Equipment III." To view other clusters or for more information about the MML visit http://matec.org/ps/library3/process_I.shtmlKey

2012-11-21

135

VLSI scaling methods and low power CMOS buffer circuit  

NASA Astrophysics Data System (ADS)

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Sharma, Vijay Kumar; Pattanaik, Manisha

2013-09-01

136

Transfer of metal MEMS packages using a wafer-level solder transfer technique  

Microsoft Academic Search

This paper presents a modular, low profile, wafer-level encapsulation technology for microelectromechanical systems (MEMS) packaging. Electroplated caps are formed on top of a solder transfer layer previously deposited on a carrier wafer, then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled

Warren C. Welch; Junseok Chae; Khalil Najafi

2005-01-01

137

Transfer of metal MEMS packages using a wafer-level solder sacrificial layer  

Microsoft Academic Search

This paper presents a modular, low profile, wafer-level encapsulation technology for 0-level MEMS packaging. Electroplated caps are formed on a carrier wafer then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled by the dewetting of the solder transfer layer from the

Warren C Welch; Khalil Najafi

2005-01-01

138

Closed-loop electroosmotic microchannel cooling system for VLSI circuits  

Microsoft Academic Search

The increasing heat generation rates in VLSI circuits motivate research on compact cooling technologies with low thermal resistance. This paper develops a closed-loop two-phase microchannel cooling system using electroosmotic pumping for the working fluid. The design, fabrication, and open-loop performance of the heat exchanger and pump are summarized. The silicon heat exchanger, which attaches to the test chip (1 cm2),

Linan Jiang; James Mikkelsen; Jae-Mo Koo; David Huber; Shuhuai Yao; Lian Zhang; Peng Zhou; James G. Maveety; Ravi Prasher; Juan G. Santiago; Thomas W. Kenny; Kenneth E. Goodson

2002-01-01

139

Metrology of 300 mm silicon wafers: Challenges and results  

Microsoft Academic Search

Challenging requirements have to be met by metrology tools for 300 mm wafers and technology generations <=0.25 mum in near future. Measurement equipment for some specific wafer parameters presently operates already at its limits and will not be able to meet the future requirements. New tools therefore were or are currently developed. The future requirements are outlined and examples for

P. Wagner

1998-01-01

140

AWV: high-throughput cross-array cross-wafer variation mapping  

NASA Astrophysics Data System (ADS)

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision(TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevy, Ofer

2008-04-01

141

RF W-band wafer-to-wafer transition  

Microsoft Academic Search

Multiwafer silicon designs must provide an avenue for electrical signals to flow from wafer to wafer. For this purpose, a two-layer electrical bond is proposed to provide electrical connection between two coplanar waveguides printed on the adjacent faces of two vertically stacked silicon wafers. In addition to serving as a versatile low-temperature thermocompression wafer bond, loss of approximately 0.1 dB

Katherine J. Herrick; Linda P. B. Katehi

2001-01-01

142

Wafer-level package interconnect options  

Microsoft Academic Search

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare

Jayaprakash Balachandran; Steven Brebels; Geert Carchon; Maarten Kuijk; Walter De Raedt; Bart K. J. C. Nauwelaers; Eric Beyne

2006-01-01

143

Scanning holographic scatterometer for wafer surface inspection  

NASA Astrophysics Data System (ADS)

The semiconductor industry requires ever smaller semiconductor structures with faster response times and more function per unit area of each chip. In addition, the industry is changing from 200 mm to 300 mm diameter wafers with fewer defects and rapid detection at all processing stages. To meet these needs, defect data must be processed in near-real-time to expedite correction of processing problems at the earliest possible stage. Under a Small Business Innovation Research (SBIR) program, sponsored by the Air Force Manufacturing Technology Division at Wright Laboratory, Dayton, Ohio, Sentec Corporation has developed a revolutionary technology for contaminant particle detection on unpatterned semiconductor wafers. A key to the Sentec technology is detection, not of the intensity of backscattered energy from particles or defects, but of the amplitude of the electro-magneitc field of this backscattered energy. This new technology will allow the detection of particles that are significantly smaller than those which can be reliably located using current scatterometers. The technical concepts for a stand-alone particle detection tool have been created. It uses a continuous scanning mechanism to perform high-speed examinations of target wafers. This tool, also, has the capability of quantifying the microroughness or background haze of a subject wafer and presenting that information separate from the contamination particle data. During the course of this project, three patent applications were filed.

Klooster, Alex; Marks, James; Hanson, Kael; Sawatari, Takeo

2004-05-01

144

Rapid isothermal processing of silicon wafers  

Microsoft Academic Search

The reduction in the size of semiconductor devices has not only increased their speed and the number that can be fitted on a chip but has also led to the need for very accurately controlled thermal processing of the semiconductor wafers. Conventional furnaces are used as standard in IC processing but now, however, alternative rapid isothermal processing technologies are gaining

S. S. Gill

1986-01-01

145

Laser cutting of CVD diamond wafers  

Microsoft Academic Search

CVD diamond has many outstanding physical properties. Because of its extreme hardness, this material is difficult to cut and polish and laser cutting and shaping is a technology of choice. Thick polycrystalline diamond layers were deposited by microwave plasma enhanced chemical vapor deposition on silicon substrates. After synthesis, the silicon substrate was dissolved in an acid mixture and diamond wafer

Hana Chmelickova; Milan Vanecek; Jan Rosa; Martin Stranyanek

2005-01-01

146

Silicon waveguides produced by wafer bonding  

SciTech Connect

X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 {mu}m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides to excite single guided modes at typical x-ray energies.

Poulsen, M.; Jensen, F.; Bunk, O.; Feidenhans'l, R.; Breiby, D.W. [Department of Micro and Nanotechnology, Technical University of Denmark, Oersteds Plads, DK-2800 Kgs. Lyngby (Denmark) and Materials Research Department, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark); DANCHIP, Technical University of Denmark, Oersteds Plads, DK-2800 Kgs. Lyngby (Denmark); Materials Research Department, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark); Danish Polymer Centre, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark)

2005-12-26

147

Fast area-efficient VLSI adders  

Microsoft Academic Search

In this paper, we study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results we obtain lead to the design of area-time efficient VLSI adders. This is a major goal of our work: to design very low latency addition circuitry that is also area efficient.

Tackdon Han; David A. Carlson; Tack-don Han

1987-01-01

148

A Cross-Cultural VLSI Design Project  

Microsoft Academic Search

Harvey Mudd College (HMC) and the Middle East Technical University (METU) have conducted a joint cross-cultural Very Large Scale Integration (VLSI) design course supported by a grant from the Mellon Foundation. In the spring of 2002, three teams of two American students HMC enrolled in E158 (Introduction to CMOS VLSI Design) worked with teams of two Turkish students from METU

David Harris; Tayfun Akin

2003-01-01

149

Wafer-scale graphene integrated circuit.  

PubMed

A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance. PMID:21659599

Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

2011-06-10

150

Wafer-level sandwiched packaging for high-yield fabrication of high-performance mems inertial sensors  

Microsoft Academic Search

A wafer-level sandwiched packaging technology is developed for micromechanical sensors such as inertial sensors, which comprise movable parts, e.g. spring-mass structures. Via a thin polymer intermediate layer of benzocyclobuene (BCB), a pre-micromachined silicon cap wafer is aligned bonded with the sensor-chip wafer. Prior to the BCB bonding, the sensor-chip wafer was formed by anodic bonding a Pyrex-7740 glass wafer to

Kun Zhang; Wei Jiang; Xinxin Li

2008-01-01

151

The test of VLSI circuits  

NASA Astrophysics Data System (ADS)

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

Baviere, Ph.

152

VLSI Array processors  

Microsoft Academic Search

High speed signal processing depends critically on parallel processor technology. In most applications, general-purpose parallel computers cannot offer satisfactory real-time processing speed due to severe system overhead. Therefore, for real-time digital signal processing (DSP) systems, special-purpose array processors have become the only appealing alternative. In designing or using such array Processors, most signal processing algorithms share the critical attributes of

S. Kung

1985-01-01

153

Thin Film Encapsulation for Secondary Batteries on Wafer Level  

Microsoft Academic Search

This paper presents results concerning the realization and characterization of thin film encapsulated wafer-level batteries. Initially, the technology concept for the construction and hermetic encapsulation of chip-size lithium-ion secondary batteries on wafer level is introduced. Parylene and thin-film metal deposition was used for hermetic encapsulation of the batteries. With this technology, battery sizes between 1 mm2 and 1 cm2, and

K. Marquardt; R. Hahn; T. Lugerl; H. Reichl

2006-01-01

154

Solder joint reliability of a polymer reinforced wafer level package  

Microsoft Academic Search

Wafer level packages (WLPs) have demonstrated a very clear cost-advantage vs traditional wire-bond technologies, especially for small components that have a high number of dice and I\\/O per wafer. Ultra CSP® is a WLP developed by the Kulicke & Soffa Flip Chip Division (formally Flip Chip Technologies). Typical products utilizing the Ultra chip scale package (CSP) have 5×5 or less

Deok-hoon Kim; Peter Elenius; Michael Johnson; Scott Barrett

2002-01-01

155

Interferometric metrology of wafer nanotopography for advanced CMOS process integration  

NASA Astrophysics Data System (ADS)

According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

2001-12-01

156

Wafer level warpage characterization of 3D interconnect processing wafers  

NASA Astrophysics Data System (ADS)

We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 ?m after thinning down to the nominal thickness of 75 ?m and 50 ?m. The measurement precision is better than 2 um.

Chang, Po-Yi; Ku, Yi-Sha

2012-03-01

157

PAPER Special Issue on Low-Power High-Performance VLSI Processors and Technologies Trends in High-Performance, Low-Power Processor Architectures  

Microsoft Academic Search

SUMMARY This paper briefly surveys architectural tech- nologies of recent or future high-performance, low-power proces- sors for improving the performance and power\\/energy consump- tion simultaneously. Achieving both high performance and low power at the same time imposes a lot of challenges on processor design, and therefore gives us a lot of opportunities for devising new technologies. The paper also tries

Kazuaki MURAKAMI; Hidetaka MAGOSHI

158

Statistical Process Control System for VLSI Fabrication.  

National Technical Information Service (NTIS)

The CMU-CAM system for statistical process control of VLSI (very large scale integration) manufacturing is described. It is a software system which can perform statistical quality control and feed-forward control rescheduling on line, and process diagnosi...

A. J. Strojwas

1989-01-01

159

A knowledge based approach to VLSI CAD  

NASA Astrophysics Data System (ADS)

Artificial Intelligence (AI) techniques offer one possible avenue toward new CAD tools to handle the complexities of VLSI. This paper summarizes the experience of the Rutgers AI/VLSI group in exploring applications of AI to VLSI design over the past few years. In particular, it summarizes our experience in developing REDESIGN, a knowledge-based system for providing interactive aid in the functional redesign of digital circuits. Given a desired change to the function of a circuit, REDESIGN combines rule-based knowledge of design tactics with its ability to analyze signal propagation through circuits, in order to (1) help the user focus on an appropriate portion of the circuit to redesign, (2) suggest local redesign alternatives, and (3) determine side effects of possible redesigns. We also summarize our more recent research toward constructing a knowledge-based system for VLSI design and a system for chip debugging, both based on extending the techniques used by the REDESIGN system.

Steinberg, L. I.; Mitchell, T. M.

1983-09-01

160

Reconfigurable VLSI architecture for a database processor  

SciTech Connect

This work brings together the processing potential offered by regularly structured VLSI processing units and the architecture of a database processor-the relational associative processor (RAP). The main motivations are to integrate a RAP cell processor on a few VLSI chips and improve performance by employing procedures exploiting these VLSI chips and the system level reconfigurability of processing resources. The resulting VLSI database processor consists of parallel processing cells that can be reconfigured into a large processor to execute the hard operations of projection and semijoin efficiently. It is shown that such a configuration can provide 2 to 3 orders of magnitude of performance improvement over previous implementations of the RAP system in the execution of such operations. 27 refs.

Oflazer, K.

1983-01-01

161

Constant fan-in digital neural networks are VLSI-optimal  

SciTech Connect

The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

Beiu, V.

1995-12-31

162

Designing of Low-Power VLSI Circuits using Non-Clocked Logic Style  

NASA Astrophysics Data System (ADS)

Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the vlsi circuits with the performance upto the acceptable level. The dominant term in a well designed vlsi circuit is the switching power and low-power design thus becomes the task of minimizing this switching power. So, to design a low-power vlsi circuit, it is preferable to use Nonclocked logic styles as they have less switching power. In this work various Non-clocked logic styles are compared by performing transistor level simulations for half adder circuit using TSMC 0.18 µm Technology and Eldo simulator of Mentor graphics.

Sharma, Vishal; Srivastava, Jitendra Kaushal

2012-08-01

163

Wafer-scale micro-optics fabrication  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Voelkel, Reinhard

2012-07-01

164

Algorithms for VLSI routing. [Very Large Scale Integration, semiconductor chip design  

Microsoft Academic Search

This thesis considers the problems arising from VLSI routing design. Algorithms are proposed for solving both global and local routing problems. For routing multiterminal nets in the gate array and sea-of-gates technologies, the author presents a global router which upper bounds the global density of the routing by 2s*, where s* is the span of the nets. For standard cell

Zhou; Dian

1990-01-01

165

The triangle processor and normal vector shader: a VLSI system for high performance graphics  

Microsoft Academic Search

Current affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated. Massively parallel VLSI system have the potential to bypass this bottleneck, but

Michael Deering; Stephanie Winner; Bic Schediwy; Chris Duffy; Neil Hunt

1988-01-01

166

Optima XE Single Wafer High Energy Ion Implanter  

SciTech Connect

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny [Axcelis Technologies, Inc. 108 Cherry Hill Drive, Beverly, MA 01915 (United States)

2008-11-03

167

Augmented reality for wafer prober  

NASA Astrophysics Data System (ADS)

The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

Gilgenkrantz, Pascal

2011-02-01

168

A coherent VLSI design environment  

NASA Astrophysics Data System (ADS)

The research discussed here is described in more detail in several published and unpublished reports cited. The CAD frame Schema has progressed to the point where it is useful for ample chip designs. The interface to CIF is complete, and work has begun on importing layout libraries. An interface to EDIF is being installed. Simulators can now be connected, and thought is going into organization of VLSI libraries. A plan for the distribution of Schema is now being worked out. Previous results on waveform bounding have been generalized to large classes of problems described in canonical control-theory form. Work has begun on models for interconnect taking account of line inductance. This domain is less general than RLC networks, and there is hope that some of the previously derived bounds still apply. During this period a novel device, the UV write-enabled PROM, was reported at a conference. Work continues on developing useful circuits employing this device.

Penfield, P., Jr.; Glasser, L. A.; Knight, T. F., Jr.; Leiserson, C. E.; Rivest, R. L.

1985-09-01

169

Wafer sampling by regression for systematic wafer variation detection  

Microsoft Academic Search

In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an

Byungsool Moon; James McNames; Bruce Whitefield; Paul Rudolph; Jeff Zola

2005-01-01

170

On the evolution of wafer level cameras  

NASA Astrophysics Data System (ADS)

The introduction of small cost effective cameras based on CMOS image sensor technology has played an important role in the revolution in mobile devices of the last 10 years. Wafer-based optics manufacturing leverages the same fabrication equipment used to produce CMOS sensors. The natural integration of these two technologies allows the mass production of very low cost surface mount cameras that can fit into ever thinner mobile devices. Nano Imprint Lithography (NIL) equipment has been adapted to make precision aspheres that can be stacked using wafer bonding techniques to produce multi-element lens assemblies. This, coupled with advances in mastering technology, allows arrays of lenses with prescriptions not previously possible. A primary motivation for these methods is that it allows the consolidation of the supply chain. Image sensor manufacturers envision creating optics by simply adding layers to their existing sensor fabrication lines. Results thus far have been promising. The current alternative techniques for creating VGA cameras are discussed as well as the prime cost drivers for lens to sensor integration. Higher resolution cameras face particularly difficult challenges, but can greatly simplify the critical tilt and focus steps needed to assemble cameras that produce quality images. Finally, we discuss the future of wafer-level cameras and explore several of the novel concepts made possible by the manufacturing advantages of photolithography.

Welch, H.

2011-02-01

171

Low temperature epoxy bonding for wafer level MEMS packaging  

Microsoft Academic Search

In this paper, we report on a technology for wafer-level MEMS packaging with vertical via holes and low temperature bonding using a patternable B stage epoxy. We fabricated via holes for vertical feed-throughs and then applied bottom-up copper electroplating to fill the via holes. For low temperature wafer level packaging, we used B-stage epoxy bonding in the sealing line. The

Yong-Kook Kim; Eun-Kyung Kim; Soo-Won Kim; Byeong-Kwon Ju

2008-01-01

172

A VLSI design concept for parallel iterative algorithms  

NASA Astrophysics Data System (ADS)

Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified ?-rotation CORDIC architecture.

Sun, C. C.; Götze, J.

2009-05-01

173

VLSI Architecture Design Approaches for Real-Time Video Processing  

Microsoft Academic Search

This paper discusses the programmable and dedicated approaches for real-time video processing applications. Various VLSI architecture including the design examples of both approaches are reviewed. Finally, discussions of several practical designs in real-time video processing applications are then considered in VLSI architectures to provide significant guidelines to VLSI designers for any further real-time video processing design works.

A. AHMAD; K. K. LOO; J. COSMAS

2008-01-01

174

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

2009-03-01

175

VLED for Si wafer-level packaging  

NASA Astrophysics Data System (ADS)

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-02-01

176

Simulating conveyor-based amhs layout configurations in small wafer lot manufacturing environments  

Microsoft Academic Search

Automated material handling systems (AMHS) using conveyors have been recently proposed as a technology option for next generation wafer fabrication facilities. This technology seems to provide an increasing capacity for moving and storing wafers in a continuous flow transport environment. The goal of this research is to design and test conveyor-based AMHS configurations, which include turntables and storage areas near

Leanna Miller; Alger Bradley; Ashley Tish; Tongdan Jin; Jesus A. Jimenez; Robert Wright

2011-01-01

177

Further investigation of EUV process sensitivities for wafer track processing  

NASA Astrophysics Data System (ADS)

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

Bradon, Neil; Nafus, K.; Shite, H.; Kitano, J.; Kosugi, H.; Goethals, M.; Cheng, S.; Hermans, J.; Hendrickx, E.; Baudemprez, B.; van den Heuvel, D.

2010-03-01

178

Channel routing for VLSI layout  

NASA Astrophysics Data System (ADS)

Channel routing for VLSI layout is reviewed and a set of features required of an industrial channel router is defined. A channel router, CAR, was implemented, based on the Greedy and Detour routers. Integrated circuit design is discussed, with attention to the various channel routing problems and models. The major requirements for an industrial channel router to be integrated within general cells and standard cells routing environments are discussed and their fulfillment in CAR is considered. CAR comprises: the Greedy router functionality; the Detour router's obstacle, obstruction and switch box extensions; rectilinear channels; ports located not on standard and immediately surrounding layers; middle ports within the channel; jog on conflict-only to reduce jog use; single layer jogs; and partial pre-routing and dynamic layer optimization. Special features of CAR include: extension of the net definition with a short range tendency; definition of net preferred track; net visibility range in rectilinear channels; an extended area mechanism to deal with obstacles, rectilinear edges, pre-routing and ports on unusual layers; unified jog cost evaluation functions; unified, efficient jog selection; a general evaluation function for track worth; and a net connectivity part to control and handle split nets. Examples are presented of CAR operations.

Schory, Michael

1988-12-01

179

Optical leak detection for wafer level hermeticity testing  

Microsoft Academic Search

Cost reduction in optoelectronic and MEMS packaging is a key issue already today and will become even more important in the future. We developed a novel hermetic packaging technology and an optical leak detector for wafer level assembly and testing, respectively. Silicon caps (HyCap®) for localized hermetic sealing are manufactured using standard MEMS technology. Sensitive optoelectronic or MEMS devices are

Gordon Elger; Lior Shiv; Nika Nikac; Frank Müller; Rainer Liebe; Marcus Grigat

2004-01-01

180

Optical pressure sensor head fabrication using ultrathin silicon wafer anodic bonding  

NASA Astrophysics Data System (ADS)

A technology for fabricating fiber optically interrogated pressure sensors is described. This technology is based on anodic bonding of ultra-thin silicon wafers to patterned, micro-machined glass wafers, providing low-cost fabrication of optical pressure sensor heads that operate with reproducible technical characteristics in various dynamic ranges. Pressure sensors using 10, 20 and 50 micron thick silicon wafers for membranes have been fabricated on 10 cm diameter, 500-micron thick, Pyrex glass wafers. The glass wafers have been micro-machined using ultrasonic drilling in order to form cavities, optical fiber feedthrough holes and vent holes. One of the main challenges of the manufacturing process is the handling of the ultra-thin silicon wafers. Being extremely flexible, the thin silicon wafers cannot be cleaned, oxidized, or dried in the same way as normal since wafers with a thickness of the order of 400 microns. Specific handling techniques have been developed in order to achieve reproducible cleaning and oxidation processes. The anodic bonding was performed using an Electronic Visions EV501S bonder. The wafers were heated at 420 degrees C and a voltage of 1200 volts was applied in vacuum of 10-5 Torr. The bonded wafer stack was then fixed in a wax and diced. The resulting chips have been used to fabricate operating pressure sensors.

Beggans, Michael H.; Ivanov, Dentcho I.; Fu, Steven G.; Digges, Thomas G.; Farmer, Kenneth R.

1999-03-01

181

Wafer-level optics enables low cost camera phones  

NASA Astrophysics Data System (ADS)

To meet market demand and enable the proliferation of camera phones for developing countries, manufacturers must be able to meet requirements for camera modules that are reduced in size and cost. Conventional camera-module technology is heading towards an asymptote, where the optics no longer scale with the required size, performance, and cost. Using wafer-level techniques and reflow compatible materials to manufacture the optics together with wafer-level chip scale packaging (WLCSP) of image sensors enables manufacturing of smaller-size, lower-cost, reflow-compatible camera modules. Focusing on VGA resolution, this paper will present a comparison between optical modules that were built using conventional technology and wafer-level technology.

Dagan, Yehudit

2009-02-01

182

Ion-implanted capacitively coupled double sided silicon strip detectors with integrated polysilicon bias resistors processed on a 100 mm wafer  

Microsoft Academic Search

Silicon strip detectors with double-sided readout have been designed and processed on 100-mm silicon wafers. Detectors with integrated coupling capacitors and polysilicon bias resistors were tested by static electrical measurements. A detector with VLSI readout electronics was measured in a test beam. Test beam measurements show signal over noise ratios of 39 on the detector p-side and 26 on the

M. Aalste; A. Hentinen; I. Hietanen; J. Lindgren; C. Ronnqvist; T. Schulman; T. Tuuva; M. Voutilainen; K. Osterberg; M. Andersson; K. Leinonen; H. Ronkainen; R. Brenner; J. Karsten; J. Straver; W. Dulinski; D. Husson; R. Turchetta; M. Schaeffer; R. Harr

1991-01-01

183

Wafer-scale microdevice transfer\\/interconnect: from a new integration method to its application in an afm-based data-storage system  

Microsoft Academic Search

We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer and interconnect method for batch fabricating system on chip (SOC) that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 freestanding cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver

M. Despont; U. Drechsler; R. Yu; H. B. Pogge; P. Vettiger

2003-01-01

184

Wafer handling and placement tool  

DOEpatents

A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

Witherspoon, Linda L. (22 Cottonwood La., Los Lunas, NM 87031)

1988-01-05

185

300 mm Epitaxy: challenges and opportunities from a wafer manufacturer’s point of view  

Microsoft Academic Search

Results on 300 mm silicon wafer epitaxy according to the 0.18 ?m design rule requirements are presented. Wafer uniformity, surface metals, geometry, and thermal stability demonstrate production capabilities. Localized light scattering particles and crystal defects are identified as the largest technological challenge. Preliminary experiments indicate that industry’s requirements can be met. The p\\/p+ epitaxial wafer is the best candidate to

Per-Ove Hansson; Martin Fuerfanger

1999-01-01

186

Switch floor plants for restructurable VLSI/WSI  

SciTech Connect

An electrically programmable switch has become a promising interconection technique for Restructurable VLSI/WSI systems because of its desirable properties, such as field reprogrammability, conventional fabrication technology and ease of changing the target architecture. However, the electrically programmable switch presents several problems to be solved, including long intermodule communication delay due to switches; the intermodule communication delay degrades VLSI/WSI system performance, particularly when it is a dominant factor in determining system speed. In this research, switch floor planning strategies (called switch floor plans) are proposed. The goal of those switch floor plans is to reduce the average intermodule communication delay and the total number of switches in the system. An ICT (Initial Configuration of Target architecture) design concept and the heterogeneous switch blocks over the target/host architecture are used to achieve such a goal. The ICT design is compared to other conventional-yield-enhancement methods by a combinatorial analysis. The proposed switch floor plans are evaluated by a computer simulation. Results show the desirability of the ICT design and the heterogeneous switches in the RVLSI/WSI system design.

Kim, C.B.

1986-01-01

187

High-performance VLSI architecture for video processing  

NASA Astrophysics Data System (ADS)

Real time image processing is a key issue in nowadays multimedia applications. Image filtering and video coding are two basic applications in image processing. Their algorithms are computationally expensive due to both, the number of points of each frame to be processed, and the calculation complexity per point. The VLSI implementation of these algorithms leads to special architectures that are based on systolic arrays, and whose implementation is greedy in silicon area. In this paper, we propose a configurable and bidimensional pipelined VLSI architecture that supports mathematical morphology operations and the block matching algorithm. Remarkable advantages include low power consumption, and a regular and compact design (in terms of core active area) versus the traditional systolic architecture. The architecture is adequate for both morphological image filtering and video compression, depending on the hardware resources of the processing elements. The main advantage of this bidimensional pipeline architecture is the area saving compared with the systolic array implementation. Total area saving was presented in terms of the number of bits of the FIFO memories that can be eliminated. The proposed architecture was verified at high level in C++, at RTL level using Verilog and at C++/RTL level using DEMETER. Required cycle times was measured for a real time morphological filter per dilation/erosion operation, as a function of the incoming resolution. Physical layouts were obtained for the basic slice of the processing element and for the systolic array using the technology of 0,35 microns CMOS from AMS.

Navarro, Héctor; Montiel-Nelson, Juan A.; Sosa, Javier; García, José C.; Sarmiento, Roberto; Nooshabadi, Saeid

2003-04-01

188

A single chip VLSI architecture for radar signal processing  

NASA Astrophysics Data System (ADS)

The problem of how much radar signal processing one can achieve with a single chip signal processor is investigated through the design of a processor architecture suitable for single chip implementation using very large scale integration (VLSI) technology. The design of the single chip processor departs from existing processor designs both in the way it is structured and the manner in which it performs computations. Major emphasis is placed on taking advantage of the parallelism and pipelining inherent in radar signal processing functions, and on novel processor architecture capable of mapping high-level computations (i.e., complex primitives such as Fast Fourier Transform) directly into hardware. The single chip design is based on state-of-the-art technology and utilizes bit-serial arithmetic and externally supplied First-In First-Out memory.

Kanopoulos, N.

189

Slip-free processing of 300 mm silicon batch wafers  

NASA Astrophysics Data System (ADS)

Under gravitational and thermal constraints of integrated-circuit (IC) process technology, 300-mm-diam silicon wafers can deform via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the upper yield point of the silicon material. The material attributes, such as oxygen content and the state of oxygen aggregation, are taken into account. The theoretical approach allows the calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. Plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design. Deformation due to gravitational forces can be prevented through appropriate equipment design. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulation of ``what if?'' experiments, and initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.

Fischer, A.; Richter, H.; Kürner, W.; Kücher, P.

2000-02-01

190

PLINT layout system for VLSI chips  

Microsoft Academic Search

PLINT is a comprehensive VAX based VLSI chip layout software system. Important features include (1) standard cell row structure layout (POLYPLINT) or randomly placed and sized rectangular macro cells (MACPLINT), (2) unlimited hierarchy, (3) automatic macrocell generation for next hierarchy level, (4) 100% routing, (5) very large chip size and\\/or complexity capability, (6) power and ground bus routing for both

Hart Anway; Greg Farnham; Rebecca Reid

1985-01-01

191

Plint Layout System for VLSI Chips  

Microsoft Academic Search

PLINT is a comprehensive VAX based VLSI chip layout software system. Important features include (1) standard cell row structure layout (POLYPLINT) or randomly placed and sized rectangular macro cells (MACPLINT), (2) unlimited hierarchy, (3) automatic macrocell generation for next hierarchy level, (4) 100% routing, (5) very large chip size and\\/or complexity capability, (6) power and ground bus routing for both

Hart Anway; Greg Farnham; Rebecca Reid

1985-01-01

192

Pipe: a high performance VLSI architecture  

Microsoft Academic Search

The pipe architecture (parallel instructions and pipelined execution) is proposed as a research vehicle for studying high performance VLSI architectures and organizations. Principal features are: 1) it is pipelined, 2) it is capable of a decoupled mode of operation where two processors cooperate in executing the same task and communicate via hardware queues, 3) it has an instruction cache, and

J. E. Smith; A. R. Pleszkun; R. H. Katz; J. R. Goodman

1983-01-01

193

Selective electroless copper for VLSI interconnection  

Microsoft Academic Search

Cu is studied as a candidate for low-resistance VLSI interconnection. Simulation studies show that for effective channel length less than 0.5 ?m, the RC time constant of interconnection is a major part of the total delay. By reducing the resistivity of the interconnect, the operating speed can be increased by more than 20% without any change in design rule. A

P.-L. Pai; C. H. Ting

1989-01-01

194

VLSI Implementation of a Neural Network Model  

Microsoft Academic Search

The authors describe a complementary metal oxide semiconductor (CMOS) very large scale integrated (VLSI) circuit implementing a connectionist neural network model that consists of an array of 54 simple processors fully interconnected with a programmable connection matrix. This experimental design tests the behavior of a large network of processors integrated on a chip. The authors can operate the circuit in

Hans Peter Graf; Lawrence D. Jackel; Wayne E. Hubbard

1988-01-01

195

Power consumption estimation in CMOS VLSI chips  

Microsoft Academic Search

Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom

Dake Liu; Christer Svensson

1994-01-01

196

Scaling VLSI design debugging with interpolation  

Microsoft Academic Search

Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design debugging uses these error traces to identify potentially erroneous modules causing the error. With the increasing size and complexity of modern VLSI designs, error traces have become longer and harder to analyze. At the same time,

Brian Keng; Andreas G. Veneris

2009-01-01

197

An aVLSI Cricket Ear Model  

Microsoft Academic Search

Female crickets can locate males by phonotaxis to the mating song they produce. The behaviour and underlying physiology has been studied in some depth showing that the cricket auditory system solves this complex problem in a unique manner. We present an analogue very large scale integrated (aVLSI) circuit model of this process and show that results from testing the circuit

André Van Schaik; Richard Reeve; Craig T. Jin; Tara Julia Hamilton

2005-01-01

198

SSI/MSI/LSI/VLSI/ULSI.  

ERIC Educational Resources Information Center

|Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

Alexander, George

1984-01-01

199

Wafer sampling by regression for systematic wafer variation detection  

NASA Astrophysics Data System (ADS)

In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an expensive and slow process. The number of sites measured on a wafer must be minimized while still providing sufficient data to monitor the process. We address two key challenges to effective wafer-level monitoring. The first challenge is to select a small sample of inspection sites that maximize detection sensitivity to the patterns of interest, while minimizing the confounding effects of other types of wafer variation. The second challenge is to develop a detection algorithm that maximizes sensitivity to the patterns of interest without exceeding a user-specified false positive rate. We propose new sampling and detection methods. Both methods are based on a linear regression model with distinct and orthogonal components. The model is flexible enough to include many types of systematic spatial variation across the wafer. Because the components are orthogonal, the degree of each type of variation can be estimated and detected independently with very few samples. A formal hypothesis test can then be used to determine whether specific patterns are present. This approach enables one to determine the sensitivity of a sample plan to patterns of interest and the minimum number of measurements necessary to adequately monitor the process.

Moon, Byungsool; McNames, James; Whitefield, Bruce; Rudolph, Paul; Zola, Jeff

2005-05-01

200

Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature  

Microsoft Academic Search

Micromechanical smart sensor and actuator systems of high complexity bemme commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated to contain the readout circuits. The individually-processed wafers can be assembled using wafer-to-wafer bonding and can be combined to one single functional electro-mechanical unit using

K. D. Wise

1994-01-01

201

WaferOptics® mass volume production and reliability  

NASA Astrophysics Data System (ADS)

The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

Wolterink, E.; Demeyer, K.

2010-04-01

202

Exploration of the design space of wafer level packaging through numerical simulation  

Microsoft Academic Search

Wafer Level Packaging (WLP) refers to the technology that integrated circuits are packaged at wafer level and after singulation such chips are then connected directly to the PCB through individual solder balls using standard SMT process [1,2,3,4]. WLP enables true chip size packages with other advantages including lower profile, lighter weight, better thermal and electrical performance, and lower cost. Since

Zhongping Bao; James Burrell; Beth Keser; Praveen Yadav; Shantanu Kalchuri; Ricky Zang

2011-01-01

203

One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications  

Microsoft Academic Search

The ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate is becoming a critical issue for a variety of semiconductor applications. For CMOS devices this technology will be applied for chip-scale packaging and also for advanced 3-D interconnect processes. In the microelectromechanical systems (MEMS) arena, accurate alignment of

A. R. Mirza

2000-01-01

204

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

205

A 16-channel analog VLSI processor for bionic ears and speech-recognition front ends  

Microsoft Academic Search

We describe a 470 ?W 16-channel analog VLSI processor for bionic ears (cochlear implants) and portable speech-recognition front ends. The power consumption of the processor is kept at low levels through the use of subthreshold CMOS technology. Each channel is composed of a programmable bandpass filter, an envelope detector, and a logarithmic dual-slope analog-to-digital converter that currently operate over 51

Michael W. Baker; T. K.-T. Lu; C. D. Salthouse; J.-J. Sit; S. Zhak; R. Sarpeshkar

2003-01-01

206

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI  

Microsoft Academic Search

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (Vt) drops

Fariborz Assaderaghi; Dennis Sinitsky; Stephen A. Parke; Jeffrey Bokor; Ping K. Ko; Chenming Hu

1997-01-01

207

Study of hybrid orientation structure wafer  

NASA Astrophysics Data System (ADS)

Two types of 5 ?m thick hybrid orientation structure wafers, which were integrated by (110) or (100) orientation silicon wafers as the substrate, have been investigated for 15-40 V voltage ICs and MEMS sensor applications. They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique, and have been presented in China for the first time. The thickness of BOX SiO2 buried in wafer is 220 nm. It has been found that the quality of hybrid orientation structure with (100) wafer substrate is better than that with (110) wafer substrate by “Sirtl defect etching of HOSW".

Kaizhou, Tan; Jing, Zhang; Shiliu, Xu; Zhengfan, Zhang; Yonghui, Yang; Jun, Chen; Tao, Liang

2011-06-01

208

Replacing design rules in the VLSI design cycle  

NASA Astrophysics Data System (ADS)

We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

Hurley, Paul; Kryszczuk, Krzysztof

2012-03-01

209

VLSI implementation of moment invariants for automated inspection  

SciTech Connect

This paper describes the design of a VLSI ASIC for use in automated inspection. The inspection scheme uses Hu and Maitra's algorithms for moment invariants. A prototype design was generated that resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain. The prototype ASIC is currently being fabricated in 2.0-{mu}m CMOS technology and has been simulated at 20 MHz. The final ASICs will be used in parallel at the board level to achieve the 230 MOPs necessary to perform the moment invariant algorithms in real time on 512 {times} 512 pixel images with 256 grey scales. 10 refs., 2 figs.

Armstrong, G.A.; Simpson, M.L. (Oak Ridge National Lab., TN (USA)); Bouldin, D.W. (Tennessee Univ., Knoxville, TN (USA))

1990-01-01

210

Wafer Scale Distributed Radio.  

National Technical Information Service (NTIS)

Modem silicon technology offers ultrafast transistors, with fT > 200 GHz in today's 45nm CMOS and fT > 300 GHz in SiGe. While extremely fast, these transistors suffer from several limitations which affect the performance of high dynamic range analog and R...

A. M. Niknejad B. Nikolic E. Alon J. Rabaey

2009-01-01

211

Wafer-scale Mitochondrial Membrane Potential Assays  

PubMed Central

It has been reported that mitochondrial metabolic and biophysical parameters are associated with degenerative diseases and the aging process. To evaluate these biochemical parameters, current technology requires several hundred milligrams of isolated mitochondria for functional assays. Here, we demonstrate manufacturable wafer-scale mitochondrial functional assay lab-on-a-chip devices, which require mitochondrial protein quantities three orders of magnitude less than current assays, integrated onto 4” standard silicon wafer with new fabrication processes and materials. Membrane potential changes of isolated mitochondria from various well-established cell lines such as human HeLa cell line (Heb7A), human osteosarcoma cell line (143b) and mouse skeletal muscle tissue were investigated and compared. This second generation integrated lab-on-a-chip system developed here shows enhanced structural durability and reproducibility while increasing the sensitivity to changes in mitochondrial membrane potential by an order of magnitude as compared to first generation technologies. We envision this system to be a great candidate to substitute current mitochondrial assay systems.

Lim, Tae-Sun; Davila, Antonio; Zand, Katayoun; Douglas, Wallace C.; Burke, Peter J.

2012-01-01

212

90nm Games Processor Wafer to Module Power Yield Optimization  

Microsoft Academic Search

When fabricating a high volume games processor (CPU) for the consumer market, due to the cost of the module package, it is important to optimize the functional yield loss between the wafer die and the finished module package. For a performance CPU in a mature 90 nm technology the primary yield drivers can be power and performance. A functional power

Raymond Mallette; Brad Rawlins

2008-01-01

213

Thermomechanical Design of Resilient Contact Systems for Wafer Level Packaging  

Microsoft Academic Search

Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased

Rainer Dudek; Hans Walter; Ralf Doering; Bernd Michel; Thorsten Meyer; Joerg Zapf; Harry Hedler

2006-01-01

214

A VLSI implementation of CAVLC for H.264/AVC  

NASA Astrophysics Data System (ADS)

H.264 is the newest video coding standard and is currently one of the hot subjects of video processing technologies. Coding quality and compression ratio have been greatly improved in the new standard compared with the previous standards. The context-based adaptive technology is introduced into the new standard, which can be said to be a technology renovation of the video coding. The main entropy coding technologies of H.264 include VLC (Variable- Length Coding) and CABAC (Context-based Adaptive Binary Arithmetic Coding). CAVLC is VLC and adopts the context-based adaptive technology, therefore the coding efficiency is greatly improved. Currently, the design of the CAVLC encoder is mainly in software method, but with the development of real-time video processing technology, it is difficult for software to meet the demands. As a result, the hardware method in designing of CAVLC coder becomes a good choice. In the paper a CAVLC entropy encoder architecture based VLSI is proposed and implemented on an Altera FPGA device. As the results of simulation and synthesis, it can process 4×4 or 2×2 blocks per 16 clock periods with pipelined architecture and can achieve the real-time processing requirement of 30 frames per second for a 720×480 video at 100 MHz operation frequency.

Luo, Li; Li, Zheying; Yu, Qinmei

2009-10-01

215

Wafer Level Camera technology - from wafer level packaging to wafer level integration  

Microsoft Academic Search

Increasing demand from consumers to integrate camera modules into electronic devices, such as cell phones, has driven the cost of camera modules down very rapidly. Now that most cell phones include at least one camera, consumers are starting to ask for better image quality and resolution - without compromising on the cost. Many applications including mobile electronics, automotive, medical, security

Hongtao Han; Moshe Kriman; Mark Boomgarden

2010-01-01

216

The impact of VLSI on microprogramming  

Microsoft Academic Search

There are four “cultures” of microprogramming: the Bit-Slice Culture, the Commercial Processor Culture, the Microprogrammable Processor Culture, and the Single-Chip Culture. The effect of trends in VLSI (Very Large Scale Integration) on microprogramming can be assessed by looking the effect on each culture. The Bit-Slice Culture will be affected because levels of integration in bipolar have reached 32-bit slices and

N. Tredennick

1986-01-01

217

VLSI and the revolution in numeric computation  

SciTech Connect

Revolutionary changes are occurring in numeric computation. A standard for floating point arithmetic has been proposed that both promotes portable software and supports important extensions like interval arithmetic. The momentum for this standard has resulted primarily from its VLSI implementation in the Intel 8087 and the Intel 432. Addition impetus has been given to the revolution by the stated intention of other semiconductor manufacturers to also support the standard. 12 references.

Palmer, J.F.

1982-01-01

218

High Performance VLSI Model Elliptic Solvers  

Microsoft Academic Search

VLSI parallel algorithms for a solution of fundamental elliptic problems with Laplace operators (Dirichlet and first boundary\\u000a value problem for Poisson and biharmonic equation respectively) on a rectangular NN grid are proposed. A standard multigrid algorithm is adopted for Poisson equation which allows a parallel solution of this\\u000a problem in T=O(logN) parallel steps. A special network consisting of NN processor

Marián Vajtersic

1995-01-01

219

Aluminium Gettering in Silicon Wafers  

NASA Astrophysics Data System (ADS)

The effect of an evaporated thick aluminium paper on electrical properties of multicrystalline and gold contaminated FZ monocrystalline silicon wafers was investigated. By means of minority carrier diffusion length measurements and Deep Level Transient Spectroscopy, it was deduced that the material improvements observed after annealing at 900°C are due to gettering of metallic impurities in the Al-Si alloyed layer.

Martinuzzi, S.; Porre, O.; Périchaud, I.; Pasquinelli, M.

1995-09-01

220

Characterization of silicon-on-insulator wafers  

NASA Astrophysics Data System (ADS)

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Park, Ki Hoon

221

Non-contacting electrostatic voltmeter for wafer potential monitoring  

NASA Astrophysics Data System (ADS)

As part of the continuing reduction of half-pitch line widths, the International Technology Roadmap for Semiconductors (ITRS) forecasts an increasing number of issues with electrostatic discharge (ESD) related phenomena and the need for improved electrostatic charge control in semiconductor wafer processing. This means that wafer metrology should encompass charge measurements as a routine operation. Additionally, with the increasing complexity of wafer processing, in-line measurements including surface voltage and charge detection and analysis are becoming more important. One of the instruments utilized in such measurements is a non-contacting electrostatic voltmeter (ESVM). In this paper the authors would like to introduce a new design for the ESVM probe which allows for the measurement of surface voltages with DC stability and millivolt sensitivity. The construction of the probe utilizes a gold plated sensor that is mounted on a vibrating tuning fork which is electromechanically excited by a piezoelectric driver.

Noras, Maciej A.; Maryniak, William A.

2007-03-01

222

MAPPER alignment sensor evaluation on process wafers  

NASA Astrophysics Data System (ADS)

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3? std) of alignment mark readings can be achieved while being robust against various process steps.

Vergeer, N.; Lattard, L.; de Boer, G.; Couweleers, F.; Dave, D.; Pradelles, J.; Bustos, J.

2013-03-01

223

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

224

High-Throughput RFIC Wafer Testing  

Microsoft Academic Search

This paper surveys the state of RFIC wafer testing as performed on production floors today, and the trends and expectations for the future. Currently, most RF chips sold as known-good die (KGD) and relatively complex RFICs are tested at-speed at the wafer level. RF wafer testing is used to reduce the cost of scrap at the next level of packaging,

Eric W. Strid

2001-01-01

225

A VLSI BAM neural network chip for pattern recognition applications  

Microsoft Academic Search

Bi-directional associative memory (BAM) is a two-level nonlinear neural network suitable for pattern recognition applications. One important performance attribute of the discrete BAM is its ability to recall stored pattern pairs, particularly in the presence of noise. In this paper the VLSI implementation of BAM is presented. A modular VLSI processor chip implementing BAM was designed. By using 2 micron

S. M. R. Hasan; Ng Kang Siong

1995-01-01

226

Mask qualification strategies in a wafer fab  

NASA Astrophysics Data System (ADS)

Having consistent high quality photo masks is one of the key factors in lithography in the wafer fab. Combined with stable exposure- and resist processes, it ensures yield increases in production and fast learning cycles for technology development and design evaluation. Preventive controlling of incoming masks and quality monitoring while using the mask in production is essential for the fab to avoid yield loss or technical problems caused by mask issues, which eventually result in delivery problems to the customer. In this paper an overview of the procedures used for mask qualification and production release, for both logic and DRAM, at Infineon Dresden is presented. Incoming qualification procedures, such as specification checks, incoming inspection, and inline litho process window evaluation, are described here. Pinching and electrical tests, including compatibility tests for mask copies for high volume products on optimized litho processes, are also explained. To avoid mask degradation over lifetime, re-inspection checks are done for re-qualification while using the mask in production. The necessity of mask incoming inspection and re-qualification, due to the repeater printing from either the processing defects of the original mask or degrading defects of being used in the fab (i.e. haze, ESD, and moving particles, etc.), is demonstrated. The need and impact of tight mask specifications, such as CD uniformity signatures and corresponding electrical results, are shown with examples of mask-wafer CD correlation.

Jaehnert, Carmen; Kunowski, Angela

2007-05-01

227

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Astrophysics Data System (ADS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-02-01

228

Manufacture and Metrology of 300 mm Silicon Wafers with Ultra-Low Thickness Variation  

NASA Astrophysics Data System (ADS)

With the evolution of exposure tools for optical lithography towards larger numerical apertures, the semiconductor industry expects continued demand for improved wafer flatness at the exposure site. The allowable site flatness for 300 mm wafers is expected to be less than 45 nm by 2010 and it may be as low as 25 nm by 2015 according to the International Technology Roadmap for Semiconductors (ITRS 2006). This requires wafers with low thickness variation and presents a challenge for both wafer polishing and metrology tools, which must be capable of meeting the specifications. We report the results of fabricating 300 mm silicon wafers with very low thickness variation using magnetorheological finishing (MRF), a deterministic subaperture finishing process. The wafer thickness metrology, which guided the finishing process, was provided by an infrared interferometer developed at the National Institute of Standards and Technology (NIST). The finishing method in combination with the interferometric wafer metrology enabled the fabrication of 300 mm silicon wafers with a total thickness variation (TTV) of about 40 nm, and between 10 nm and 15 nm thickness variation at 25 mm×25 mm exposure sites.

Griesmann, Ulf; Wang, Quandou; Tricard, Marc; Dumas, Paul; Hall, Christopher

2007-09-01

229

MEMS Wafer-Level Packaging with Conductive Vias and Wafer Bonding  

Microsoft Academic Search

Micromachined accelerometers were packaged at wafer-level using both via-last and via-first approaches. In the via-last approach, a through-hole etched cap wafer was bonded to a micromachined device wafer using glass frit. Interconnections from the bond pads on the device wafer to the top of the cap wafer were made through the holes using sputter-deposition of metals. The bonded pair was

C. H. Yun; J. R. Martin; T. Chen; D. Davis

2007-01-01

230

Wafer bonding of 75 mm diameter GaP to AlGaInP-GaP light-emitting diode wafers  

Microsoft Academic Search

The AlGaInP\\/GaP wafer-bonded transparent-substrate (TS) light-emitting diodes (LEDs) have been shown to exhibit luminous efficiencies\\u000a exceeding many conventional lightning sources including 60 W incandescent sources. This paper will demonstrate the feasibility\\u000a of scaling wafer bonding technology to 75 mm diameter wafers and some of the unique challenges associated with this scaling.\\u000a The quality and uniformity of bonding were characterized via

I.-H. Tan; D. A. Vanderwater; J.-W. Huang; G. E. Hofler; F. A. Kish; E. I. Chen; T. D. Ostentowski

2000-01-01

231

The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics  

Microsoft Academic Search

Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect

W. Stephen Lacy; José L. Cruz-Rivera; D. Scott Wills

1998-01-01

232

New fabrication method of glass packages with inclined optical windows for micromirrors on wafer level  

NASA Astrophysics Data System (ADS)

For many applications it is inevitable to protect MEMS devices against environmental impacts like humidity which can affect their performance. Moreover recent publications demonstrates that micro mirrors can achieve very large optical scan angles at moderate driving voltages even exceeding 100 degrees when hermetically sealed under vacuum. While discrete chips may be evacuated and sealed on single die level using small can packages like TO housings, it is obvious that for high volume production a much more economical solution for the realisation of transparent optical packages already on wafer level must be developed. However, since any laser beam crossing a transparent glass surface is partly reflected even when anti-reflective coatings are applied, the construction of a wafer level optical housing suitable for laser projection purpose requires more than the integration of simple plane glass cap. The use of inclined optical windows avoids the occurrence of intense reflections of the incident laser beam in the projected images. This paper describes a unique technology to fabricate glass packages with inclined optical windows for micro mirrors on 8 inch wafers. The new process uses a high temperature glass forming process based on subsequent wafer bonding. A borosilicate glass wafer is bonded together with two structured silicon wafers. By grinding both sides of the wafer stack, a pattern of isolated silicon structures is defined. This preprocessed glass wafer is bonded thereon on a third structured silicon wafer, wherein the silicon islands are inserted into the cavities. By setting a defined pressure level inside the cavities during the final wafer bonding, the silicon glass stack extruded and it is out of plane during a subsequent annealing process at temperatures above the softening point of the glass. Finally the silicon is selectively removed in a wet etching process. This technique allows the fabrication of 8 inch glass wafers with oblique optical surfaces with surface roughness <1 nm and an evenness of < 300 nm.

Stenchly, Vanessa; Quenzer, Hans-Joachim; Hofmann, Ulrich; Janes, Joachim; Jensen, Björn; Benecke, Wolfgang

2013-03-01

233

Board level solder joint reliability modeling of Embedded Wafer Level BGA (eWLB) packages under temperature cycling test conditions  

Microsoft Academic Search

Embedded Wafer-Level Ball Grid Array (eWLB) technology was developed to provide a wafer-level packaging solution for semiconductor devices requiring a higher integration level and a greater number of external contacts. Essentially, eWLB is a fan-out wafer-level packaging in which silicon die is embedded in the mold compound and the redistributed layer can be carried out over both silicon die and

Seng Guan Chow; Won Kyoung Choi; Roger Emigh; Eric Ouyang

2011-01-01

234

Sea of Leads (SoL) ultrahigh density wafer-level chip input\\/output interconnections for gigascale integration (GSI)  

Microsoft Academic Search

Sea of Leads (SoL) is an ultrahigh density (>104\\/cm2) compliant chip input\\/output (I\\/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I\\/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of

Muhannad S. Bakir; Hollie A. Reed; Hiren D. Thacker; Chirag S. Patel; Paul A. Kohl; Kevin P. Martin; James D. Meindl

2003-01-01

235

Development of a Lapping Film Utilizing Agglomerative Superfine Silica Abrasives for Edge Finishing of a Silicon Wafer  

Microsoft Academic Search

In the present manufacturing process of a silicon wafer, wafer edge finishing with loose abrasives is essential for preventing\\u000a wafer breakage and particle contamination due to micro cracks. Loose-abrasive machining, however, has problems involving inefficiency\\u000a and an unclean working environment. Therefore, fixed-abrasive machining such as film lapping has received attention as an\\u000a alternative technology, but conventional lapping films have problems

Toshiyuki Enomoto; Yasuhiro Tani; Kazuya Orii

236

An artificial intelligence approach to VLSI routing  

SciTech Connect

An Artificial Intelligence Approach to VLSI Routing presents a system that performs routing close to what human designers do. As is carefully outlined in the book, the proposed system heavily capitalizes on the knowledge of human expertise in this area. Included in this test is background of some representative techniques for routing, and a summary of their characteristics. A detailed study is also included of the different factors that affect the routing quality and the criteria that can e used to optimize these factors.

Joobbani, R.

1985-01-01

237

VLSI binary multiplier using residue number systems  

SciTech Connect

The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.

Barsi, F.; Di Cola, A.

1982-01-01

238

Optimal VLSI dictionary machines without compress instructions  

SciTech Connect

The authors present several designs for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The authors' initial design objectives included: single-cycle operability of host-issued modify and query commands (no compress instructions), complete processor utilization (no wasted processors), and optimal 2 log {ital n} response times, where {ital n} is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously.

Li, H.F.; Probst, D.K. (Dept. of Computer Science, Concordia Univ., Montreal (CA))

1990-05-01

239

Development of a monolithic, multi-MEMS microsystem on a chip demonstrating iMEMS{trademark} VLSI technology. R and D status report number 10, January 1--March 31, 1996  

SciTech Connect

This quarter saw the first silicon from the iMEMS{reg_sign} test chip, with complete circuits and beam structures. The wafers looked fine cosmetically and the circuits functioned as designed, but the beams suffered an anomaly that the authors have never seen before. Diagnostic work is under way to sort out the root cause, and other wafers are coming out this quarter to see if it was a one-time anomaly. Work on the process-development front has slowed because of the construction of a dedicated fabrication line for the last-generation process. With the current robust market place for ADI`s business, the existing fabrication line has been operating at 100% capacity. On the device front, great progress has been made by both Berkeley and ADI in the area of gyroscopes. Measurements of close to a degree per second or better have been made for gyros of all three axes and of both single- (linear) and double- (rotary) axis devices. In addition, ADI has designed a gyro that can be packaged in air that very well might meet some of the low-precision needs. Accelerometers of several new formats have been designed and several have been implemented in silicon. First samples of the ADXL 181 designed especially for the fuzing, safe and arming application have been assembled and are in characterization by ADI and others. In addition, 2-axis, Z-axis and digital output designs have been demonstrated. A 3-axis micro-watt accelerometer has been designed and is in fabrication. A 2-axis design for tilt applications is also nearing silicon realization. This portfolio of linear accelerometers, and even angular versions of the same provide, an arsenal of capability for specialized needs as they arise in both commercial and military applications.

NONE

1996-04-17

240

Algorithms for VLSI routing. [Very Large Scale Integration, semiconductor chip design  

SciTech Connect

This thesis considers the problems arising from VLSI routing design. Algorithms are proposed for solving both global and local routing problems. For routing multiterminal nets in the gate array and sea-of-gates technologies, the author presents a global router which upper bounds the global density of the routing by 2s*, where s* is the span of the nets. For standard cell technology, he presents a global router which achieves the optimal horizontal density while upper bounding the vertical density by 2s*. The parallel implementations of the proposed global routing algorithms are presented.

Zhou, Dian.

1990-01-01

241

Low temperature, high strength, wafer-to-wafer bonding  

SciTech Connect

This paper reports on high strength bonds which can be formed between portions of silicon wafer coated with reflowed BPSG at temperatures as low as 160[degrees]C. Both a novel modified cantilever beam analysis, and crude physical methods attest to the strength of the bonds formed. Strong bonds between thermal oxides also have been observed, indicating that neither boron nor phosphorous are essential to the process. Preparation cleanliness may be the key to low temperature, high strength bonding,. Recent work in the glass sol-gel area supports the hypothesis that this process is the result of a low temperature condensation reaction.reaction.

Fleming, J.G.; Roherty-Osmun, E.; Godshall, N.A. (Sandia National Labs., Albuquerque, NM (United States))

1992-11-01

242

Wafer bonding for three dimensional (3D) integration  

NASA Astrophysics Data System (ADS)

Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 · Gtip · t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400°C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400°C. Thermal cycling performed at a temperature 450°C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

Kwon, Yongchai

2003-10-01

243

Wafer CD variation for random units of track and polarization  

NASA Astrophysics Data System (ADS)

After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

2012-03-01

244

Accurate surface profilometry of ultrathin wafers  

NASA Astrophysics Data System (ADS)

Geometric characterization of 50 mm diameter, 50 µm thick single-crystal Si(1 1 1) wafers has been performed using complementary methods: industry-standard capacitance measurements of warp and total thickness variation (TTV), and a technique we term scanned chromatic confocal profilometry (SCCP). We compare the measurements made by the two techniques and demonstrate the limitations of capacitance measurements when applied to ultrathin wafers. The two-dimensional SCCP measurements are shown to enhance the description of wafer thickness variations beyond that generated by the standard test method. We discuss a Fourier transform-based analysis and show it to be useful in wafer quality assessment. Adding a summary of spatial frequencies in a wafer's thickness map to the conventional measures of warp and TTV provides a more complete summary of the salient features of a wafer's geometry.

Weeks, A. E.; Litwin, D.; Galas, J.; Surma, B.; Piatkowski, B.; MacLaren, D. A.; Allison, W.

2007-09-01

245

Fundamental aspects of particulate contamination of tungsten and thermal oxide wafers during chemical-mechanical polishing  

Microsoft Academic Search

Chemical-mechanical polishing (CMP) has emerged as a new processing technique for achieving a high degree of planarity (<10 mum) for submicron devices in very large scale integrated (VLSI) process technology. Metal as well dielectic films can be planarized using CMP. Polishing of tungsten (W) and interlayer dielectric (SiOsb2) films is carried out using alumina (Alsb2Osb3) based slurries which typically contain

Raghunath R. Chilkunda

1997-01-01

246

PROGRESS IN COPPER-BASED WAFER BONDING  

Microsoft Academic Search

This article discusses a method of wafer-to-wafer bonding using metallic copper as the bonding medium. This method is commonly known as thermo-compression bonding. Bonding process is described and characterization results are presented. Reliability issues related to voids formation in the bonded layer is discussed. A survey on progress of copper-based wafer bonding and its application for 3-D ICs is included.

Chuan Seng Tan

247

Macroporous-based micromachining on full wafers  

Microsoft Academic Search

This paper reports on a technique of macroporous-based micromachining for full wafers. A 3.6kW xenon lamp of whose intensity can be varied is employed to generate electronic holes during the etching. In order to apply a uniform electric field to whole 3in. wafer, a mesh electrode is formed on the backside of the wafer after implantation of an n+ layer.

H. Ohji; S. Izuo; P. J. French; K. Tsutsumi

2001-01-01

248

Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010  

SciTech Connect

1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

Lorenz, A.

2011-06-01

249

Across-wafer CD uniformity control through lithography and etch process: experimental verification  

NASA Astrophysics Data System (ADS)

Process variation on lot-to-lot and wafer-to-wafer level has been well addressed using R2R control in advanced process control, however, to tackle the ever increasing die-to-die (i.e. across-wafer) level process variation at the 65nm technology node and beyond, the process control must be extended into finer domain: across-wafer level. A novel model based process control approach [2] was proposed to reduce the critical dimension (CD) variation on across-wafer level. The central idea of the proposed approach is to compensate for upstream and downstream systematic CD variation by adjusting the across-wafer Post-Exposure Bake (PEB) temperature profile of a multi-zone bake plate. A temperature-to-offset model relating the PEB temperature profile of multi-zone bake plate to its heater zone offsets was constructed experimentally using wireless temperature sensors from OnWafer Technologies. The baseline post-etch CD signature and plasma etch bias signature were extracted to characterize the lithography and etch processes. And a post-etch CD variation reduction of 40% was realized in the verification experiment, which validated the efficacy of the proposed approach.

Zhang, Qiaolin; Tang, Cherry; Cain, Jason; Hui, Angela; Hsieh, Tony; Maccrae, Nick; Singh, Bhanwar; Poolla, Kameshwar; Spanos, Costas J.

2007-03-01

250

Si Wafer Bonding with Ta Silicide Formation  

NASA Astrophysics Data System (ADS)

Bonded SOI wafers with a Ta silicide layer are fabricated. The 0.08-?m-thick Ta film sputtered on an oxidized Si wafer is bonded to another Si wafer with a native oxide. When the wafers are uniformly bonded by pulse-field-assisted bonding, Ta silicide forms at the interface. The buried Ta silicide layer is 0.12 ?m thick and the sheet resistance is 9 ?/\\Box. From a SIMS analysis, Ta decreases rapidly in Si. This proves that a pure SOI layer for devices can be obtained.

Fukuroda, Atsushi; Sugii, Toshihiro; Arimoto, Yoshihiro; Ito, Takashi

1991-10-01

251

The Transition to Optical Wafer Flatness Metrology  

NASA Astrophysics Data System (ADS)

As optical lithography requirements drive wafer flatness toward increasing levels of perfection, the industry is faced with a need to transition from current standard practice. In this paper we present a historical perspective on starting material dimensional metrology, leading to the current standard for wafer manufacturing quality control, capacitance-based wafer flatness metrology. We then investigate the market and technical factors that compel a transition to optical flatness metrology. Comparative data (from advanced 300mm wafers) between capacitive and optical flatness measurement tools permits us to conclude that the industry transition to optical dimensional metrology can occur without disruption of accepted manufacturing baselines.

Valley, John F.; Poduje, Noel

2003-09-01

252

RF–MEMS wafer-level packaging using through-wafer interconnect  

Microsoft Academic Search

In this paper, development of a wafer-level packaging (WLP) process suitable for RF–MEMS applications is presented. The packaging concept is based on a high-resistivity silicon capping substrate that is wafer-level bonded to an RF–MEMS device wafer providing MEMS device protection and vertical electrical signal interconnect. The capping substrate contains Cu-plated through-wafer electrical vias and optional through-substrate cavities allowing for hybrid

J. Tian; S. Sosin; J. Iannacci; R. Gaddi; M. Bartek

2008-01-01

253

Stress Voiding During Wafer Processing  

SciTech Connect

Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

Yost, F.G.

1999-03-01

254

Techniques for the evaluation of outgassing from polymeric wafer pods  

Microsoft Academic Search

In recent years there has been increasing interest in using wafer-level isolation environments or pods (microenvironments) to provide a more controllable, cleaner wafer environment during wafer processing. It has been shown that pods can be effective in reducing the amount of particulate contamination on wafers during manufacturing. However, there have also been studies that indicate that pods and wafer boxes

D. C. McIntyre; A. Liang; S. M. Thornberg; S. F. Bender; R. D. Lujan; R. S. Blewer; W. D. Bowers

1994-01-01

255

Notation for Describing Multiple Views of VLSI Circuits.  

National Technical Information Service (NTIS)

A declarative hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the nation in a way that emphasizes common elements. ...

J. L. Baer L. McMurchie L. Snyder M. C. Liem R. Nottrott

1988-01-01

256

32-Bit CMOS VLSI Image Processor, T9506.  

National Technical Information Service (NTIS)

High precision, high performance, and flexibility are vital in gray scale image processing applications, such as remote sensing and medical diagnosis. A VLSI image processor, T9506, has been developed to meet these requirements at low cost. This image pro...

A. Kanuma M. Noda K. Suzuki

1987-01-01

257

Overall Wafer Effectiveness (OWE): A Novel Industry Standard for Wafer Productivity  

Microsoft Academic Search

Overall equipment efficiency (OEE) is an index that is widely used to measure equipment performance for semiconductor manufacturing. However, little research has been done to address productivity from the perspective of wafer exposure performance. This study aims to propose a novel standard, overall wafer effectiveness (OWE), to evaluate the effectiveness of wafer exposure rather than only considering tool productivity. Furthermore,

Chen-Fu Chien; Chia-Yu Hsu; Hong-Shing Chou; Chih-Wei Lin

2006-01-01

258

Single wafer process to generate reliable swing  

NASA Astrophysics Data System (ADS)

Swing curve generation is an important and common exercise in the design, characterization, and optimization of photolithography processes. The development of a robust anti-reflective strategy for a given process often necessitates multiple experimental iterations of the swing curve generation. The traditional methodology for generating a photoresist thickness swing curve plot is time and silicon intensive; usually involving processing and metrology on a dozen or more wafers. In addition, the resulting curve often can convolve systematic and random wafer-wafer effects due to other track/resist/scanner related variables. In some cases, such as very low reflectivity underlying substrate the signal to noise ratio is poor enough to effectively mask the sinusoidal swing behavior from visibility. In this paper, we present a new methodology to generate a swing curve by using a single wafer. The critical point of this method is to generate a temperature gradient on the wafer during the initial step of photoresist dispense and coating. Since the resist viscosity is inversely proportional to the temperature, a significant resist thickness variation can be produced across the wafer, which can easily encompass one swing period of thickness or more. The resulting resist thickness signature across the wafer is seen to be very repeatable, such that a companion wafer can be measured at multiple positions corresponding to CD metrology lcoations on the patterned wafer. The possibility of deconvolving systematic across wafer CD variability due to other process variables is discussed by characterizing a control wafer with conventional uniform resist thickness. Our experiments for I-line and DUV resists indicated that this method not only provides reliable swing curves but also saves photoresist, silicon, and time both for engineering and machine. Moreover, this methodology represents an improved signal to noise ratio such that makes it particularly useful for ARC thickness/composition optimization. Several examples utilizing this method will be presented.

Gu, Yiming; Zhu, Cynthia; Sturtevant, John L.

2003-05-01

259

Focal-Plane and Multiple Chip VLSI Approaches to CNNs  

Microsoft Academic Search

In this paper, three alternative VLSI analog implementations of CNNs are described, which have been devised to perform image processing and vision tasks: a programmable low-power CNN with embedded photo-sensors, a compact fixed-template CNN based on unipolar current-mode signals, and basic CMOS circuits to implement an extended CNN model using spikes. The first two VLSI approaches are intended for focal-plane

M. Anguita; F. J. Pelayo; E. Ros; D. Palomar; A. Prieto

1998-01-01

260

Mask extraction from optical images of VLSI circuits  

NASA Astrophysics Data System (ADS)

This paper explores line labeling algorithms for extracting the mask layers from an optical image of a VLSI chip. Next, representation schemes for object features are introduced, together with the natural constraints these features satisfy. This label set is an extension of Huffman, Clowes, and Kanade's label sets. Finally, it is shown how to interpret VLSI scenes by using a constrained labeling strategy. Performance of the labeling algorithms is demonstrated on some simple but representative simulated images of CMOS logic gates.

Jeong, Hong; Musicus, Bruce R.

261

Information transfer and area-time tradeoffs for VLSI multiplication  

Microsoft Academic Search

The need to transfer information between processing elements can be a major factor in determining the performance of a VLSI circuit. We show that communication considerations alone dictate that any VLSI design for computing the 2n-bit product of two n-bit integers must satisfy the constraint AT2 ? n2\\/64 where A is the area of the chip and T is the

Harold Abelson; Peter Andreae

1980-01-01

262

CDU improvement with wafer warpage control oven for high-volume manufacturing  

NASA Astrophysics Data System (ADS)

Immersion lithography has been developed for 45nm technology node generation during the last several years. Currently, IC manufacturers are moving to high volume production using immersion lithography. Due to the demand of IC manufactures, as the critical dimension (CD) target size is shrinking, there are more stringent requirements for CD control. Post Exposure Bake (PEB) process, which is the polymer de-protection process after exposure, is one of the important processes to control the CD in the 193nm immersion lithography cluster. Because of the importance of the PEB process for CD uniformity, accurate temperature control is a high priority. Tokyo Electron LTD (TEL) has been studying the temperature control of PEB plates. From our investigation, total thermal history during the PEB process is a key point for controlling intra wafer and inter wafer CD [1]. Further, production wafers are usually warped, which leads to a nonuniform thermal energy distribution during the PEB process. So, it is necessary to correct wafer warpage during the baking process in order to achieve accurate CD control on production wafers. TEL has developed a new PEB plate for 45nm technology node mass production, which is able to correct wafer warpage. The new PEB plate succeeded in controlling the wafer temperature on production wafers using its warpage control function. In this work, we evaluated CD process capability using the wafer warpage control PEB plate, which is mounted on a CLEAN TRACKTM LITHIUS ProTM-i (TEL) linked with the latest immersion exposure tool. The evaluation was performed together with an IC manufacturer on their 45nm production substrates in order to determine the true performance in production.

Tomita, T.; Weichert, H.; Hornig, S.; Trepte, S.; Shite, H.; Uemura, R.; Kitano, J.

2009-03-01

263

Platinum\\/palladium thin-film thermocouples for temperature measurements on silicon wafers  

Microsoft Academic Search

A platinum versus palladium thin-film thermocouple system has been established for measuring temperatures on silicon wafers in a rapid thermal processing (RTP) tool. The application includes a silicon wafer with an array of thin-film thermocouples welded to wire thermocouples, used to calibrate radiometric temperature measurements of the RTP tool. The thin-film thermocouples have advantages over present technology using wire thermocouples

Kenneth G. Kreider; Frank DiMeo

1998-01-01

264

Characterization of stacked die using die-to-wafer integration for high yield and throughput  

Microsoft Academic Search

We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-mum thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding steps. In

K. Sakuma; P. S. Andry; C. K. Tsang; K. Sueoka; Y. Oyama; C. Patel; B. Dang; S. L. Wright; B. C. Webb; E. Sprogis; R. Polastre; R. Horton; J. U. Knickerbocker

2008-01-01

265

Methanol steam reformer on a silicon wafer  

Microsoft Academic Search

A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Packed bed microchannel reactors were fabricated using silicon DRIE, followed by wafer bonding. The reactor bed was subsequently filled with catalyst particles. Thermal control is achieved through on-chip resistive heaters, whereby methanol steam reforming reactions were studied

Hyung Gyu Park; Jonathan A. Malen; W. Thomas Piggott; Jeffrey D. Morse; Ralph Greif; Costas P. Grigoropoulos; Mark A. Havstad; Ravi Upadhye

2006-01-01

266

Capacity planning for development wafer fab expansion  

Microsoft Academic Search

The simulation model described offers many different opportunities for increasing understanding of a development wafer fab. The results of simulation runs must be analyzed with an understanding of the effect of randomness on the model. Multiple random number runs might be required to confirm a model result. Simulation models can account for dynamic interactions between wafers, tools and operators. The

W. Chou; J. Everton

1996-01-01

267

Substrate bonding techniques for CMOS processed wafers  

NASA Astrophysics Data System (ADS)

Transferring a CMOS circuit to a foreign substrate can be accomplished by bonding a processed silicon wafer to the substrate and subsequently thinning the silicon wafer. This paper presents both anodic bonding and adhesive bonding and evaluates their potential for circuit transfer.

van der Groen, S.; Rosmeulen, M.; Baert, K.; Jansen, P.; Deferm, L.

1997-09-01

268

Frame vibration suppression for wafer transfer system  

Microsoft Academic Search

The rapid development of the Integrated Circuit (IC) manufacturing equipment industry requires greater efficiency for wafer transfer. However, the faster wafer transfer robot moves, the bigger the force applied on its support frame is, and also the bigger vibration aroused on the frame because of the low stiffness of the support frame. Meanwhile, some IC equipment are ultra-high sensitive to

Yanjie Liu; Mingyue Wu; Guobao Xu; Lining Sun

2011-01-01

269

A wafer scale dynamic thermal scene generator  

Microsoft Academic Search

As a prototype WSTA (wafer scale transducer array), a wafer scale dynamic thermal scene generator is being developed to generate a controllable infrared (IR) image for use in calibrating IR detector arrays. The basic array consists of two cell types, one being a thermal pixel containing a poly Si resistor sitting on a suspended oxide bridge. The second cell contains

G. H. Chapman; M. Parameswaran; M. J. Syrzycki

1992-01-01

270

Molecular dynamics simulations of silicon wafer bonding  

Microsoft Academic Search

Molecular dynamics simulations based on a modified Stillinger-Weber potential are used to investigate the elementary steps of bonding two Si(0 0 1) wafers. The energy dissipation and thus the dynamic bonding behaviour are controlled by the transfer rates for the kinetic energy. The applicability of the method is demonstrated by studying the interaction of perfect wafer surfaces (UHV conditions). First

D. Conrad; K. Scheerschmidt; U. Gösele

1995-01-01

271

Analog VLSI system for active drag reduction  

SciTech Connect

In today`s cost-conscious air transportation industry, fuel costs are a substantial economic concern. Drag reduction is an important way to reduce costs. Even a 5% reduction in drag translates into estimated savings of millions of dollars in fuel costs. Drawing inspiration from the structure of shark skin, the authors are building a system to reduce drag along a surface. Our analog VLSI system interfaces with microfabricated, constant-temperature shear stress sensors. It detects regions of high shear stress and outputs a control signal to activate a microactuator. We are in the process of verifying the actual drag reduction by controlling microactuators in wind tunnel experiments. We are encouraged that an approach similar to one that biology employs provides a very useful contribution to the problem of drag reduction. 9 refs., 21 figs.

Gupta, B.; Goodman, R.; Jiang, F.; Tai, Y.C. [California Inst. of Technology, Pasadena, CA (United States); Tung, S.; Ho, C.M. [Univ. of California, Los Angeles, CA (United States)

1996-10-01

272

Cryogenic wafer prober for Josephson devices  

SciTech Connect

A wafer probing system has been built for the testing of Josephson junction devices at helium temperature. A mechanism moves a probe card from one position to another on a two inch wafer while immersed in liquid helium. The mechanism is actuated by shafts which connect to stepper motors positioned above the helium dewar. A positioning accuracy of + or - 50 ..mu..m at the probe tips is achieved. The replaceable probe card is all ceramic and carries 120 rigidly mounted palladium-alloy needles, arranged in signal-ground pairs and positioned in an array which matches the pad design of the particular device under test. Controlled impedance transmission lines are maintained all the way to the wafer's surface. A computer interface is included so that probing of a whole wafer can be conducted under software control. The system is intended for routine testing of Josephson devices in wafer form as well as for testing very large numbers of individual junctions.

Geary, J.; Vella-Coleiro, G.

1983-05-01

273

A self-priming, high performance, check valve diaphragm micropump made from SOI wafers  

NASA Astrophysics Data System (ADS)

In this paper, we describe a self-priming high performance piezoelectrically actuated check valve diaphragm micropump. The micropump was fabricated from three wafers: two silicon-on-insulator (SOI) wafers and one silicon wafer. A process named 'SOI/SOI wafer bonding and etching back followed by a second wafer bonding' was developed in order to make the core components of this device which included an inlet check valve, an outlet check valve, a diaphragm and a chamber. The movable structures of this device, i.e. the check valves and the diaphragm, were fabricated from the device layers of the two bonded SOI wafers. Taking advantages of SOI wafer technology and etch-stop layers, the vertical parameters of the movable structures were precisely controlled in fabrication. The micropump was self-priming without any pre-filling process. The pumping rate of the micropump was linearly adjustable from 0 to 650l µm min-1 by adjusting frequency. The maximum pumping rate was 860 µl min-1 and the maximum pumping pressure was approximately 10.5 psi. The power consumption of the device was less than 1.2 mW.

Kang, Jianke; Mantese, Joseph V.; Auner, Gregory W.

2008-12-01

274

Time memory cell VLSI for the PHENIX drift chamber  

SciTech Connect

A high-precision Time-to-Digital-Converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and one level of trigger buffering required in very high rate experiments. In addition to a fixed data size readout, the chip also supports a zero-suppression mode readout. The chip records both rising and falling edge timings, and has a least timing count of 0.83 ns/bit and 1.66 ns/bit respectively. A level 1 buffer has a recording depth of 6.8 {micro}sec and a readout FIFO has a depth of 128 words. High precision timing was derived from an asymmetric ring oscillator stabilized with a PLL. The chip runs at 4 times faster clock (37.6 MHz) of the RHIC bunch clock, and was fabricated with 0.5 {micro}m CMOS gate-array technology.

Arai, Y.; Ikeno, M. [National High Energy Accelerator Research Organization, Tsukuba, Ibaraki (Japan). Inst. of Particle and Nuclear Studies; Sagara, M.; Emura, T. [Tokyo Univ. of Agriculture and Technology, Koganei, Tokyo (Japan)

1998-06-01

275

Automated routing method for VLSI with three interconnection layers  

SciTech Connect

Recently, to the extent allowed by the fabricating technology, approaches have been made to develop an automated router for the multi-layer IC layout design. This thesis examines the VLSI routing problem where three layers are available for interconnection. The author investigates the routing problem in three stages: global routing, power/ground routing, and channel routing. The global routing for the three-interconnection layer model is not much different from that of the two layer model. The global routing problem is studied for two cases: gate array and general cell layout. In the three-layer grid model, power/ground wires keep the direction-per-layer scheme as signal net wires. However, the power/ground routing is further constrained by the width of wires and the layers they are laid on. The major result presented in this dissertation is an algorithm for a channel routing problem. Given a rectangular channel with terminals on top and bottom sides, the algorithm will find a three-layer channel routing that minimizes the channel width and the wire length. Experimental results show that the router is close to optimal.

Lee, C.H.

1986-01-01

276

A VLSI architecture for high performance CABAC encoding  

NASA Astrophysics Data System (ADS)

One key technique for improving the coding e+/-ciency of H.264 video standard is the entropy coder, context- adaptive binary arithmetic coder (CABAC). However the complexity of the encoding process of CABAC is signicantly higher than the table driven entropy encoding schemes such as the Hu®man coding. CABAC is also bit serial and its multi-bit parallelization is extremely di+/-cult. For a high denition video encoder, multi-giga hertz RISC processors will be needed to implement the CABAC encoder. In this paper, we provide an e+/-cient, pipelined VLSI architecture for CABAC encoding along with an analysis of critical issues. The solution encodes a binary symbol every cycle. An FPGA implementation of the proposed scheme capable of 104 Mbps encoding rate and test results are presented. An ASIC synthesis and simulation for a 0.18 ¹m process technology indicates that the design is capable of encoding 190 million binary symbols per second using an area of 0.35 mm2. ¤

Shojania, Hassan; Sudharsanan, Subramania

2005-07-01

277

Fabrication of carbon nanotube emitters in an anodic aluminium oxide nanotemplate on a Si wafer by multi-step anodization  

NASA Astrophysics Data System (ADS)

AAO template technology was combined with silicon technology to be directly applied to electronic device fabrication. Thin film anodic aluminium oxide (AAO) templates were fabricated on a silicon wafer by multiple anodizations. No electropolishing was used after the deposition of the aluminium layer on Si wafers. The ordering of the pore arrangement was improved by repeated anodizations, and highly ordered AAO templates could be obtained on Si wafers. CNT field emitter arrays were made with the AAO templates on Si wafers. Field emission measurement revealed that the emission current density increased with the synthesis temperature of CNTs. The large field enhancement factor in the range of 2440-4000 indicates the potential of the CNT field emitter array based on the AAO template on a Si wafer.

Hwang, Sun-Kyu; Lee, Junghyun; Jeong, Soo-Hwan; Lee, Pyung-Soo; Lee, Kun-Hong

2005-06-01

278

Signal Processing Applications of Systolic Array Technology.  

National Technical Information Service (NTIS)

Architectures and algorithms are examined for exploiting the large number of degrees of freedom available in current VLSI and projected VHSIC integrated circuit technologies to provide real-time implementations for sonar signal processing tasks. Such real...

H. J. Whitehouse J. M. Speiser K. Bromley

1983-01-01

279

Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001  

SciTech Connect

The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.

Beetz, C.P.; Steinbeck, J.; Hsueh, K.L.

2001-03-31

280

Wafer scale integration of micro-optic and optoelectronic elements by polymer UV reaction molding  

NASA Astrophysics Data System (ADS)

A replication technique allowing for the wafer scale integration of microoptical elements is presented and illustrated by various examples. The technique is based on polymer UV reaction moulding using a modified contact mask aligned where mask and wafer are replaced by the replication tool and an arbitrary substrate, respectively. The technology takes advantage of the high precision and adjustment accuracy of photolithography equipment. The replication masters are nickel shims, etched Silicon wafers or uv-transparent fused silica tools. The latter ones allow for replication on opaque substrates. Additionally, polymer elements with unique properties can be obtained by the combination of replication and resist technology using partially transparent replication tools. Wafer scale hybrid integration of microoptical subsystems is accomplished by replication of polymer elements like lenses, lens arrays, micro prisms etc. onto semiconductor wafers containing detectors or VCSELs, or by combining microoptical elements on both sides of a glass wafer. The use of thin layers of uv cured polymers on inorganic substrates results in good thermal and mechanical stability compare to all-polymer devices.

Dannberg, Peter; Bierbaum, Ralf; Erdmann, Lars; Braeuer, Andreas H.

1999-04-01

281

Development of megasonic cleaning for silicon wafers  

NASA Astrophysics Data System (ADS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-09-01

282

Metal Enhanced Fluorescence on Silicon Wafer Substrates.  

PubMed

We report on the fluorescence enhancement induced by silver island film (SIF) deposited on a silicon wafer. The model immunoassay was studied on silvered and unsilvered wafers. The fluorescence brightness of Rhodamine Red X increased about 300% on the SIF, while the lifetime was reduced by several fold and the photostability increased substantially. We discuss potential uses of silicon wafer substrates in multiplex assays in which the fluorescence is enhanced due to the SIF, and the multiplexing is achieved by using micro transponders. PMID:19137060

Gryczynski, I; Matveeva, E G; Sarkar, P; Bharill, S; Borejdo, J; Mandecki, W; Akopova, I; Gryczynski, Z

2008-10-01

283

MUSE - a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer-scale integration. Technical report  

SciTech Connect

This report describes an architecture for a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which we call MUSE (Matrix Update Systolic Experiment), and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 decibel of signal-to-noise improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI (Very Large Scale Integration). The complete design of such a wafer is described.

Rader, C.M.; Allen, D.L.; gLASCO , D.B.; Woodward, C.E.

1990-05-18

284

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

Kim, Dae Jong; Yoo, Hyung Won; Kim, Chul Hong; Lee, Hak Kwon; Kim, Sung Su; Bae, Koon Ho; Spielberg, Hedvi; Lee, Yun Ho; Levi, Shimon; Bustan, Yariv; Rozentsvige, Moshe

2010-03-01

285

Mask CD uniformity metrology for logic patterning and its correlation to wafer data  

NASA Astrophysics Data System (ADS)

With the next technology nodes 193nm lithography is pushed to its utmost limits. The industry is forced to print at low k1 factor which goes along with a high MEEF. Additionally, new blank materials are being introduced for smaller nodes. From 4x node and beyond, global CD uniformity on wafer is getting more critical and becomes key factor to ensure a high yield in chip production. Advanced process control is required and correction strategies are applied to maintain tight wafer CD uniformity. Beside other parameters, like scanner and etch process, mask CD uniformity is one main contributor to the intra-field CD on wafer. To enable effective CDU correction strategies it is necessary to establish a mask CD uniformity metrology which shows a good correlation to wafer prints. Especially for logic pattern mask uniformity measurements to control intra-field CD uniformity becomes challenging. In this paper we will focus on mask CD uniformity measurement for logic application utilizing WLCD, which is based on aerial image technology. We will investigate 40nm node and 28nm node gate masks using 6% MoSi phase shifting mask and MoSi binary mask respectively. Furthermore, we will correlate the mask CD uniformity data to wafer data to evaluate the capability of WLCD to predict the intra-field wafer CD uniformity correctly in order to support feedforward correction strategies. We will show that WLCD shows an excellent correlation to wafer data. Additionally, we will provide an outlook on logic contact-hole masks showing first CD uniformity data and wafer correlation data.

Le Gratiet, Bertrand; Zékri, Raphaël.; Sundermann, Frank; Trautzsch, Thomas; Thaler, Thomas; Birkner, Robert; Buttgereit, Ute

2012-06-01

286

ELID supported grinding of thin sapphire wafers  

NASA Astrophysics Data System (ADS)

Sapphire material is, due to its crystal structure, difficult to machine in an economic way. There is a request for thin, i.e. below 0.2 mm thickness, sub surface damage free wafers to produce sensor elements. ELID -- electrolytic in process dressing -- is an innovative high end grinding technology, using small grain sizes, which enable to manufacture surfaces in a quality that is close to polished. ELID grinding requires exactly aligned machining parameters of the grinding process. To grind sapphire the material's behavior is additionally to be considered. Studies on the necessary oxide layer on the grinding wheel and influences on its build-up process will be presented. The presentation shows the results of comparing grinding experiments on different -- c-plane and r-plane -- sapphire materials. Different tool specifications are used. Infeed and grinding velocity are varied and the results on wear, removal rate and surface quality are shown. The process parameters the stiffness of the machine, the grinding forces and pressure are evaluated. The ELID grinding is compared in its results to conventional grinding steps. The material removal rate on sapphire is relatively small due to the extreme hardness of sapphire. The achieved excellent surface roughness will be discussed.

Makarenko, Igor; Vogt, Christian; Rascher, Rolf; Sperber, Peter; Stirner, Thomas

2010-05-01

287

VLSI architecture for computer vision based on neurobiological principles of organization  

SciTech Connect

Biological and technological (wide-field-of-view) vision systems are confronted with the formidable task of managing data sets at a rate in excess of 10/sup 0/10 bits per second. In both cases, however, considering the required tasks, it appears that the data are highly redundant, and therefore must be reorganized before any type of higher level processing is applied to them. Reorganizations may include compression, and dimensional reduction according to the various relevant parameters. Biological processing at both the retinal and cortical levels often consists of repetitive simple operations applied to spatial and/or temporal neighborhoods, limited in their extend and duration. These are most adequate for the very high image data rates, in spite of the fact that those neurobiological systems actually consists of simple components which are several orders of magnitude slower than electronic components. It is the authors' goal to follow biological algorithms and principles of organization in the design of VLSI architectures, and to achieve similar or better performance in image processing and machine vision. Their efforts have yielded the following families of VLSI devices and systems. A highly parallel Intelligent Scan Image Acquisition VLSI sensing device has been constructed. It selectively scans only the relevant areas of interest in each image, thus effectively providing a compressed image for later processing stages. The device is controlled by an algorithm which is highly sensitive to image content. This sensor imitates the capability of the eye to concentrate on (attend) certain parts of the image, and even extends this by processing multiple focal points simultaneously. This is an example of how we applied the nonuniform sample-and-process algorithm, characteristic of biological vision, in a highly parallel architecture which surpasses the performance of the human eye.

Ginosar, R.; Zeevi, Y.Y.

1988-09-01

288

Capacitor Technology.  

National Technical Information Service (NTIS)

The bibliography is a compilation of unclassified-unlimited references on Capacitor Technology. This report presents information on miniature and microelement capacitors formed by deposition of dielectric substance on a ribbon, sheet, or wafer, and discre...

1973-01-01

289

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

2012-11-29

290

Silicon wafer bonding through RF dielectric heating  

Microsoft Academic Search

This paper presents a new silicon wafer bonding process based on radio-frequency (RF) heating of an intermediate dielectric layer. The method uses a capacitive RF field to heat a dielectric interlayer up to its glass transition temperature and permanently join two wafers. A 500W 14MHz source was used to deliver RF power to the substrates. A 5cm diameter 300?m thick

Andrey Bayrashev; Babak Ziaie

2003-01-01

291

A bulk silicon dissolved wafer process for microelectromechanical devices  

Microsoft Academic Search

A single-sided bulk silicon dissolved wafer process that has been used to fabricate several different micromechanical structures is described. It involves the simultaneous processing of a glass wafer and a silicon wafer, which are eventually bonded together electrostatically. The silicon wafer is then dissolved to leave heavily boron doped devices attached to the glass substrate. Overhanging features can be fabricated

Yogesh B. Gianchandani; Khalil Najafi

1992-01-01

292

Full-wafer loss measurements of silicon ridge waveguides  

Microsoft Academic Search

We present full-wafer loss data for ridge waveguides for three different geometries fabricated on 150 mm silicon-on- insulator wafers. Full-wafer testing was made possible by a vertically coupled, automated test system. Keywords-silicon; integrated photonics; waveguide; full wafer; grating coupler

Michael Gould; Jing Li; Tom Baehr-Jones; Michael Hochberg

2011-01-01

293

Surface Impurities Encapsulated by Silicon Wafer Bonding  

NASA Astrophysics Data System (ADS)

Wafer bonding techniques are shown to provide an important addition to methods used for the detection of residual impurities on the surfaces of polished and cleaned silicon wafers. Impurities were encapsulated in the interface made by wafer bonding, and analyzed by SIMS depth profiling. Significant concentrations of H, C, N, O, F and Cl were detected. The concentration of these elements did not change after two hour wafer bonding anneals in the range of 200°C to 800°C. For anneals at 1000°C and above both the diffusion of H and C from the bonded interface, and the aggregation of N and O were observed. It was confirmed by IR absorption and HR-TEM that oxygen in CZ crystals outdiffuses into the bonded interface and produces an SiO2 layer. Low-oxygen FZ wafers were used as a reference comparison. Elements such as F and Cl contained in the chemicals used to clean the wafers remained fixed at the bonded interface for the entire temperature range tested.

Abe, Takao; Uchiyama, Atsuo; Yoshizawa, Katsuo; Nakazato, Yasuaki; Miyawaki, Mamoru; Ohmi, Tadahiro

1990-12-01

294

Incremental placement and routing of VLSI macrocells  

SciTech Connect

This dissertation proposes a strategy to automatically position and interconnect a set of rectangular VLSI macrocell blocks by using an integrated set of incremental algorithms. The set of tools is subdivided into three major modules - design manager, floor planner (ExPlan), and global router (MAP). Design manager is used as an interface between the database and the user to simplify the user's task of cell library management by a use of simple command language. ExPlan is used to generate a transformation matrix of given cell list and netlist by best first heuristic search mechanism. The resulting floorplan provides coordinate and orientation of each cell in the cell list with sufficient channel dimension between cells for all nets to be successfully connected and total net lengths minimized. Absolute placement and routing is performed by MAP to create a layout which minimizes overall area by incrementally compacting channels. Each rectangular channel is partitioned such that they can be routed in a predetermined sequence to eliminate the usage of a switchbox router. MAP has capability to route nets with multiple terminals as well as perform connections on standard cells. The final routed result is automatically checked against the netlist for verifying the connectivity of all nets.

Ozeki, T.

1989-01-01

295

Relationship between coefficient of friction and surface roughness of wafer in nanomachining process  

NASA Astrophysics Data System (ADS)

Fixed abrasive polishing technology can obtain a nanoscale surface and is one of the future nano machining directions. The coefficient of friction between the pad and the wafer in the polishing process can influence on the surface quality of the wafer. The relationship between the coefficient of friction and surface roughness of the wafer was investigated to improve the efficiency and surface quality. Based on the Florida model, the adhesion, asperity plough and abrasive plough from the pad in the polishing process was analyzed. The friction force per unit area was calculated by the properties of the pad and wafer. Based on the rod model, the actual contact area was calculated by the surface roughness and the properties of the pad and wafer. The relational model between the surface roughness of the wafer and the friction coefficient was established. The model was verified by the experiments of fixed abrasive polishing of BK7 glass. When the friction coefficient is less than 1.9, the data of the experiment and theory match very well in the comparison process.

Li, Jun; Xia, Lei; Li, Pengpeng; Zhu, Yongwei; Sun, Yuli; Zuo, Dunwen

2013-08-01

296

Applications of VLSI in electronic turbine engine controls  

NASA Astrophysics Data System (ADS)

In electronic controls for turbine engines, VLSI has several benefits to system designers in meeting size and weight constraints. Along with reviewing these advantages, this paper describes the selection process and criteria, the design process, and test of VLSI circuits for engine control applications using a standard cell library and a CAD development system similar to commercially available systems. The author emphasizes the development of standard, written procedures to ensure that designs proceed in a regular and predictable manner, from system partitioning and device selection to chip testing. Specific cases of problems encountered in chip design and the solutions found are also discussed.

Goodzey, Gregory P.

297

Mask and wafer cost of ownership (COO) from 65 to 22 nm half-pitch nodes  

NASA Astrophysics Data System (ADS)

Anticipating the cost of ownership (COO) of different lithography approaches into the future is an act of faith. It requires that one believe that all of the lithographic problems with next generation lithography (NGL) approaches will be sufficiently resolved to support the production of manufacturing wafers. This paper assumes that all of the necessary technologies will be available in the future and that the cost of the components can be extrapolated from historic cost trends. Mask and wafer costs of a single critical lithography layer for the 65, 45, 32 and 22 nm half-pitch (HP) nodes will be compared for immersion, double process (DP), double expose (DE), extreme ultraviolet (EUV), and imprint technologies. The mask COO analysis assumes that the basic yield of an optical mask is constant from node to node and that the infrastructure that allows this performance will be in place when the technologies are needed. The primary differences in mask costs among lithography approaches are driven by the patterning write time and materials. The wafer COO is driven by the mask cost (for the low wafer-per-mask use case), the lithography tool cost, and the effective wafers per hour (wph) for the lithography approach being considered.

Hughes, Greg; Litt, Lloyd C.; Wüest, Andrea; Palaiyanur, Shyam

2008-06-01

298

Materials integration for high-performance photovoltaics by wafer bonding  

NASA Astrophysics Data System (ADS)

The fundamental efficiency limit for state of the art triple-junction photovoltaic devices is being approached. By allowing integration of non-lattice-matched materials in monolithic structures, wafer bonding enables novel photovoltaic devices that have a greater number of subcells to improve the discretization of the solar spectrum, thus extending the efficiency limit of the devices. Additionally, wafer bonding enables the integration of non-lattice-matched materials with foreign substrates to confer desirable properties associated with the handle substrate on the solar cell structure, such as reduced mass, increased thermal conductivity, and improved mechanical toughness. This thesis outlines process development and characterization of wafer bonding integration technologies essential for transferring conventional triple-junction solar cell designs to potentially lower cost Ge/Si epitaxial templates. These epitaxial templates consist of a thin film of single-crystal Ge on a Si handle substrate. Additionally, a novel four-junction solar cell design consisting of non-lattice matched subcells of GaInP, GaAs, InGaAsP, and InGaAs based on InP/Si wafer-bonded epitaxial templates is proposed and InP/Si template fabrication and characterization is pursued. In this thesis the detailed-balance theory of the thermodynamic limiting performance of solar cell efficiency is applied to several device designs enabled by wafer bonding and layer exfoliation. The application of the detailed-balance theory to the novel four-junction cell described above shows that operating under 100 suns at 300 K a maximum efficiency of 54.9% is achievable with subcell bandgaps of 1.90, 1.42, 1.02, and 0.60 eV, a material combination achievable by integrating two wide-bandgap subcells lattice matched to GaAs and two narrow-bandgap subcells lattice matched to InP. Wafer bonding and layer transfer processes with sufficient quality to enable subsequent material characterization are demonstrated for both Ge/Si and InP/Si structures. The H-induced exfoliation process in each of these materials is studied using TEM, AFM, and FTIR to elucidate the chemical states of hydrogen leading to exfoliation. Additionally, the electrical properties of wafer-bonded interfaces between bulk-Ge/Si and bulk-InP/Si structures are show Ohmic, low-resistance electrical contact. Further studies of p-p isotype heterojunctions in Ge/Si indicate that significant conduction paths exist through defects at the bonded interface. The first known instance of epitaxy of III-V compound semiconductors on wafer-bonded Ge/Si epitaxial templates is demonstrated. Additionally InGaAs is grown on InP/Si templates that have been improved by removal of damage induced by the ion implantation and exfoliation processes.

Zahler, James Michael

299

Built-in self-repair of VLSI memories employing neural nets  

NASA Astrophysics Data System (ADS)

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

Mazumder, Pinaki

1998-10-01

300

Compact VLSI neural computer integrated with active pixel sensor for real-time ATR applications  

NASA Astrophysics Data System (ADS)

A compact VLSI neural computer integrated with an active pixel sensor has been under development to mimic what is inherent in biological vision systems. This electronic eye- brain computer is targeted for real-time machine vision applications which require both high-bandwidth communication and high-performance computing for data sensing, synergy of multiple types of sensory information, feature extraction, target detection, target recognition, and control functions. The neural computer is based on a composite structure which combines Annealing Cellular Neural Network (ACNN) and Hierarchical Self-Organization Neural Network (HSONN). The ACNN architecture is a programmable and scalable multi- dimensional array of annealing neurons which are locally connected with their local neurons. Meanwhile, the HSONN adopts a hierarchical structure with nonlinear basis functions. The ACNN+HSONN neural computer is effectively designed to perform programmable functions for machine vision processing in all levels with its embedded host processor. It provides a two order-of-magnitude increase in computation power over the state-of-the-art microcomputer and DSP microelectronics. A compact current-mode VLSI design feasibility of the ACNN+HSONN neural computer is demonstrated by a 3D 16X8X9-cube neural processor chip design in a 2-micrometers CMOS technology. Integration of this neural computer as one slice of a 4'X4' multichip module into the 3D MCM based avionics architecture for NASA's New Millennium Program is also described.

Fang, Wai C.; Udomkesmalee, Gabriel; Alkalai, Leon

1997-04-01

301

On VLSI Design of Rank-Order Filtering using DCRAM Architecture  

PubMed Central

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 ?m 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7?m2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

Lin, Meng-Chun; Dung, Lan-Rong

2009-01-01

302

On VLSI Design of Rank-Order Filtering using DCRAM Architecture.  

PubMed

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 ?m 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7?m(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply. PMID:19865599

Lin, Meng-Chun; Dung, Lan-Rong

2008-02-01

303

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

304

Measurement Sites for Wafer Map Visualization and Process Monitoring  

NASA Astrophysics Data System (ADS)

This paper proposes measurement site selection to visualize a wafer characterization map and also monitor wafer-to-wafer and batch-to-batch variation. In the manufacturing line of thin film devices such as large-scale integrated circuits, magnetic heads of hard disk drives and thin-film-transistor substrates of liquid-crystal projectors, several critical dimensions are generally measured and monitored for quality control. To monitor wafer-to-wafer and batch-to-batch variation, engineers control average and standard deviation of measured dimensions as statistical process control. To monitor characterization across a wafer, the engineers observe an sculptured surface as a wafer map. The paper presents a selection method to decide measurement sites across a wafer for both of the wafer map visualization and the process monitoring and examines their accuracies experimentally.

Ono, Makoto; Hayashi, Hirohito; Kondo, Akira; Hamaguchi, Daisuke; Kaneko, Shun'ichi

305

VLSI (Very Large Scale Integration) floating point chip design study  

Microsoft Academic Search

This report describes techniques for very large scale integration (VLSI) implementation of arithmetic algorithms. The report describes an algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and iterative algorithms for performing square root.

J. G. Nash

1985-01-01

306

Generalized Data Compression Techniques for Testable Design of VLSI.  

National Technical Information Service (NTIS)

An innovative data compression technique suitable for the Built-in-Test (BIT) of a generalized VLSI application was investigated. The technique used logic block partitioning and counting to achieve a high degree of fault coverage and resolution. An a-prio...

C. S. Venkatraman

1988-01-01

307

Highly secured high throughput VLSI architecture for AES algorithm  

Microsoft Academic Search

This paper provides an efficient VLSI architecture to increase the throughput and security of the Advanced Encryption Standard (AES) Algorithm. The existing architecture provide the Look up Table technique for the Subbytes and inverse Subbytes transformation used in AES algorithm, our proposed technique uses combinational circuit and pipelining technique which increase the throughput and reduce the delay. This design proposes

M. Vanitha; R. Sakthivel; Subha

2012-01-01

308

Using Texture Mapping With Mipmapping to Render a VLSI Layout.  

National Technical Information Service (NTIS)

This paper presents a method of using texture mapping with mip- mapping to render a VLSI layout. Texture mapping is used to save already rasterized areas of the layout from frame to frame, and to take advantage of any hardware accelerated capabilities of ...

J. Solomon M. Horowitz

2001-01-01

309

Low power intracardiac electrogram classification using analogue VLSI  

Microsoft Academic Search

A system has been developed for the classification of intracardiac electrograms (ICEG). The system is comprised of an analogue VLSI neural network, an implantable cardioverter defibrillator (ICD) and a PC based software training environment. Analogue implementation techniques were chosen to meet the strict power and area requirements of implantable systems. The robustness of the neural network architecture reduces the impact

Richard Coggins; Marwan Jabri; Barry Flower; Stephen Pickard

1994-01-01

310

and Simulation of VLSI Cellular Neural Network Chips  

Microsoft Academic Search

This paper presents SIRENA, a CAD environment for the simulation and modeling of mixed-signal VLSI parallel processing chips based on Cellular Neural Netw orks. SIRENA includes capabilities for: a) the description of nominal and non-ideal operation of CNN analog circuitry at the behavioral level; b) performing realistic simulations of the transient e volution of physical CNNs including deviations due to

R. Carmona; I. García-Vargas; G. Liñán; R. Domínguez-Castr; S. Espejo

311

SPIDER -- A CAD System for Modeling VLSI Metallization Patterns  

Microsoft Academic Search

A system of CAD programs, called SPIDER, for ensuring adequate current-carrying capacity in VLSI circuits has been developed. The approach is hierarchical, and it automates and simplifies many of the tasks previously performed by the circuit designer. The system converts transient current waveforms into dc electromigration equivalent values, and includes an algorithm for determining the line width adjustments necessary for

Joseph E. Hall; Dale E. Hocevar; Ping Yang; Michael J. Mcgraw

1987-01-01

312

Wirelength Based Clustering Technique for VLSI Physical Design  

Microsoft Academic Search

Physical design of Very Large Scale Integrated (VLSI) circuits is the phase where the physical shape of a circuit is decided. Layout is part of the physical design step where the locations of all circuit components and their wiring are decided. Layout typically consists of 3 stages: partitioning, placement, and routing. The main focus of this research is on the

Jie Huang; Jianhua Li; Logan Rakai; Laleh Behjat

2007-01-01

313

Channel\\/switchbox definition for VLSI building-block layout  

Microsoft Academic Search

A study is made of the problem of routing region definition and ordering in VLSI building-block layout design. An algorithm to decompose the routing area into straight channels and rectangular switchboxes corresponding to line segments in the routing structure of the placement such that the number of switchboxes is minimized, is presented. The algorithm is based on a graph-theory approach

Yang Cai; Martin D. F. Wong

1991-01-01

314

Implementation of Complex Fuzzy Logic Modules with VLSI Approach  

Microsoft Academic Search

Summary The hybrid intelligent systems are gaining popularity due to extensive success of these systems in many real world complex problems. In this paper, the implementation of the complex fuzzy logic modules have been undertaken with VLSI design approach. Complex fuzzy logic is a generalization of traditional fuzzy logic based on complex fuzzy sets. The general scheme of Complex Fuzzy

A. Y. Deshmukh; P. R. Bajaj

2008-01-01

315

A Dictionary Machine Emulation on a VLSI Computing Tree System  

Microsoft Academic Search

In this paper, we propose a dictionary machine emulation using a novel VLSI tree structure that operates on the dictionary using a blocking technique. We show that dictionary machine operations can be performed through the implementation of a number of processing and communication tasks overlapped on a simple structure. By manipulating the key-records bit serially, and storing them in an

Adger E. Harvin III; José G. Delgado-frias

1998-01-01

316

VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications  

Microsoft Academic Search

The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is

Rozita Teymourzadeh; Masuri Othman

317

Probabilistic simulation for reliability analysis of CMOS VLSI circuits  

Microsoft Academic Search

A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of the tedious task of specifying

Farid N. Najm; Richard Burch; Ping Yang; Ibrahim N. Hajj

1990-01-01

318

Fuzzy Partitioning applied to VLSI-Floorplanning and Placement  

Microsoft Academic Search

Fast hierarchical optimization methods applied to VLSI-floorplanning and placement play a major role in advancing the state of the art in physical design, because circuits get more and more complex. This paper presents a new approach for floorplanning and placement using fuzzy logic as the framework for optimal partitioning. Two hierarchical partitioning strategies are described, both based on the fuzzy

Carsten F. Ball; Peter V. Kraus; Dieter A. Mlynski

1994-01-01

319

System theoretic models for high density VLSI structures  

Microsoft Academic Search

This research project involved the development of mathematical models for analysis, synthesis, and simulation of large systems of interacting devices. The work was motivated by problems that may become important in high density VLSI chips with characteristic feature sizes less than 1 micron: it is anticipated that interactions of neighboring devices will play an important role in the determination of

Bradley W. Dickinson; William E. Hopkins Jr.

1989-01-01

320

Yoda: a framework for the conceptual design VLSI systems  

Microsoft Academic Search

As the complexity of the VLSI design process grows, it becomes increasingly more costly to conduct design in a trial-and-error fashion because the number of possible design alternatives, as well as the cost of a complete synthesis and fabrication cycle, increase dramatically. A conceptual design addresses this problem by allowing the designer to conduct initial feasibility studies, giving guidance on

A. M. Dewey; Stephen W. Director

1989-01-01

321

Knowledge based system for designing testable VLSI circuits  

Microsoft Academic Search

A knowledge based system that can be used for designing testable VLSI circuits is described. First, a model for capturing circuit designs which incorporates all the relevant aspects of a design from the testing point of view is introduced. Next, a methodology that incorporates structural, behavioral, qualitative, and quantitative aspects of known design for testability (DFT) techniques is presented. A

Abadir

1986-01-01

322

Generating test patterns for VLSI circuits using a genetic algorithm  

Microsoft Academic Search

The authors present the development of a technique that uses genetic algorithms for the generation of test patterns that detect single stuck-at faults in combinational VLSI circuits. As the genetic algorithm evolves, an efficient set of test patterns are produced, by searching the solution space for patterns that detect the highest number of remaining faults in the fault list.

M. J. O'Dare; T. Arslan

1994-01-01

323

Architectures and VLSI Implementations of the AES-Proposal Rijndael  

Microsoft Academic Search

Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit\\/sec. It performs efficiently in

Nicolas Sklavos; Odysseas G. Koufopavlou

2002-01-01

324

Fault model development for fault tolerant VLSI design  

Microsoft Academic Search

Fault models provide systematic and precise representations of physical defects in microcircuits in a form suitable for simulation and test generation. The current difficulty in testing VLSI circuits can be attributed to the tremendous increase in design complexity and the inappropriateness of traditional stuck-at fault models. This report develops fault models for three different types of common defects that are

C. R. Hartmann; P. K. Lala; A. M. Ali; G. S. Visweswaran; S. Ganguly

1988-01-01

325

Low-power VLSI synthesis of DSP systems  

Microsoft Academic Search

In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this true expect for portable, battery-operated applications, where power consumption has perhaps superceded speed and area, which are the overriding implementation constraints. This adds another degree of freedom and complexity to the design process, and mandates the need for design techniques that address

Sanjay Sharma; Sanjay Attri; R. C. Chauhan

2003-01-01

326

Databases and Cell-Selection Algorithms for VLSI Cell Libraries  

Microsoft Academic Search

The issues that must be addressed before commercial database management systems can be used to manage VLSI CAD data are defined. A survey is presented of approaches addressing four of the defined issues: design hierarchies and multilevel representations, design alternatives and version control, common interface between cell libraries and efficient cell selection based on given design constraints. A frame-based model

Simon Y. Foo; Yoshiyasu Takefuji

1990-01-01

327

Curriculum Development for Semiconductor Industry in Malaysia: A Case Study of Technical Development Programs for Technicians and Engineers in Wafer Manufacturing Company  

Microsoft Academic Search

Recently, Malaysia has made a remarkable progress in engineering and technical development of semiconductor wafer fabrication. This began with the set up of the Malaysian Institute of Microelectronic Systems (MIMOS) in Kuala Lumpur. MIMOS's Semiconductor Technology Centre, established in 1997, was the 1st Malaysian wafer fabrication facility. The facility was set up as a catalyst for the growth of the

A. bin Lin

2006-01-01

328

Simple tilt and height location monitoring of wafers  

NASA Astrophysics Data System (ADS)

Good alignment is needed in various wafer processes. Reflectometry is a well-established technique that continues to be widely used to monitor the thickness of wafer thin films. The use of a reflectometer was investigated to detect incorrect tilt and height of wafer placement. We found that it could be used in the spectroscopic or the monochromatic mode and provided results whether the wafer was bare or coated. We also found that the technique was somewhat more sensitive to tilt of bare wafers, and more sensitive to height displacements of coated wafers.

Ng, Tuck Wah; Tay, Arthur E. B.

2006-05-01

329

Calculation of emissivity of Si wafers  

SciTech Connect

A computer-software, Emissivity, has been developed to calculate the emissivity ({epsilon}) of silicon wafers of any surface morphology, for a given temperature and dopant concentration. The software uses a combination of ray- and wave-optics approaches to include the interference and the polarization effects necessary for multilayer surface coatings and multi-reflections within thin wafers. The refractive index and the absorption coefficient are calculated as a function of temperature and dopant concentration using an empirical model for an indirect bandgap semiconductor. The results of this model are compared with conventional emissivity calculations and experimental data.

Sopori, B.; Chen, W.; Madjdpour, J.; Ravindra, N.M.

1999-11-12

330

Optical metrology of semiconductor wafers in lithography  

NASA Astrophysics Data System (ADS)

This paper presents a concise description of 3 optical measurement systems that play a critical role in optical lithography of semiconductor devices. A level sensor and alignment sensor are described that are used to measure, respectively, wafer height variations and the wafer location prior to resist exposure. The third sensor is an angle-resolved scatterometer that is used to measure the shape (CD) and placement (Overlay) of the resist patterns. It will be shown how these sensors deal with the common challenge of realizing sub-nm precision on a large variety of product stacks in the presence of process variations.

den Boef, Arie J.

2013-06-01

331

Wafer bonding of wide bandgap materials  

NASA Astrophysics Data System (ADS)

Wafer bonding is a powerful technique for integration of materials. It enables creation of junctions and structures not attainable by the epitaxial growth due to lattice mismatch. Wafer bonding may involve no intermediate layer and allow the joined wafers to be stable at elevated temperatures. Atomically smooth and flat wafers of almost any material spontaneously bond to each other even at room temperature, although further annealing might be required to increase the strength of bonding. High values of surface roughness make the bonding process more challenging. In this case, high temperature combined with applied stress is an effective route for a successful process. The goal of the current work was to assess the potential of pressure assisted wafer bonding technique applied to diamond/silicon and silicon carbide/silicon carbide systems, where the wafer surface smoothness was limited. Polished and unpolished (100) highly oriented diamond (HOD) films with an RMS roughness of 5 nm and 150 nm, respectively, as well as polished, polycrystalline diamond films with an RMS roughness of 15 nm were bonded to single-side polished silicon in ultra high vacuum at 32 MPa of applied uniaxial pressure. Successful fusion of unpolished HOD and polished polycrystalline diamond was observed at temperatures as low as 950°C while bonding of polished HOD to silicon was achieved at 850°C. Fusion of polished polycrystalline diamond to silicon resulted in the formation of a non-uniform bonded interface. An abrupt boundary between the two wafers existed only in some regions of the interface, while other regions contained an up to 40 nm thick amorphous interlayer consisting of C, Si and O. A local phase transformation of diamond to graphite near the diamond surface asperities followed by inter-diffusion of C and Si has been suggested. Fusion of polished HOD to Si resulted in the formation of the abrupt interface between the wafers, in the areas away from the diamond grain boundaries. Voids, partially filled with amorphous material, were observed at the fused interface near the diamond grain boundaries. Diamond polishing defects, potential out-diffusion of hydrogen from diamond and oxygen from Si are believed to have contributed to the observed non-uniformity of the bonded interface. SiC wafers with an RMS roughness of 2 run were successfully bonded at temperatures as low as 800°C. Cross-section transmission electron microscopy (XTEM) of specimens bonded at 1100°C revealed an atomically abrupt interface between the bonded wafers without any intermediate layer between them. The bonded SiC retained its high crystalline quality; no extended defects emanating from the interface were observed within the sampling region. Electrical measurements showed that azimuthal orientation of the bonded couple significantly influences the electrical character of the junction. A low resistance Ohmic interface can be created by high temperature fusion of aligned 6H-SiC/6H-SiC wafers.

Yushin, Gleb Nikolayevich

332

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder  

NASA Astrophysics Data System (ADS)

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

333

Mask and wafer cost of ownership (COO) from 65 to 22 nm half-pitch nodes  

Microsoft Academic Search

Anticipating the cost of ownership (COO) of different lithography approaches into the future is an act of faith. It requires that one believe that all of the lithographic problems with next generation lithography (NGL) approaches will be sufficiently resolved to support the production of manufacturing wafers. This paper assumes that all of the necessary technologies will be available in the

Greg Hughes; Lloyd C. Litt; Andrea Wüest; Shyam Palaiyanur

2008-01-01

334

Development of Fixture Element for Vacuum Transportation of Silicon Wafer Using Electro-Rheological Gel  

Microsoft Academic Search

Semiconductor process technology increasingly requires high accuracy and efficiency. In the case of processing thin fragile substrate such as silicon wafer, it has to be fixed with low strain. In addition, its fixture device can be used under vacuum condition because some processes are carried out in vacuum. It is required to develop a new fixture device for vacuum transportation

Masayuki Tanaka; Yasuhiro Kakinuma; Tojiro Aoyama; Hidenobu Anzai; Takafumi Kawaguchi

2008-01-01

335

Study on Board Level Drop Reliability of Wafer Level Chip Scale Package with Leadfree Solder  

Microsoft Academic Search

Wafer level chip scale package (WLCSP) is a promising packaging technology to accommodate the demand for small, portable handheld electronic. This bare-die bumped package is able to offer significant area savings, improve package electrical parasitics and power dissipation performance over substrate-based BGA packages. However, its board level reliability especially mechanical performance under shock impact is a great concern for handheld

Zhang Xueren; Zhu Wenhui; P. Edith; Tan Hien Boon

2008-01-01

336

Thermal-Electrical Co-simulation for Wafer-level Chip Scale Package Maximum Bearing Current  

Microsoft Academic Search

As the trend of smaller and higher density packaging technology developing, the wafer-level chip scale package (WLCSP) is becoming the popular choice for device assembly. While many high performance chip often with high power, the power dissipation through the chip also leads to higher die temperatures. With the redistribution layer of the WLCSP getting more narrow and thinner, in order

Rui-Yu; Shu-Qiang Zhang; Chang-Lin Yeh; Chi-Sheng Chung; Chih-Pin Hung

2008-01-01

337

Wafer-level MEMS packaging via thermally released metal-organic membranes  

Microsoft Academic Search

This paper reports on the design, implementation and characterization of wafer-level packaging technology for a wide range of microelectromechanical system (MEMS) devices. The encapsulation technique is based on thermal decomposition of a sacrificial polymer through a polymer overcoat to form a released thin-film organic membrane with scalable height on top of the active part of the MEMS. Hermiticity and vacuum

Pejman Monajemi; Paul J. Joseph; Paul A. Kohl; Farrokh Ayazi

2006-01-01

338

Influence of Silicon on Insulator Wafer Stress Properties on Placement Accuracy of Stencil Masks  

Microsoft Academic Search

The issue of placement control is one of the key challenges of stencil mask technology. A high placement accuracy can only be achieved with a precise control of mechanical stress on a global and local scale. For this reason, the stress properties of the mask blank material -typically silicon on insulator (SOI) wafers- have to be known and adjusted properly.

Frank-Michael Kamm; Albrecht Ehrmann; Herbert Schäfer; Werner Pamler; Rainer Käsmaier; Jörg Butschke; Reinhard Springer; Ernst Haugeneder; Hans Löschner

2002-01-01

339

Thermal isolation of high-temperature superconducting thin films using silicon wafer bonding and micromachining  

Microsoft Academic Search

Using a new micromachining technology, thermally isolated thin films of high-temperature superconductor have been microfabricated. The intended application for these structures is in infrared bolometers. A silicon wafer bonding process produces a low thermal mass island of single-crystal silicon on a silicon nitride membrane which provides thermal isolation. The silicon can act as a seed for the epitaxial growth of

Christopher A. Bang; Joseph P. Rice; Markus I. Flik; David A. Rudman; Martin A. Schmidt

1993-01-01

340

Device Array Scribe Characterization Vehicle Test Chip for Ultra Fast Product Wafer Variability Monitoring  

Microsoft Academic Search

Lower supply voltages and aggressive OPC on 65 nm and below technologies are causing larger variability of critical device parameters like Vt and Id. With ever increasing clock frequencies, more and more performance related yield loss can be observed even for purely digital circuits. To design more robust circuits it is required to characterize device variability within die, within wafer,

C. Hess; S. Saxena; H. Karbasi; S. Subramanian; M. Quarantelli; A. Rossoni; S. Tonello; Sa Zhao; D. Slisher

2007-01-01

341

Design Of Neural Network Circuit Inside High Speed Camera Using Analog CMOS 0.35 ?m Technology  

Microsoft Academic Search

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and\\/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities

Brahmantyo Heruseto; Yulisdin Mukhlis; Eri Prasetyo; Hamzaf Afandi

342

Study on Homogeneous Wafer Level Dielectric Film Preparation Using Chemical Solution Deposition Method  

NASA Astrophysics Data System (ADS)

Process parameters of lead zirconate titanate thin film preparation using metal organic decomposition method were optimized by a statistical method and their effects on the film properties were investigated quantitatively in this study. The crystallization temperature and the precursor formation temperature were found to be important factors for high quality thin films. We also investigated the films deposited on the 4-in. wafer under the optimum conditions and found that it exhibited great film properties. Furthermore, the process damage to the wafer sample by photolithography was clarified experimentally. The results will be useful for the fabrication of the MEMS devices and integration technology of electrical devices including piezoelectric films.

Sueshige, Kazutaka; Ichiki, Masaaki; Suga, Tadatomo; Itoh, Toshihiro

2013-06-01

343

Development and optimization of a cryogenic-aerosol-based wafer-cleaning system  

SciTech Connect

A summary of recent advances in cryogenic-aerosol-based wafer-processing technology for semiconductor wafer cleaning is presented. An argon/nitrogen cryogenic-aerosol-based tool has been developed and optimized for removal of particulate contaminants. The development of the tool involved a combination of theoretical (modeling) and experimental efforts aimed at understanding the mechanisms of aerosol formation and the relation between aerosol characteristics and particle-removal ability. It is observed that the highest cleaning efficiencies are achieved, in general, when the cryogenic aerosol is generated by the explosive atomization of an initially liquid jet of the cryogenic mixture.

Narayanswami, N.; Heitzinger, J.; Patrin, J. [FSI International Inc., Chaska, MN (United States); Rader, D.; O`Hern, T.; Torczynski, J. [Sandia National Labs., Albuquerque, NM (United States)

1998-04-01

344

Smart power technologies evolution  

Microsoft Academic Search

This paper reviews the evolution in the mixed power process field driven by the need to integrate more and more functions onto the same chip. The more recent BCD (Bipolar, CMOS, DMOS) and VIPower(R) (Vertical Intelligent Power) examples are a demonstration of how Smart Power technologies evolves today following, with some delay, the road maps of VLSI CMOS and BiCMOS

Bruno Murari; Claudio Contiero; Roberto Gariboldi; S. Sueri; A. Russo

2000-01-01

345

Contactless magnetically levitated silicon wafer transport system  

Microsoft Academic Search

A new magnetically levitated wafer transport system is developed for the semiconductor fabrication process to get rid of the particle and oil contaminations that normally exist in conventional transport systems. The transport system consists of levitation, stabilization tracks, and a propelling system. Stabilities needed for levitation in the transport system are achieved by an antagonistic property produced in the tracks

K. H. Park; S. K. Lee; J. H. Yi; S. H. Kim; Y. K. Kwak; I. A. Wang

1996-01-01

346

Methanol Steam Reformer on a Silicon Wafer  

SciTech Connect

A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Comparison of computed and measured conversion efficiencies are shown to be favorable. Concepts for insulating the reactor while maintaining small overall size and starting operation from ambient temperature are analyzed.

Park, H; Malen, J; Piggott, T; Morse, J; Sopchak, D; Greif, R; Grigoropoulos, C; Havstad, M; Upadhye, R

2004-04-15

347

Innovative optical alignment technique for CMP wafers  

Microsoft Academic Search

Detecting position of the wafers such as after CMP process is critical theme of current and forthcoming IC manufacturing. The alignment system must be with high accuracy for any process. To satisfy such requirements, we have studied and analyzed factors that have made alignment difficult. From the result of the studies, we have developed new optical alignment techniques which improve

Ayako Sugaya; Yuho Kanaya; Shinichi Nakajima; Tadashi Nagayama; Naomasa Shiraishi

2002-01-01

348

Release of arsenic from semiconductor wafers  

SciTech Connect

The production of integrated circuits and other semiconductor devices requires the introduction of impurities or dopants into the crystal lattice of a silicon substrate. This doping or junction formation is achieved through one of two processes: thermal diffusion or ion implantation. Ion implantation, the more contemporary and more accurate of the two processes, accomplishes junction formation by bombarding selected areas of the silicon wafer with a beam of dopantions. Inorganic arsenic, which is regulated by the Occupational Health and Safety Administration (OSHA) as a carcinogen, is frequently used as dopant material. Silicon wafers are found to emit inorganic arsenic following ion implantation. Data collected during this experiment demonstrate that arsenic is released over a 3.5-hour period following implantation and that the total amount of arsenic emitted may approach 6.0 ..mu..g per 100 wafers processed within 4 hours after implantation. The discovery and quantification of this phenomenon suggest that newly implanted silicon wafers are a potential source of arsenic contamination-a source that may impact both the quality of the work environment and the integrated circuit product.

Ungers, L.J.; Jones, J.H.; McIntyre, A.J.; McHenry, C.R.

1985-08-01

349

Release of arsenic from semiconductor wafers.  

PubMed

The production of integrated circuits and other semiconductor devices requires the introduction of impurities or dopants into the crystal lattice of a silicon substrate. This "doping" or junction formation is achieved through one of two processes: thermal diffusion or ion implantation. Ion implantation, the more contemporary and more accurate of the two processes, accomplishes junction formation by bombarding selected areas of the silicon wafer with a beam of dopant ions. Inorganic arsenic, which is regulated by the Occupational Health and Safety Administration (OSHA) as a carcinogen, is frequently used as dopant material. Silicon wafers are found to emit inorganic arsenic following ion implantation. Data collected during this experiment demonstrate that arsenic is released over a 3.5-hour period following implantation and that the total amount of arsenic emitted may approach 6.0 micrograms per 100 wafers processed within 4 hours after implantation. The discovery and quantification of this phenomenon suggest that newly implanted silicon wafers are a potential source of arsenic contamination--a source that may impact both the quality of the work environment and the integrated circuit product. PMID:4050678

Ungers, L J; Jones, J H; McIntyre, A J; McHenry, C R

1985-08-01

350

Low-temperature full wafer adhesive bonding  

Microsoft Academic Search

We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 µm and 18 µm. The tested polymer materials were benzocyclobutene (BCB)

Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

2001-01-01

351

Characterization of Charging Control of a Single Wafer High Current Spot Beam Implanter  

SciTech Connect

This paper focuses on the characterization of charging control of an Axcelis Optima HD single wafer high current spot beam implanter using MOS capacitors with attached antennas of different size and shape. Resist patterns are implemented on Infineon Technologies own charging control wafers to investigate the influence of photo resist on charging damage. Compared to batch high current implanters the design of the beamline and the beam shape are comparable to single wafer high current spot beam implanters, however due to the different scanning architecture the dose rate of the single wafer high current spot beam implanters is significantly higher compared to the batch tools. Therefore, the risk of charging damage will be higher. The charging damage was studied as a function of the energy, the beam current and the most important plasma flood gun parameters. The results have shown that for very high antenna ratios the charging damage for single wafer implanters, even spot or ribbon beam implanters, is higher than for high current batch implanters.

Schmeide, Matthias; Bukethal, Christoph [Infineon Technologies Dresden GmbH and Co. OHG, Koenigsbruecker Str. 180, D-01099 Dresden (Germany)

2008-11-03

352

In-line failure analysis on productive wafers with dual-beam SEM/FIB systems  

NASA Astrophysics Data System (ADS)

Modern dual beam SEM/FIB tools will allow physical failure analysis on productive wafers in the cleanroom if contamination of wafer and production equipment can be controlled. In this study we show that the risks of Ga- diffusion and -desorption as well as heavy metal contamination can be overcome. The reentry of analyzed wafers into the production flow results in lower overall costs and a dramatically shortened feedback loop to production engineers, leading to reduced down times of production tools etc. Most FIB-applications (i.e. highlight etch of cross sections) can be processed with appropriate gas chemistry. Ion Beam deposition of an insulating material to refill the crater created by the sputtering process is also investigated. If either resolution is not sufficient or more complex analyses have to be applied a sample lift-out technique was developed making it obsolete to sacrifice wafers also in these cases. The fixed sample can be analyzed off-line with all PFA- methods, even plasma etching or lift-off in HF is possible. The benefits of this quantum leap for physical failure analysis are reduction of wafer costs and the possibility to reduce analysis cycle time as well as the number of learning cycles in technology development.

Weiland, Rainer; Boit, Christian; Dawes, Nick; Dziesiaty, Andreas; Demm, Ernst; Ebersberger, Bernd; Frey, Lothar; Geyer, Stefan; Hirsch, Alexander; Lehrer, Christoph; Meis, Peter; Kamolz, Matthias; Lezec, Henri; Rettenmaier, Hans; Tittes, Wolfgang; Treichler, Rolf; Zimmermann, Harald

2001-04-01

353

Characterization of Charging Control of a Single Wafer High Current Spot Beam Implanter  

NASA Astrophysics Data System (ADS)

This paper focuses on the characterization of charging control of an Axcelis Optima HD single wafer high current spot beam implanter using MOS capacitors with attached antennas of different size and shape. Resist patterns are implemented on Infineon Technologies own charging control wafers to investigate the influence of photo resist on charging damage. Compared to batch high current implanters the design of the beamline and the beam shape are comparable to single wafer high current spot beam implanters, however due to the different scanning architecture the dose rate of the single wafer high current spot beam implanters is significantly higher compared to the batch tools. Therefore, the risk of charging damage will be higher. The charging damage was studied as a function of the energy, the beam current and the most important plasma flood gun parameters. The results have shown that for very high antenna ratios the charging damage for single wafer implanters, even spot or ribbon beam implanters, is higher than for high current batch implanters.

Schmeide, Matthias; Bukethal, Christoph

2008-11-01

354

A wafer-scale 170000-gate FFT processor with built-in test circuits  

NASA Astrophysics Data System (ADS)

The wafer-scale 170,000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor performs parallel 16-bit, eight-point complex FFTs and is implemented with 725 I/O pads in triple-metal 2.3-micron p-well CMOS technology on a 4-in. wafer. It is mounted by controlled-collapse bonding facedown on a 11.8 x 11.8-sq cm substrate.

Yamashita, Koichi; Kanasugi, Akinori; Hijiya, Shinpei; Goto, Gensuke; Matsumura, Nobutake

1988-04-01

355

Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer  

SciTech Connect

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

1999-09-07

356

Thin silicon wafer dicing with a dual-focused laser beam  

NASA Astrophysics Data System (ADS)

Driven by the ever-growing desire for more compact electronic devices, the semiconductor industry has moved toward thinner silicon wafers. Simultaneously, the semiconductor industry has introduced new and better materials to facilitate the size shrinking. These factors introduce serious limitation in current saw blade semiconductor wafer dicing technology and needs new processing tools. Although nanosecond laser dicing overcomes most of the issues related to saw blade dicing, the dicing throughput remains below the current industrial requirement. In this paper a novel dual focus mechanism is introduced to increase the throughput of laser wafer dicing. Experimental results proved that dual focus increases the dicing speed, reduces the kerf width, eliminates the debris and enhances the die fracture strength. Cutting strategy and laser parameters, such as back focus power, repetition rate and wavelength, that influence the machining efficiency and quality, were studied in detail. The industrial implement of laser singulation is discussed.

Venkatakrishnan, Krishnan; Tan, Bo

2007-12-01

357

Waveguide probe tackles V-band on-wafer tests  

Microsoft Academic Search

As millimeter-wave MMIC processes mature, requirements for manufacturing process control and product performance testing drive the need for V-band on-wafer testing. Semiconductor wafer probes for RF measurements are outlined, as well as commercial wafer probes based on the 1.85-mm coaxial connector supporting on-wafer device measurements up to 65 GHz. A waveguide architecture requiring the development of a waveguide-to-coplanar -waveguide (CPW)

Keith Jones; Ed Godshalk

1990-01-01

358

Advanced laser mask repair in the current wafer foundry environment  

NASA Astrophysics Data System (ADS)

Contrary to the prior assumptions of its technical demise, deep UV (DUV) femtosecond pulsed laser repair of photomasks is continuing to mature and improve as a technology. Similar to the optical enhancements that allow for 193 nm wavelength light to continue being used down to the 32, or even in some cases 22 nm, node, the process regimes for this type of laser repair continue to expand as new processes are discovered. This work reviews the qualification of repair performance for production at a major wafer foundry site. In addition advances are shown in the area of through-pellicle repair (TRP) process development. These advances include the preferential (versus surrounding reference mask structures) removal of soft defects and the capability to remove or manipulate particles on top of a flat absorber region with no detectable removal of the absorber. These developments will further demonstrate the progressive decoupling of the laser repair spot size from the minimum technology node for laser repair.

Robinson, Tod; Yi, Daniel; Leclaire, Jeff; White, Roy; Bozak, Ron; Archuletta, Mike

2010-09-01

359

Impact of VLSI/VHSIC on satellite on-board signal processing  

NASA Astrophysics Data System (ADS)

Forecasted improvements in IC fabrication techniques, such as the use of X-ray lithography, are expected to yield submicron circuit feature sizes within the decade of the 1980s. As dimensions decrease, reliability, cost, speed, power consumption and density improvements will be realized which have a significant impact on the capabilities of onboard spacecraft signal processing functions. This will in turn result in increases of the intelligence that may be deployed on spaceborne remote sensing platforms. Among programs oriented toward such goals are the silicon-based Very High Speed Integrated Circuit (VHSIC) researches sponsored by the U.S. Department of Defense, and efforts toward the development of GaAs devices which will compete with silicon VLSI technology for future applications. GaAs has an electron mobility which is five to six times that of silicon, and promises commensurate computation speed increases under low field conditions.

Aanstoos, J. V.; Ruedger, W. H.; Snyder, W. E.; Kelly, W. L.

360

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture  

NASA Astrophysics Data System (ADS)

This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.

Hariyama, Masanori; Ishihara, Shota; Kameyama, Michitaka

361

Automated reticle inspection data analysis for wafer fabs  

Microsoft Academic Search

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the

Derek Summers; Gong Chen; Bryan Reese; Trent Hutchinson; Marcus Liesching; Hai Ying; Russell Dover

2008-01-01

362

Automated reticle inspection data analysis for wafer fabs  

Microsoft Academic Search

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the

Derek Summers; Gong Chen; Bryan Reese; Trent Hutchinson; Marcus Liesching; Hai Ying; Russell Dover

2009-01-01

363

Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)  

SciTech Connect

A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

Rupnowski, P.; Sopori, B.

2008-05-01

364

Development of quasi half coax lines for wafer level packaging  

Microsoft Academic Search

A 50 ohm micromachined interconnect is designed, fabricated, and measured as a broadband interconnect that is compatible with the standard thickness of wafers. It is developed in two applications: a transition from a commercially available 1 mm connector launch assembly to wafer based systems and an interconnect within wafer level designs. S-parameter measured data is shown for coaxially launched structures

S. R. Banerjee; R. F. Drayton

2005-01-01

365

Wafer-scale fabrication of penetrating neural microelectrode arrays  

NASA Astrophysics Data System (ADS)

In order to have an efficient neural interface, uniformity and predictability of electrodes electrical, and mechanical characteristics are desired. Furthermore, the electrodes should have small active sites to selectively record or stimulate neural signals. Also, there should be close geometrical match between the electrode array and the targeted tissue for long-term stability. Currently the Utah electrode array (UEA) is in either constant electrode length (UEA) or varying length configurations (Utah slant electrode array: USEA). The current processes used to fabricate the UEAs impose limitations in the tolerances of the electrode array geometry. Furthermore, the flat architecture of the UEA and convoluted geometry of the targeted tissue results in poor coupling between the two "mating" surfaces, leading in active electrode tips that are not in proximity to the neuronal tissue. Therefore, a robust, flexible and high precision fabrication technology is needed that can produce (a) uniformly shaped microelectrodes (b) small and uniformly exposed active tip sites and (c) convoluted electrode arrays for better geometrical match. This dissertation presents a wafer-scale fabrication process for both the UEA and the USEA. A wafer-scale etching method has been developed and optimum etching conditions are established to achieve uniform shape electrode arrays. Also, the etching rate of silicon columns, produced by dicing, is studied as a function of temperature, etching time and stirring rate in the acid solution. Furthermore, a novel photoresist based masking technique for procuring extremely small active area has been developed on wafer-scale. In this technique, the tip exposure is controlled by varying the spin speed during photoresist coating. The technique allows fabrication of uniformly exposed tip lengths, over a range of 30 to 350 microm in length. Lastly, a novel array fabrication technique is developed for building a variety of neural interface devices having complex three-dimensional geometries using variable depth dicing and wet etching. The wafer-scale technique results in fabrication of highly controlled electrode shape, size and tip exposure which inturn allows better controllability in the electrical characteristics (impedance) of the electrode array. The uniformity in electrode impedance would lead to better understanding of observed variations in physiological results.

Bhandari, Rajmohan

366

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force  

Microsoft Academic Search

This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of

Minoru Sudou; Hidekuni Takao; Kazuaki Sawada; Makoto Ishida

2007-01-01

367

Fault model development for fault tolerant VLSI design  

NASA Astrophysics Data System (ADS)

Fault models provide systematic and precise representations of physical defects in microcircuits in a form suitable for simulation and test generation. The current difficulty in testing VLSI circuits can be attributed to the tremendous increase in design complexity and the inappropriateness of traditional stuck-at fault models. This report develops fault models for three different types of common defects that are not accurately represented by the stuck-at fault model. The faults examined in this report are: bridging faults, transistor stuck-open faults, and transient faults caused by alpha particle radiation. A generalized fault model could not be developed for the three fault types. However, microcircuit behavior and fault detection strategies are described for the bridging, transistor stuck-open, and transient (alpha particle strike) faults. The results of this study can be applied to the simulation and analysis of faults in fault tolerant VLSI circuits.

Hartmann, C. R.; Lala, P. K.; Ali, A. M.; Visweswaran, G. S.; Ganguly, S.

1988-05-01

368

Steel bridge fatigue crack detection with piezoelectric wafer active sensors  

NASA Astrophysics Data System (ADS)

Piezoelectric wafer active sensors (PWAS) are well known for its dual capabilities in structural health monitoring, acting as either actuators or sensors. Due to the variety of deterioration sources and locations of bridge defects, there is currently no single method that can detect and address the potential sources globally. In our research, our use of the PWAS based sensing has the novelty of implementing both passive (as acoustic emission) and active (as ultrasonic transducers) sensing with a single PWAS network. The combined schematic is using acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since methods such as ultrasonics are unable to quantify the initial condition of crack growth since most of the fatigue life for these details is consumed while the fatigue crack is too small to be detected. Hence, combing acoustic emission with ultrasonic active sensing will strengthen the damage detection process. The integration of passive acoustic emission detection with active sensing will be a technological leap forward from the current practice of periodic and subjective visual inspection, and bridge management based primarily on history of past performance. In this study, extensive laboratory investigation is performed supported by theoretical modeling analysis. A demonstration system will be presented to show how piezoelectric wafer active sensor is used for acoustic emission. Specimens representing complex structures are tested. The results will also be compared with traditional acoustic emission transducers to identify the application barriers.

Yu, Lingyu; Giurgiutiu, Victor; Ziehl, Paul; Ozevin, Didem; Pollock, Patrick

2010-03-01

369

An advanced modeling approach for mask and wafer process simulation  

NASA Astrophysics Data System (ADS)

A new modeling technique to accurately represent the mask and wafer process behavior is presented. The lithography simulation can be done in three steps: i) mask simulation, ii) latent image calculations and iii) resist process simulation. The leading edge designs, such as 32 nm and beyond, require higher-fidelity models to adequately represent each of these actual processes. Effects previously considered secondary, have become more pronounced with each new technology node. In this approach, we utilized separate physical models for both mask and wafer processes. We demonstrate that the residual errors can be further reduced when nonlinear mappers are used in addition. The advantage of the presented approach compared to standard curve-fitting or statistics-based models is its predictive power and adaptive nature. The physical model parameters were calibrated by a genetic algorithm whose details were outlined in [1]. The nonlinear mapper model parameters were identified by a gradient descent method. Given the computational requirements for a practical solution, our approach uses graphics processors as well as CPUs as computation hardware.

Karakas, Ahmet; Elsen, Erich; Torunoglu, Ilhami; Andrus, Curtis

2010-09-01

370

Gradient Flow Independent Component Analysis in Micropower VLSI  

Microsoft Academic Search

We present micropower mixed-signal VLSI hardware for real-time blind separation and localization of acoustic sources. Gradient flow represen- tation of the traveling wave signals acquired over a miniature (1cm di- ameter) array of four microphones yields linearly mixed instantaneous observations of the time-differentiated sources, separated and localized by independent component analysis (ICA). The gradient flow and ICA processors each measure

Abdullah Celik; Milutin Stanacevic; Gert Cauwenberghs

2005-01-01

371

A new VLSI-oriented FFT algorithm and implementation  

Microsoft Academic Search

In this paper, we present a new VLSI-oriented fast Fourier transform (FFT) algorithm-radix-2\\/4\\/8, which can effectively minimize the number of complex multiplications. This algorithm can be implemented efficiently using a pipelined architecture. Based on this pipelined architecture, an 8 K FFT ASIC is designed for use in the DVB (Digital Video Broadcasting) application in 0.6 ?m-3.3 V triple-metal CMOS process

Lihong Jia; Yonghong Gao; Jouni Isoaho; Hannu Tenhunen

1998-01-01

372

Parallel VLSI-based architecture for multimotion estimation  

NASA Astrophysics Data System (ADS)

This paper describes a new parallel architecture dedicated to multimotion estimation. The input image is scanned by a standard video camera with 256 grey levels. Motion computing is based on the optical flow determination. Some constraints are proposed to allow multimotion evaluation. The algorithm is presented and the main features of a 1-D systolic architecture which is based on a custom VLSI chip is given. This architecture allows a real-time implementation of the multimotion estimation algorithm.

Legat, Jean-Didier; Cornil, J. P.; Macq, Damien; Verleysen, M.

1992-03-01

373

A systematic method for configuring VLSI networks of spiking neurons.  

PubMed

An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems. PMID:21732859

Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

2011-07-06

374

A VLSI-based biological interface for prosthetic devices  

Microsoft Academic Search

A circuit was developed to serve as an interface from an intact biological neuron to an electromechanical device. The circuit is a custom VLSI IC that contains a highly sensitive buffer, a neuron-like threshold discriminator, and a dedicated four-phase output driver. Nerve-like in behavior, the circuit detects action potentials from living nerve tissue, and if the activity exceeds a given

Michael J. Osborn; Seth Wolpert

1992-01-01

375

Time memory cell VLSI for the PHENIX drift chamber  

Microsoft Academic Search

A high-precision Time-to-Digital-Converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and a trigger buffering which are necessary for very high rate experiments. In addition to the fixed data size readout, the chip also supports zero-suppression mode readout. The chip records both rising and falling edge

Y. Arai; M. Ikeno; M. Sagara; T. Emura

1997-01-01

376

Time memory cell VLSI for the PHENIX drift chamber  

Microsoft Academic Search

A high-precision time-to-digital-converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and one level of trigger buffering required in very high rate experiments. In addition to a fixed data size readout, the chip also supports a zero-suppression mode readout. The chip records both rising and falling

Y. Arai; M. Ikeno; M. Sagara; T. Emura

1998-01-01

377

VLSI-NEMS chip for AFM data storage  

Microsoft Academic Search

We report the microfabrication of a 32×32 (1024) 2D cantilever array chip and its electrical testing. It has been designed for ultrahigh-density, high-speed data storage applications using thermomechanical writing and thermal readout in thin polymer film storage media. The fabricated chip is the first VLSI-NEMS (NanoEMS) for nanotechnological applications. For electrical and thermal stability, the levers are made of silicon

M. Despont; J. Brugger; U. Drechsler; U. Durig; W. Haberle; M. Lutwyche; H. Rothuizen; R. Stutz; R. Widmer; H. Rohrer; G. Binnig; P. Vettiger

1999-01-01

378

VLSI-NEMS chip for parallel AFM data storage  

Microsoft Academic Search

We report the microfabrication of a 32×32 (1024) 2D cantilever array chip and its electrical testing. It has been designed for ultrahigh-density, high-speed data storage applications using thermomechanical writing and readout in thin polymer film storage media. The fabricated chip is the first very large scale integration (VLSI)-NEMS (NanoEMS) for nanotechnological applications. For electrical and thermal stability, the levers are

M. Despont; J. Brugger; U. Drechsler; U. Dürig; W. Häberle; M. Lutwyche; H. Rothuizen; R. Stutz; R. Widmer; G. Binnig; H. Rohrer; P. Vettiger

2000-01-01

379

Drift chamber tracking with a VLSI neural network  

SciTech Connect

We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We`ll briefly discuss possible applications in high energy physics detector triggers.

Lindsey, C.S.; Denby, B.; Haggerty, H. [Fermi National Accelerator Lab., Batavia, IL (United States); Johns, K. [Arizona Univ., Tucson, AZ (United States). Dept. of Physics

1992-10-01

380

VLSI block placement using less flexibility first principles  

Microsoft Academic Search

A deterministic algorithm for VLSI block placement was developed through human's accumulated experience in solving “packing” problem. Rectangle packing problem is just a simplified case of the polygon-shape stone plate packing problem that the ancient masons needed to face. Several “packing” principles derived from the so-called “less flexibility first” experience of the masons. A k-d tree data structure is used

Sheqin Dong; Xianlong Hong; Youliang Wu; Yizhou Lin; Jun Gu

2001-01-01

381

On High-Speed VLSI Interconnects: Analysis and Design  

Microsoft Academic Search

We survey our recent work in the analysis and design of interconnect topologies forhigh-speed VLSI. Results include: a new, fast distributed RLC analysis method based ona two-pole approximation; an A-tree formulation for performance-driven interconnect; anoptimal wiresizing algorithm; and new critical-path dependent routing tree algorithms.1 IntroductionInterconnection design is becoming a major concern in the design of high-speed systems, wherestate-of-the-art integrated circuits

K. D. Boese; J. Cong; K. S. Leung; A. B. Kahng; D. Zhou Cs

1992-01-01

382

New CMOS VLSI linear self-timed architectures  

Microsoft Academic Search

The implementation of digital signal processor circuits via self-timed techniques is currently a valid alternative to solve some problems encountered in synchronous VLSI circuits. However, a main difference between synchronous and asynchronous circuits is the hardware resources needed to implement asynchronous circuits. This communication presents four less-costly alternatives to a previously reported linear self-timed architecture, and their application in the

Antonio J. Acosta; Manuel J. Bellido; Manuel Valencia; Angel Barriga Barrios; Raúl Jiménez; José L. Huertas

1995-01-01

383

A complete set of VLSI circuits for ATM switching  

Microsoft Academic Search

The broadband services offered via the ATM-based B-ISDN range from high-speed data services to imaging services. A complete chip set for ATM switching systems is presented. The VLSI components allow one to implement the most significant functions in an ATM node. Three chips are located in the exchange termination: the cell header processor that processes the ATM cells for label

M. Collivignarelli; A. Daniele; P. De Nicola; L. Licciardi; M. Turolla; A. Zappalorto

1994-01-01

384

A Nanosensor Array-Based VLSI Gas Discriminator  

Microsoft Academic Search

Chemiresistive nanowires can be organized as cross-reactive sensor arrays to mimic the human olfactory system in terms of sensing and discriminating various gases and odors. This paper presents a single chip gas discrimination system that integrates a cross-reactive array of chemiresistive nanosensors with an underlying VLSI pattern classifier to accurately and efficiently identify the gas\\/odor to which the system is

Kevin M. Irick; Wei Xu; Narayanan Vijaykrishnan; Mary Jane Irwin

2005-01-01

385

A high performance VLSI chip of the elliptic curve cryptosystems  

Microsoft Academic Search

A high performance VLSI for elliptic curve cryptosystems, based on the elliptic curve K-233 in the field GF(2233), THECC\\/233-100, is presented in this paper. It can perform all four computational functionalities: the digital signature generation and verification; the curve point-multiplication; and the public-secret key-pair generation, needed by the ECDSA protocol. The chip has been successfully designed and fabricated with Shanghai

BAI Guoqiangl; Huang Zhun; Yuan Hang; Chen Hongyi; Liu Ming; Chen Gang; Zhou Tao; Chen Zhihua

2004-01-01

386

Computing perspectives: the rise of the VLSI processor  

Microsoft Academic Search

Around 1970 Intel discovered it could put 2,000 transistors—or perhaps a few more—on a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), an event which had been long heralded, but had been seemingly slow to come. At the time, it went almost unnoticed in the computer industry. This was partly

Maurice V. Wilkes

1990-01-01

387

Impact of 16 bit VLSI computer power on robotics applications  

SciTech Connect

Robots are being used today in a wide variety of applications. The next generation of robots demands higher performance from the VLSI microprocessors to improve the reliability and meet the added functional requirements. The MK68000 is ideally suited for robotics applications because of its clean architecture, powerful instruction set designed for high level language implementation, generous exception handling for security and reliability, large memory addressing range, and multiprocessing features.

Gupta, P.

1982-01-01

388

VLSI Implementation of Fuzzy Adaptive Resonance and Learning Vector Quantization  

Microsoft Academic Search

We present a mixed-mode VLSI chip performing unsupervised clustering and classification, implementing models of Fuzzy Adaptive Resonance Theory (ART) and Learning Vector Quantization (LVQ), and extending to variants such as Kohonen Self-Organizing Maps (SOM). The parallel processor classifies analog vectorial data into a digital code in a single clock, and implements on-line learning of the analog templates, stored locally and

Jeremy Lubkin; Gert Cauwenberghs

2002-01-01

389

L? Voronoi Diagrams and Applications to VLSI Layout and Manufacturing  

Microsoft Academic Search

In this paper we address the L\\u000a ? Voronoi diagram of polygonal objects and present applications in VLSI layout and manufacturing. We show that in L\\u000a ? the Voronoi diagram of segments consists only of straight line segments and is thus much simpler to compute than its Euclidean\\u000a counterpart. Moreover, it has a natural interpretation. In applications where Euclidean precision

Evanthia Papadopoulou

390

A parametric solder joint reliability model for wafer level-chip scale package  

Microsoft Academic Search

The micro-SMD is a Wafer Level-Chip-Scale Package (WL-CSP) designed to have external dimensions equal to that of the silicon device. This new package type extends flip-chip packaging technology to standard surface mount technology. The package has been successfully targeted for low pin count (less than 30), high volume applications such as cellular phones, hand-held PDAs, etc. Since the WL-CSP is

J. Pitarresi; S. Chaparala; B. Sammakia; L. Nguyen; V. Patwardhan; L. Zhang; N. Kelkar

2002-01-01

391

Determining photoresist coat sensitivities of 300-mm wafers  

NASA Astrophysics Data System (ADS)

This paper presents preliminary data on 300 nm wafer coatings by comparing photoresist coats on 150 nm, 200 mm and 300 mm wafers. Conventional methods of applying photoresist have ben prove effective on wafers with diameters up to 200 nm. How well 150 mm and 200 mm coating processes apply to 300 mm substrates is the focus of this paper. Spin speed versus photoresists thickness curves will be reviewed for all three wafer sizes.Additionally, two major coating uniformity factors, photoresist and cool plate temperature, will be studied for 200 mm and 300 mm wafers.

Crowell, Robert M.

1998-06-01

392

Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards. [Very Large Scale Integration (VLSI)  

SciTech Connect

This paper discusses the sensor-based driving of a car in a-priori unknown environments using human-like'' reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver's aid using the new fuzzy inferencing VLSI hardware and human-like'' reasoning schemes.

Pin, F.G.; Watanabe, Y.

1992-01-01

393

TOPICAL REVIEW: Wafer level packaging of MEMS  

NASA Astrophysics Data System (ADS)

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

Esashi, Masayoshi

2008-07-01

394

Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing  

Microsoft Academic Search

Semiconductor manufacturing involves lengthy and complex processes, and hence is capital intensive. Companies compete with each other by continuously employing new technologies, increasing yield, and reducing costs. Yield improvement is increasingly important as advanced fabrication technologies are complicated and interrelated. In particular, wafer bin maps (WBM) that present specific failure patterns provide crucial information to track the process problems in

Shao-Chung Hsu; Chen-Fu Chien

2007-01-01

395

A test methodology for wafer scale system  

Microsoft Academic Search

To efficiently access and control on-chip design for test (DFT) circuitry, a standard test interface is required. A uniform testing interface is defined for each functional cell, with built-in self-test incorporated whenever possible. Use of a standard interface will reduce test complexity and costs by allowing entire wafer probing by a common standardized probe card, irrespective of the number of

David L. Landis

1992-01-01

396

A W-band wafer probe  

Microsoft Academic Search

A W-band (75-110 GHz) wafer probe was successfully designed and built. The probe uses a ridge-trough waveguide as a transition from a rectangular waveguide input to the coplanar waveguide (CPW) used on the probe board output. Typical insertion loss and return loss figures were 3.5 dB and better than 13 dB, respectively. Losses were minimized in the CPW probe board

Edward M. Godshalk

1993-01-01

397

Wafer probing at W-band  

Microsoft Academic Search

A W-band (75-110 GHz) wafer probe is presented. The probe uses ridge-trough waveguide to transition from a rectangular waveguide input to coplanar waveguide used on the probe board output. Research was conducted on radiation loss and moding in coplanar waveguide to minimize insertion loss and maintain a coplanar mode. The probe is shown to work successfully and data is presented

Edward M. Godshalk

1993-01-01

398

3D EM Characterization of Wafer Probes  

Microsoft Academic Search

The following paper describes a method to characterize wafer probes using a 3D EM simulator. Rather than following the traditional method of building a custom test fixture for different probe setups and measuring the S-parameters, this 3D EM characterization method yields multi-port S-parameters of a specific probe structure by utilizing simulations. For a standard characterization, the S-parameters can be a

Hanyi Ding; Randy Wolf; John Ferrario

2001-01-01

399

New calibration simplifies MMIC wafer probing  

Microsoft Academic Search

MMAVERIC (MMIC Metrology with Automatic Verification in Time), a novel technique for performing wafer-probe calibration, is described. MMAVERIC flow graphs describe systematic errors in terms of power flow; errors arise from imperfections in response tracking, directivity, source and load matches, and isolation. One-port and two-port calibrations are discussed. It is noted that MMAVERIC is fast and requires very little hardware

H. B. Sequeira; M. W. Trippe; R. Jakhete

1988-01-01

400

A 5 Gbps Wafer-Level Tester  

Microsoft Academic Search

This paper describes an economical approach to highspeed testing of high-density wafer-level packaged logic devices. The solution assumes that the devices to be tested have built-in self-test features, thereby reducing the complexity of functional testing required. This also reduces the need for expensive automated test equipment (ATE). A stand alone miniature tester is developed and connected to the top of

A. M. Majid; David C. Keezer; J. V. Karia

2005-01-01

401

Infrared spectroscopy of bonded silicon wafers  

Microsoft Academic Search

Infrared spectra of multiple frustrated total internal reflection and transmission for silicon wafers obtained by direct bonding\\u000a in a wide temperature range (200–1100C) are studied. Properties of the silicon oxide layer buried at the interface are investigated\\u000a in relation to the annealing temperature. It is shown that the thickness of the SiO2 layer increases from 4.5 to 6.0 nm as

A. G. Milekhin; C. Himcinschi; M. Friedrich; K. Hiller; M. Wiemer; T. Gessner; S. Schulze; D. R. T. Zahn

2006-01-01

402

Etching methodologies in ?111?-oriented silicon wafers  

Microsoft Academic Search

New methodologies in anisotropic wet-chemical etching of ?111?-oriented silicon, allowing useful process designs combined with smart mask-to-crystal-orientation-alignment are presented in this paper. The described methods yield smooth surfaces as well as high-quality plan-parallel beams and membranes. With a combination of pre-etching and wall passivation, structures can be etched at different depths in a wafer. Designs, using the ?111?-crystal orientation, supplemented

R. Edwin Oosterbroek; J. W. Berenschot; H. V. Jansen; A. J. Nijdam; G. Pandraud; A. van den Berg; M. C. Elwenspoek

2000-01-01

403

Very high efficiency VLSI chip-pair for full search block matching with fractional precision  

Microsoft Academic Search

VLSI architecture design and implementation of a chip pair for the motion compensation full search block matching algorithm are described. This pair of ASICs (application-specific integrated circuits) is motivated by the intensive computational demands for performing motion compensation in real time. They have been developed to calculate fractional motion vectors with quarter-pel precision. The VLSI architecture is based on some

Kiln-Min Yang; M.-T. Sun; L. Wu; I-Fei G. Chifang

1989-01-01

404

Las Vegas is better than determinism in VLSI and distributed computing (Extended Abstract)  

Microsoft Academic Search

In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean

Kurt Mehlhorn; Erik Meineche Schmidt

1982-01-01

405

Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size  

NASA Astrophysics Data System (ADS)

For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

2013-06-01

406

Positive-tone wafer coating materials evaluation on lithography process  

NASA Astrophysics Data System (ADS)

The polyimide technology has bene used extensively for semiconductor industry, includes buffer coating, interlayer dielectric and passivation, Alpha ray shielding and protective/insulating films. The features of the polyimide material for the new generation of advanced semiconductor products must have excellent properties and high performances to meet various demands in the microelectronics application. The requirements include high resolution, low internal stress, process cost reduction, environment safety, excellent process stability and window in the future. Three kinds of heat-resistant base polymers had been widely applied on wafer-coating processing microelectronic device including polyamic acids, ring-closure type soluble polyimides with hydroxyl groups, and PBO precursors. In this work, we had evaluated positive-tone photosensitivity with aqueous developed polyimide consisting of previous base resins, and compared the difference of process conditions, cured-film properties, adhesion properties, etching recipes as one mask process and reliability test, etc.

Huang, D. F.; Chiou, Jian-Yuan; Hung, Chih-Chien; Young, B. R.

2001-05-01

407

Toshiba Review, Vol. 44, No. 10, 1989. Special Issue: Artificial Intelligence Technology.  

National Technical Information Service (NTIS)

The special issue on artificial intelligence technology features: VLSI chip for AI workstations; Highly-parallel AI machine; Knowledge base machine; Programming languages for AI; Neural networks and their applications; Image understanding; Speech recognit...

1989-01-01

408

A 3D-WLCSP package technology: Processing and reliability characterization  

Microsoft Academic Search

A new low cost 3 dimensional wafer level chip scale package (3D-WLCSP) technology that leverages the existing infrastructures of wafer level packaging and high volume flip chip assembly is presented. This paper provides an overview of the new 3D-WLCSP technology including flip chip on wafer bonding assembly technologies required to produce the 3D face to face flip chip on wafer

Paul Houston; Zhaozhi Li; Daniel F. Baldwin; Gene Stout; Ted Tessier

2008-01-01

409

Graphene for VLSI: FET and interconnect applications  

Microsoft Academic Search

Because of their remarkable physical properties, graphene should be one of the most important Emerging Research Materials (ERM) for not only the front-end but also back-end devices of VLSIs for the next decade. In this paper, we discuss the present status of their material technologies and some issues to be addressed for realizing graphene channels and wiring devices for a

Yuji Awano

2009-01-01

410

Transfer of semiconductor and oxide films by wafer bonding and layer cutting  

NASA Astrophysics Data System (ADS)

Material integration by wafer bonding and layer transfer is one of the main approaches to increase functionality of semiconductor devices and to enhance integrated circuits (IC) performance. Even though most mismatches such as different lattice constants betweeen bonding materials present no obstacle for wafer direct bonding, thermal stresses caused by thermal mismatches must be minimized by low temperature bonding to avoid debonding, sliding or cracking. In order to achieve a strong bond at low temperatures, two approaches may be adopted: 1) Bonding at room temperature by hydrogen bonding of OH, NH, or FH terminated surfaces followed by polymerization to form covalent bonds. Within this approach the key is to remove the by-products of the reaction at the bonding interface. 2) Direct formation of a covalent bond between clean surfaces without adsorbents in ultra high vacuum conditions. Low temperature bonding allows bonding processed wafers for technology integration. Layer transfer requires uniform thinning of one wafer of a bonded pair. The most promising technology involves a buried embrittled region by hydrogen implantation. A layer with a thickness corresponding to the hydrogen implantation depth is then transferred onto a bonded desired substrate by either splitting due to internal gas pressure or by forced peeling as long as the bonding energy is higher than the fracture energy in the embrittled region at the layer transfer temperature. This approach is quite generic in nature and may be applied to almost all materials. We have found that B+H co-implantation and/or H implantation at high temperatures can significantly lower the splitting temperature. However, the wafer temperature during H implantation has to be within a temperature window that is specific for each material. The experimentally determined temperature windows for some semiconductors and single crystalline oxides will be given.

Tong, Qin-Yi; Huang, Li-Juan; Gösele, Ulich M.

2000-07-01

411

Interferometric total thickness variation measurement of glass wafer  

NASA Astrophysics Data System (ADS)

Total thickness variation (TTV) is one of the important specifications of glass wafer. Glass wafers are thin and transparent parallel plates. In order to measure a flat surface by interferometer, at least one reference flat of same size is required. And the interference between two reflected wavefronts by the front and rear surfaces of the glass wafer also exists. Therefore interferometric measurements of thin glass wafers are not easy. So TTV is mainly measured not by interferometer, but by thickness gauge devices. But these devices measure only the TTV of several positions of glass wafer and don't measure the whole area. To measure the whole area or sufficient points, it requires more time. We developed a relatively simple and inexpensive interferometric TTV measurement method using Haidinger interferometer. This method can be applied to large glass wafers without large reference flat.

Song, Jae-Bong; Lee, Hoi-Youn; Lee, Yun-Woo; Lee, In-Won

2007-11-01

412

Waveguide probe tackles V-band on-wafer tests  

NASA Astrophysics Data System (ADS)

As millimeter-wave MMIC processes mature, requirements for manufacturing process control and product performance testing drive the need for V-band on-wafer testing. Semiconductor wafer probes for RF measurements are outlined, as well as commercial wafer probes based on the 1.85-mm coaxial connector supporting on-wafer device measurements up to 65 GHz. A waveguide architecture requiring the development of a waveguide-to-coplanar -waveguide (CPW) transmission to send test signals from a wafer of interest to an automatic vector network analyzer is suggested. Waveguide-to-CPW transition characteristics are assessed, and a commercial V-band wafer probe with ground-signal-ground contact configuration for low common-lead inductance is described. The probe's specified performance includes maximum insertion loss of 5 dB from 50 to 75 GHz.

Jones, Keith; Godshalk, Ed

1990-10-01

413

Low frequency noise spectroscopy of SOI wafers  

NASA Astrophysics Data System (ADS)

Low Frequency Noise (LFN) is important in analog and digital circuits. In analog circuits it affects the performance of low-noise amplifiers and the phase noise of voltage-controlled oscillators. In digital circuits it becomes more important as the supply voltage is reduced and it degrades substrate noise coupling. Low-frequency noise is due to interactions of the channel carriers with oxide/semiconductor interface traps and oxide charges. It is very dependent on the quality of the oxide/semiconductor interface and noise measurements can give important information about such interfaces and defects. Silicon-on-insulator Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have two oxide/semiconductor interfaces: the top interface between the gate oxide and the active silicon (Si) layer and the bottom interface between the buried oxide and the active Si layer. The bottom interface is generally worse than the top interface. Most LFN measurements are made after MOSFET fabrication, but it is desirable to characterize such materials without fabricating devices. In this thesis we discuss Silicon-On-Insulator (SOI) low-frequency noise and interface trap density measurements using a Ground-Signal-Ground (GSG) and circular pseudo MOSFET structure with minimum fabrication. The pseudo MOSFET (Psi-MOSFET) is a simple, yet powerful, device to characterize various aspects of SOI wafers and is routinely used for incoming wafer inspection to determine material parameters. This device comes in point contact and mercury probe (HgFET) configurations. The point-contact pseudo MOSFET simply requires two probes on an SOI wafer. However, the contact geometry is poorly defined leading to questions in the interpretation of the ID-VG data. The HgFET has the advantage of well-defined source/drain contacts, but it has an Hg/Si interface and all the vagaries that accompany metal/Si contacts, where barrier heights change with time due to surface state changes. For reproducible measurements we use deposited metal electrodes on the SOI wafer forming Schottky barrier source/drain contacts, and using the substrate as the gate. Two configurations of electrodes are proposed: the GSG arrangement and the circular pattern. Both designs allow performing of low frequency noise and frequency response measurements. This is the first time the pseudo MOSFET has been used for such measurements.

Kushner, Vadim

414

Wafer-scale charge isolation technique  

DOEpatents

An apparatus and method are described which improve the performance of charge-coupled devices (CCD) in the presence of ionizing radiation. The invention is a wafer scale charge isolation technique which inhibits or reduces the flow of electrons created by the passage of ionizing radiation in the bulk regions of a silicon CCD. The technique has been tested in a device designed for operating in the infra-red wavelength band. The technique prevents charge from reaching the active charge collection volume of a pixel in a CCD.

Colella, N.J.; Kimbrough, J.R.

1994-12-31

415

High-speed VLSI fuzzy processors designed for HEPE  

NASA Astrophysics Data System (ADS)

Neural chips now are used in the trigger devices for HEPE. Three years ago we talked the problem of using also fuzzy chip microprocessors because a fuzzy system in principle can work as a neural system and is more flexible. We made them a comparison between the two approaches and the conclusions were: fuzzy chips running at a speed suitable for trigger devices were not available on the market, therefore one should have to design his own VLSI chip while, for the neural solution, one can use commercial chips or design a dedicated VLSI chip; the fuzzy solution requires an expert to develop the fuzzy system, that is the rules, while the neural solution requires a training phase; the fuzzy solution is more flexible because you known its knowledge basis and you can improve on-line the related performances by changing the rules. To day this situation is improved because there are SW tools, called Rule Generators, able to develop a fuzzy system by means of Neural Network or Genetic Algorithms. This paper starts with a comparison between Neural Networks and Fuzzy Logic with the aim to summarize the advantages of using both the HEPE trigger devices, then are described the chips already constructed or designed: a first 1 micrometers VLSI fuzzy chip with four 7 bits input and one output running at 50 Mega Fuzzy Inference per Second therefore its processing rate depends upon the fuzzy system to process; a second one, which will be sent to the foundry next march with four 7 bit inputs running at a rate of 300 ns whichever is the fuzzy system; a third one, now in design phase, with 8 - 16 inputs running at 100 - 50 MFIPS with a rule selector to further reduce the total processing speed.

Gabrielli, Alessandro; Gandolfi, Enzo; Masetti, Massimo; Russo, Marco

1996-03-01

416

6W/25mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing  

NASA Astrophysics Data System (ADS)

Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6W/25mm2 power transfer density over a distance of up to 0.32mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits.

Radecki, Andrzej; Chung, Hayun; Yoshida, Yoichi; Miura, Noriyuki; Shidei, Tsunaaki; Ishikuro, Hiroki; Kuroda, Tadahiro

417

Microdisplay wafer-flatness metrology by optical interferometry  

Microsoft Academic Search

We report a microdisplay wafer-flatness metrology technique based on digital high-pass filtering of topography data obtained from a commercial optical interferometer. This technique dis- criminates against both wafer-scale bow\\/warp and pixel-scale roughness to reveal die-scale flatness variations that are the most relevant to microdisplay gap uniformity. We report flatness measurements of a variety of live and test silicon wafers supporting

Christopher M. Walker; Mark Handschy

2001-01-01

418

Cerebral edema associated with Gliadel wafers: Two case studies  

PubMed Central

While the introduction of carmustine wafers (Gliadel wafers) into the tumor resection cavity has been shown to be a beneficial therapy for malignant glioma, it is recognized that clinically significant cerebral edema is a potential adverse effect. Following are two clinical case reports demonstrating profound cerebral edema associated with implantation of Gliadel wafers. As a result, one of these individuals had premature death. A brief literature review is provided to assist in explaining the mechanisms by which clinically significant cerebral edema may develop.

Weber, Emil L.; Goebel, Eric A.

2005-01-01

419

A digital neuron-type processor and its VLSI design  

SciTech Connect

A set of neuron-type circuits elements based on logic gate circuits with multi-input capability is described. Three types of elements are introduced, one called the cell body with its dendritic inputs and synaptic junction, another representing the axon base and finally the axon circuit. These three elements are cascaded to form a neuron type processing element. The circuit performs input temporal and spatial summation as well as thresholding. The entire neuron circuit is simulated and a design is given using VLSI techniques.

Habib, M.K.; Akel, H. (Electrical and Computer Engineering Dept., Kuwait Univ., 13060 Safat (KW))

1989-05-01

420

A VLSI design of a pipeline Reed-Solomon decoder.  

PubMed

A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new coder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a RS code. PMID:11539661

Shao, H M; Truong, T K; Deutsch, L J; Yuen, J H; Reed, I S

1985-05-01

421

VLSI fast Fourier transform digital signal processor chip  

NASA Astrophysics Data System (ADS)

A high performance VLSI chip has been designed to perform the Fast Fourier Transform (FFT) used in digital signal processing systems. This Bendix proprietary, custom digital signal processor (DSP) chip performs a 128 Point FFT and has a wide range of avionics and aerospace applications ranging from radar to sonar systems. The chip employs a novel algorithm designed to efficiently implement the FFT with a minimum of hardware by eliminating all multiply operations while achieving high throughput rates. It executes both the Fast Fourier Transform and the Inverse Fast Fourier Transform which are powerful tools in frequency domain analysis.

Hutchinson, S. A.; Kagey, D. R.; Kantowski, J. W.; Miller, M. A.

422

Refractory metal gate processes for VLSI applications  

Microsoft Academic Search

The conventional n-channel silicon-gate MOS technology faces limitations due to poly-sheet resistance, patterning, and overall process compatibility as feature dimensions shrink and circuit sizes increase. This work describes an investigation of refractory metals as alternate gate material due to their potential advantages in terms of patternability, film sheet resistance that is 50 to 100 times lower comparable to polysilicon, and

PRADEEP L. SHAH

1979-01-01

423

Wafer-to-Wafer Bonding Techniques: From MEMS Packaging to IC Integration Applications  

Microsoft Academic Search

Device stacking and packaging on wafer-level plays a key role for the continuous miniaturization, expansion of functionality and reduction of production costs of MEMS and MCMs. The field of applications for integrated devices and MEMS is huge and the packaging requirements for the different systems are versatile. Driven by the automotive industry, extensive research and development in the field of

R. Pelzer; H. Kirchberger; P. Kettner

2005-01-01

424

Micro-miniature gas chromatograph column disposed in silicon wafers  

DOEpatents

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, Conrad M. (Antioch, CA)

2000-01-01

425

Micro-miniature gas chromatograph column disposed in silicon wafers  

SciTech Connect

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, C.M.

2000-05-30

426

Wide-band low-loss MEMS packaging technology  

Microsoft Academic Search

This paper presents a wafer scale low-loss and broad-band RF MEMS packaging technology developed at MIT Lincoln Laboratory. The fabrication includes CMOS compatible front-end processing and thick Au backend processing. Au thermo-compression bonding is used to mate a metal coated capping wafer to a device wafer, offering high-isolation and low-loss transmission lines within the cavity. Hermetic thru-wafer vias carry the

Jeremy Muldavin; Carl Bozler; Steve Rabe; Craig Keast

2005-01-01

427

Wafer-scale fabrication of magneto-photonic structures in Bismuth Iron Garnet thin film  

Microsoft Academic Search

In this paper we report on a reproducible technological process for wafer-scale fabrication of different photonic structures in Bismuth Iron Garnet (BIG: Bi3Fe5O12) thin films: two-dimensional magneto-photonic crystals (PhC), ring circulators, Bragg gratings or ridge waveguides. Different fabrication techniques such as Ion Beam Etching (IBE), Focused Ion Beam (FIB) etching, wet chemical etching and Reactive Ion etching are compared. The

L. Magdenko; E. Popova; M. Vanwolleghem; C. Pang; F. Fortuna; T. Maroutian; P. Beauvillain; N. Keller; B. Dagens

2010-01-01

428

A numerical study of fatigue life of copper column interconnections in wafer level packages  

Microsoft Academic Search

A copper column (CuC) interconnect technology is proposed in the nano wafer level packaging program as a chip-to-substrate interconnect solution for 20 mm by 20 mm package with 100 ?m pitch. Currently thermo-mechanical reliability of solder joint continues to be a major concern due to the CTE (coefficient of thermal expansion) mismatch between chip and substrate A FEA (finite element

Wei Sun; A. A. O. Tay; S. Vedantam

2004-01-01

429

A novel approach: high resolution inspection with wafer plane defect detection  

Microsoft Academic Search

High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yield-limiting mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newly-developed Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask

Carl Hess; Mark Wihl; Rui-fang Shi; Yalin Xiong; Song Pang

2008-01-01

430

Packaged photonic probes for an on-wafer broad-band millimeter-wave network analyzer  

Microsoft Academic Search

We report the fabrication of integrated and packaged active photonic probes that enable on-wafer measurements of electrical scattering parameters with a bandwidth exceeding 300 GHz. The probes use a high-speed uni-traveling-carrier photodiode (UTC-PD) to optically generate the electrical stimulus and the electro-optic sampling (EOS) technique to measure the electrical signals. The modules are packaged using micro-optic technology and exhibit excellent

Nabil Sahri; Tadao Nagatsuma

2000-01-01

431

Modeling and Simulation of Spiral Inductors in Wafer Level Packaged RF\\/Wireless Chips  

Microsoft Academic Search

In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP)RF\\/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic)simulations. The performance of spiral inductors fabricated with various geometrical and technological parameterswas analyzed. It is shown that Q (the quality factor) and fres (theself-resonance frequency) could be improved by using the thick insulator layer and thick\\/wide metal line,which are fabricated by

Xinzhong Duo; Li-Rong Zheng; Hannu Tenhunen

2003-01-01

432

Mechanisms for room temperature direct wafer bonding  

NASA Astrophysics Data System (ADS)

Reducing the temperature needed for high strength bonding which was and is driven by the need to reduce effects of coefficient of thermal expansion mismatch, reduce thermal budgets, and increase throughput has led to the development of plasma treatment procedures capable of bonding Si wafers below 300 °C with a bond strength equivalent to Si bulk. Despite being widely used, the physical and chemical mechanisms enabling low temperature wafer bonding have remained poorly understood. We developed an understanding of the beneficial surface modifications by plasma and a model based on short range low temperature diffusion through bonding experiments combined with results from spectroscopic ellipsometry, depth resolving Auger electron spectroscopy, and transmission electron microscopy measurements. We also present experimental results showing that even at room temperature reasonable bond strength can be achieved. We conclude that the gap closing mechanism is therefore a process which balances the lowering of the total energy by minimizing the sum of the free surface energy (maximizing the contact area between the surfaces) and strain energy in the oxide at the bond interface.

Plach, T.; Hingerl, K.; Tollabimazraehno, S.; Hesser, G.; Dragoi, V.; Wimplinger, M.

2013-03-01

433

Low-temperature thin-film indium bonding for reliable wafer-level hermetic MEMS packaging  

NASA Astrophysics Data System (ADS)

This paper reports on low-temperature and hermetic thin-film indium bonding for wafer-level encapsulation and packaging of delicate and temperature sensitive devices. This indium-bonding technology enables bonding of surface materials commonly used in MEMS technology. The temperature is kept below 140?°C for all process steps and no surface treatment is applied before and during bonding. This bonding technology allows hermetic sealing at 140?°C with a leak rate below 4?×?10?12?mbar l s?1 at room temperature. The tensile strength of the bonds up to 25 MPa goes along with a very high yield.

Straessle, R.; Pétremand, Y.; Briand, D.; Dadras, M.; de Rooij, N. F.

2013-07-01

434

Through silicon vias technology for CMOS image sensors packaging  

Microsoft Academic Search

In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. The design rules of the vias will be briefly described and then, the steps of the technology will be presented : glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific

D. Henry; F. Jacquet; M. Neyret; X. Baillin; T. Enot; V. Lapras; C. Brunet-Manquat; J. Charbonnier; B. Aventurier; N. Sillon

2008-01-01

435

Efficient parallel algorithms and VLSI architectures for manipulator Jacobian computation  

SciTech Connect

The real-time computation of manipulator Jacobian that relates the manipulator joint velocities to the linear and angular velocities of the manipulator end-effector is pursued. Since the Jacobian can be expressed in the form of the first-order linear recurrence, the time lower bound to complete the Jacobian can be proved to be of order O(N) on uniprocessor computers, and of order O(log{sub 2}N) on both parallel single-instruction-stream multiple-data-stream (SIMD) computers and parallel VLSI pipelines, where N is the number of links of the manipulator. To achieve the computation time lower bound, we developed the generalized-k method on uniprocessor computers, the parallel forward and backward recursive doubling algorithm (PFABRD) on SIMD computers, and a parallel systolic architecture on VLSI pipelines. All the methods are capable of computing the Jacobian at any desired reference coordinate frame k from the base coordinate frame to the end-effector coordinate frame. The computation effort in terms of floating point operations is minimal when k is in the range (4, N {minus} 3) for the generalized-k method, and k = (N + 1)/2 for both the PFABRD algorithm and the parallel pipeline.

Yeung, T.B. (LSI Logic Corp., Milpitas, CA (US)); Lee, C.S.G. (Of Electrical Enginerring, Purdue Univ., West Lafayette, IN (US))

1989-09-01

436

Photonic VLSI for on-chip computing architectures  

NASA Astrophysics Data System (ADS)

In this paper, we demonstrate the feasibility of using on-chip optoelectronics within VLSI systems to address a wide range of signal distribution issues by examining the following fundamental question: how can we transmit information from one source to many destinations while minimizing propagation delay, skew, jitter, and noise in a way that is compatible with low-cost manufacturing and CMOS circuits? Example systems with such information distribution requirements include banked arrayable memories such as a DRAM or a dense imager with scanned high speed readout, or a clock distribution system. In all instances individual lines are typically connnected to thousands of gates, slowing cell access times and generating skew. We demonstrate how the use of on-chip photonics within VLSI systems can reduce delays introduced by electrical wires in system-on-a-chip interconnects, busses, caches, and control lines at distances shorter than one meter and as short as a few millimeters. We also describe and demonstrate how a simple on-chip optoelectronic system addressing these problems can be realized at low cost, with monolithic photodetectors and on-chip waveguides in a commercial CMOS process, benefiting both ultra-short and one meter link architectures. This unexplored signal distribution architecture promises high optical to electrical efficiency, low noise, and the benefits of monolithic photodetection not previously achieved in existing approaches.

Apsel, Alyssa B.; Yin, Tao; Pappu, Anand M.

2004-10-01

437

Orientation-selective aVLSI spiking neurons.  

PubMed

We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC microcontroller, and a transceiver chip whose integrate-and-fire neurons are connected in a soft winner-take-all architecture. The circuit on this multi-neuron chip approximates a cortical microcircuit. The neurons can be configured for different computational properties by the virtual connections of a selected set of pixels on the silicon retina. The virtual wiring between the different chips is effected by an event-driven communication protocol that uses asynchronous digital pulses, similar to spikes in a neuronal system. We used the multi-chip spike-based system to synthesize orientation-tuned neurons using both a feedforward model and a feedback model. The performance of our analog hardware spiking model matched the experimental observations and digital simulations of continuous-valued neurons. The multi-chip VLSI system has advantages over computer neuronal models in that it is real-time, and the computational time does not scale with the size of the neuronal network. PMID:11665759

Liu, S C; Kramer, J; Indiveri, G; Delbrück, T; Burg, T; Douglas, R

438

A Cost-Effective Production DC\\/RF On-Wafer GaAs FET Measurement System  

Microsoft Academic Search

This paper describes a cost-effective DC and microwave test system for production screening of discrete and process-monitor GaAs FETs. Topics covered include system hardware, test software and data storage, DC error-correction, RF GaAs FET modeling, RF probe card technology, error-correction for common-mode inductance, and on-wafer calibration.

Eric S. Copeland; Matthew Borg; Kevin J. Kerwin

1989-01-01

439

Surface-Defect Detection System for Patterned Wafers.  

National Technical Information Service (NTIS)

A high-speed, highly sensitive surface-defect detection system for semiconductor patterned wafers suitable for use in factory environments has been developed. The system detects submicron surface defects and inspects a six-inch wafer in 30min. The system ...

H. Tanaka T. Oshige Y. Miyazaki H. Ichimura T. Tomoda

1990-01-01

440

Wafer back side inspection applications for yield protection and enhancement  

Microsoft Academic Search

Semiconductor manufacturers employ various techniques and tools to detect and identify the physical defects that limit product and process yields. Most of these techniques focus on measuring the front side of the semiconductor wafer where the devices are manufactured. Attention to defectivity on the wafer backside has been minimal. Two possible reasons are the lack of suitable equipment and methods,

Lesley A. Cheema; Leonard J. Olmer; Oliver D. Patterson; S. S. Lopez; M. B. Burns

2002-01-01

441

500 GHz GaAs MMIC sampling wafer probe  

Microsoft Academic Search

A 500 GHz bandwidth GaAs MMIC sampling wafer probe is reported which incorporates a mechanical flexure and a micromachined GaAs IC for time domain on-wafer measurements. The GaAs IC incorporates a novel high speed pulse sharpener and a two-diode sampling bridge with a micromachined GaAs tip.

M. S. Shakouri; A. Black; B. A. Auld; D. M. Bloom

1993-01-01

442

100 GHz wafer probes based on photoconductive sampling  

Microsoft Academic Search

The authors fabricated optoelectronic wafer probes with both free-space and fiber-optic input, and they adapted microwave error correction techniques to allow calibrated measurements with the new probes. Photoconductive switches on the probe tip define stimulus pulses and sampling intervals, and signals are transferred to and from the wafer under test by coplanar waveguide transmission lines and plated contact bumps. Vector

M. D. Feuer; S. C. Shunk; P. R. Smith; M. C. Nuss; N. H. Law

1993-01-01

443

Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint  

SciTech Connect

This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

Rupnowski, P.; Sopori, B.

2008-05-01

444

Alternative facility layouts for semiconductor wafer fabrication facilities  

Microsoft Academic Search

Semiconductor wafer fabrication facilities are widely acknowledged to be among the most complicated industrial systems from a production planning and control point of view. The design of most wafer fabrication facilities has followed the process layout, where similar machines are located together. This feeds to complex, reentrant product flows through the facility. In this paper, we examine the effects on

Christopher D. Geiger; Rieko Hase; Christos G. Takoudis; Reha Uzsoy

1997-01-01

445

P/N Inp Solar Cells on Ge Wafers.  

National Technical Information Service (NTIS)

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick ...

S. Wojtczuk S. Vernon E. A. Burke

1994-01-01

446

Development of wafer bonded vertical cavity surface emitting lasers  

Microsoft Academic Search

This thesis describes the development of wafer bonded vertical cavity surface emitting lasers. By employing a reactive low temperature bonding technique, we have successfully demonstrated oxide-defined 850 nm vertical- cavity surface-emitting lasers (VCSELs) on silicon substrates. In this dissertation the design, fabrication, characterization, and applications of wafer bonded vertical cavity surface emitting lasers have been studied. The reactive low temperature

Yanyan Xiong

2001-01-01

447

Height Inspection of Wafer Bumps Without Explicit 3-D Reconstruction  

Microsoft Academic Search

Die bonding in the semiconductor industry requires placement of solder bumps not on PCBs but on wafers. Such wafer bumps, which are much miniaturized from their counterparts on printed circuit boards (PCBs), require their heights meet rigid specifications. Yet the small size, the lack of texture, and the mirror-like nature of the bump surface make the inspection task a challenge.

Mei Dong; Ronald Chung; Edmund Y. Lam; Kenneth S. M. Fung

2010-01-01

448

A Model for the Silicon Wafer Bonding Process  

Microsoft Academic Search

The bonding speed (or contact wave velocity) of silicon and fused quartz wafers has been measured as a function of temperature. The results show that the bonding process stops to operate at temperatures above 90°C and 320°C for fused quartz and bare silicon wafers, respectively. By comparing our results to infrared spectra obtained from silica gel we develop a tentative

R. Stengl; T. Tan; U. Gösele

1989-01-01

449

Design of sealed cavity microstructures formed by silicon wafer bonding  

Microsoft Academic Search

Three fabrication issues related to the design and fabrication of micromechanical devices using sealed cavities within bonded silicon wafers are discussed. The first concerns the resultant residual gas pressure within a sealed cavity between two bonded wafers after bonding and a high-temperature anneal. The second concerns the prediction of plastic deformation in capping layers of single-crystal silicon over sealed cavities.

Michael A. Huff; Alex D. Nikolich; Martin A. Schmidt

1993-01-01

450

Light scatter from defects on chemically-mechanically polished wafers  

Microsoft Academic Search

Detection and reduction of defects on chemically-mechanically polished (CMP) wafers are important concerns in semiconductor manufacturing. The physical and light scattering characteristics of typical CMP wafer surface defects including roughness, dishing, particles, and scratches are investigated in this dissertation. A new scatterometer is developed for the light scattering study. The system measured \\

Ping Ding

2000-01-01

451

LSI\\/VLSI ion implanted GaAs IC processing  

Microsoft Academic Search

During this reporting period, growth of low dislocation GaAs crystals by the horizontal Bridgman method is reported. LEC semi-insulating substrate material from a commercial supplier of 3 inch diameter wafers was evaluated finding that three out of four ingots passed the qualification tests. The major process activities centered on the testing of processing equipment before the start of the 3

R. Zucca; A. Fistenberg

1983-01-01

452

Reduction of Thermal Conductivity in Wafer-Bonded Silicon  

SciTech Connect

Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

2006-11-27

453

Wafer scale synthesis of bilayer graphene film  

NASA Astrophysics Data System (ADS)

The discovery of electric field induced bandgap opening in bilayer graphene paves the way for making semiconducting graphene without aggressive size scaling, or using expensive substrates. Despite intensive research, synthesizing homogeneous bilayer graphene in large size has proven extremely challenging, and the size of bilayer graphene was limited to micrometer scale by exfoliation Here we demonstrate homogeneous bilayer graphene films over at least square inch area, synthesized by chemical vapor deposition on copper foil and subsequently transferred to arbitrary substrates. Bilayer coverage of over 99% is confirmed by spatially resolved Raman spectroscopy. The result is further supported by electrical transport measurements on bilayer graphene transistors with dual-gate configuration, where field induced bandgap opening is observed in 98% of the devices. The size of our bilayer graphene film is only limited by the synthesis apparatus and can be readily scaled up, thus enabling wafer scale graphene electronics and photonics.

Lee, Kyunghoon; Lee, Seunghyun; Zhong, Zhaohui

2011-03-01

454

Technology trends in microcomputer control of electrical machines  

Microsoft Academic Search

A comprehensive review of technology trends in microcomputer control of electrical machines is presented. Although microcomputer control and computer-aided design techniques are the main themes of discussion, motion control as multidisciplinary technology has been reviewed in the broad perspective of electrical machines, power semiconductor devices, converter technology, microcomputers, and VLSI circuits. The concepts discussed are valid not only for small

B. K. Bose

1988-01-01

455

Reliability-Driven CAD System for Deep-Submicron VLSI Circuits.  

National Technical Information Service (NTIS)

This report describes the development of a hierarchical reliability- driven CAD system for deep-submicron VLSI/ULSI circuits. Three general issues are addressed in this report: layout extraction, circuit simulation, and experiment. Conventional layout ext...

S. M. Kang E. Rosenbaum Y. K. Cheng L. P. Yuan T. Li

1998-01-01

456

Performance of VLSI (Very Large Scale Integration) Engines for Lattice Computations,  

National Technical Information Service (NTIS)

We address the problem of designing and building efficient custom VLSI-based processors to do computations on large multi-dimensional lattices. The design tradeoffs for two architectures which provide practical engines for lattice updates are derived and ...

K. Steiglitz R. Squier S. D. Kugelmass

1987-01-01

457

High density and through wafer copper interconnections and solder bumps for MEMS wafer-level packaging  

Microsoft Academic Search

This paper proposes an innovative process combining the electroforming of high-density and through-wafer copper interconnections and solder bumps for advanced MEMS packaging. Vias with the diameter of 30 to 100 ?m were etched through on a 4-inch and 550 ?m-thick silicon substrate by ICP-DRIE process for an aspect ratio up to 18.3. MRTV1 silicon rubber layer was employed for substrates

C.-J. Lin; M.-T. Lin; S.-P. Wu; F.-G. Tseng

2004-01-01

458

Bubble-Free Silicon Wafer Bonding in a Non-Cleanroom Environment  

Microsoft Academic Search

Bubble-free bonding of 4-inch silicon wafers on either silicon or quartz wafers is achieved outside a cleanroom. Two wafers are stacked horizontally in a rack with the two mirror-polished surfaces facing each other. In order to avoid wafer contact during hydrophilization, cleaning, and drying, the wafers are separated in the rack by teflon spacers introduced at the wafer edges. After

R. Stengl; K.-Y. Ahn; U. Gösele

1988-01-01

459

Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits  

Microsoft Academic Search

Scaling the minimum feature size of VLSI circuits to sub-quar- ter micron and the clock frequency to 2GHz has caused the crosstalk noise to become a serious problem, degrading the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI cir- cuits. In particular, we provide closed-form

Payam Heydari; Massoud Pedram

2001-01-01

460

Weight perturbation: an optimal architecture and learning technique for analog VLSI feedforward and recurrent multilayer networks  

Microsoft Academic Search

Previous work on analog VLSI implementation of multilayer perceptrons with on-chip learning has mainly targeted the implementation of algorithms such as back-propagation. Although back-propagation is efficient, its implementation in analog VLSI requires excessive computational hardware. It is shown that using gradient descent with direct approximation of the gradient instead of back-propagation is more economical for parallel analog implementations. It is

Marwan Jabri; Barry Flower

1992-01-01

461

200-mm GaN-on-Si Based Blue Light-Emitting Diode Wafer with High Emission Uniformity  

NASA Astrophysics Data System (ADS)

We investigated the emission wavelength uniformity of 200-mm GaN-on-Si based blue light-emitting diode (LED) wafer grown by metalorganic vapor phase epitaxy (MOVPE). The larger the Si substrate diameter becomes, the more difficult to obtain uniform distribution of the emission wavelength because of the larger bow during growth, resulting in larger on-wafer inhomogeneity in growth temperature. Owing to the GaN-on-Si buffer strain management, optimized gas flow condition, and precise control of temperature balance in a reactor, we have achieved high thickness and crystal quality uniformity over the 200-mm GaN-on-Si based blue LED wafer. As a result, excellent blue photoluminescence emission wavelength uniformity from the InGaN-multi-quantum wells can be demonstrated on a 200-mm wafer with a standard deviation of 2.53 nm (0.57%). Less wavelengths binning with these highly uniform emission over the 200-mm wafer show the capability of sustainable cost reduction in LED fabrication based on GaN-on-Si technology.

Nishikawa, Atsushi; Groh, Lars; Solari, William; Lutgen, Stephan

2013-08-01

462

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

463

1.55 ?m hybrid waveguide laser made by ion-exchange and wafer bonding  

NASA Astrophysics Data System (ADS)

Distributed Feed Back (DFB) lasers working in the third telecom window are essential for optical communications, eyesafe sensors and lab-on-chip devices. Glass integrated optics technology allows realizing such devices by using rareearth doped substrates. Despite their good output power and spectral characteristic, DFB lasers still present some reliability issues concerning the Bragg grating protection. Moreover Erbium doped glasses are not compatible with the realization of passive optical functions. In order to solve the DFB lasers reliability issues and to ensure a monolithic integration between active and passive functions, we propose an hybrid-device architecture based on ion-exchange technology and wafer bonding. The Ag+/Na+ ion-exchange in the silicate glass wafer is used to realize the passive functions and the lateral confinement of the electromagnetic field. Through a second ion exchange step, a slab waveguide is made on the Erbium-Ytterbium doped glass wafer. The Bragg grating is processed on the passive substrate and the two glasses are bonded. The potential of this structure has been demonstrated through the realization of a DFB hybrid laser with a fully encapsulated Bragg grating.

Casale, Marco; Bucci, Davide; Bastard, Lionel; Broquin, Jean-Emmanuel

2012-02-01

464

Knowledge-based synthesis of custom VLSI router software. [Very Large Scale Integration  

SciTech Connect

This thesis describes a synthesis architecture for automatic generation of technology-sensitive VLSI physical design tools from high-level specifications. Physical design refers to the process of reducing a structural description of a piece of hardwater down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The author argues that the appropriate place for technology-dependent information is not in the run-time environment of such tools, but in a generator for these tools. They describe a synthesis architecture and its prototype implementation - called ELF - that integrates knowledge of the application domain with knowledge of generic programming mechanics. ELF strives to meet the demands of the target technology by automatically generating an implementation of the tool to match the application requirements. The ELF synthesis architecture has three key features. First, a very high level language, lacking data structure implementation specifications, is used to describe algorithm design styles. Second, application domain knowledge and generic program synthesis knowledge are used to guide search among candidate design styles for all necessary component algorithms, and to deduce compatible data structure implementations for these components. Third, code generation is used to transform the resulting abstract descriptions of selected algorithms and data structures into final, executable code. Code generation is an incremental, stepwise refinement process, and also relies on application domain knowledge, as well as generic program synthesis knowledge. A wide variety of fully-functional routers has been synthesized by ELF, and verified on both synthetic and industrial routing benchmarks. ELF demonstrates a synthesis architecture that efficiently generates router software using router domain-specific and generic program synthesis knowledge as a synthesis guide.

Setliff, D.E.

1989-01-01

465

Study of temperature distributions in wafer exposure process  

NASA Astrophysics Data System (ADS)

During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

Lin, Zone-Ching; Wu, Wen-Jang

466

A novel VLSI architecture for pixel purity index algorithm  

NASA Astrophysics Data System (ADS)

The Pixel Purity Index (PPI) algorithm is one of the most successful algorithms for hyperspectral image endmembers extraction. But it has high computational complexity so it is hard to meet the real-time processing demands of some onboard application. In this paper, we present a novel Very-Large-Scale Integration (VLSI) architecture for PPI algorithm to meet the on-board demands. With parallelism and improved I/O communication strategy, our implementation is significantly time saving than other architectures in the same hardware resources. We evaluate our implementation using the well-known "Cuprite" scene and assess endmembers signature purity using the U.S. Geological Survey (USGS) library. It demonstrates that our hardware implementation can get endmembers in less processing time to meet the onboard demands.

Yi, Fang; Guo, Jie; Li, Yunsong; Huang, Bormin

2013-09-01

467

Efficient VLSI architecture for training radial basis function networks.  

PubMed

This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

Fan, Zhe-Cheng; Hwang, Wen-Jyi

2013-03-19

468

A laser plotting system for VLSI chip layouts  

NASA Astrophysics Data System (ADS)

One of the most time consuming facets of custom Very Large Scale Integration (VLSI) design is obtaining hardcopy plots of the mask geometries of cells and chips. The traditional method of generating these plots is to use a multicolor pen plotter. Pen plotters are inherently slow and the plotting speed increases linearly with the number of edges that must be plotted. A moderate custom chip design at the Jet Propulsion Laboratory (JPL) now consists of more than 200,000 such edges and can take as much as eight hours to plot using a pen plotter. Software is described that was written at JPL to produce similar plots using a laser printer. It is shown that, for rather small layouts, the laser printer can provide nearly instantaneous turnaround. For moderate to large chip designs, the laser printer provides a factor of five or more improvement is speed over pen plotting.

Deutsch, L. J.; Harding, J. A.

1985-11-01

469

Efficient VLSI architecture for block-matching motion estimation  

NASA Astrophysics Data System (ADS)

Motion estimation reduces temporal redundancies in a video sequence, and becomes the most demanding part in video source encoders where motion compensated transform coding method is used. Block matching algorithm needs a large amount of computational load, but its regular data flow structure is good to implement with various parallel processing architectures. In this paper, we present a new VLSI architecture for block matching motion estimation in video encoding systems. The proposed architecture is based on linear systolic arrays. The proposed architecture has (1) fully pipelining operation which achieves 100 percent efficiency of processing elements, (2) efficient data input scheme for high input-rate video encoding systems, (3) glueless interfaces for easy extension of search range by cascaded multiple chip connections, (4) very regular and modular structure which is good to ASIC implementation.

Lee, Hankyu; Kim, Jinwoong; Ohk, Youngmi; Lee, Kangwhan

1996-09-01

470

Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System  

PubMed Central

Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L.; Wennekers, Thomas; Chicca, Elisabetta

2011-01-01

471

AlN wafers fabricated by hydride vapor phase epitaxy  

SciTech Connect

The authors report on AlN wafers fabricated by hydride vapor phase epitaxy (HVPE). AlN thick layers were grown on Si substrates by HVPE. Growth rate was up to 60 microns per hour. After the growth of AlN layers, initial substrates were removed resulting in free-standing AlN wafers. The maximum thickness of AlN layer was about 1 mm. AlN free-standing single crystal wafers with a thickness ranging from 0.05 to 0.8 mm were studied by x-ray diffraction, transmission electron microscopy, optical absorption, and cathodoluminescence.

Nikolaev, A.; Nikitina, I.; Zubrilov, A.; Mynbaeva, M.; Melnik, Y.; Dmitriev, V.

2000-07-01

472

Investigation of Surface Integrity in the Case of Chemical Mechanical Polishing Silicon Wafer by Molecular Dynamics Simulation Method  

Microsoft Academic Search

\\u000a With the development of semiconductor industry, the chemical mechanical polishing technology has already become the mainstream\\u000a method of realizing the surface global flatness. In order to understanding physical essence underlying this technology, the\\u000a author carried out nanometer polishing experiment of silicon wafer using molecular dynamics (MD) simulation method. The simulation\\u000a result shows that using larger slurry grain can generate much

Xuesong Han

2006-01-01

473

A 5 mm ×5 mm ×1.37 mm hermetic FBAR duplexer for PCS handsets with wafer-scale packaging  

Microsoft Academic Search

We describe the design and measured performance of a 5 mm ×5 mm ×1.37 mm antenna duplexer for the U.S. PCS band (Tx: 1850-1910 MHz, Rx: 1930-1990 MHz) for cellular handsets based on FBAR (film acoustic resonator) technology. The FBARs are fabricated in a silicon-based IC process technology and are hermetically sealed in a wafer-level packaging process. Two dice, Tx

P. D. Bradley; R. Ruby; A. Barfknecht; F. Geefay; C. Han; G. Gan; Y. Oshmyansky

2002-01-01

474

Closed-loop job release control for VLSI circuit manufacturing  

Microsoft Academic Search

A closed-loop job release mechanism for job shops where the main source of randomness is due to machine failure and repair is introduced. The release policy adapts concepts of the reorder-point method of inventory control to the context of job-shop scheduling. The control mechanism, called starvation avoidance, is compared empirically with other input control mechanisms on several semiconductor wafer manufacturing

C. Roger Glassey; Mauricio G. C. Resende

1988-01-01

475

Analytic modeling, optimization, and realization of cooling devices in silicon technology  

Microsoft Academic Search

A novel cooling device fully built in silicon technology is presented. The new concept developed in this work consists of micromachining the bottom side of the circuit wafer in order to embed heat sinking microchannels directly into the silicon material. These microchannels are then sealed, by a direct wafer bonding procedure, with another silicon wafer where microchannels and inlet-outlet nozzles

Corinne Perret; Jumana Boussey; Christian Schaeffer; Martin Coyaud

2000-01-01

476

Cohesive zone model for direct silicon wafer bonding  

NASA Astrophysics Data System (ADS)

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Kubair, D. V.; Spearing, S. M.

2007-05-01

477

Analysis of wafer stresses during millisecond thermal processing  

SciTech Connect

A flash lamp has been used to uniformly anneal large wafers with diameters approaching 100 mm. The equipment applies a pulse, with duration of 3-20 ms, resulting in large transient thermal gradients in the wafer. In this paper, we present separate models of the thermal reaction of this process and its effect upon the mechanical behavior, in order to predict stresses and shape changes, and to capture practical phenomenon. We further use the model to follow changes in the expected response consequent on altering process conditions, such as preheating and pulse duration, as well as exploring important issues associated with scaling to large wafer sizes. This work presents an initial description of the thermomechanical response of wafers to flash lamp annealing in the millisecond time regime and is therefore fundamental to the use of this technique in the fabrication of semiconductor devices.

Smith, M. P.; Seffen, K. A.; McMahon, R. A.; Voelskow, M.; Skorupa, W. [Department of Engineering, University of Cambridge, Trumpington Street, Cambridge CB2 1PZ (United Kingdom); Forschungszentrum Rossendorf, P.O. Box 510119, D-01314 Dresden (Germany)

2006-09-15

478

Efficient data transmission from silicon wafer strip detectors  

SciTech Connect

An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

1991-01-01

479

Efficient data transmission from silicon wafer strip detectors  

SciTech Connect

An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

1991-12-31

480

Partitioning and Redundancy Model for Wafer-Scale Integrated Circuits.  

National Technical Information Service (NTIS)

A general, architecture independent model to calculate the required amount of redundancy and the necessary degree of partitioning of the circuit to achieve a maximum efficiency are presented. In wafer scale integration, a certain amount of redundancy is r...

M. F. Beusekamp

1991-01-01

481

An innovative platform for high-throughput high-accuracy lithography using a single wafer stage  

NASA Astrophysics Data System (ADS)

For 32 nm half-pitch node, double patterning is recognized as the most promising technology since some significant obstacles still remain in EUV in terms of technology and cost. This means much higher productivity and overlay performance will be required for lithography tools. This paper shows the technical features of Nikon's new immersion tool, NSR-S620 based on newly developed platform "StreamlignTM" designed for 2nm overlay, 200wph throughput and 2week setup time. The S620 is built basically upon Nikon's Tandem Stage and Local Fill Nozzle technology, but has several additional features. For excellent overlay, laser encoders with short optical path are applied for wafer stage measurement in addition to interferometers. By using this hybrid metrology, the non-linearity of the encoder scale can be easily calibrated, while eliminating the air fluctuation error of interferometer. For high throughput, a method with a new alignment microscope system and a new auto focus mapping, called Stream Alignment is introduced. It makes it possible to reduce the overhead time between the exposures remarkably. The target productivity is 4,000 wafer outs per day. Accuracy is also improved because many more alignment points and a continuous wafer height map without stitching are available. Higher acceleration and faster scan velocity of the stages are also achieved by optimal vibration dynamics design and new control system. The main body, including the projection lens, is isolated by Sky Hook Technology used already on the NSR-SF150 and SF155 steppers, and also the reticle stage is mechanically isolated from the main body. With this new platform, the imaging performance can be maximized.

Shibazaki, Yuichi; Kohno, Hirotaka; Hamatani, Masato

2009-03-01

482

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

483

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

484