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1

Overlay Tolerances For VLSI Using Wafer Steppers  

NASA Astrophysics Data System (ADS)

In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

Levinson, Harry J.; Rice, Rory

1988-01-01

2

A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers  

Microsoft Academic Search

As the VLSI manufacturing technology advances into the deep sub-micron (DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put different dies onto the same set of masks is a good cost-sharing approach. Every design needs to be produced by its desired technology process, such as 1 poly with 4 metal layers

Chien-Chang Chen; Wai-Kei Mak

2006-01-01

3

A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers  

Microsoft Academic Search

As the VLSI manufacturing technology advances into the deep sub-micron(DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put different dies onto the same set of masks is a good cost-sharing approach. Every design needs to be produced by its desired technology process, such as 1 poly with 4 metal layers (1P4M),

Chien-chang Chen; Wai-kei Mak

2006-01-01

4

The evolution of silicon wafer cleaning technology  

Microsoft Academic Search

The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as RCA Standard Clean. This is still the primary method used in the industry. What

Werner Kern

1990-01-01

5

A robust production control policy for VLSI wafer fabrication  

Microsoft Academic Search

The authors present control policy for shop-level scheduling in a semiconductor wafer fabrication facility. The policy is designed to reduce the work in process in the shop floor and to follow the production plan as closely as possible. It is also robust against random interference such as machine breakdowns. The flow rate control policy is compared with two other approaches

SHELDON X. C. LOU; PATRICK W. KAGER

1989-01-01

6

Wafer level reliability for high-performance VLSI design  

NASA Technical Reports Server (NTRS)

As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

Root, Bryan J.; Seefeldt, James D.

1987-01-01

7

LSA project perspective of wafering technology  

NASA Technical Reports Server (NTRS)

The economics and techniques for eliminating wafering as a part of ingot technology in the production of silicon sheets for photovoltaic applications are considered. Technical progress in both ingot and non-ingot technologies for the low cost solar array project is described in the context of process economics. The critical areas of research in wafering are delineated and their payoff potential discussed.

Koliwad, K. M.

1982-01-01

8

VLSI architecture  

SciTech Connect

This book is a collection of course papers which discusses the latest (1982) milestone of electronic building blocks and its effect on computer architecture. Contributions range from selecting a VLSI process technology to Japan's Fifth Generation Computer Architecture. Contents, abridged: VLSI and machine architecture. Graphic design aids: HED and FATFREDDY. On the LUCIFER system. Clocking of VLSI circuits. Decentralised computer architectures for VLSI. Index.

Randell, B.; Treleaven, P.C.

1983-01-01

9

Impact of Deep Submicron Technology on Dependability of VLSI Circuits  

Microsoft Academic Search

Advances in semiconductor technology have led to impressive performance gains of VLSI circuits, in general, and microprocessors, in particular. However, smaller transistor and interconnect dimensions, lower power voltages, and higher operating frequencies have contributed to increased rates of occurrence of transient and intermittent faults. We address the impact of deep submicron technology on permanent, transient and intermittent classes of faults,

Cristian Constantinescu

2002-01-01

10

GaAs VLSI technology and circuit elements for DSP  

NASA Astrophysics Data System (ADS)

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Mikkelson, James M.

1990-10-01

11

Deep sub-micron stud-via technology of superconductor VLSI circuits  

NASA Astrophysics Data System (ADS)

A fabrication process has been developed for fully planarized Nb-based superconducting interlayer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of etched contact holes in the interlayer dielectric it employs etched and planarized Nb pillars (studs) as connectors between adjacent wiring layers. Detailed results are presented for one version of the process that utilizes Nb/Al/Nb trilayers for each wiring layer instead of single Nb wiring layers. Nb studs are etched in the top layer of the trilayer to provide vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A ?m-2 and approaches the depairing current density of Nb films.

Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

2014-02-01

12

Dominant mechanisms of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology  

Microsoft Academic Search

The dominant mechanisms are analyzed of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology. Data\\u000a reliability under transient irradiation is discussed in relation to photocurrents, rail-span collapse, and the circuit and\\u000a layout design of memory cells. The response is simulated of SOS integrated resistors to transient radiation. Optimal parameter\\u000a values are thus determined for the resistor used

A. V. Kirgizova; A. Y. Nikiforov; N. G. Grigor’ev; I. V. Poljakov; P. K. Skorobogatov

2006-01-01

13

Automotive SOI-BCD Technology Using Bonded Wafers  

SciTech Connect

The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N{sup +} layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

Himi, H.; Fujino, S. [DENSO CORPORATION, Ashinoya, Kota-cho, Nukata-gun, Aichi Pref., 444-0193 (Japan)

2008-11-03

14

Wafer-level manufacturing technology of glass microlenses  

NASA Astrophysics Data System (ADS)

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

15

Bonding pad models for silicon VLSI technologies and their effects on the noise figure of RF NPNs  

Microsoft Academic Search

VLSI technologies such as BiCMOS and high speed ECL Bipolar are candidates for mixed mode applications which include RF receiver functions. In order for these silicon technologies to achieve low noise characteristics one needs to optimize both the active device and the signal path to the IC interface. Studies in the bonding pad parasitics indicate that these path losses can

Natalino Camilleri; J. Kirschgessner; Julio Costa; David Ngo; David Lovelace

1994-01-01

16

A Wafer Transfer Technology for MEMS Adaptive Optics  

NASA Technical Reports Server (NTRS)

Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

Yang, Eui-Hyeok; Wiberg, Dean V.

2001-01-01

17

Material and process limits in silicon VLSI technology  

Microsoft Academic Search

The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely believed that this process will continue for at least another ten years. However there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur, and beyond ten years

JAMES D. PLUMMER; PETER B. GRIFFIN

2001-01-01

18

Kerf-free wafering: Technology overview and challenges for thin PV manufacturing  

Microsoft Academic Search

Eliminating high absorber material loss while allowing thin and ultra-thin crystalline silicon PV has been a “Holy Grail” of the crystalline silicon PV industry for decades. Generally called “kerf-free wafering”, the fundamental approach is to substitute slurry saws with an alternative waste-free wafering technology. Ideally, the technology would also eliminate the difficulty to process thin to ultra-thin wafers inherent to

Francois J. Henley

2010-01-01

19

Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies  

NASA Astrophysics Data System (ADS)

Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a consequence, computational lithography solutions are currently under development in order to correct wafer topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer stack. In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC flow for chip scale mask correction is presented with quality and run time penalty analysis.

Michel, J.-C.; Le Denmat, J.-C.; Sungauer, E.; Robert, F.; Yesilada, E.; Armeanu, A.-M.; Entradas, J.; Sturtevant, J. L.; Do, T.; Granik, Y.

2013-09-01

20

A Novel VLSI Technology to Manufacture High-Density Thermoelectric Cooling Devices  

E-print Network

This paper describes a novel integrated circuit technology to manufacture high-density thermoelectric devices on a semiconductor wafer. With no moving parts, a thermoelectric cooler operates quietly, allows cooling below ambient temperature, and may be used for temperature control or heating if the direction of current flow is reversed. By using a monolithic process to increase the number of thermoelectric couples, the proposed solid-state cooling technology can be combined with traditional air cooling, liquid cooling, and phase-change cooling to yield greater heat flux and provide better cooling capability.

H. Chen; L. Hsu; X. Wei

2008-01-07

21

VLSI-distributed architectures for smart cameras  

Microsoft Academic Search

Smart cameras use video\\/image processing algorithms to capture images as objects, not as pixels. This paper describes architectures for smart cameras that take advantage of VLSI to improve the capabilities and performance of smart camera systems. Advances in VLSI technology aid in the development of smart cameras in two ways. First, VLSI allows us to integrate large amounts of processing

Wayne H. Wolf

2001-01-01

22

NASA VLSI 2007 Mohanty, Vadlamudi and  

E-print Network

NASA VLSI 2007 Mohanty, Vadlamudi and Kougianos 1 A Universal Voltage Level Converter for Multi University of North Texas dhruva@unt.edu #12;NASA VLSI 2007 Mohanty, Vadlamudi and Kougianos 2 Agenda Custom layout design at 90nm technology Conclusion and future works #12;NASA VLSI 2007 Mohanty, Vadlamudi

Mohanty, Saraju P.

23

All-glass wafer-level lens technology for array cameras  

NASA Astrophysics Data System (ADS)

We present a novel all-glass wafer-level lens manufacturing technology. Compared to existing wafer-level lens manufacturing technologies, we realize lenses all in glass, which has a number of distinct advantages, including the availability of different glass types with largely varying dispersion for efficient achromatic lens design. Another advantage of all-glass solutions is the ability to dice the lens stack to match the form factor of a rectangular sensor area without compromising the optical performance of the lens, thereby allowing to significantly reducing the footprint of an array camera.

Dinesen, Palle G.

2014-03-01

24

Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors  

NASA Astrophysics Data System (ADS)

Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm2/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

Kim, SangHyeon; Ikku, Yuki; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung; Takenaka, Mitsuru; Takagi, Shinichi

2014-07-01

25

High performance VLSI for space and commercial applications  

Microsoft Academic Search

High performance VLSI is a key electronic technology required to advance science and commercial space missions. This paper illustrates several such NASA applications which require special purpose VLSI. In addition to being able to solve unique scientific problems, specialized VLSI can provide breakthrough technology for new commercial products. For example, the basic technology used to solve a key problem for

G. K. Maki; H. C. Shaw; K. Q. Chen

1996-01-01

26

Microneedle arrays fabricated using suspended etch mask technology combined with fluidic through wafer vias  

Microsoft Academic Search

We report the fabrication and characterization of microneedle arrays combined with (i) reservoirs for therapeutic or analytic fluids, (ii) sharp edges suitable as cutting and flaring features to increase skin permeability, and (iii) fluidic through wafer connections. Microneedle fabrication relies on a new approach combining deep reactive ion etching of silicon with suspended etch masks. This fabrication technology applies an

A. Trautmann; P. Ruther; O. Paul

2003-01-01

27

Development of Planar Microcoils for an Electromagnetic Linear Actuator Fabricated in Batch-Type Wafer Technology  

Microsoft Academic Search

This paper presents the characterization of planar microfabricated coils designed for an electromagnetic system which is realized in batch-type wafer technology. The challenge is to fabricate good coils in the simplest and economic way. The process flow used for their fabrication in the clean room as well as the manufacture results are discussed. After the magnetic simulations and the electric

Sebastiano Merzaghi; Pascal Meyer; Yves Perriard

2008-01-01

28

Self-adaptive phosphor coating technology for wafer-level scale chip packaging  

NASA Astrophysics Data System (ADS)

A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

2013-05-01

29

Epitaxial liftoff technology onto processed silicon foundry wafers  

NASA Astrophysics Data System (ADS)

Technical objectives are to research the application of liftoff transfer of epitaxial material to foreign substrates including: surface chemistry and electrical, mechanical, thermal, and optical properties of Van der Waals bonded materials; III-V devices bonded to silicon circuitry and to other substrates with enhanced optical, electrical, or thermal properties; and integrated optical devices incorporating lifted-off material and/or devices with LiNbO3 glass or other substrates. This effort addresses the need for new technologies which can fully utilize the performance advantages of III-V (GaAs, InGaAs, InGaAsP, and InP) materials for electronic and optoelectronic applications. Specifically, the program is directed at demonstrating the potential of epitaxial liftoff as a technology to enable the realization of 'monolithic' optoelectronic devices with the characteristics of epitaxial material, that is, by transfer of epitaxial material to foreign substrates in a form that permits material processing and device fabrication to proceed as though the epitaxial material were grown directly on the substrate.

Yablonovitch, Eli

30

Laser Closing of Window as a Novel Wafer-Level Hermetic Packaging Technology  

Microsoft Academic Search

We propose a novel method to achieve wafer-level, localized, high-vacuum encapsulation that is fully compatible with CMOS\\/MEMS processing for the packaging of electronic and MEMS devices and sensors. The same technology can also seal-in any desired chemical atmosphere at a wide range of pressure (including above atmospheric pressure). It is entirely thin film based and therefore does not need precision

K. P. Cheung; Y. Wang; C. S. Pai

2005-01-01

31

Diamond MEMS: wafer scale processing, devices, and technology insertion  

NASA Astrophysics Data System (ADS)

Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD® (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

Carlisle, J. A.

2009-05-01

32

The VLSI Design Automation Assistant: Prototype system  

Microsoft Academic Search

This paper describes an approach to VLSI design synthesis that uses knowledge-based expert systems to proceed from an algorithmic description of a VLSI system to a list of technology-independent registers, operators, data paths, and control signals. This paper describes how the prototype Design Automation Assistant uses large amounts of expert knowledge to design an architecture with little searching. It also

T. J. Kowalski; D. E. Thomas

1983-01-01

33

VLSI design automation assistant: learning to walk  

Microsoft Academic Search

This paper describes an approach to VLSI design synthesis using both knowledge-based expert systems and data and control flow analysis. The authors are concerned with design synthesis as it proceeds from an algorithmic description of a VLSI system to a list of technology-independent registers, operators, data paths, and control signals. This paper discusses the development of the design automation assistant

T. J. Kowalski; D. E. Thomas

1983-01-01

34

Optical interconnections for VLSI systems  

Microsoft Academic Search

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The

S.-Y. Kung; R. A. Athale; Sun-Yuan Kung

1984-01-01

35

Customizable VLSI artificial neural network chips based on a novel technology  

SciTech Connect

The human cerebral cortex contains approximately 10{sup 11} neurons and 10{sup 14} synapses. It thus seems logical that any technology intended to mimic human capabilities should have the ability to fabricate a very large number of neurons and even larger numbers of synapses. This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems.

Fu, C. Y.; Law, B.; Chapline, G. [Lawrence Livermore National Lab., CA (United States); Swenson, D. [Naval Air Warfare Center, China Lake, CA (United States)

1993-09-14

36

Technology for integrated circuit micropackages for neural interfaces, based on gold-silicon wafer bonding  

NASA Astrophysics Data System (ADS)

Progress in the development of active neural interface devices requires a very compact method for protecting integrated circuits (ICs). In this paper, a method of forming micropackages is described in detail. The active areas of the chips are sealed in gas-filled cavities of the cap wafer in a wafer-bonding process using Au-Si eutectic. We describe the simple additions to the design of the IC, the post-processing of the active wafer and the required features of the cap wafer. The bonds, which were made at pressure and temperature levels within the range of the tolerance of complementary metal-oxide-semiconductor ICs, are strong enough to meet MIL STD 883G, Method 2019.8 (shear force test). We show results that suggest a method for wafer-scale gross leak testing using FTIR. This micropackaging method requires no special fabrication process and is based on using IC compatible or conventional fabrication steps.

Saeidi, N.; Schuettler, M.; Demosthenous, A.; Donaldson, N.

2013-07-01

37

Advanced diffuser technology helps reduce vent-up times while maintaining wafer integrity on vacuum tools loadlock chambers  

NASA Astrophysics Data System (ADS)

Wafer throughput and particle counts are key metrics for any semiconductor manufacturer's yield enhancement programs. Recent advancements in diffuser technology have helped manufacturers enhance these metrics while improving the attributes for most vacuum processes. These processes include dry etch, chemical vapor deposition (CVD), physical vapor deposition (PVD), rapid thermal processing (RTP) and Epitaxial deposition (Epi). Execution of membrane diffuser technology dramatically decreases required vent time and has become a highly effective tool upgrade option. An early implementation of this technology was used on 200mm batch-style loadlocks that had an inherently large internal volume. The loadlock was prone to long vent cycles to prevent particle contamination. As the industry transitioned to a 300mm wafer platform, factories increased their development of single-wafer loadlocks (SWLL) in an effort to boost tool throughput. Gas diffusers with ultra fine filtration membranes solved these issues. Compared to the 200mm batch-style loadlocks, the SWLLs had extremely low internal volumes and were designed to cycle vacuum to atmosphere very quickly. With the low volumes inherent in the SWLL, the velocity of the incoming vent gas became critical, since any particles on the bottom of the loadlock chamber would easily sweep onto the wafer should they be hit with a high velocity gas. Particles are typically present in the loadlock due to mechanical wafer handling devices and environmental exposure. Gas diffusers allowed a large, uniform volumetric flowrate of gas into the loadlock chamber at low downstream gas velocities. While now standard on most 300mm loadlocks, the majority of 200mm tools in the field do not utilize membrane diffusers. Typically a screen, frit and/or soft vent procedure is used to control the flow into the loadlock. However, these tools can now be retrofitted with membrane diffuser technology. The result is a large reduction in particle count while maintaining throughput levels at a low cost with minimal downtime.

Vroman, Chris; Quartaro, Chris; Randolph, Marshall

2008-03-01

38

Thin hermetic passivation of semiconductors using low temperature borosilicate glass - benchmark of a new wafer-level packaging technology  

Microsoft Academic Search

A novel approach on wafer-level passivation using a thin, hermetic borosilicate glass layer replacing the polymers in redistribution is presented here. The technology will be benchmarked to those conventional technologies. The glass layer is deposited at low temperatures (T<100degC) using a plasma-enhanced e-beam deposition and can be structured by a lift-off process using a standard photoresist process for masking. The

Juergen Leib; Oliver Gyenge; Ulli Hansen; Simon Maus; Thorsten Fischer; Kai Zoschke; Michael Toepper

2009-01-01

39

A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies  

Microsoft Academic Search

This paper addresses the critical issue of scaling limits of local interconnects, contact plugs and local vias made of metal. It is shown that the current carrying capacity of copper vias\\/contacts fails to meet ITRS cur- rent density requirements beyond the 45 nm technology node. Additionally, the electrical properties of local interconnects\\/vias made of carbon nanotube (CNT) ar- rays are

Navin Srivastava; Kaustav Banerjee

40

A novel technology for fabricating customizable VLSI artificial neural network chips  

SciTech Connect

This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems. These neural networks are programmed using precision laser cutting and deposition. The fast turnaround of laser-based customization allows us to explore different neural network architectures and to rapidly program the synaptic weights. Our customizable chip allows us to expand an artificial network laterally and vertically. This flexibility permits us to build very large neural network systems.

Fu, C.Y.; Law, B.; Chapline, G. [Lawrence Livermore National Lab., CA (United States); Swenson, D. [Naval Air Warfare Center, China Lake, CA (United States)

1992-02-05

41

978-1-4244-6455-5/10/$26.00 2010 IEEE 38 11th Int'l Symposium on Quality Electronic Design VLSI circuits of 45nm technology and beyond are  

E-print Network

Abstract VLSI circuits of 45nm technology and beyond are increasingly affected by process variations in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power for variation compensation is clear only after chip fabrication, adaptive circuit (or post-silicon tuning

Hu, Jiang

42

Ultra-high heat flux cooling characteristics of cryogenic micro-solid nitrogen particles and its application to semiconductor wafer cleaning technology  

NASA Astrophysics Data System (ADS)

The ultra-high heat flux cooling characteristics and impingement behavior of cryogenic micro-solid nitrogen (SN2) particles in relation to a heated wafer substrate were investigated for application to next generation semiconductor wafer cleaning technology. The fundamental characteristics of cooling heat transfer and photoresist removal-cleaning performance using micro-solid nitrogen particulate spray impinging on a heated substrate were numerically investigated and experimentally measured by a new type of integrated computational-experimental technique. This study contributes not only advanced cryogenic cooling technology for high thermal emission devices, but also to the field of nano device engineering including the semiconductor wafer cleaning technology.

Ishimoto, Jun; Oh, U.; Guanghan, Zhao; Koike, Tomoki; Ochiai, Naoya

2014-01-01

43

CSCE 6933/5933 Advanced Topics in VLSI Systems  

E-print Network

a digital output. 10 Advanced Topics in VLSI Systems #12;Sigma-Delta Modulator · Sigma-Delta modulation based analog to digital (A/D) conversion technology is an effective alternative for high resolution Topics in VLSI Systems 1 Lecture 6: Sigma-Delta Modulator and Evaluation of SPICE NOTE: The figures, text

Mohanty, Saraju P.

44

VLSI-Chip Tester  

NASA Technical Reports Server (NTRS)

Compact test set integrated in computer-aided design system. Test set performs functional tests on very-large-scale integrated (VLSI) circuits. Makes tests from points within VLSI chip as well as at input and output pins. Used for quality control and design; in latter capacity, checks internal logic functions on chip and feed results directly to computer-aided design system for correction. Also simulates operation of chip design before chip is made. VLSI Tester contains three power supplies, control logic, and standard multibus circuit board in aluminum chassis. Chassis fits under platform of microprobe station. Multibus board links tester to interactive terminals and to host computer.

Deutsch, Leslie J.; Olson, Erlend M.

1987-01-01

45

Miniaturization and Optimization of RF SAW Filter Using Wafer Level Packaging Technology  

Microsoft Academic Search

In this paper, we describes the wafer level surface acoustic wave (SAW) filter package, 1.0times0.8 mm2, which is applicable for radio frequency (RF) stage in mobile phones. The SAW filter is reduced in size and thickness by using a 4\\

Tae Hoon Kim; Won Kyu Jeung; Si Joong Yang; Seog Moon Choi; Seung Wook Park; Hyun Ho Kim; J. Ha; Mi Jin Park; S. Kao; J. P. Hong; Sung Yi; Jun Sik Hwang; Ji Hyuk Lim; Woon Bae Kim

2007-01-01

46

Restructurable VLSI program  

NASA Astrophysics Data System (ADS)

This report describes work performed on the Restructurable VLSI Program sponsored by the information Processing Techniques Office of the Defense Advanced Research Projects Agency during the period 1 October 1984 through 31 March 1985.

Oleary, G. C.

1985-03-01

47

Restructurable VLSI program  

NASA Astrophysics Data System (ADS)

This report describes work performed on the Restructurable VLSI Program sponsored by the Information Processing Techniques Office of the Defense Advanced Research Projects Agency during the period 1 April through 30 September 1985.

Oleary, G. C.

1985-09-01

48

VLSI Interconnect Optimization Considering Non-uniform Metal Stacks  

E-print Network

With the advances in process technology, comes the domination of interconnect in the overall propagation delay in modern VLSI designs. Hence, interconnect synthesis techniques, such as buffer insertion, wire sizing and layer assignment play critical...

Tsai, Jung-Tai

2013-08-01

49

Area-time complexity for VLSI  

Microsoft Academic Search

The complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of computation appropriate to VLSI technology. This model focuses on two key parameters, the amount of silicon area and time required to implement a DFT on a single chip. Lower bounds on area (A) and time (T) are related to the number of points

Clark D. Thompson

1979-01-01

50

Toward 300 mm Wafer-Scalable High-Performance Polycrystalline Chemical Vapor Deposited Graphene Transistors.  

PubMed

The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26?000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ?74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ?40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available. PMID:25198884

Rahimi, Somayyeh; Tao, Li; Chowdhury, Sk Fahad; Park, Saungeun; Jouvray, Alex; Buttress, Simon; Rupesinghe, Nalin; Teo, Ken; Akinwande, Deji

2014-10-28

51

VLSI-distributed architectures for smart cameras  

NASA Astrophysics Data System (ADS)

Smart cameras use video/image processing algorithms to capture images as objects, not as pixels. This paper describes architectures for smart cameras that take advantage of VLSI to improve the capabilities and performance of smart camera systems. Advances in VLSI technology aid in the development of smart cameras in two ways. First, VLSI allows us to integrate large amounts of processing power and memory along with image sensors. CMOS sensors are rapidly improving in performance, allowing us to integrate sensors, logic, and memory on the same chip. As we become able to build chips with hundreds of millions of transistors, we will be able to include powerful multiprocessors on the same chip as the image sensors. We call these image sensor/multiprocessor systems image processors. Second, VLSI allows us to put a large number of these powerful sensor/processor systems on a single scene. VLSI factories will produce large quantities of these image processors, making it cost-effective to use a large number of them in a single location. Image processors will be networked into distributed cameras that use many sensors as well as the full computational resources of all the available multiprocessors. Multiple cameras make a number of image recognition tasks easier: we can select the best view of an object, eliminate occlusions, and use 3D information to improve the accuracy of object recognition. This paper outlines approaches to distributed camera design: architectures for image processors and distributed cameras; algorithms to run on distributed smart cameras, and applications of which VLSI distributed camera systems.

Wolf, Wayne H.

2001-03-01

52

NASA Space Engineering Research Center for VLSI System Design  

NASA Technical Reports Server (NTRS)

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

1993-01-01

53

Low-power VLSI techniques for applications in embedded computing  

Microsoft Academic Search

Power dissipation is an important factor in the design of CMOS VLSI circuits for battery and externally powered applications in embedded computing. This paper presents an overview of a set of techniques that are suitable for CMOS technology and are readily usable by the VLSI system and circuit designer Supply-voltage-scaled CMOS is presented as a low-power approach for digital logic

William Athas

1999-01-01

54

VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.  

PubMed

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (?1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology. PMID:24628497

Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip

2014-04-01

55

Bondability of processed glass wafers  

NASA Astrophysics Data System (ADS)

The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness will result in small real area of contact, and therefore yield voids in the bonding interface. Usually, the root mean square roughness (RMS) or the mean roughness (Ra) are used as parameters to evaluate the wafer bondability. It was found from experience that for a bondable wafer surface the mean roughness must be in the subnanometer range, preferentially less than 0.5 nm. When the surface roughness exceeds a critical value, the wafers will not bond at all. However RMS and Ra were found to be not sufficient for evaluating the wafer bondability. Hence one tried to relate wafer bonding to the spatial spectrum of the wafer surface profile and indeed some empirical relations that have been found. The first, who proposed a theory on the problem of the closing gaps between contacted wafers was Stengl. This gap-closing theory was then further developed by Tong and Gosele. The elastomechanics theory was used to study the balance between the decrease of surface energy due to the bonding and the increase of elastic energy due to the distortion of the wafer. They considered the worst case by assuming that both wafers have a waviness, with a wavelength (lambda) and a height amplitude h, resulting in a gap height of 2h in a head to head position. This theory is simple and can be used in practice, for studying the formation of the voids, or for constructing design rules for the bonding of deliberately structured wafers. But it is insufficient to know what is the real area of contact in the wafer interface after contact at room temperature because the wafer surface always possesses a random distribution of the surface topography. Therefore Gui developed a continuous model on the influence of the surface roughness to wafer bonding, that is based on a statistical surface roughness model Pandraud demonstrated experimentally that direct bonding between processed glass wafers is possible. This result cannot be explained by considering the RMS value of the surfaces only, because the wafers used show a RMS value larger than 1 nm. Based on the approach exposed in reference six, a rigorous analysis of wafer bonding of these processed glass wafers is presented. We will discuss the relation between the bonding process and different waveguide technologies used for implementing optical waveguides into one or both glass wafers, and give examples of optical devices benefiting from such a bonding process.

Pandraud, Gregory; Gui, Cheng-Qun; Pigeon, Florent; Lambeck, Paul V.; Parriaux, Olivier M.

1999-09-01

56

Firehose Architectures for Free-Space Optically-Interconnected VLSI Circuits  

E-print Network

: the shrinking feature size of silicon VLSI, resulting in a higher density of gates per unit area. Krishnamoorthy Bell Laboratories Lucent Technologies 101 Crawfords Corner Road Holmdel, NJ 07733-3030 and D. A. B-Interconnected VLSI Circuits Ashok V. Krishnamoorthy and David A. B. Miller* Bell Laboratories Lucent Technologies 101

Miller, David A. B.

57

A high aspect-ratio silicon substrate-via technology and applications: through-wafer interconnects for power and ground and Faraday cages for SOC isolation  

Microsoft Academic Search

The reduction of ground inductance is crucial to the gain of RF and microwave circuits. To provide a low-inductance interconnect, we have developed a through-wafer via technology in silicon that incorporates a silicon nitride barrier liner and is filled with electroplated Cu. We have demonstrated vias with an aspect ratio as high as 14 and an inductance that approaches the

J. H. Wu; J. A. Del Alamo; K. A. Jenkins

2000-01-01

58

Modeling of defect propagation\\/growth for early yield impact prediction in VLSI fabrication  

Microsoft Academic Search

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material and the underlying IC topography. A rigorous topography simulator, METROPOLE has been developed to allow the prediction and correlation

Xiaolei Li; Andrzej Strojwas; Mahesh Reddy; L. Milor; Y.-T. Lin

1997-01-01

59

Application of rigorous topography simulation for modeling of defect propagation\\/growth in VLSI fabrication  

Microsoft Academic Search

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the effect location, size, material and the underlying IC topography. A rigorous 2D topography simulator based on the photolithography simulator METROPOLE, has been developed

Xiaolei Li; Mahesh Reddy; Andrzej J. Strojwas; Linda Milor; Yung-Tao Lin

1997-01-01

60

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology  

NASA Astrophysics Data System (ADS)

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

61

Wafer-scale processing technology for monolithically integrated GaSb thermophotovoltaic device array on semi-insulating GaAs substrate  

NASA Astrophysics Data System (ADS)

This paper presents the entire fabrication and processing steps necessary for wafer scale monolithic integration of series interconnected GaSb devices grown on semi-insulating GaAs substrates. A device array has been fabricated on complete 50 mm (2 inch) diameter wafer using standard photolithography, wet chemical selective etching, dielectric deposition and single-sided metallization. For proof of concept of the wafer-scale feasibility of this process, six large-area series interconnected GaSb p-n junction thermophotovoltaic cells with each cell consisting of 24 small-area devices have been fabricated and characterized for its electrical connectivity. The fabrication process presented in this paper can be used for optoelectronic and electronic device technologies based on GaSb and related antimonide based compound semiconductors.

Kim, Jung Min; Dutta, Partha S.; Brown, Eric; Borrego, Jose M.; Greiff, Paul

2013-06-01

62

Verification of VLSI designs  

NASA Technical Reports Server (NTRS)

In this paper we explore the specification and verification of VLSI designs. The paper focuses on abstract specification and verification of functionality using mathematical logic as opposed to low-level boolean equivalence verification such as that done using BDD's and Model Checking. Specification and verification, sometimes called formal methods, is one tool for increasing computer dependability in the face of an exponentially increasing testing effort.

Windley, P. J.

1991-01-01

63

APPLIED PHYSICS REVIEWSFOCUSED REVIEW Adhesive wafer bonding  

E-print Network

APPLIED PHYSICS REVIEWS­FOCUSED REVIEW Adhesive wafer bonding F. Niklausa Microsystem Technology 9 February 2006 Wafer bonding with intermediate polymer adhesives is an important fabrication-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive

Salama, Khaled

64

Development of vertical and tapered via etch for 3D through wafer interconnect technology  

Microsoft Academic Search

Two types of dry silicon etch techniques are developed to cover two different areas of demand for interconnect technology: one for high aspect ratio (AR) vertical vias and one for tapered vias. Various sizes of vertical vias and trenches with diameters\\/widths ranging from 1-100 mum with an AR up to 50 are realized using Bosch deep reactive ion etch (DRIE)

Deniz Sabuncuoglu Tezcan; K. De Munck; N. Pham; O. Luhn; A. Aarts; P. De Moor; K. Baert; C. Van Hoof

2006-01-01

65

Very Large Scale Integration (VLSI).  

ERIC Educational Resources Information Center

Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

Yeaman, Andrew R. J.

66

Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding  

E-print Network

Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

Spearing, S. Mark

67

EEL 5322 VLSI CIRCUITS AND TECHNOLOGY SYLLABUS Course Outline: (See Course Video Lectures Tab for Streaming Videos and Video Downloads)  

E-print Network

and Permission Form, Class 2 Notes CMOS Technology, Gaussian Analysis Handout Statistics Web References, Implant Concept Graphics, Ion Implant Web references, Class Notes 3 Ion Implantation, Ion Implant Range Tables) Lecture 4 - Ion Implantation Notes Additional Implant Graphics, Implant Example Problems, Implant patent

Fang, Yuguang "Michael"

68

Princeton VLSI project  

NASA Astrophysics Data System (ADS)

There are three major aspects to our project: ALI, Census, and Testing. ALI, our procedural language for VLSI design and layout, is now up and running. It has already been used by Dobkin and Drysdale to redesign a divider they previously designed on a graphics system at Xerox. In addition, LaPaugh's VLSI class has already used ALI for their VLSI projects. Dobkin is currently beginning to explore ways to create graphics interfaces to the ALI system. The ALI2, the second version of our layout system is coming along well. The census language is a new way to express parallel algorithms that use a fairly loosely coupled method of control. Work is under way to understand the limits and powers of such languages. North is beginning to identify those problem areas that can be successfully mapped onto the census language. We are also thinking about implementations of census, but no implementations is yet started. Our work on testing divides into two areas. Arden is beginning to work on first silicon testing especially with respect to scanning electron microscopes (SEM). In the future we expect that we will be able to use a SEM that the Princeton Siemens group is about to get. LaPaugh and Lipton have begun to work in the area of production testing. They have already successfully been able to completely characterize the testability of prefix computations. Prefix computations arise naturally in a number of places; for instance, in carry look ahead adders. Such characterizations link the self test of these computations with classic semigroup theory.

Lipton, R. J.

69

Large array VLSI filter  

NASA Technical Reports Server (NTRS)

A 35 by 35 element pipelined convolutional kernel is being fabricated using VLSI chips, each containing a 5 by 1 segment of the kernel. Three levels of printed circuitry are used: the first level is used for the VLSI chips, the second level connects seven chips together on one platform, and the third level connects seven platforms with associated delay lines, all fitting on one board. Therefore, on each board there are seven rows of the kernel containing 245 multipliers and adders, and five such boards complete the kernel array. Each multiplier accepts an 8 bit picture element which is multiplied by a 16 bit weight. A truncated 22 bit product is added to a previously stored product sum and the results are shifted to the following multiplier as the next picture element is read in. The multiplier uses a modified Booth algorithm to reduce the number of shift add operations nearly in half. The filter box is presently configured as an ancillary box to a VAX 11/780, but can be connected to essentially any CPU. The I/O bandwidth is easily compatible with most CPU devices.

Nathan, R.

1983-01-01

70

Mixed voltage VLSI design  

NASA Technical Reports Server (NTRS)

A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

Panwar, Ramesh; Rennels, David; Alkalaj, Leon

1993-01-01

71

Wafer Manufacturing and Slicing Using Wiresaw  

NASA Astrophysics Data System (ADS)

Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer quality are presented. Summary and further reading are also provided.

Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

72

Laser wafering for silicon solar.  

SciTech Connect

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

73

SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface  

NASA Astrophysics Data System (ADS)

This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

2010-10-01

74

An interconnect structure for wafer scale neurocomputers  

Microsoft Academic Search

Silicon technology has two limitations: fabrication defects and limited interconnect. The authors believe the fault-tolerance of neural network models can compensate for fabrication defects. In this paper the authors present the design of an interconnect structure for wafer scale neural network emulation based on CMOS silicon technology that solves the interconnect problem. Thus, massively parallel, wafer scale neurocomputer architectures are

M. Rudnick; D. Hammerstrom

1988-01-01

75

Titanic: a VLSI based content addressable parallel array processor  

SciTech Connect

A design is presented for a content addressable parallel array processor (CAPAP) which is both practical and feasible. Its practicality stems from an extensive program of research into real applications of content addressability and parallelism. The feasibility of the design stems from development under a set of conservative engineering constraints tied to limitations of VLSI technology. 1 ref.

Weems, C.; Levitan, S.; Foster, C.

1982-01-01

76

Design automation for wafer scale integration  

SciTech Connect

Wafer scale integration (WSI) is a technique for implementing large digital systems on a single wafer. This thesis describes a system of design automation tools developed to aid in the implementation of wafer scale integrated systems. An overview of wafer scale integration is given with fabrication details and yield considerations discussed. The Wafer architectural Design Language (WDL) used to describe and specify a system architecture to the development system is introduced along with a compiler that translates the high level WDL description into net lists and other internal data bases. Interactive placement tools used to map the system architecture onto the functional die sites on a wafer are described. A very fast line probe router was developed to perform the custom wafer level routing need to personalize each wafer. Router data structures, algorithms, techniques, and results are discussed in detail. Sample wafer scale architectures and the result of their WSI implementations are shown. Also presented is the Wafer Transmission Module (WTM) a packaging technology related to wafer scale integration.

Donlan, B.J.

1986-01-01

77

Fine grinding of silicon wafers: effects of chuck shape on grinding marks  

Microsoft Academic Search

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were

Wangping Sun; Z. J. Pei; G. R. Fisher

2005-01-01

78

Recursive computer architecture for VLSI  

SciTech Connect

A general-purpose computer architecture based on the concept of recursion and suitable for VLSI computer systems built from replicated (lego-like) computing elements is presented. The recursive computer architecture is defined by presenting a program organisation, a machine organisation and an experimental machine implementation oriented to VLSI. The experimental implementation is being restricted to simple, identical microcomputers each containing a memory, a processor and a communications capability. This future generation of lego-like computer systems are termed fifth generation computers by the Japanese. 30 references.

Treleaven, P.C.; Hopkins, R.P.

1982-01-01

79

Environmental Sensors VLSI VS1011  

E-print Network

. Light Sensor Ambient light levels are read in from the surrounding environment and used as input Sensor An embedded motion sensor detects near field motion and provides user control. The Team Tim ChinEnvironmental Sensors VLSI VS1011 The VS1011 uses a wide variety of industry standards for decoding

Liebling, Michael

80

Circuits programmables 1 Circuits VLSI  

E-print Network

Circuits programmables 1 Circuits VLSI programmables Alain GUYOT TIMA TIMA Techniques de l,version1-12Sep2006 #12;Circuits programmables 2 Du Micro au Micron Microprocesseur, micro-ordinateur monoboitier Circuits programmables dynamiquement Circuits programmables statiquement Tableaux, mer de portes

Paris-Sud XI, Université de

81

Scheduling semiconductor wafer fabrication  

Microsoft Academic Search

The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

LAWRENCE M. WEIN

1988-01-01

82

Role of wafer geometry in wafer chucking  

NASA Astrophysics Data System (ADS)

Wafer chucks are used in advanced lithography systems to hold and flatten wafers during exposure. To minimize defocus and overlay errors, it is important that the chuck provide sufficient pressure to completely chuck the wafer and remove flatness variations across a broad range of spatial wavelengths. Analytical and finite element models of the clamping process are presented here to understand the range of wafer geometry features that can be fully chucked with different clamping pressures. The analytical model provides a simple relationship to determine the maximum feature amplitude that can be chucked as a function of spatial wavelength and chucking pressure. Three-dimensional finite element simulations are used to examine the chucking of wafers with various geometries, including cases with simulated and measured shapes. The analytical and finite element results both demonstrate that geometry variations with short spatial wavelengths (e.g., high-frequency wafer shape features) present the greatest challenge to achieving complete chucking. The models and results presented here can be used to provide guidance on wafer geometry and chuck designs for advanced exposure tools.

Turner, Kevin T.; Ramkhalawon, Roshita; Sinha, Jaydeep K.

2013-04-01

83

The Fifth NASA Symposium on VLSI Design  

NASA Technical Reports Server (NTRS)

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

1993-01-01

84

An interconnect structure for wafer scale neurocomputers  

SciTech Connect

Silicon technology has two limitations: fabrication defects and limited interconnect. The authors believe the fault-tolerance of neural network models can compensate for fabrication defects. In this paper the authors present the design of an interconnect structure for wafer scale neural network emulation based on CMOS silicon technology that solves the interconnect problem. Thus, massively parallel, wafer scale neurocomputer architectures are feasible. Their design is part of the Cognitive Architecture Project (CAP) at the Oregon Graduate Center. The CAP architecture is a hybrid using analog computation and multiplexed digital interconnect. The long term goal is to emulate a million nodes, each with a thousand connections, on a single wafer.

Rudnick, M.; Hammerstrom, D.

1988-09-01

85

Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits  

E-print Network

Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this dissertation, we study three challenging issues in delay test: fault modeling, variational delay evaluation...

Lu, Xiang

2006-04-12

86

VLSI architecture design of MPEG4 shape coding  

Microsoft Academic Search

This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 video standard. The real-time constraint of MPEG-4 shape coding leads to a heavy computational bottleneck on today's computer architectures. To overcome this problem, design analysis and optimization of MPEG-4 shape coding are addressed. By utilizing

Hao-chieh Chang; Yung-chi Chang; Yi-chu Wang; Wei-ming Chao; Liang-gee Chen

2002-01-01

87

Closed-loop electroosmotic microchannel cooling system for VLSI circuits  

Microsoft Academic Search

The increasing heat generation rates in VLSI circuits motivate research on compact cooling technologies with low thermal resistance. This paper develops a closed-loop two-phase microchannel cooling system using electroosmotic pumping for the working fluid. The design, fabrication, and open-loop performance of the heat exchanger and pump are summarized. The silicon heat exchanger, which attaches to the test chip (1 cm2),

Linan Jiang; James Mikkelsen; Jae-Mo Koo; David Huber; Shuhuai Yao; Lian Zhang; Peng Zhou; James G. Maveety; Ravi Prasher; Juan G. Santiago; Thomas W. Kenny; Kenneth E. Goodson

2002-01-01

88

A ``Zero-Time'' VLSI Sorter  

Microsoft Academic Search

A hardware sorter suitable for VLSI implementation is proposed. It operates in a parallel and pipelined fashion, with the actual sorting time absorbed by the input\\/output time. A detailed vlsi implementation is described which has a very favorable device count compared to existing static RAM. 18 references.

Glen S. Miranker; Luong Tang; Chak-kuen Wong

1983-01-01

89

Model Reduction for VLSI Physical Verification  

Microsoft Academic Search

In this paper, we will first introduce physical verification of Very Large Scale Integration (VLSI) circuits and put the challenges in perspective from a computational electro-magnetics point of view. We argue that any models obtained from electromagnetic (electrostatic) analysis should be as simple as possible for a given accuracy. We will then focus on two aspects of VLSI physical verification,

N. P. van der Meijs

90

Three wafer stacking for 3D integration.  

SciTech Connect

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

2011-11-01

91

High temperature materials for thin-film thermocouples on silicon wafers  

Microsoft Academic Search

We have developed an instrumented calibration wafer for radiometric temperature measurements in rapid thermal processing (RTP) tools for semiconductor processing. The instrumented wafers have sputter deposited thin-film thermocouples to minimize the thermal disturbance of the wafer by the sensors. The National Institute of Standards and Technology (NIST) calibration wafer also employs platinum–palladium wire thermocouples to achieve a combined standard uncertainty

Kenneth G Kreider; Greg Gillen

2000-01-01

92

Image quality and wafer level optics  

NASA Astrophysics Data System (ADS)

Increasing demand from consumers to integrate camera modules into electronic devices, such as cell phones, has driven the cost of camera modules down very rapidly. Now that most cell phones include at least one camera, consumers are starting to ask for better image quality - without compromising on the cost. Wafer level optics has emerged over the past few years as an innovative technology enabling simultaneous manufacturing of thousands of lenses, at the wafer level. Using reflow-compatible materials to manufacture these lenses permits a reduction in the cost and size of camera module, thus answering the market demand for lowering the cost. But what about image quality? The author will present image quality analysis that was conducted for both VGA and megapixel camera resolutions. Comparison between conventional camera modules and wafer level camera modules shows wafer level technology brings equivalent, if not better, image quality performance compared to conventional camera modules.

Dagan, Y.; Humpston, G.

2010-05-01

93

Extremely long life and low-cost 193nm excimer laser chamber technology for 450mm wafer multipatterning lithography  

NASA Astrophysics Data System (ADS)

193nm ArF excimer lasers are widely used as light sources for the lithography process of semiconductor production. 193nm ArF exicmer lasers are expected to continue to be the main solution in photolithography, since advanced lithography technologies such as multiple patterning and Self-Aligned Double Patterning (SADP) are being developed. In order to apply these technologies to high-volume semiconductor manufacturing, the key is to reduce the total operating cost. To reduce the total operating cost, life extension of consumable part and reduction of power consumption are an important factor. The chamber life time and power consumption are a main factor to decide the total operating cost. Therefore, we have developed the new technology for extension of the chamber life time and low electricity consumption. In this paper, we will report the new technology to extend the life time of the laser chamber and to reduce the electricity consumption.

Tsushima, Hiroaki; Katsuumi, Hisakazu; Ikeda, Hiroyuki; Asayama, Takeshi; Kumazaki, Takahito; Kurosu, Akihiko; Ohta, Takeshi; Kakizaki, Kouji; Matsunaga, Takashi; Mizoguchi, Hakaru

2014-04-01

94

Automated wafer transport in the wafer Fab  

Microsoft Academic Search

Through simulations with models, HP's Inkjet Supplies Business Unit has determined that intrabay material transport with automated delivery of wafers directly to process tools substantially increases the throughput of our semiconductor manufacturing facility (Fab). To fully utilize limited Fab space, an architecture using overhead track and vehicles has been selected. HP cooperated with a Supplier of automated material handling systems

U. Kaempf

1997-01-01

95

VLSI Processor For Vector Quantization  

NASA Technical Reports Server (NTRS)

Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

Tawel, Raoul

1995-01-01

96

Fully-depleted silicon-on-sapphire and its application to advanced VLSI design  

NASA Technical Reports Server (NTRS)

In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

Offord, Bruce W.

1992-01-01

97

Wafer characteristics via reflectometry  

DOEpatents

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

98

Scriber for silicon wafers  

NASA Technical Reports Server (NTRS)

A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

Yamakawa, K. A.; Fortier, E. P. (inventors)

1981-01-01

99

Minimizing and exploiting leakage in VLSI  

E-print Network

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a...

Jayakumar, Nikhil

2009-05-15

100

Restructurable VLSI (Very large scale integration) program  

NASA Astrophysics Data System (ADS)

This report describes work performed on the Restructurable VLSI Program sponsored by the Information Processing Techniques Office of the Defense Advanced Research Projects Agency during the period 1 April through 30 September 1984.

Oleary, G. C.

1984-09-01

101

Application of network coding for VLSI routing  

E-print Network

This thesis studies the applications of the network coding technique for intercon- nect optimization and improving the routability of Very-large-scale integration (VLSI) designs. The goal of the routing process is to connect the required sets...

Nemade, Nikhil Pandit

2009-05-15

102

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses  

NASA Astrophysics Data System (ADS)

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

103

Stable wafer-carrier system  

DOEpatents

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

104

Development of a 2 micrometer silicon-gate-CMOS-technology for microcomputer oriented VLSI circuits with a supply voltage range between 1.5 and 5 V  

NASA Astrophysics Data System (ADS)

The processes necessary for a 2 micron CMOS-technology were developed, including projection lithography, the oxidation process, the fabrication of thin oxides, and dry etching techniques for patterning silicon nitride, polysilicon, silicon oxide, and aluminum. With the aid of process simulations and experimental results, a process flow chart was established. A test chip with a large number of single structures and circuit blocks was designed in 2 micron tubes. Different runs of this test chip are produced. The success of the developed technology is demonstrated on different logic circuit blocks.

Fischer, G.; Kiss, T.; Kummerow, K.; Link, M.; Scharzmann, U.

1984-10-01

105

Transfer of metal MEMS packages using a wafer-level solder sacrificial layer  

Microsoft Academic Search

This paper presents a modular, low profile, wafer-level encapsulation technology for 0-level MEMS packaging. Electroplated caps are formed on a carrier wafer then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled by the dewetting of the solder transfer layer from the

Warren C Welch; Khalil Najafi

2005-01-01

106

Transfer of metal MEMS packages using a wafer-level solder transfer technique  

Microsoft Academic Search

This paper presents a modular, low profile, wafer-level encapsulation technology for microelectromechanical systems (MEMS) packaging. Electroplated caps are formed on top of a solder transfer layer previously deposited on a carrier wafer, then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled

Warren C. Welch; Junseok Chae; Khalil Najafi

2005-01-01

107

The VLSI design of an error-trellis syndrome decoder for certain convolutional codes  

NASA Technical Reports Server (NTRS)

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

1986-01-01

108

The VLSI design of error-trellis syndrome decoding for convolutional codes  

NASA Technical Reports Server (NTRS)

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

1985-01-01

109

The triangle processor and normal vector shader: a VLSI system for high performance graphics  

Microsoft Academic Search

Current affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated. Massively parallel VLSI system have the potential to bypass this bottleneck, but

Michael Deering; Stephanie Winner; Bic Schediwy; Chris Duffy; Neil Hunt

1988-01-01

110

A new method for noise analysis in nano-scale VLSI circuits using wavelet  

Microsoft Academic Search

This paper analyzes signals in nanometer VLSI circuits using wavelet techniques; afterwards, noise source (aggressor line) and interconnect effects are studied. As becoming integrated circuits denser, using nanometer scale technologies, shrinking dimensions of interconnects, the role of interconnect parasitic effects in the signal integrity at high speeds, become increasingly significant which may result in the aggravation of crosstalk noise amplitude

Amir Haghayegh; Behjat Forouzandeh; Davood Fathi; Kaveh Kangarloo

2011-01-01

111

AWV: high-throughput cross-array cross-wafer variation mapping  

NASA Astrophysics Data System (ADS)

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

2008-03-01

112

Low-cost wafer level packaging process  

NASA Astrophysics Data System (ADS)

Today, semiconductors are being connected to other components of the system through three main interconnect technologies - Wirebond, TAB and Solder bump. Of the three technologies, use of solder bump provides the lowest impedance electrical path and a high er I/O density as compared to wirebond and TAB. Wafer bumping is often accompanied by a need for redistribution of the current carrying pads on the silicon in order to reduce the substrate cost and better manufacturing yields, Besides, there is a need to deposit a metallic layer underneath the bump for good reliability of the packaged system. The two widely used processes used for depositing a thin metal film, either for redistribution or UBM are Physical Vapor Deposition and evaporation. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for going towards wafers level packaging solutions in order to minimize the packaging cost and giving high production rates.

Kapoor, Rahul; Khim, Swee Y.; Hwa, Goh H.

2000-10-01

113

CSCE 6933/5933 Advanced Topics in VLSI Systems  

E-print Network

· Static Power · Low Power Design 2 Advanced Topics in VLSI Systems #12;Power Dissipation Trend 3 Advanced and Harris 2005 Power Dissipation Static Dissipation Dynamic Dissipation Sub-threshold current Gate Leakage Advanced Topics in VLSI Systems #12;Dynamic and Static Power Sources 9 Advanced Topics in VLSI Systems #12

Mohanty, Saraju P.

114

3D eWLB (embedded wafer level BGA) technology for 3D-packaging\\/3D-SiP (Systems-in-Package) applications  

Microsoft Academic Search

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. There are some restrictions in possible applications for Fan-In WLPs since global chip trends tend toward smaller chip areas with an increasing number of

Seung Wook Yoon; A. Bahr; X. Baraton; P. C. Marimuthu; Flynn CARSON

2009-01-01

115

Parallel architectures for optoelectronic VLSI processing  

NASA Astrophysics Data System (ADS)

Limited bandwidth because of too few and too slow external pins is one of the major problems in current VLSI systems. Increasing clock rates and the growing transistor density in future microprocessor will enlarge the imbalance between satisfying computing power and insufficient communication performance. Optoelectronic VLSI (OE-VLSI) circuits using highly dense 3D optical interconnections offer the potential to overcome these problems. To lead OE-VLSI processing to success it is necessary to point out a diversity of architectures that profit extremely from a 2D optical input/output interface. Such architectures have to be developed especially for an optoelectronic solution. We demonstrate this for various architectures like binary neural associative memories and fine-grain 3D processor cores for integer and digital signal processing. We specify the electronic circuits and the optical interconnection schemes. We found out that an optoelectronic approach for the associative memory offers two orders of magnitude more performance than all-electronic solutions. The stacked 3D integer processor offers a performance increase of about 10 to 50 over current RISC processors. For the realization of the OE-VLSI circuits we developed a CMOS-SEED chip and a smart detector test chip consisting of CMOS circuitry monolithically integrated with a silicon based array of photo diodes.

Fey, Dietmar; Grimm, Guido; Erhard, Werner

1999-04-01

116

ELID supported grinding of thin sapphire wafers  

Microsoft Academic Search

Sapphire material is, due to its crystal structure, difficult to machine in an economic way. There is a request for thin, i.e. below 0.2 mm thickness, sub surface damage free wafers to produce sensor elements. ELID -- electrolytic in process dressing -- is an innovative high end grinding technology, using small grain sizes, which enable to manufacture surfaces in a

Igor Makarenko; Christian Vogt; Rolf Rascher; Peter Sperber; Thomas Stirner

2010-01-01

117

Etching Of Semiconductor Wafer Edges  

DOEpatents

A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

2003-12-09

118

Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter  

NASA Technical Reports Server (NTRS)

The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

Chen, C. P.; Leipold, M. H.

1984-01-01

119

MIL-STD-1553 VLSI components  

NASA Astrophysics Data System (ADS)

The performance, physical and electrical characteristics of novel VLSI components which will support all MIL-STD-1553 terminals are described. A transceiver, protocol, and computer interface set of chips supports remote terminal unit, bus controller, and bus monitor modes of operation. A discussion of these VLSI components is given, and their special features are explored. These features include size and packaging options, radiation hardness, power, and reliability considerations. The special capabilities of these devices are highlighted, along with programming options that facilitate a broad array of applications.

Friedman, Steven N.

120

30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology  

NASA Technical Reports Server (NTRS)

An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

1986-01-01

121

Sapphire Wafer Bumping by Lead-free Solder Paste Printing Process  

Microsoft Academic Search

Peregrine's silicon on sapphire technology provides high performance RF IC devices to wireless market, while for bumping on this type of sapphire wafer new challenges will be encountered. High residual stress accumulated on sapphire wafer surface may cause bumping reliability performance issue. Sapphire wafer's singulation process, which uses three-point breaking method, requires bumping must be of a reasonable structure to

Y. J. Zhiyuan

2007-01-01

122

Design Technologies for Low Power VLSI  

Microsoft Academic Search

Low power has emerged as a principal theme in today's electronics indus- try. The need for low power has caused a major paradigm shift where power dis- sipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power cir- cuits and systems. It describes the many issues facing designers

Massoud Pedram

1997-01-01

123

Wafer bonding : mechanics-based models and experiments  

E-print Network

Direct wafer bonding has emerged as an important technology in the manufacture of silicon-on-insulator substrates (SOI), microelectromechanical systems (MEMS), and three-dimensional integrated circuits (3D IC's). While the ...

Turner, Kevin Thomas, 1977-

2004-01-01

124

An artificial intelligence approach to VLSI design  

Microsoft Academic Search

This work focuses on the VLSI design synthesis method for designing hardware that starts with an algorithmic description and uses interactive computer programs to create a finished design. The author sets forth that this structured approach can decrease the time it takes to design a chip, automatically provide multi-level documentation for the finished design, and create reliable and testable designs.

Thaddeus J. Kowalski

1985-01-01

125

Analog VLSI motion projects at Caltech  

Microsoft Academic Search

We present different compact analog VLSI motion sensors that compute the 1-D velocity of optical stimuli over a large range and are suitable for integration in focal plane arrays. They have been extensively tested and optimized for robust performance under varying light conditions. Since their output signals are only weakly dependent on contrast, they directly extract optical flow data from

Joerg Kramer; Giacomo Indiveri; Christof Koch

1996-01-01

126

E24: VLSI Design Syllabus -Fall 2011  

E-print Network

estimation · Circuit simulation · Combinational and sequential circuit design · Static and dynamic CMOS gatesE24: VLSI Design Syllabus - Fall 2011 T Th 8:30-9:45, Hicks 211 Course Website: http · Memory system design · Design methodology and tools Please check the course website for an updated course

Moreshet, Tali

127

E77: VLSI Design Syllabus -Fall 2007  

E-print Network

· Circuit simulation · Combinational and sequential circuit design · Static and dynamic CMOS gates · MemoryE77: VLSI Design Syllabus - Fall 2007 MWF 9:30-10:20, Hicks 211 Course Website: http system design · Design methodology and tools Please check the course website for an updated course

Moreshet, Tali

128

SSI/MSI/LSI/VLSI/ULSI.  

ERIC Educational Resources Information Center

Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

Alexander, George

1984-01-01

129

The theory of signature testing for VLSI  

Microsoft Academic Search

Several methods for testing VLSI chips can be classified as signature methods. Both conventional and signature testing methods apply a number of test patterns to the inputs of the circuit. The difference is that a conventional method examines each output, while a signature method first accumulates the outputs in some data compression device, then examines the signature - the final

J. Lawrence Carter

1982-01-01

130

Analog VLSI model of binaural hearing  

Microsoft Academic Search

The stereausis model of biological auditory processing is proposed as a representation that encodes both binaural and spectral information in a unified framework. A working analog VLSI chip that implements this model of early auditory processing in the brain is described. The chip is a 100000-transistor integrated circuit that computes the stereausis representation in real time, using continuous-time analog processing.

Carver A. Mead; Xavier Arreguit; John Lazzaro

1991-01-01

131

VLSI floorplanning based on Particle Swarm Optimization  

Microsoft Academic Search

Floorplanning is an important problem in the very large integrated circuit (VLSI) design automation. It¿s an NP-hard combinatorial optimization problem. The particle swarm optimization (PSO) has been proved to be a good optimization algorithm with outstanding global performance. However, PSO cannot be directly used in the combinatorial optimization problem due to its continuous characteristic. In this paper a novel floorplanning

Guolong Chen; Wenzhong Guo; Hongju Cheng; Xiang Fen; Xiaotong Fang

2008-01-01

132

Beyond Steiner's Problem: A VLSI Oriented Generalization  

Microsoft Academic Search

We consider a generalized version of Steiner's problem in graphs, motivated by the wire routing phase in physical VLSI design: given a connected, undirected distance graph with groups of required vertices and Steiner vertices, find a shortest connected subgraph containing at least one required vertex of each group. We propose two efficient approximation algorithms computing different approximate solutions in time

Gabriele Reich I; Peter Widmayer

1989-01-01

133

Statistical Circuit Simulation Modeling of CMOS VLSI  

Microsoft Academic Search

This paper describes a complete modeling approach for MOS VLSI circuit design which is highly automated and provides statistically relevant parameter files. A description of key model equations, which includes the effects of nonuniformly doped channels, charge sharing bulk-charge terms, and lateral and vertical field mobility reduction terms, will be given. A methodology of parameter extraction for both physical and

Norm Herr; John J. Barnes

1986-01-01

134

1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics  

SciTech Connect

The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

Lorenz, Adam [1366 Technologies] [1366 Technologies

2013-08-30

135

Wafer-scale micro-optics fabrication  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Voelkel, Reinhard

2012-07-01

136

Augmented reality for wafer prober  

NASA Astrophysics Data System (ADS)

The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

Gilgenkrantz, Pascal

2011-03-01

137

RICE UNIVERSITY An Integrated CAD Framework Linking VLSI  

E-print Network

RICE UNIVERSITY An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators. Tittel J. S. Abercrombie Professor Electrical and Computer Engineering Houston, Texas November, 1998 #12

Cavallaro, Joseph R.

138

Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip Matthias Fugger, Ulrich Schmid, Gottfried Fuchs  

E-print Network

, Gottfried Fuchs Vienna University of Technology Email: {fuegger, s, fuchs}@ecs.tuwien.ac.at Gerald Kempf. 809456-SCK/SAI) and the Austrian FWF project Theta (proj. no. P17757). 1 #12;1 Motivation Shrinking feature sizes and increasing clock speeds are the most visible signs of the tremendous advances in VLSI

139

Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits  

Microsoft Academic Search

Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to radiation-induced single-event-upsets (SEUs). Redundancy insertion has been adopted to provide the circuit with additional transient error resiliency. However, its applicability and efficiency are limited by the tight design constraints and budgets. In this paper, we present an intelligent ldquoconstraint-aware robustness insertionrdquo methodology. By selectively protecting sequential elements in

Chong Zhao; Yi Zhao; Sujit Dey

2008-01-01

140

A 16-channel analog VLSI processor for bionic ears and speech-recognition front ends  

Microsoft Academic Search

We describe a 470 ?W 16-channel analog VLSI processor for bionic ears (cochlear implants) and portable speech-recognition front ends. The power consumption of the processor is kept at low levels through the use of subthreshold CMOS technology. Each channel is composed of a programmable bandpass filter, an envelope detector, and a logarithmic dual-slope analog-to-digital converter that currently operate over 51

Michael W. Baker; T. K.-T. Lu; C. D. Salthouse; J.-J. Sit; S. Zhak; R. Sarpeshkar

2003-01-01

141

VLSI Electronics Design and Testing for the Silicon Drift Sensor System of the ALICE Experiment  

Microsoft Academic Search

Large sensor systems in modern high energy physics experiments combine state-of-the-art technologies in sensor development, electronics and large-system integration. The silicon drift sensor system (SDD), part of the inner tracking system of the ALICE experiment at LHC required the development of full-custom VLSI electronics. The high number of integrated ADCs, as well as low-noise and low-power operation are the key

Sorin Martoiu; L. Toscano

2006-01-01

142

Accelerating litho technology development for advanced design node flash memory FEOL by next-generation wafer inspection and SEM review platforms  

NASA Astrophysics Data System (ADS)

Development of an advanced design node for NAND flash memory devices in semiconductor manufacturing requires accelerated identification and characterization of yield-limiting defect types at critical front-end of line (FEOL) process steps. This enables a shorter development cycle time and a faster production ramp to meet market demand. This paper presents a methodology for detecting defects that have a substantial yield impact on a FEOL after-develop inspection (ADI) layer using an advanced broadband optical wafer defect inspector and a scanning electron microscope (SEM) review tool. In addition, this paper presents experimental data that demonstrates defect migration from an ADI layer to an after-clean inspection (ACI) layer, and provides clear differentiation between yield-impacting critical defects and noncritical defects on the layers. The goal of these studies is to determine the feasibility of implementing an inspection point at ADI. The advantage of capturing yield-limiting defects on an ADI layer is that wafers can be reworked when an excursion occurs, an option that is not always possible for ACI layers. Our investigation is divided into two parts: (1) Inspection of an ADI layer with high sensitivity to find an accurate representation of the defect population and to gain understanding on the propagation of defects from the ADI layer to the ACI layer; and, (2) Inspection of an ACI layer to develop an understanding of unique defects generated by the ACI process step. Overall, this paper discusses the advantages of baselining defectivity at ADI process levels for accelerated development of advanced design node memory devices.

Lee, Byoung Ho; Ahn, Jeongho; Ihm, Dongchul; Chin, Soobok; Lee, Dong-Ryul; Choi, Seongchae; Lee, Junbum; Kang, Ho-Kyu; Sivaraman, Gangadharan; Yamamoto, Tetsuya; Lakhawat, Rahul; Sanapala, Ravikumar; Lee, Chang Ho; Lobo, Arun

2012-03-01

143

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

2009-03-01

144

VLSI Microsystem for Rapid Bioinformatic Pattern Recognition  

NASA Technical Reports Server (NTRS)

A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

Fang, Wai-Chi; Lue, Jaw-Chyng

2009-01-01

145

Leak detection utilizing analog binaural (VLSI) techniques  

NASA Technical Reports Server (NTRS)

A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

Hartley, Frank T. (inventor)

1995-01-01

146

Multi-Wafer Plasma Anodization.  

National Technical Information Service (NTIS)

A prototype multi-wafer plasma anodization apparatus was designed and constructed to investigate the multi-wafer process. The apparatus uses a hot hollow cathode to generate a dense discharge capable of yielding high oxide growth rates. The samples are pl...

W. B. Orcutt

1972-01-01

147

Silicon cast wafer recrystallization for photovoltaic applications  

E-print Network

Current industry-standard methods of manufacturing silicon wafers for photovoltaic (PV) cells define the electrical properties of the wafer in a first step, and then the geometry of the wafer in a subsequent step. The ...

Hantsoo, Eerik T. (Eerik Torm)

2008-01-01

148

A VLSI implementation of CAVLC for H.264/AVC  

NASA Astrophysics Data System (ADS)

H.264 is the newest video coding standard and is currently one of the hot subjects of video processing technologies. Coding quality and compression ratio have been greatly improved in the new standard compared with the previous standards. The context-based adaptive technology is introduced into the new standard, which can be said to be a technology renovation of the video coding. The main entropy coding technologies of H.264 include VLC (Variable- Length Coding) and CABAC (Context-based Adaptive Binary Arithmetic Coding). CAVLC is VLC and adopts the context-based adaptive technology, therefore the coding efficiency is greatly improved. Currently, the design of the CAVLC encoder is mainly in software method, but with the development of real-time video processing technology, it is difficult for software to meet the demands. As a result, the hardware method in designing of CAVLC coder becomes a good choice. In the paper a CAVLC entropy encoder architecture based VLSI is proposed and implemented on an Altera FPGA device. As the results of simulation and synthesis, it can process 4×4 or 2×2 blocks per 16 clock periods with pipelined architecture and can achieve the real-time processing requirement of 30 frames per second for a 720×480 video at 100 MHz operation frequency.

Luo, Li; Li, Zheying; Yu, Qinmei

2009-10-01

149

Implementation of a neuromorphic vestibular sensor with analog VLSI neurons  

E-print Network

Implementation of a neuromorphic vestibular sensor with analog VLSI neurons Giovanni Passetti neuromorphic vestibular sensor using a commercial Inertial Mea- surement Unit (IMU) and a custom analog VLSI neuromorphic chip. We investigate a model of the vestibular sensor that emu- lates the spiking responses

150

Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI  

E-print Network

Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI Rajit Manohar and Clinton, Ithaca NY 14853 Abstract We introduce the notion of a network-on-a-chip: a programmable, asynchronous VLSI archi- tecture for fast and efficient simulation of wireless networks. The approach is inspired

Manohar, Rajit

151

Image Compression on a VLSI Neural-Based Vector Quantizer.  

ERIC Educational Resources Information Center

Describes a modified frequency-sensitive self-organization (FSO) algorithm for image data compression and the associated VLSI architecture. Topics discussed include vector quantization; VLSI neural processor architecture; detailed circuit implementation; and a neural network vector quantization prototype chip. Examples of images using the FSO…

Chen, Oscal T.-C.; And Others

1992-01-01

152

VLSI architectures for geometrical mapping problems in high-definition image processing  

NASA Technical Reports Server (NTRS)

This paper explores a VLSI architecture for geometrical mapping address computation. The geometric transformation is discussed in the context of plane projective geometry, which invokes a set of basic transformations to be implemented for the general image processing. The homogeneous and 2-dimensional cartesian coordinates are employed to represent the transformations, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme for a processor, which utilizes full-pipelining at the macro-level and parallel constant-factor-redundant arithmetic and full-pipelining at the micro-level, is assessed to produce a single VLSI chip for HDTV applications using state-of-art MOS technology.

Kim, K.; Lee, J.

1991-01-01

153

Computer aided fast turnaround laboratory for research in VLSI (Very Large Scale Integration)  

NASA Astrophysics Data System (ADS)

The principal objectives of the computer aided/Automated fast turn-around laboratory (CAFTAL) for VLSI are: application of cutting edge computer science and software systems engineering to fast turn-around fabrication in order to develop more productive and flexible new approaches; fast turn-around fabrication of optimized VLSI systems achieved through synergistic integration of system research and device research in aggressive applications such as superfast computers, and investigation of physical limits on submicron VLSI in order to define and explore the most promising technologies. To make a state-of-the-art integrated circuit process more manufacturable, we must be able to understand both the numerous individual process technologies used to fabricate the complete device as well as the important device, circuit and system limitations in sufficient detail to monitor and control the overall fabrication sequence. Specifically, we must understand the sensitivity of device, circuit and system performance to each important step in the fabrication sequence. Moreover, we should be able to predict the manufacturability of an integrated circuit before we actually manufacture it. The salient objective of this program is to enable accurate simulation and control of computer-integrated manufacturing of ultra large scale integrated (ULSI) systems, including millions of submicron transistors in a single silicon chip.

Meindl, James D.; Shott, John

1987-05-01

154

VLED for Si wafer-level packaging  

NASA Astrophysics Data System (ADS)

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

155

Wafer Fusion for Integration of Semiconductor Materials and Devices  

SciTech Connect

We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

1999-05-01

156

Second-order sound field during megasonic cleaning of patterned silicon wafers: Application to ridges and trenches  

E-print Network

Second-order sound field during megasonic cleaning of patterned silicon wafers: Application MHz. The direction of propagation differs whether one cleans a single wafer or multiple wafers are processed simul- taneously. Despite the success of this technology, the actual clean- ing mechanism is still

Deymier, Pierre

157

Wafer Replacement Cluster Tool (Presentation);  

SciTech Connect

This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

Branz, H. M.

2008-04-01

158

Warpage Measurement of Thin Wafers by Reflectometry  

NASA Astrophysics Data System (ADS)

To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

Ng, Chi Seng; Asundi, Anand Krishna

159

Plasma-assisted InP-to-Si low temperature wafer bonding  

Microsoft Academic Search

The applicability of wafer bonding as a tool to integrate the dissimilar material system InP-to-Si is presented and discussed with recent examples of InP-based optoelectronic devices on Si. From there, the lowering of annealing temperature in wafer bonding by plasma-assisted bonding is the essence of this review paper. Lower annealing temperatures would further launch wafer bonding as a competitive technology

Donato Pasquariello; Klas Hjort

2002-01-01

160

Resonating microbridge mass flow sensor with low-temperature glass-bonded cap wafer  

Microsoft Academic Search

A resonating microbridge mass flow sensor has been realized suspended inside a micro flow channel. Thin-film technologies and micromachining are used for the fabrication of the sensor wafer and a cap wafer with opposing V-grooves. A low-temperature glass-bonding technique is used to assemble the wafers allowing for feedthrough of the electrical connections. Measurements show sensitivities of the resonance frequency of

Rob Legtenberg; Siebe Bouwstra; Jan H. J. Fluitman

1991-01-01

161

Virtual instrument realization of non-contact silicon wafer test  

Microsoft Academic Search

Based on virtual instrument technology, the paper conducts organic integration of capacitive displacement sensor ranging technology, eddy current sensor resistance testing technology and semiconductor P\\/N polarity of infrared pulse sensor testing technology, and develops dynamic non-contact silicon wafer testing instrument, which not only simulates the testing instruments like signal generator, digital oscilloscope, programmable power supply and digital multi-meter, but also

Yan Youjun; Li Yunfei

2009-01-01

162

Development of Megasonic cleaning for silicon wafers. Final report  

SciTech Connect

The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

Mayer, A.

1980-09-01

163

Algorithms for VLSI routing. [Very Large Scale Integration, semiconductor chip design  

SciTech Connect

This thesis considers the problems arising from VLSI routing design. Algorithms are proposed for solving both global and local routing problems. For routing multiterminal nets in the gate array and sea-of-gates technologies, the author presents a global router which upper bounds the global density of the routing by 2s*, where s* is the span of the nets. For standard cell technology, he presents a global router which achieves the optimal horizontal density while upper bounding the vertical density by 2s*. The parallel implementations of the proposed global routing algorithms are presented.

Zhou, Dian.

1990-01-01

164

Wafer characteristics via reflectometry and wafer processing apparatus and method  

DOEpatents

An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

Sopori, Bhushan L. (Denver, CO)

2007-07-03

165

Fast Inductance Extraction of Large VLSI Circuits Hemant Mahawar  

E-print Network

Fast Inductance Extraction of Large VLSI Circuits Hemant Mahawar mahawarh@cs.tamu.edu Vivek Sarin sarin@cs.tamu.edu Weiping Shi wshi@cs.tamu.edu Texas A&M University College Station, TX 77843 Abstract

Sarin, Vivek

166

Circuits for high-performance low-power VLSI logic  

E-print Network

The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and ...

Ma, Albert

2006-01-01

167

Gallium Arsenide Integrated Circuits 1988 ANZAAS Congress, VLSI Section  

E-print Network

Gallium Arsenide Integrated Circuits 1988 ANZAAS Congress, VLSI Section Anthony E. Parker are collaborating to establish a local GaAs digital integrated design and fabrication capability. Gallium Arsenide Laboratory for Communication Science and Engineering, Sydney University Electrical Engineering Gallium

168

Algorithms for VLSI Circuit Optimization and GPU-Based Parallelization  

E-print Network

This research addresses some critical challenges in various problems of VLSI design automation, including sophisticated solution search on DAG topology, simultaneous multi-stage design optimization, optimization on multi-scenario and multi...

Liu, Yifang

2010-07-14

169

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Vosen, Steven R. (Berkeley, CA)

1999-01-01

170

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

171

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?  

NASA Astrophysics Data System (ADS)

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Green, Martin A.

2014-03-01

172

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers  

NASA Astrophysics Data System (ADS)

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

173

Fine grinding of silicon wafers: a mathematical model for the chuck shape  

Microsoft Academic Search

Fine grinding of silicon wafers is a patented technology to manufacture super flat semiconductor wafers cost-effectively. Two papers on fine grinding were previously published in this journal, one discussed its uniqueness and special requirements, and the other presented the results of a designed experimental investigation. As a follow up, this paper presents a study aiming at overcoming one of the

S. Chidambaram; Z. J. Pei; S. Kassir

2003-01-01

174

Wafer fab construction cost analysis and cost reduction strategies: applications of SEMATECH's future factory analysis methodology  

Microsoft Academic Search

This paper discusses semiconductor wafer fabrication (fab) factory construction costs as they relate to emerging technologies. The generation of factories studied represents facilities supporting 200 mm wafers, and products utilizing 0.25 micron line-width geometries. An analytical approach to categorizing and evaluating fab costs is presented. A pareto analysis of four recent factories' costs is presented. The organization of fab construction

David Art; Michael O'Halloran; Brian Butler

1994-01-01

175

Analog VLSI system for active drag reduction  

SciTech Connect

In today`s cost-conscious air transportation industry, fuel costs are a substantial economic concern. Drag reduction is an important way to reduce costs. Even a 5% reduction in drag translates into estimated savings of millions of dollars in fuel costs. Drawing inspiration from the structure of shark skin, the authors are building a system to reduce drag along a surface. Our analog VLSI system interfaces with microfabricated, constant-temperature shear stress sensors. It detects regions of high shear stress and outputs a control signal to activate a microactuator. We are in the process of verifying the actual drag reduction by controlling microactuators in wind tunnel experiments. We are encouraged that an approach similar to one that biology employs provides a very useful contribution to the problem of drag reduction. 9 refs., 21 figs.

Gupta, B.; Goodman, R.; Jiang, F.; Tai, Y.C. [California Inst. of Technology, Pasadena, CA (United States)] [California Inst. of Technology, Pasadena, CA (United States); Tung, S.; Ho, C.M. [Univ. of California, Los Angeles, CA (United States)] [Univ. of California, Los Angeles, CA (United States)

1996-10-01

176

PLA realizations for VLSI state machines  

NASA Technical Reports Server (NTRS)

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

1990-01-01

177

Periodic binary sequence generators: VLSI circuits considerations  

NASA Technical Reports Server (NTRS)

Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

Perlman, M.

1984-01-01

178

Allowable silicon wafer thickness versus diameter for ingot rotation ID wafering  

NASA Technical Reports Server (NTRS)

Inner diameter (ID) wafering of ingot rotation reduce the ID saw blade diameter was investigated. The blade thickness can be reduced, resulting in minimal kerf loss. However, significant breakage of wafers occurs during the rotation wafering as the wafer thickness decreases. Fracture mechanics was used to develop an equation relating wafer thickness, diameter and fracture behavior at the point of fracture by using a model of a wafer, supported by a center column and subjected to a cantilever force. It is indicated that the minimum allowable wafer thickness does not increase appreciably with increasing wafer diameter and that fracture through the thickness rather than through the center supporting column limits the minimum allowable wafer thickness. It is suggested that the minimum allowable wafer thickness can be reduced by using a vacuum chuck on the wafer surface to enhance cleavage fracture of the center core and by using 111 ingots.

Chen, C. P.; Leipold, M. H.

1982-01-01

179

Thermomechanical global response of the EUVL wafer during exposure  

Microsoft Academic Search

Extreme ultraviolet lithography (EUVL) is one of the leading technologies for Next-Generation Lithography. Continued progress in its development will be facilitated by characterizing all sources of distortion in the chip fabrication process. These include the thermal distortions of the wafer caused by deposited EUVL energy during scanning exposure. Absorbed energy from the beam produces temperature increases and structural displacements in

Jaehyuk Chang; Carl J. Martin; Roxann L. Engelstad; Edward G. Lovell

2002-01-01

180

Comparison of EUV and optical device wafer heating  

Microsoft Academic Search

The International Technology Roadmap for Semiconductors requires improvements in resolution for each lithographic node. In essence, all sources of distortion in the chip fabrication process must be minimized to meet the stringent error budgets for the sub-90-nm nodes. These include the thermal distortions of the device wafer caused by energy deposition during exposure. Absorbed energy from the beam produces temperature

Jaehyuk Chang; Roxann L. Engelstad; Edward G. Lovell

2003-01-01

181

Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements  

E-print Network

the yield per crystal and to reduce the cost. In this paper, the vibration model of wiresaw system crystalline ingots as well as ceramic materials such as alumina. In the study and modeling of wiresaw. Introduction: Wiresaw is an emerging technology for wafer production in both photovoltaic and semiconductor

Kao, Imin

182

Development of an architectural design tool for 3-D VLSI sensors  

E-print Network

Three dimensional integration schemes for VLSI have the potential for enabling the development of new high-performance architectures for applications such as focal plane sensors. Due to the high costs involved in 3-D VLSI ...

Tyrrell, Brian (Brian Matthew)

2004-01-01

183

Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.  

PubMed

Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array. PMID:17271192

Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

2004-01-01

184

VLSI/VHSIC (Very Large Scale Integrated/Very High Speed Integrated Circuits) package test development  

NASA Astrophysics Data System (ADS)

The test methods of MIL-STD-883 were reviewed to assess their appropriateness in view of the new package styles and materials being used for VLSI/VHSIC devices. Experiments were performed to judge the effectiveness of existing tests. Changes to existing tests are proposed where deemed necessary and new tests are developed where no existing method adequately assesses new technology devices. Proposed changes and/or new package tests evaluate: solderability of leads; pin grid lead pull strength; leadless chip carrier bond strength; die attach bond analysis; characteristic impedance, capacitance, and delay time of high speed signals; crosstalk; and flip-chip pull strength.

Clark, Kay E.

1986-12-01

185

Automated routing method for VLSI with three interconnection layers  

SciTech Connect

Recently, to the extent allowed by the fabricating technology, approaches have been made to develop an automated router for the multi-layer IC layout design. This thesis examines the VLSI routing problem where three layers are available for interconnection. The author investigates the routing problem in three stages: global routing, power/ground routing, and channel routing. The global routing for the three-interconnection layer model is not much different from that of the two layer model. The global routing problem is studied for two cases: gate array and general cell layout. In the three-layer grid model, power/ground wires keep the direction-per-layer scheme as signal net wires. However, the power/ground routing is further constrained by the width of wires and the layers they are laid on. The major result presented in this dissertation is an algorithm for a channel routing problem. Given a rectangular channel with terminals on top and bottom sides, the algorithm will find a three-layer channel routing that minimizes the channel width and the wire length. Experimental results show that the router is close to optimal.

Lee, C.H.

1986-01-01

186

A VLSI architecture for high performance CABAC encoding  

NASA Astrophysics Data System (ADS)

One key technique for improving the coding e+/-ciency of H.264 video standard is the entropy coder, context- adaptive binary arithmetic coder (CABAC). However the complexity of the encoding process of CABAC is signicantly higher than the table driven entropy encoding schemes such as the Hu®man coding. CABAC is also bit serial and its multi-bit parallelization is extremely di+/-cult. For a high denition video encoder, multi-giga hertz RISC processors will be needed to implement the CABAC encoder. In this paper, we provide an e+/-cient, pipelined VLSI architecture for CABAC encoding along with an analysis of critical issues. The solution encodes a binary symbol every cycle. An FPGA implementation of the proposed scheme capable of 104 Mbps encoding rate and test results are presented. An ASIC synthesis and simulation for a 0.18 ¹m process technology indicates that the design is capable of encoding 190 million binary symbols per second using an area of 0.35 mm2. ¤

Shojania, Hassan; Sudharsanan, Subramania

2005-07-01

187

MAPPER alignment sensor evaluation on process wafers  

NASA Astrophysics Data System (ADS)

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3? std) of alignment mark readings can be achieved while being robust against various process steps.

Vergeer, N.; Lattard, L.; de Boer, G.; Couweleers, F.; Dave, D.; Pradelles, J.; Bustos, J.

2013-03-01

188

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

189

Industrial Challenges For Thin Wafer Manufacturing  

Microsoft Academic Search

Because of limited supply of Silicon, there has been an industry-driven requirement for reduction of material consumption per Wp of solar power. As a consequence, the thickness of wafers has been reduced, which in turn has introduced new challenges for the industry. During the wafer manufacturing cycle, the wafers are exposed to mechanical loads caused by sawing, manual handling, liquid

Per Arne Wang; REC Wafer

2006-01-01

190

Correlation of wafer backside defects to photolithography hot spots using advanced macro inspection  

NASA Astrophysics Data System (ADS)

Defects on the backside of a wafer during processing can come from many sources. Particles and scratches on the backsides of wafers can be caused by wafer handling equipment such as robots and chucks, as well as by CMP processes. In addition, cross-contamination of wafers and handling equipment can occur when wafers move from tool to tool, through the production line. When wafers are exposed, backside defects can cause localized areas of poor lithography pattern resolution on the frontsides of wafers, resulting in increased rework rates, decreased throughput, and yield loss. As minimum feature sizes continue to shrink with each new technology node, devices become denser and exposure tool depth of focus decreases - making the elimination of lithography hot spots an even more critical issue. At a major worldwide IDM, automated macro defect inspection tools for integrated front, edge, and backside inspection have been implemented to inspect wafers at several After Develop Inspection (ADI) and post-etch inspection steps. These tools have been used to detect foreign material and scratches on the backsides of several lots that were caused by another process tool, causing photolithography hot spots. This paper describes advanced macro inspection of wafer front and back surfaces and how the inspection data was used to correlate backside defects to photolithography hot spots, and take corrective action.

Carlson, Alan; Le, Tuan

2006-03-01

191

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Technical Reports Server (NTRS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

192

A Novel Neural Oscillatorand Its Implementationin Analog VLSI Qlang Luo John G. Harris  

E-print Network

numerical simulation. Here, we propose to use analog VLSI to build efficient, real-time simulations in the literature including work in our lab involving networks of Chua oscillators [5, 61 and a VLSI implementation present the simulated results of the VLSI implementation. 2. SINGLENEURAL OSCILLATORMODEL The relation

Harris, John G.

193

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder  

NASA Technical Reports Server (NTRS)

A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

194

1IUCEE Workshop: VLSI Design, Day 5 Today's Topic: Research Topics  

E-print Network

1IUCEE Workshop: VLSI Design, Day 5 A. Mason July 2008 ·Today's Topic: Research Topics VLSI;4IUCEE Workshop: VLSI Design, Day 5 A. Mason July 2008 Research Topics Time permitting, we can discuss my · several current research topics ·Your job now · transfer what you have learned into your lives Session 4

Mason, Andrew

195

An error decoder for the Compact Disc player as an example of VLSI programming  

Microsoft Academic Search

Using a programming language for VLSI design, called Tangram, they design a fast and simple VLSI circuit for error decoding in the Compact Disc player. The derivation of the design is straightforward and the result is succinctly expressed in less than one page of Tangram text. All design decisions are based merely on algorithmic and architectural considerations. No particular VLSI

Joep Kessels; Kees van Berkel; Ronan Burgess; Marly Roncken; F. Schalij

1992-01-01

196

A reconfigurable neuromorphic VLSI multi-chip system applied to visual motion computation  

Microsoft Academic Search

We present a multi-chip neuromorphic system in which an address event representation is used for inter-chip communication. The system comprises an analog VLSI transient imager with adaptive photoreceptors, an analog VLSI motion receiver chip and a prototyping communication infrastructure which allows for programmability of connections between the elements on the two chips. We describe the properties of the two VLSI

Giacomo Indiveri; Adrian M. Whatley; Jorg Kramer

1999-01-01

197

Low temperature wafer direct bonding  

Microsoft Academic Search

A pronounced increase of interface energy of room temperature bonded hydrophilic Si\\/Si, Si\\/SiO2, and SiO2\\/SiO 2 wafers after storage in air at room temperature, 150°C for 10-400 h has been observed. The increased number of OH groups due to a reaction between water and the strained oxide and\\/or silicon at the interface at temperatures below 110°C and the formation of

Qin-Yi Tong; Giho Cha; Roman Gafiteanu; Ulrich Gosele

1994-01-01

198

Wafer bonding of 75 mm diameter GaP to AlGaInP-GaP light-emitting diode wafers  

Microsoft Academic Search

The AlGaInP\\/GaP wafer-bonded transparent-substrate (TS) light-emitting diodes (LEDs) have been shown to exhibit luminous efficiencies\\u000a exceeding many conventional lightning sources including 60 W incandescent sources. This paper will demonstrate the feasibility\\u000a of scaling wafer bonding technology to 75 mm diameter wafers and some of the unique challenges associated with this scaling.\\u000a The quality and uniformity of bonding were characterized via

I.-H. Tan; D. A. Vanderwater; J.-W. Huang; G. E. Hofler; F. A. Kish; E. I. Chen; T. D. Ostentowski

2000-01-01

199

Position paper role of technology design rules in Design Automation  

Microsoft Academic Search

Today when VLSI is the major concern of Design Automation system designers, we must remember that size and complexity are not the only problems. This is a time of rapidly changing and evolving semiconductor process technologies, and advancements in this area make the realization of VLSI possible. The Design Automation community must recognize the severity of the problems associated with

Gayla J. Von Ehr

1983-01-01

200

Performance optimization of digital VLSI circuits  

SciTech Connect

Designers of digital VLSI circuits have virtually no computer tools available for the optimization of circuit performance. Instead, a designer relies extensively on circuit-analysis tools, such as circuit simulation (SPICE) and/or critical-delay-path analysis. A circuit-analysis approach to digital design is very labor-intensive and seldom produces a circuit with optimum area/delay or power/delay trade off. The goal of this research is to provide a synthesis approach to the design of digital circuits by finding the sizes of transistors that optimize circuits by finding the sizes of transistors that optimize circuit performance (delay, area, power). Solutions are found that are optimum for all possible delay paths of a given circuit and not for just a single path. The approach of this research is to formulate the problem of area/delay or power/delay optimization as a nonlinear program. Conditions for optimality are then established using graph theory and Kuhn-Tucker conditions. Finally, the use of augmented-Lagrangian and projected-Lagrangian algorithms are reviewed for the solution of the nonlinear programs. Two computer programs, PLATO and COP, were developed by the author to optimize CMOS PLA's (PLATO) and general CMOS circuits (COP). These tools provably find the globally optimum transistor sizes for a given circuit. Results are presented for PLA's and small- to medium-sized cells.

Marple, D.P.

1987-01-01

201

Incremental placement and routing of VLSI macrocells  

SciTech Connect

This dissertation proposes a strategy to automatically position and interconnect a set of rectangular VLSI macrocell blocks by using an integrated set of incremental algorithms. The set of tools is subdivided into three major modules - design manager, floor planner (ExPlan), and global router (MAP). Design manager is used as an interface between the database and the user to simplify the user's task of cell library management by a use of simple command language. ExPlan is used to generate a transformation matrix of given cell list and netlist by best first heuristic search mechanism. The resulting floorplan provides coordinate and orientation of each cell in the cell list with sufficient channel dimension between cells for all nets to be successfully connected and total net lengths minimized. Absolute placement and routing is performed by MAP to create a layout which minimizes overall area by incrementally compacting channels. Each rectangular channel is partitioned such that they can be routed in a predetermined sequence to eliminate the usage of a switchbox router. MAP has capability to route nets with multiple terminals as well as perform connections on standard cells. The final routed result is automatically checked against the netlist for verifying the connectivity of all nets.

Ozeki, T.

1989-01-01

202

Wafer Inspection in the Photolithography Process  

NSDL National Science Digital Library

This is a description for a learning module from Maricopa Advanced Technology Education Center. This PDF describes the module; access may be purchased by visiting the MATEC website. In this module, your learners begin to master the sensitive after develop inspection (ADI) methods that follow photolithography. MATEC describes macro- and micro-inspection techniques and distinguishes qualitative (inspection) from quantitative (metrology) methods. The chief focus is on teaching learners to examine wafers under an optical microscope; a simulated microscope is also provided in a computer-based training (CBT) format. The module covers edge bead inspection and provides extensive practice in flash boundary inspection, including evaluating Nikon crosses, overlay boxes, scanning electronic microscope features, resolution bars, Verniers, and product identification numbers.

2012-12-03

203

New fabrication method of glass packages with inclined optical windows for micromirrors on wafer level  

NASA Astrophysics Data System (ADS)

For many applications it is inevitable to protect MEMS devices against environmental impacts like humidity which can affect their performance. Moreover recent publications demonstrates that micro mirrors can achieve very large optical scan angles at moderate driving voltages even exceeding 100 degrees when hermetically sealed under vacuum. While discrete chips may be evacuated and sealed on single die level using small can packages like TO housings, it is obvious that for high volume production a much more economical solution for the realisation of transparent optical packages already on wafer level must be developed. However, since any laser beam crossing a transparent glass surface is partly reflected even when anti-reflective coatings are applied, the construction of a wafer level optical housing suitable for laser projection purpose requires more than the integration of simple plane glass cap. The use of inclined optical windows avoids the occurrence of intense reflections of the incident laser beam in the projected images. This paper describes a unique technology to fabricate glass packages with inclined optical windows for micro mirrors on 8 inch wafers. The new process uses a high temperature glass forming process based on subsequent wafer bonding. A borosilicate glass wafer is bonded together with two structured silicon wafers. By grinding both sides of the wafer stack, a pattern of isolated silicon structures is defined. This preprocessed glass wafer is bonded thereon on a third structured silicon wafer, wherein the silicon islands are inserted into the cavities. By setting a defined pressure level inside the cavities during the final wafer bonding, the silicon glass stack extruded and it is out of plane during a subsequent annealing process at temperatures above the softening point of the glass. Finally the silicon is selectively removed in a wet etching process. This technique allows the fabrication of 8 inch glass wafers with oblique optical surfaces with surface roughness <1 nm and an evenness of < 300 nm.

Stenchly, Vanessa; Quenzer, Hans-Joachim; Hofmann, Ulrich; Janes, Joachim; Jensen, Björn; Benecke, Wolfgang

2013-03-01

204

NASA Space Engineering Research Center for VLSI systems design  

NASA Technical Reports Server (NTRS)

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

1991-01-01

205

Wafer bonding for three dimensional (3D) integration  

NASA Astrophysics Data System (ADS)

Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 · Gtip · t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400°C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400°C. Thermal cycling performed at a temperature 450°C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

Kwon, Yongchai

2003-10-01

206

Characterization of wafer-level bonded hermetic packages using optical leak detection  

NASA Astrophysics Data System (ADS)

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

207

Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001  

SciTech Connect

The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.

Beetz, C.P.; Steinbeck, J.; Hsueh, K.L.

2001-03-31

208

Thin film effects in ultrasonic wafer thermometry  

Microsoft Academic Search

We use an ultrasonic technique where the temperature dependence of lowest order anti-symmetric Lamb wave velocity in the silicon wafer is utilized for in-situ temperature measurement in the 20-1000°C range. In almost all wafer processing steps, one or more layers of thin films are present on the wafers. The effects of these films on temperature sensitivity is investigated. A theoretical

F. L. Degertekin; J. Pei; B. V. Honein; B. T. Khuri-Yakub; K. C. Saraswat

1994-01-01

209

Performance Evaluations of Ceramic Wafer Seals  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

210

A multi coding technique to reduce transition activity in VLSI circuits  

NASA Astrophysics Data System (ADS)

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

Vithyalakshmi, N.; Rajaram, M.

2014-02-01

211

Realistic statistical worst-case simulations of VLSI circuits  

Microsoft Academic Search

A simple and cost-effective method for evaluating the parametric product manufacturability of VLSI circuits is presented. The method, named gradient analysis, enables designers to predict the standard deviation of the circuit performance from measured or specified design parameter variations. This method, with a minimum extra design cost, avoids the overdesign associated with the traditional prediction of the worst-case performance of

Michael Bolt; Marc Rocchi; Jan Engel

1991-01-01

212

Biophysical Neural Spiking and Bursting Dynamics in Reconfigurable Analog VLSI  

E-print Network

Biophysical Neural Spiking and Bursting Dynamics in Reconfigurable Analog VLSI Theodore Yu1 92037 Abstract--We study a range of neural dynamics under varia- tions in biophysical parameters kinetics and biophysical membrane dynamics. We present simulation and measurement results and observe

Cauwenberghs, Gert

213

CRIS: a test cultivation program for sequential VLSI circuits  

Microsoft Academic Search

This paper discusses a novel approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The approach uses hierarchical simulation technique in the analysis to drastically reduce

Daniel G. Saab; Youssef G. Saab; Jacob A. Abraham

1992-01-01

214

Why VLSI implementations of associative VLCNs require connection multiplexing  

Microsoft Academic Search

A discussion is presented of some of the implementation constraints imposed on VLSI architectures for emulations of very large connectionist\\/neural networks (VLCNs). Specifically, the authors show that multiplexing of interconnections is necessary for networks exhibiting poor locality. They show that it is more feasible to build a VLCN system with sharing or multiplexing of interconnections than to build one with

Jim Bailey; Dan Hammerstrom

1988-01-01

215

A special purpose silicon compiler for designing supercomputing VLSI systems  

NASA Technical Reports Server (NTRS)

Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

1991-01-01

216

Algorithms for the scaling toward nanometer VLSI physical synthesis  

E-print Network

Along the history of Very Large Scale Integration (VLSI), we have successfully scaled down the size of transistors, scaled up the speed of integrated circuits (IC) and the number of transistors in a chip - these are just a few examples of our...

Sze, Chin Ngai

2007-04-25

217

Thermal conduction phenomena in VLSI circuits and systems  

Microsoft Academic Search

Continuous scaling of very large scale integrated (VLSI) circuits poses severe thermal problems, which have major implications for performance and reliability in high-performance planar (2-D) integrated circuits (ICs) and emerging circuit architectures, such as vertically integrated (3-D) ICs. This dissertation aims to understand the thermal conduction phenomena from the fundamental material level to the system level and provides guidelines to

Sungjun Im

2006-01-01

218

"Seeing" in the Dark: Neuromorphic VLSI Modeling of Bat Echolocation  

E-print Network

processing using neuromorphic very large scale integration (VLSI) tech- niques and robotics have provided sensor arrays that have incredible imag- ing and localization capabilities, the question of what bats (MAV) are trying to achieve. Such devices need to operate in environments where global position- ing

Horiuchi, Timothy K.

219

Process physics determining 2-D impurity profiles in VLSI devices  

Microsoft Academic Search

Physically robust diffusion models are required to simulate two-dimensional (2D) impurity profiles in VLSI devices. The accuracy of the initial dopant profiles severely limits the predictive capability of 2D device simulators. Historically, the most successful diffusion models have been based on point defect mechanisms involving either vacancy or in terstitial assisted diffusion. It is clear that the local con centration

P. B. Griffin; J. D. Plummer

1986-01-01

220

RICE UNIVERSITY A Systolic VLSI Architecture for Complex SVD  

E-print Network

RICE UNIVERSITY A Systolic VLSI Architecture for Complex SVD by Nariankadu D. Hemkumar A Thesis. Peter J. Varman Associate Professor Electrical and Computer Engineering Dr. Dan C. Sorensen Professor and suggestions a orded by Dr. Peter J. Varman and Dr. Dan C. Sorensen and their consenting to serve on the thesis

Cavallaro, Joseph R.

221

RICE UNIVERSITY E cient VLSI Architectures for Matrix  

E-print Network

RICE UNIVERSITY E cient VLSI Architectures for Matrix Factorizations by Nariankadu D. Hemkumar Engineering Dr. Peter J. Varman Associate Professor Electrical and Computer Engineering Dr. Danny C. Sorensen way I have aided in his successful quest for tenure at Rice is but only a repayment in part

Cavallaro, Joseph R.

222

SPIDER -- A CAD System for Modeling VLSI Metallization Patterns  

Microsoft Academic Search

A system of CAD programs, called SPIDER, for ensuring adequate current-carrying capacity in VLSI circuits has been developed. The approach is hierarchical, and it automates and simplifies many of the tasks previously performed by the circuit designer. The system converts transient current waveforms into dc electromigration equivalent values, and includes an algorithm for determining the line width adjustments necessary for

Joseph E. Hall; Dale E. Hocevar; Ping Yang; Michael J. Mcgraw

1987-01-01

223

Global Routing in VLSI Design: Algorithms, Theory, and ...  

E-print Network

Dec 15, 2010 ... Global routing in VLSI (very large scale integration) design is one of the most ...... The motivation for this heuristic is that sequential routers are ..... J.M. Smith and J.H. Rubinstein Eds.), Kluwer Academic Publishers, 2000, 81-.

2010-12-15

224

CMOS VLSI Layout and Verification of a SIMD Computer  

NASA Technical Reports Server (NTRS)

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

Zheng, Jianqing

1996-01-01

225

Decentralized Fault-Tolerant Clock Pulse Generation in VLSI Chips  

E-print Network

Decentralized Fault-Tolerant Clock Pulse Generation in VLSI Chips The invention offers a solution for various problems associated with the steady increase of clock rates of chips. It offers a fault of faults; · self generation of clock pulses. Instead of globally distributing the clock produced

Szmolyan, Peter

226

Hybrid VLSI/QCA Architecture for Computing FFTs  

NASA Technical Reports Server (NTRS)

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

227

Macromodeling and Optimization of Digital MOS VLSI Circuits  

Microsoft Academic Search

Power consumption and signal delay are crucial to the design of high-performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based

Mark Douglas Matson; Lance A. Glasser

1986-01-01

228

An Interactive Multimedia Learning Environment for VLSI Built with COSMOS  

ERIC Educational Resources Information Center

This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

Angelides, Marios C.; Agius, Harry W.

2002-01-01

229

Elimination of wafer edge die yield loss for accelerometers  

Microsoft Academic Search

Residual stresses from deposition of several micron thick polysilicon film on accelerometer wafers caused wafer to warp towards edge of wafer. The average peak to valley difference for wafer flat across wafer is 16 +\\/- 1 micrometers . The photo layer following the thick polysilicon deposition process is a CD critical layer with 1 micrometers spacing to be resolved. With

Zhenjun Zhang; Kim A. Eskes

2000-01-01

230

Electrostatic Wafer Chuck for Electron Beam Microfabrication  

Microsoft Academic Search

Vacuum wafer chucks are useless for electron beam microfabrication. An analysis of the required electrostatic forces and frequency response of a specimen wafer on a field plate is made. An experimental electrostatic chuck and its high voltage square wave power supply have been fabricated. Full clamping action has been provided by electrostatic pressures of 1?6 atm, and 1 atm pressures

George A. Wardly

1973-01-01

231

Designing a mechanism to cleave silicon wafers  

E-print Network

A device was designed and manufactured to precisely cleave silicon wafers. Two vacuum chucks were designed to support a 150 mm diameter silicon wafer and cleave it by providing a pure moment at a pre-etched v-notch while ...

Figueroa, Victor, 1982-

2004-01-01

232

Wafer level packaging of silicon pressure sensors  

Microsoft Academic Search

In this paper, a new pre-packaging technique for silicon pressure sensors on the wafer level is presented. It is based on the use of UV photopatternable silicone which is deposited over the whole wafer by means of a novel device suitable for low-viscosity material coating and mask alignment. The process consists of the exposure of the deposited layer to UV

H Krassow; F Campabadal; E Lora-Tamayo

2000-01-01

233

A Sharp methodology for VLSI layout  

NASA Astrophysics Data System (ADS)

The layout problem for VLSI circuits is recognized as a very difficult problem and has been traditionally decomposed into the several seemingly independent sub-problems of placement, global routing, and detailed routing. Although this structure achieves a reduction in programming complexity, it is also typically accompanied by a reduction in solution quality. Most current placement research recognizes that the separation is artificial, and that the placement and routing problems should be solved ideally in tandem. We propose a new interconnection model, Sharp and an associated partitioning algorithm. The Sharp interconnection model uses a partitioning shape that roughly resembles the musical sharp 'number sign' and makes extensive use of pre-computed rectilinear Steiner trees. The model is designed to generate strategic routing information along with the partitioning results. Additionally, the Sharp model also generates estimates of the routing congestion. We also propose the Sharp layout heuristic that solves the layout problem in its entirety. The Sharp layout heuristic makes extensive use of the Sharp partitioning model. The use of precomputed Steiner tree forms enables the method to model accurately net characteristics. For example, the Steiner tree forms can model both the length of the net and more importantly its route. In fact, the tree forms are also appropriate for modeling the timing delays of nets. The Sharp heuristic works to minimize both the total layout area by minimizing total net length (thus reducing the total wiring area), and the congestion imbalances in the various channels (thus reducing the unused or wasted channel area). Our heuristic uses circuit element movements amongst the different partitioning blocks and selection of alternate minimal Steiner tree forms to achieve this goal. The objective function for the algorithm can be modified readily to include other important circuit constraints like propagation delays. The layout technique first computes a very high-level approximation of the layout solution (i.e., the positions of the circuit elements and the associated net routes). The approximate solution is alternately refined, objective function. The technique creates well defined sub-problems and offers intermediary steps that can be solved in parallel, as well as a parallel mechanism to merge the sub-problem solutions.

Bapat, Shekhar

1993-01-01

234

Platinum\\/palladium thin-film thermocouples for temperature measurements on silicon wafers  

Microsoft Academic Search

A platinum versus palladium thin-film thermocouple system has been established for measuring temperatures on silicon wafers in a rapid thermal processing (RTP) tool. The application includes a silicon wafer with an array of thin-film thermocouples welded to wire thermocouples, used to calibrate radiometric temperature measurements of the RTP tool. The thin-film thermocouples have advantages over present technology using wire thermocouples

Kenneth G. Kreider; Frank DiMeo

1998-01-01

235

Improvement in ability of wafer-formed cleaning material \\  

Microsoft Academic Search

To minimize particles on the back surface of wafer, the operator usually cleans the wafer chuck table regularly. We have introduced a new cleaning method with the use of our wafer-formed cleaning material called \\

N. Maruoka; Y. Terada; D. Uenda; M. Namikawa; T. Hayashi

2003-01-01

236

Wafer Probe Station, Low Noise Amplifiers, and Wideband Feed Developments  

E-print Network

-ridge flared horn wideband feeds #12;Wafer Fabrication of LNA's and Other Radiometer Components 20-Sep-2011. · Station can handle a 100mm diameter wafer with several thousand MMIC's · Motor-driven precision wafer

Weinreb, Sander

237

Desirable wafer edge flatness for CD control in photolithography  

Microsoft Academic Search

Desirable wafer edge flatness was investigated to obtain optimum free-standing wafer edge shape for photolithography. In order to obtain the criteria of free-standing edge shape, we clarified the desirable post-chuck flatness at edge sites in advance. We investigated a desirable free-standing wafer edge, taking into consideration both the wafer and wafer holder shape. Firstly, to obtain a desirable post-chuck wafer

Tadahito Fujisawa; Soichi Inoue; Tsuneyuki Hagiwara; Kodama Kennichi; Makoto Kobayashi; Katsuya Okumura

2003-01-01

238

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

Kim, Dae Jong; Yoo, Hyung Won; Kim, Chul Hong; Lee, Hak Kwon; Kim, Sung Su; Bae, Koon Ho; Spielberg, Hedvi; Lee, Yun Ho; Levi, Shimon; Bustan, Yariv; Rozentsvige, Moshe

2010-03-01

239

ALD Enabled Wafer Level Polymer Packaging for MEMS  

NASA Astrophysics Data System (ADS)

Wafer level polymer packaging for MEMS is a cost-effective approach that is also compatible with microelectronic packaging technologies. However, polymer packages are not hermetic and cannot be used for MEMS devices, which usually demand vacuum or low moisture environment inside the packages. This problem can be solved by applying atomic layer deposition (ALD) of nano-scaled Al 2O3 or other inorganic materials over the polymer packages. Defects and mechanical cracks in ALD coatings are major concerns for hermetic/vacuum sealing. Several techniques have been developed to inspect such defects and cracks. Assisted by the electroplating copper technique, we have reduced the defect density by 1000 times for an ultra-thin, 2-nm ALD Al2O 3 film. Such an ultra-thin coating is essential to enhance coating's mechanical toughness. The toughness is usually determined by monitoring coating's crack initiation and growth in a bending test. A real-time, non-destructive inspection technique has been developed for in-situ characterization of an ALD film coated on a surface or buried in a multilayer structure. With the knowledge and technology established, we have successfully demonstrated a wafer-level polymer packaging process for MEMS using a Pirani gauge as the vacuum sensor. The leak rate through the polymer package has been reduced by 100 times by the ALD Al2O3 coating. More importantly, we have developed models and identified issues that are critical to ALD-enabled wafer level polymer packaging for MEMS.

Zhang, Yadong

240

Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm  

E-print Network

This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.

Wladyslaw Szczesniak

2008-01-07

241

Effect of annealing of multi crystalline edge wafers and Cz mono crystalline wafers based on metallurgical silicon  

Microsoft Academic Search

The objective of this study has been to investigate the effect of annealing of multi crystalline edge wafers and Cz mono crystalline wafers based on metallurgically refined silicon. Sets of neighboring wafers have been annealed at different temperatures and compared with as cut wafers as well as P-gettered wafers. The wafers have been characterized by ?-PCD, QSSPC, FeB-pair splitting and

Arve Holt; Birger RetterstllJl Olaisen; Erik Enebakk; Anne-Karin Soiland

2008-01-01

242

Development of megasonic cleaning for silicon wafers  

NASA Technical Reports Server (NTRS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-01-01

243

Opto-VLSI-based tunable single-mode fiber laser.  

PubMed

A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature. PMID:20372600

Xiao, Feng; Alameh, Kamal; Lee, Tongtak

2009-10-12

244

Noise-margin limitations on gallium-arsenide VLSI  

NASA Technical Reports Server (NTRS)

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Long, Stephen I.; Sundaram, Mani

1988-01-01

245

Systolic VLSI and FPGA Realization of Artificial Neural Networks  

Microsoft Academic Search

\\u000a Systolic architectures are established as a widely popular class of VLSI structures for repetitive and computation-intensive\\u000a applications due to the simplicity of their processing elements (PEs), modularity of design, regular and nearest neighbor\\u000a interconnections between the PEs, high-level of pipelinability, small chip-area and low-power consumption. In systolic arrays,\\u000a the desired data is pumped rhythmically in a regular interval across the

Pramod Kumar Meher

246

Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture  

Microsoft Academic Search

A low-power VLSI processor architecture that com- putes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adap- tive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a

Karim Abdelhalim; Vadim Smolyakov; Roman Genov

2011-01-01

247

Micromachined jets for liquid impingement cooling of VLSI chips  

Microsoft Academic Search

Two-phase microjet impingement cooling is a potential solution for removing heat from high-power VLSI chips. Arrays of microjets promise to achieve more uniform chip temperatures and very high heat transfer coefficients. This paper presents the design and fabrication of single-jets and multijet arrays with circular orifice diameters ranging from 40 to 76 ?m, as well as integrated heater and temperature

Evelyn N. Wang; Lian Zhang; Linan Jiang; Jae-Mo Koo; James G. Maveety; Eduardo A. Sanchez; Kenneth E. Goodson; Thomas W. Kenny

2004-01-01

248

X-ray holography for VLSI using synthetic bilevel holograms  

Microsoft Academic Search

The gains are pointed out of the potential replacement of the usual patterned transmission x-ray mask, in consideration of high-resolution proximity lithography for VLSI, by a diffraction element, or bilevel in-line hologram, to be projected under near-field conditions using synchrotron radiation. The hologram can be configured to correct for diffraction blurring due to projection, and be designed for pre-determined gaps

Ronald E. Burge; Joachim Knauer; Xiaocong Yuan; Keith Powell

1997-01-01

249

Parallel Random Number Generation for VLSI Systems Using Cellular Automata  

Microsoft Academic Search

A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in parallel from various cells in the cellular automaton on each

Peter D. Hortensius; Robert D. Mcleod; Howard C. Card

1989-01-01

250

VLSI interconnects and their testing: prospects and challenges ahead  

Microsoft Academic Search

Purpose – The purpose of this paper is to explore the functioning of very-large-scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects. Design\\/methodology\\/approach – In the past, on-chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring-up of on-chip devices takes place through various conductors produced during fabrication process.

D. K. Sharma; B. K. Kaushik; R. K. Sharma

2011-01-01

251

VLSI designs for redundant binary-coded decimal addition  

Microsoft Academic Search

A binary-coded decimal system provides rapid binary-decimal conversion. However, BCD arithmetic operations are often slow and require complex hardware. One can eliminate the need for carry propagation and thus improve performance of BCD operations by using a redundant binary-coded decimal (RBCD) system. The VLSI design of an RBCD adder is introduced. The design consists of two small PLAs and two

B. Shirazi; D. Y. Y. Yun; C. N. Zhang

1988-01-01

252

Spike-Driven Synaptic Plasticity: Theory, Simulation, VLSI Implementation  

Microsoft Academic Search

We present a model for spike-driven dynamics of a plastic synapse, suited for aVLSI implementation. The synaptic device behaves as a capacitor on short timescales and preserves the memory of two stable states (efficacies) on long timescales. The transitions (LTP\\/LTD) are stochastic because both the number and the distribution of neural spikes in any finite (stimula- tion) interval fluctuate, even

Stefano Fusi; Mario Annunziato; Davide Badoni; Andrea Salamon; Daniel J. Amit

2000-01-01

253

ELID supported grinding of thin sapphire wafers  

NASA Astrophysics Data System (ADS)

Sapphire material is, due to its crystal structure, difficult to machine in an economic way. There is a request for thin, i.e. below 0.2 mm thickness, sub surface damage free wafers to produce sensor elements. ELID -- electrolytic in process dressing -- is an innovative high end grinding technology, using small grain sizes, which enable to manufacture surfaces in a quality that is close to polished. ELID grinding requires exactly aligned machining parameters of the grinding process. To grind sapphire the material's behavior is additionally to be considered. Studies on the necessary oxide layer on the grinding wheel and influences on its build-up process will be presented. The presentation shows the results of comparing grinding experiments on different -- c-plane and r-plane -- sapphire materials. Different tool specifications are used. Infeed and grinding velocity are varied and the results on wear, removal rate and surface quality are shown. The process parameters the stiffness of the machine, the grinding forces and pressure are evaluated. The ELID grinding is compared in its results to conventional grinding steps. The material removal rate on sapphire is relatively small due to the extreme hardness of sapphire. The achieved excellent surface roughness will be discussed.

Makarenko, Igor; Vogt, Christian; Rascher, Rolf; Sperber, Peter; Stirner, Thomas

2010-10-01

254

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

2012-11-29

255

vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM  

ERIC Educational Resources Information Center

This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

2014-01-01

256

Fabrication of wafer-level thermocompression bonds  

Microsoft Academic Search

Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding. The fabrication process for wafer bonding at 300°C via compressing gold under 7 MPa of pressure is described in detail. One of the issues encountered in the process development was e-beam source spitting, which resulted in micrometer diameter sized Au on the surfaces, and made bonding

Christine H. Tsau; S. M. Spearing; M. A. Schmidt

2002-01-01

257

Transient thermal analysis of sapphire wafers subjected to thermal shocks  

Microsoft Academic Search

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed

T. Vodenitcharova; L. C. Zhang; I. Zarudi; Y. Yin; H. Domyo; T. Ho

2006-01-01

258

A novel wafer baking system using hot air streams  

Microsoft Academic Search

This paper presents a novel wafer baking system that uses hot air streams as heating media and achieves good temperature uniformity across the entire wafer surfaces during the baking process. Wind tunnel experiments have been carried out to verify the concept of using hot air streams for wafer baking. A simple prototyping wafer baking system has been designed and fabricated,

Lan Wang; Siew Loong Chow; Ai Poh Loh; Zhi Ming Gong; Woei Wan Tan; Arthur E. B. Tay; Weng Khuen Ho

2004-01-01

259

Analog VLSI implementation of spatio-temporal frequency tuned visual motion algorithms  

Microsoft Academic Search

The computation of local visual motion can be accomplished very efficiently in the focal plane with custom very large-scale integration (VLSI) hardware. Algorithms based on measurement of the spatial and temporal frequency content of the visual motion signal, since they incorporate no thresholding operation, allow highly sensitive responses to low contrast and low-speed visual motion stimuli. We describe analog VLSI

Charles M. Higgins; Vivek Pant; Rainer Deutschmann

2005-01-01

260

A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh  

E-print Network

A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh JosC G. Delgado University of New York Binghamton, NY 13902-6000 Abstract A VLSI implementation of a programmable router schemefor parallel interconnectionnetwork architectures is presented in this paper. The router executes

Nyathi, Jabulani

261

Fast Computation of Temperature Profiles of VLSI ICs with High Spatial Resolution  

Microsoft Academic Search

The reality of high temperature non-uniformity has become a serious concern in the CMOS VLSI industry limiting both the performance and the reliability of packaged chips. Thus the surface temperature profile of VLSI ICs has become critical information in chip design flow. for fast computation of surface temperature profile, power blurring (PB) method has been developed. This method can be

Je-Hyoung Park; Xi Wang; Ali Shakouri; Sung-Mo Kang

2008-01-01

262

A conic section function network synapse and neuron implementation in VLSI hardware  

Microsoft Academic Search

An analogue VLSI design which computes radial basis function (RBF) and multilayer perceptron (MLP) propagation rules on a single chip is proposed to form a conic section function network (CSFN) synapse and neuron. This novel VLSI circuit has been designed to compute both the dot product (weighted sum) for MLP and the Euclidean distance for RBF. These two propagation rules

Tiilay YILDIRIM; John S. MARSLAND

1996-01-01

263

A NEW TEST METRIC AND A NEW SCAN ARCHITECTURE FOR EFFICIENT VLSI TESTING  

E-print Network

A NEW TEST METRIC AND A NEW SCAN ARCHITECTURE FOR EFFICIENT VLSI TESTING A DISSERTATION SUBMITTED. To overcome the difficulty and cost of VLSI testing, we need to search for better testing techniques. Chip testing can be classified into two categories: production testing and characterization testing

Stanford University

264

Parallel algorithms and VLSI architectures for stack filtering using Fibonacci p-codes  

Microsoft Academic Search

A parallel decompositional algorithm and VLSI architecture is proposed for computation of the output of a stack filter over a single window of input samples using Fibonacci p-codes. For a subclass of positive Boolean functions, a more efficient parallel algorithm and VLSI architecture for running stack filtering is also presented. The area-time complexities of the proposed designs are estimated

David Z. Gevorkian; K. O. Egiazarian; S. S. Agaian; J. T. Astola; O. Vainio

1995-01-01

265

Algorithm partition for a fixed-size VLSI architecture using space-time domain expansion  

Microsoft Academic Search

The space-time domain expansion method has recently been used to transform a computational task with a recursive formula into a VLSI architecture. In addition to its simplicity and completeness, an important advantage of this method is that it can easily solve the problem of partitioning an algorithm to fit a fixed size VLSI architecture. We propose a computational model and

H. D. Cheng; K. S. Fu

1985-01-01

266

A VLSI Reed-Solomon decoder architecture for concatenate-coded space and spread spectrum communications  

NASA Technical Reports Server (NTRS)

In this paper, a VLSI Reed-Solomon (RS) decoder architecture for concatenate-coded space and spread spectrum communications, is presented. The known decoding procedures for RS codes are exploited and modified to obtain a repetitive and recursive decoding technique which is suitable for VLSI implementation and pipeline processing.

Liu, K. Y.

1983-01-01

267

A Memory Aware Behavioral Synthesis Tool for Real-Time VLSI Circuits  

E-print Network

A Memory Aware Behavioral Synthesis Tool for Real-Time VLSI Circuits Gwenol´e Corre, Eric Senn the mem- ory architecture and the memory mapping in the Behav- ioral Synthesis of Real-Time VLSI circuits. We formalize the memory mapping as a set of constraints for the syn- thesis, and defined a Memory

Paris-Sud XI, Université de

268

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits  

E-print Network

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits Harish in the circuit. In 1 , the algorithm was demonstrated for simple gate delay and current models. In this paper, we Abstract Excessive voltage drops in power and ground P&G buses of CMOS VLSI circuits can severely degrade

Najm, Farid N.

269

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits  

E-print Network

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits Harish in the circuit. In [1], the algorithm was demonstrated for simple gate delay and current models. In this paper Abstract Excessive voltage drops in power and ground (P&G) buses of CMOS VLSI circuits can severely degrade

Najm, Farid N.

270

EEE 5322 VLSI Circuits and Technology 1. Catalog Description -(3 credit hours) Introduction to VLSI circuit technology and  

E-print Network

can result in missing materials tested on exams. Cell phones and other electronic devices. Publication date and edition - 2nd Edition, Modular Series on Solid State Devices, Volume 5, Prentice Hall d Implantation 2, Diffusion 1, Chap. 4.1, 4.2, 4.3, 4.4, 4.5, 4.6 of Jaeger Week 3: Diffusion 2, Oxidation 1

Fang, Yuguang "Michael"

271

Packaging solution for VLSI electronic photonic chips  

E-print Network

As the demand of information capacity grows, the adoption of optical technology will increase. The issue of resistance and capacitance is limiting the electronic transmission bandwidth while fiber optic delivers data at ...

Lee, Chieh-feng

2007-01-01

272

ARPA\\/CSTO rapid VLSI implementation  

Microsoft Academic Search

The task objective was to provide rapid access to cost effective, state-of-the-art U.S. microelectronics industry fabrication technology for DoD customers and the educational community. This access was provided through the establishment of a prototyping service for use by the DARPA and NSF research communities which offered access to a variety of technologies unobtainable from a single fabrication source. The Defense

Cesar A. Pina

1993-01-01

273

Detection of Metal Contamination on Silicon Wafer Backside and Edge by New TXRF Methods  

NASA Astrophysics Data System (ADS)

In conventional 200 mm wafer processing, backside defects are not considered to be of much concern because they are obscured by wafer backside topography. However, in current 300 mm wafer processing where both sides of a wafer are polished, backside defects require more consideration. In the beginning, backside defect inspection examined particle contamination because particle contamination adversely influences the depth of field in lithography. Recently, metal contamination is of concern because backside metal contamination causes cross-contamination in a process line, and backside metals easily transfer to the front surface. As the industry strives to yield more devices from the area around the wafer edge, edge exclusion requirements have also become more important. The current International Technology Roadmap for Semiconductors [1] requires a 2 mm edge exclusion. Therefore, metal contamination must be controlled to less than 2 mm from the edge because metal contamination easily diffuses in silicon wafers. To meet these current semiconductor processing requirements, newly developed zero edge exclusion TXRF (ZEE-TXRF) and backside measurement TXRF (BAC-TXRF) are effective metrology methods.

Kohno, Hiroshi; Yamagami, Motoyuki; Formica, Joseph; Shen, Liyong

2009-09-01

274

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays  

NASA Technical Reports Server (NTRS)

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

2009-01-01

275

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

276

Wafer-level colinearity monitoring for TFH applications  

NASA Astrophysics Data System (ADS)

Advances in thin film head (TFH) designs continue to outpace those in the IC industry. The transition to giant magneto resistive (GMR) designs is underway along with the push toward areal densities in the 20 Gbit/inch2 regime and beyond. This comes at a time when the popularity of the low-cost personal computer (PC) is extremely high, and PC prices are continuing to fall. Consequently, TFH manufacturers are forced to deal with pricing pressure in addition to technological demands. New methods of monitoring and improving yield are required along with advanced head designs. TFH manufacturing is a two-step process. The first is a wafer-level process consisting of manufacturing devices on substrates using processes similar to those in the IC industry. The second half is a slider-level process where wafers are diced into 'rowbars' containing many heads. Each rowbar is then lapped to obtain the desired performance from each head. Variation in the placement of specific layers of each device on the bar, known as a colinearity error, causes a change in device performance and directly impacts yield. The photolithography tool and process contribute to colinearity errors. These components include stepper lens distortion errors, stepper stage errors, reticle fabrication errors, and CD uniformity errors. Currently, colinearity is only very roughly estimated during wafer-level TFH production. An absolute metrology tool, such as a Nikon XY, could be used to quantify colinearity with improved accuracy, but this technique is impractical since TFH manufacturers typically do not have this type of equipment at the production site. More importantly, this measurement technique does not provide the rapid feedback needed in a high-volume production facility. Consequently, the wafer-fab must rely on resistivity-based measurements from slider-fab to quantify colinearity errors. The feedback of this data may require several weeks, making it useless as a process diagnostic. This study examines a method of quickly estimating colinearity at the wafer-level with a test reticle and metrology equipment routinely found in TFH facilities. Colinearity results are correlated to slider-fab measurements on production devices. Stepper contributions to colinearity are estimated, and compared across multiple steppers and stepper generations. Multiple techniques of integrating this diagnostic into production are investigated and discussed.

Moore, Patrick; Newman, Gary; Abreau, Kelly J.

2000-06-01

277

Formal specification and verification of hierarchical VLSI design  

SciTech Connect

Hierarchical design is widely accepted as a most-efficient method to deal with the complexity of a VLSI design. The author presents a new specification language to fully support a hierarchical design at functional levels and investigate a verification method to use a mathematical proving for the consistency in a hierarchy instead of a simulation. In supporting a hierarchical design, this language addresses three major concerns: a module as a single entity, a module body as a decomposition result, and the mapping to relate a module body. A generalized specification model is developed and supporting language constructs are discussed. The expressive power and versatility of a language is demonstrated by various examples.

Huh, Y.

1986-01-01

278

Using wafer stacks as neutron monochromators  

NASA Astrophysics Data System (ADS)

A process to introduce a spatially homogeneous but anisotropic mosaic structure into thin, single-crystal wafers, which are then stacked and used as neutron monochromators, is described. The advantages compared to conventional techniques are good reproduceability, low cost and reduced risk of process failure. A focusing Ge(115) monochromator made from 24 wafer stacks was built for the high-resolution neutron powder diffractometer at the High Flux Beam Reactor at Brookhaven National Laboratory. Besides building "classical" monochromators for elastic neutron scattering experiments, individual wafers with a given peak reflectivity can be tilted with respect to each other to increase the reflected wavelength band ??/?. Such "fanned" arrays present a competitive alternative to monochromators using highly-oriented pyrolitic graphite (HOPG).

Vogt, T.; Passell, L.; Cheung, S.; Axe, J. D.

1994-01-01

279

Biocompatible "click" wafer bonding for microfluidic devices.  

PubMed

We introduce a novel dry wafer bonding concept designed for permanent attachment of micromolded polymer structures to surface functionalized silicon substrates. The method, designed for simultaneous fabrication of many lab-on-chip devices, utilizes a chemically reactive polymer microfluidic structure, which rapidly bonds to a functionalized substrate via"click" chemistry reactions. The microfluidic structure consists of an off-stoichiometry thiol-ene (OSTE) polymer with a very high density of surface bound thiol groups and the substrate is a silicon wafer that has been functionalized with common bio-linker molecules. We demonstrate here void free, and low temperature (< 37 °C) bonding of a batch of OSTE microfluidic layers to a silane functionalized silicon wafer. PMID:22760578

Saharil, Farizah; Carlborg, Carl Fredrik; Haraldsson, Tommy; van der Wijngaart, Wouter

2012-09-01

280

Experimental study of restructurable VLSI techniques  

E-print Network

available a design methodology that gives the designer great flexibility and product per- formance at low costs [2]. In order to make this This thesis follows the format of the PROCEEDINGS OF THE IEEE. possible, additional equipment such as a laser, X.../or ROS (read-only storage) in digital system design. Technological progress which tends to allow extremely small geometries has reached the point where large arrays are physically realizable. These arrays represent sufficient means of implementing...

Fanini, Otto Nilson

2012-06-07

281

Making Porous Luminescent Regions In Silicon Wafers  

NASA Technical Reports Server (NTRS)

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

282

Comparison of surface roughness of polished silicon wafers measured by light scattering topography, soft-x-ray scattering, and atomic-force microscopy  

Microsoft Academic Search

Chemomechanically polished silicon wafers are used in a wide range of technologies. In many of these applications, the desired properties are influenced by the Si surface mor- phology. Improvement of polishing methods to increase Si wafer surface quality has been a continuing goal of silicon manufacturers. Among the various methods used for the characterization of microroughness, light scattering topogra- phy

C. Teichert; J. F. Mackay; D. E. Savage; M. G. Lagally; M. Brohl; P. Wagner

1995-01-01

283

A NOVEL METHOD FOR ACHIEVING VERY LOW COPS IN CZ WAFERS  

Microsoft Academic Search

INTRODUCTION: As the IC industry moves toward development of future technology nodes and application of new materials, more innovation is required at the wafer substrate level. The silicon-on-insulator (SOI) technology will be a key factor in extending planar CMOS technologies beyond sub-50nm gate sizes. Many of the process and materials constrains facing continuous device scaling are relaxed or removed for

J. L. Vasat; T. Torack

284

Logic verification and test generation for VLSI circuits  

SciTech Connect

This dissertation focuses on efficient test-pattern generation, efficient redundancy identification, and efficient logic verification for scan-testable VLSI circuits. For logic verification, applicable circuits also include non-scan-testable VLSI circuits for which correspondence of memory elements between two-verified circuits can be established. New approaches to solving these problems and the systems implementing these approaches are presented. For efficient test-pattern generation of multi-level combinational circuits, a new front-end heuristic test pattern generator, VICTOR-III, a new line-justification algorithm for the D-algorithm and its derivatives, DIJUST, and a method for test-set compaction, BUSIM, are presented. MAHJONG, a user-configurable automatic test-pattern generation system employing these techniques was developed. For efficient redundancy identification, a system of three programs: VICTOR-III, TRIP, and TAUT, to be executed in that order, is presented. The set of faults is gradually classified into the set of irredundant faults and truly redundant faults through the introduction of potentially redundant faults. For efficient logic verification, PROTEUS, a system of many logic verification programs, mostly based on newly developed algorithms, is presented. Direct comparison of these programs is performed and many important conclusions are drawn.

Wei, R.

1986-01-01

285

Testing interconnected VLSI circuits in the Big Viterbi Decoder  

NASA Technical Reports Server (NTRS)

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.

1991-01-01

286

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing  

NASA Technical Reports Server (NTRS)

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Aanstoos, J. V.; Snyder, W. E.

1981-01-01

287

Technology advances in wideband packet switching  

Microsoft Academic Search

The authors examine some recent technology advances in the evolution of wideband packet technology (WPT). These advances include contention resolution in WPT switch fabrics, GaAs implementation of WPT switch fabric, and packet processing in trunk interfaces. It is concluded that WPT architectures are ideally suited for aggressive incorporation in advanced VLSI technology particularly for the implementation of the core of

A. K. Vaidya; M. A. Pashan

1988-01-01

288

A microneedle-based glucose monitor: fabricated on a wafer-level using in-device enzyme immobilization  

Microsoft Academic Search

This paper presents a disposable minimally invasive self-calibrating continuous glucose monitor consisting of hollow out-of-plane microneedles to sample interstitial fluid from the epidermis, an integrated porous poly-Si dialysis membrane and an integrated enzyme-based flow-through glucose sensor. The proposed system can be fabricated on a wafer-level using standard MEMS technology and a novel in-device enzyme immobilization technique that allows wafer-level patterning

Stefan Zimmermann; Doerte Fienbork; Boris Stoeberb; Albert W. Flounders; Dorian Liepmann

2003-01-01

289

Microcantilever Probe Cards With Silicon and Nickel Composite Micromachining Technique for Wafer-Level Burn-In Testing  

Microsoft Academic Search

A new type of probe card is designed and fabricated for wafer-level integrated circuit (IC) testing. Using micromachining technology, roughly 18000 cantilever-tip probes can be integrated in one 4-in wafer, with a minimum pitch of 90 mum for adjacent probing tips. The probe card employs a silicon-and-metal composite structure, in which the bulk-micromachined silicon cantilever arrays provide uniform probing height

Fei Wang; Xinxin Li; Songlin Feng

2009-01-01

290

Apparatus for edge etching of semiconductor wafers  

NASA Technical Reports Server (NTRS)

A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

Casajus, A.

1986-01-01

291

Wafer Bonded Subwavelength Metallo-Dielectric Laser  

E-print Network

core radius) operating at 77 K, as well as near-subwavelength (450-nm gain core radius) operating compatible active optical components is critical for creating integrated silicon photonic circuits that include integration of the optical gain material with a silicon-on-insulator (SOI) wafer,

Fainman, Yeshaiahu

292

4600 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 24, NO. 12, DECEMBER 2006 Silicon Photonics  

E-print Network

(VLSI), silicon photonics must be compatible with the economics of silicon manufacturing and must as a catalyst by raising awareness to this new technology. This led to increased level of investments by large

Jalali. Bahram

293

Study on Board Level Drop Reliability of Wafer Level Chip Scale Package with Leadfree Solder  

Microsoft Academic Search

Wafer level chip scale package (WLCSP) is a promising packaging technology to accommodate the demand for small, portable handheld electronic. This bare-die bumped package is able to offer significant area savings, improve package electrical parasitics and power dissipation performance over substrate-based BGA packages. However, its board level reliability especially mechanical performance under shock impact is a great concern for handheld

Zhang Xueren; Zhu Wenhui; P. Edith; Tan Hien Boon

2008-01-01

294

The Simulation and Forecast Model for Human Resources of Semiconductor Wafer Fab Operation  

Microsoft Academic Search

The efficiency of fabrication (fab) operation is one of the key factors in order for a semiconductor manufacturing company to stay competitive. Optimization of manpower and forecasting manpower needs in a modern fab is an essential part of the future strategic planing and a very important to the operational efficiency. As the semiconductor manufacturing technology has entered the 8-inch wafer

Gwo-Hshiung Tzeng; Chun-Yen Chang; Mei-Chen Lo

2005-01-01

295

Geometry control of recrystallized silicon wafers for solar applications  

E-print Network

The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

Ruggiero, Christopher W

2009-01-01

296

Study on Homogeneous Wafer Level Dielectric Film Preparation Using Chemical Solution Deposition Method  

NASA Astrophysics Data System (ADS)

Process parameters of lead zirconate titanate thin film preparation using metal organic decomposition method were optimized by a statistical method and their effects on the film properties were investigated quantitatively in this study. The crystallization temperature and the precursor formation temperature were found to be important factors for high quality thin films. We also investigated the films deposited on the 4-in. wafer under the optimum conditions and found that it exhibited great film properties. Furthermore, the process damage to the wafer sample by photolithography was clarified experimentally. The results will be useful for the fabrication of the MEMS devices and integration technology of electrical devices including piezoelectric films.

Sueshige, Kazutaka; Ichiki, Masaaki; Suga, Tadatomo; Itoh, Toshihiro

2013-06-01

297

On the chemo-mechanical polishing for nano-scale surface finish of brittle wafers.  

PubMed

Chemo-mechanical polishing (CMP) has been a common method to produce nano-scale surface finish of brittle wafers. This paper provides a relatively comprehensive review on the CMP of silicon, silicon carbide and sapphire including both patents and papers. The discussion includes the limitations and further research directions of the CMP technology, the material removal mechanisms, and the control and optimization of the CMP for brittle wafers. The paper concluded that the usage of mix- or coated- abrasives may improve the CMP in terms of less subsurface damage and higher material removal rate. PMID:20415661

Wang, Y G; Zhang, L C

2010-06-01

298

Fundamental characteristics of electrostatic wafer chuck with insulating sealant  

Microsoft Academic Search

In the semiconductor industry, many manufacturing processes, such as CVD or dry etching, are performed in vacuum condition. The electrostatic wafer chuck is the most preferable handling method under such circumstances. It enables retention of a wafer flat and enhanced heat transfer through the whole surface area because the wafer can firmly contact with the chuck. We have investigated the

Kyoko YATSUZUKA; Fumikazu HATAKEYAMA; Kazutoshi ASANO; Shinichiro AONUMA

1998-01-01

299

Experimental investigation and finite element analysis of bump wafer probing  

Microsoft Academic Search

The purpose of this paper is to analyze the bump height variation and probe mark profile with various bump materials for wafer probing. It is necessary to establish different material bump wafer probing criteria, because the bump height variation and probe mark area have severe influence on the sort flip chip wafers that will affects the quality of the contact

Hao-Yuan Chang; Wen-Fung Pan; Meng-Kai Shih; Yi-Shao Lai

2009-01-01

300

Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)  

SciTech Connect

A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

Rupnowski, P.; Sopori, B.

2008-05-01

301

Graphic script provides quick classification of GaAs wafers  

Microsoft Academic Search

Infrared transmission topography has long been used to detect variations in gallium arsenide wafers that can cause dark-line defects that limit lifetime of GaAs lasers and solar cells. In the past, infrared transmission was measured over a whole wafer by scanning a small spot mechanically. Absorption was calculated at each location across the surface of the wafer and used to

Millard G. Mier

2000-01-01

302

In-situ ultrasonic thermometry of semiconductor wafers  

Microsoft Academic Search

We report a temperature measurement technique based on the temperature dependence of acoustic wave velocity in silicon wafers. The zeroth order antisymmetric Lamb wave is excited in the wafer using the quartz pins which support the wafer during processing. Extensional waves are generated in the quartz pin by a PZT-SH transducer and the acoustic energy is coupled to the Lamb

F. L. Degertekin; J. Pei; Y. J. Lee; B. T. Khuri-Yakub; K. C. Saraswat

1993-01-01

303

Multivariable feedback relevant system identification of a wafer stepper system  

Microsoft Academic Search

This paper discusses the approximation and feedback relevant parametric identification of a positioning mechanism present in a wafer stepper. The positioning mechanism in a wafer stepper is used in chip manufacturing processes for accurate positioning of the silicon wafer on which the chips are to be produced. The accurate positioning requires a robust and high-performance feedback controller that enables a

Raymond A. de Callafon; Paul M. J. Van den Hof

2001-01-01

304

Room temperature wafer level glass\\/glass bonding  

Microsoft Academic Search

The findings of this study report the bonding of glass\\/glass wafers by using the surface activated bonding (SAB) method at room temperature (RT) without heating. In order to bond, the glass wafers were activated by a sequential plasma activation process, in which the wafers were cleaned with reactive ion etching (RIE) oxygen radio frequency (rf) plasma and nitrogen radical microwave

M. M. R. Howlader; Satoru Suehara; Tadatomo Suga

2006-01-01

305

Integratible process for fabrication of fluidic microduct networks on a single wafer  

NASA Astrophysics Data System (ADS)

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 mm, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectric materials.

Matzke, Carolyn M.; Ashby, Carol I. H.; Bridges, Monica M.; Griego, Leonardo; Wong, C. Channy

1999-08-01

306

Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer  

SciTech Connect

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

1999-09-07

307

Voltage and Timing Adaptation for Variation and Aging Tolerance in Nanometer VLSI Circuits  

E-print Network

Process variations and circuit aging continue to be main challenges to the power-efficiency of VLSI circuits, as considerable power budget must be allocated at design time to mitigate timing variations. Modern designs incorporate adaptive techniques...

Shim, Kyu-Nam 1978-

2012-09-10

308

Novel on chip-interconnection structures for giga-scale integration VLSI ICS  

NASA Astrophysics Data System (ADS)

Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

Nelakuditi, Usha R.; Reddy, S. N.

2013-01-01

309

DFT-Based SoC\\/VLSI IP Protection and Digital Rights Management Platform  

Microsoft Academic Search

In this paper, the author proposes a novel testing-based system-on-a-chip (SoC)\\/very large scale integration (VLSI) intellectual property (IP) identification and protection platform in SoC\\/VLSI design. The principles are established for the development of a new IP identification, protection procedures, and a digital rights management system that depends on the current IP-based design flow. This platform can successfully survive synthesis, placement,

Yu-Cheng Fan; Jan-Hung Shen

2009-01-01

310

An Extensible Object-Oriented Approach to Databases for VLSI\\/CAD  

Microsoft Academic Search

This paper describes an approach to the specification and modeling of information associated with the design and evolution of VLSI components. The approach is characterized by combined structural and behavioral descriptions of a component. Database modeling requirements specific to the VLSI design domain are considered and techniques t.o address them are described. An extensible object-oriented information management framework, the 3DIS

Hamideh Afsarmanesh; Dennis Mcleod; David Knapp; Alice C. Parker

1985-01-01

311

A Convolutional Neural Network VLSI for Image Recognition Using Merged\\/Mixed Analog-Digital Architecture  

Microsoft Academic Search

Abstract: Hierarchical convolutional neural networks,are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power con- sumption,is required. This paper proposes a VLSI convolutional network architecture using a hybrid approach,composed,of pulse-width modulation (PWM) and digital circuits. We call this approach merged\\/mixed,analog-digital architecture.

Keisuke Korekado; Takashi Morie; Osamu Nomura; Hiroshi Ando; Teppei Nakano; Masakazu Matsugu; Atsushi Iwata

2003-01-01

312

A VLSI convolutional neural network for image recognition using merged\\/mixed analog-digital architecture  

Microsoft Academic Search

Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power con- sumption is required. This paper proposes a VLSI convolutional network architecture using a hybrid approach composed of pulse-width modulation (PWM) and digital circuits. We call this

Keisuke Korekado; Takashi Morie; Osamu Nomura; Hiroshi Ando; Teppei Nakano; Masakazu Matsugu; Atsushi Iwata

2004-01-01

313

Face position detection by a convolutional neural network using an image filtering processor VLSI  

Microsoft Academic Search

Image filtering with large receptive-field area is essential for brain-like vision systems. The typical processing model using such filtering is convolutional neural networks (CoNNs). The CoNNs are a well-known robust image-recognition processing model, which imitates the vision nerve system in the brain. To realize such image processing, we have developed an image-filtering processor VLSI. The VLSI designed using a 0.35 ?m

Keisuke Korekado; Takashi Morie; Osamu Nomura; Teppei Nakano; Masakazu Matsugu; Atsushi Iwata

2006-01-01

314

Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon wafers  

E-print Network

Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon microscopy, profilometer and wafer bow measurements. Plasma-activated direct bonding of DOI wafers to thermal September 2010 Keywords: Diamond-on-insulator Plasma activation Ultrananocrystalline diamond Direct bonding

Akin, Tayfun

315

Development of GaN wafers via the ammonothermal method  

NASA Astrophysics Data System (ADS)

This paper reviews the current progress of ammonothermal growth at SixPoint Materials and discusses some of the remaining challenges to commercialize the technology. The mass production of the ammonothermal grown wafers of GaN for high power devices has substantial commercial potential but is currently limited by two problems: impurities which lead to semitransparent coloration and stress in the crystals which leads to cracking. To improve the coloration, it is important to understand and reduce the impurities in the crystal. Oxygen impurities were found to be the primary source of coloration. By reducing the oxygen impurities the absorption coefficient at 450 nm was improved to 3.9 cm-1 yielding semitransparent crystals. The second and more serious issue is a cracking that occurs when thick boules are produced. Currently we routinely produce ammonothermal growth over a millimeter in thickness without any cracking. However, as the thickness increases cracks develop. From a production viewpoint, the production of thick crystals is beneficial since it allows a single wafer to be processed into many. By improving a variety of parameters, the crack density was reduced and the maximum crack-free growth increased from 1 mm to 2.6 mm.

Letts, Edward; Hashimoto, Tadao; Hoff, Sierra; Key, Daryl; Male, Keith; Michaels, Mathew

2014-10-01

316

Opto-VLSI-based reconfigurable photonic RF filter  

NASA Astrophysics Data System (ADS)

Radio frequency (RF) signal processors based on photonics have several advantages, such as broadband capability, immunity to electromagnetic interference, flexibility, and light weight in comparison to all-electronics RF filters. It still requires innovative research and development to achieve high-resolution reconfigurable photonic RF signal processors featuring high selectivity, resolution, wide tunability, and fast reconfigurability. In this paper, we propose and experimentally demonstrate the concept of a reconfigurable photonic RF filter structure integrating an Amplified Spontaneous Emission (ASE) source, an Opto-VLSI processor that generates arbitrary phase-only steering and multicasting holograms for wavelength selection and attenuation, arrayed waveguide gratings (AWGs) for waveband multiplexing and demultiplexing, high-dispersion fibres for RF delay synthesis, and a balanced photodetector for generating positive and negative processor weights. Independent control of the weights of a reconfigurable photonic RF filter is experimentally demonstrated.

Xiao, Feng; Shen, Mingya; Juswardy, Budi; Alameh, Kamal

2009-08-01

317

Efficient VLSI Architecture for Training Radial Basis Function Networks  

PubMed Central

This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

Fan, Zhe-Cheng; Hwang, Wen-Jyi

2013-01-01

318

A novel VLSI architecture for pixel purity index algorithm  

NASA Astrophysics Data System (ADS)

The Pixel Purity Index (PPI) algorithm is one of the most successful algorithms for hyperspectral image endmembers extraction. But it has high computational complexity so it is hard to meet the real-time processing demands of some onboard application. In this paper, we present a novel Very-Large-Scale Integration (VLSI) architecture for PPI algorithm to meet the on-board demands. With parallelism and improved I/O communication strategy, our implementation is significantly time saving than other architectures in the same hardware resources. We evaluate our implementation using the well-known "Cuprite" scene and assess endmembers signature purity using the U.S. Geological Survey (USGS) library. It demonstrates that our hardware implementation can get endmembers in less processing time to meet the onboard demands.

Yi, Fang; Guo, Jie; Li, Yunsong; Huang, Bormin

2013-09-01

319

Spike-driven synaptic plasticity: theory, simulation, VLSI implementation.  

PubMed

We present a model for spike-driven dynamics of a plastic synapse, suited for aVLSI implementation. The synaptic device behaves as a capacitor on short timescales and preserves the memory of two stable states (efficacies) on long timescales. The transitions (LTP/LTD) are stochastic because both the number and the distribution of neural spikes in any finite (stimulation) interval fluctuate, even at fixed pre- and postsynaptic spike rates. The dynamics of the single synapse is studied analytically by extending the solution to a classic problem in queuing theory (Takacs process). The model of the synapse is implemented in aVLSI and consists of only 18 transistors. It is also directly simulated. The simulations indicate that LTP/LTD probabilities versus rates are robust to fluctuations of the electronic parameters in a wide range of rates. The solutions for these probabilities are in very good agreement with both the simulations and measurements. Moreover, the probabilities are readily manipulable by variations of the chip's parameters, even in ranges where they are very small. The tests of the electronic device cover the range from spontaneous activity (3-4 Hz) to stimulus-driven rates (50 Hz). Low transition probabilities can be maintained in all ranges, even though the intrinsic time constants of the device are short (approximately 100 ms). Synaptic transitions are triggered by elevated presynaptic rates: for low presynaptic rates, there are essentially no transitions. The synaptic device can preserve its memory for years in the absence of stimulation. Stochasticity of learning is a result of the variability of interspike intervals; noise is a feature of the distributed dynamics of the network. The fact that the synapse is binary on long timescales solves the stability problem of synaptic efficacies in the absence of stimulation. Yet stochastic learning theory ensures that it does not affect the collective behavior of the network, if the transition probabilities are low and LTP is balanced against LTD. PMID:11032032

Fusi, S; Annunziato, M; Badoni, D; Salamon, A; Amit, D J

2000-10-01

320

Fracture of GaAs Wafers  

Microsoft Academic Search

Fracture characteristics of undoped and several kinds of doped GaAs single-crystal wafers were studied. The fracture toughness value determined by four-point bending fracture test of specimens precracked by indentation at room temperature showed no difference for In-, Si-, Cr- and undoped crystals. Indentation microcracking characteristics of In-, Si- and undoped crystals and probability distribution functions of the fracture stresses of

Kiyoshi Yasutake; Yoshito Konishi; Kaoru Adachi; Kumayasu Yoshii; Masataka Umeno; Hideaki Kawabe

1988-01-01

321

Precipitating Chromium Impurities in Silicon Wafers  

NASA Technical Reports Server (NTRS)

Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

Salama, A. M.

1982-01-01

322

Advanced Modelling of Silicon Wafer Solar Cells  

NASA Astrophysics Data System (ADS)

Modelling of solar cells today is general practice in research and widely-used in industry. Established modelling software is typically limited to one dimension and/or to small scales. Additionally, novel effects, like, e.g., the use of diffractive structures or luminescent materials, are not established. In this paper we discuss how the combination of different modelling techniques can be used to overcome these limitations. In this context two examples are presented. The first example concerns the combination of the open source simulation software PC1D with circuit modelling to investigate the effect of local shunts on the global characteristics of a silicon wafer solar cell. For the investigated example (4.5 cm2 cell area) we find that a local point shunt reduces the solar cell efficiency by 4% relative. The second example concerns the modelling of diffractive gratings for thin silicon wafer solar cells. For this purpose, we use the rigorous coupled wave analysis to simulate Sentaurus technical computer-aided design (TCAD) is combined with the rigorous coupled wave analysis, a method to solve Maxwell's equations for periodic structures. Here we show that a grating can be used to improve the absorption in a thin silicon wafer solar cell considerably.

Peters, Marius; Fajun, Ma; Siyu, Guo; Hoex, Bram; Blaesi, Benedikt; Glunz, Stefan; Aberle, Armin; Luther, Joachim

2012-10-01

323

Optical characterization of SiC wafers  

SciTech Connect

Raman spectroscopy has been used to investigate wafers of both 4H-SiC and 6H-SiC. The two-phonon Raman spectra from both 4H- and 6H-SiC have been measured and found to be polytype dependent, consistent with changes in the vibrational density of states. They have observed electronic Raman scattering from nitrogen defect levels in both 4H- and 6H-SiC at room temperature. They have found that electronic Raman scattering from the nitrogen defect levels is significantly enhanced with excitation by red or near IR laser light. These results demonstrate that the laser wavelength is a key parameter in the characterization of SiC by Raman scattering. These results suggest that Raman spectroscopy can be used as a noninvasive, in situ diagnostic for SiC wafer production and substrate evaluation. They also present results on time-resolved photoluminescence spectra of n-type SiC wafers.

Burton, J.C.; Pophristic, M.; Long, F.H.; Ferguson, I.

1999-07-01

324

Decoupling bulk- and surface-limited lifetimes in thin kerfless silicon wafers using spectrally resolved transient absorption pump-probe spectroscopy and computer simulations  

E-print Network

One of the key technological objectives to further decrease the cost of silicon (Si) PV and enable manufacturing of crystalline silicon is to improve the quality of thin, kerfless Si wafers to monocrystalline equivalent. ...

Siah, Sin Cheng

2013-01-01

325

Knowledge-based synthesis of custom VLSI router software. [Very Large Scale Integration  

SciTech Connect

This thesis describes a synthesis architecture for automatic generation of technology-sensitive VLSI physical design tools from high-level specifications. Physical design refers to the process of reducing a structural description of a piece of hardwater down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The author argues that the appropriate place for technology-dependent information is not in the run-time environment of such tools, but in a generator for these tools. They describe a synthesis architecture and its prototype implementation - called ELF - that integrates knowledge of the application domain with knowledge of generic programming mechanics. ELF strives to meet the demands of the target technology by automatically generating an implementation of the tool to match the application requirements. The ELF synthesis architecture has three key features. First, a very high level language, lacking data structure implementation specifications, is used to describe algorithm design styles. Second, application domain knowledge and generic program synthesis knowledge are used to guide search among candidate design styles for all necessary component algorithms, and to deduce compatible data structure implementations for these components. Third, code generation is used to transform the resulting abstract descriptions of selected algorithms and data structures into final, executable code. Code generation is an incremental, stepwise refinement process, and also relies on application domain knowledge, as well as generic program synthesis knowledge. A wide variety of fully-functional routers has been synthesized by ELF, and verified on both synthetic and industrial routing benchmarks. ELF demonstrates a synthesis architecture that efficiently generates router software using router domain-specific and generic program synthesis knowledge as a synthesis guide.

Setliff, D.E.

1989-01-01

326

Investigation of VLSI Bipolar Transistors Irradiated with Electrons, Ions and Neutrons for Space Application  

NASA Astrophysics Data System (ADS)

A systematic investigation of radiation effects on a BICMOS technology manufactured by STM has been undertaken. Bipolar transistors were irradiated by neutrons, C, Ar and Kr ions, and recently by electrons. Fast neutrons, as well as other types of particles, produce defects mainly by displacing silicon atoms from their lattice positions to interstitial locations, i.e. generating vacancy-interstitial pairs (the so-called Frenkel pairs). Although imparted doses differ largely, the experimental results indicate that the gain (?) variation is mostly related to the non-ionizing energy-loss (NIEL) deposition for neutrons, ions and electrons. The variation of the inverse of the gain degradation, ?(1/?), is found to be linearly related (as predicted by the Messenger-Spratt equation for neutron irradiations) to the concentrations of the Frenkel pairs generated independently of the kind of incoming particle. For space applications, this linear dependence on the concentration of Frenkel pairs allows to evaluate the total amount of the gain degradation of VLSI components due to the flux of charged particles during the full life of operation of any pay-load. In fact, the total amount of expected Frenkel pairs can be estimated taking into account the isotopic spectra. It has to be point out that in cosmic rays there is relevant flux of electrons and isotopes up to Ni, which are within the range of particles presently investigated.

D'Angelo, P.; Fallica, G.; Galbiati, A.; Mangoni, R.; Modica, R.; Pensotti, S.; Rancoita, P. G.

2006-04-01

327

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003 627 VLSI Architectures for SISO-APP Decoders  

E-print Network

VLSI Architectures for SISO-APP Decoders Mohammad M. Mansour, Student Member, IEEE, and Naresh R and implementation complexities of high-speed, low-power soft-input soft-output (SISO) a posteriori probability (APP-known recursion bottleneck of the SISO-APP algorithm. This paper provides a rigorous analysis of the requirements

Shanbhag, Naresh R.

328

CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.  

PubMed

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits. PMID:19086836

Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

2009-01-01

329

High density circuit technology, part 1  

NASA Technical Reports Server (NTRS)

The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

Wade, T. E.

1982-01-01

330

Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins  

NASA Astrophysics Data System (ADS)

Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

Müller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

2014-04-01

331

Characterization of mirror-polished silicon wafers by Makyoh method  

NASA Astrophysics Data System (ADS)

Makyoh, the "Magic Mirror" is a very useful tool with which to visualize local irregularities of the surface of a mirror-like polished silicon wafer. Using the Makyoh method, bright and dark spots are visible in the image of wafers projected on an instrument screen. However, these spots have not yet been correlated to specific defects on a wafer surface. First, local convex-type defects on the mirror-like surface of silicon wafers are observed with Makyoh, a flatness tester and other micro surface measurement systems. Next, we report our attempts to create actrual convex and concave shapes on silicon wafer surfaces by intentionally varying polishing conditions, and which shapes are observed. We also discuss the relationship between silicon wafer flatness and the Makyoh magic mirror image.

Tokura, Seitaro; Fujino, Nobukatsu; Ninomiya, Masaharu; Masuda, Kenji

1990-06-01

332

A VLSI Self-Compacting Bu er for DAMQ Communication Switches Jos e G. Delgado-Frias and Richard Diaz  

E-print Network

A VLSI Self-Compacting Bu er for DAMQ Communication Switches Jos e G. Delgado-Frias and Richard-6000 Abstract This paper describes a novel VLSI CMOS imple- mentation of a self-compacting bu er SCB data regions within the input bu er for each output channel. The proposed implementation pro- vides

Delgado-Frias, José G.

333

Wafer-scale aluminum nano-plasmonics  

NASA Astrophysics Data System (ADS)

The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

2014-09-01

334

Wafer bonding of gallium arsenide on sapphire  

Microsoft Academic Search

\\u000a $1\\\\overline{1} 02$  ) sapphire in a micro-cleanroom at room temperature under hydrophilic or hydrophobic surface conditions. Subsequent heating\\u000a up to 500 °C increased the bond energy of the GaAs-on-sapphire (GOS) wafer pair close to the fracture energy of the bulk material.\\u000a The bond energy was measured as a function of the temperature. Since the thermal expansion coefficients of GaAs and sapphire\\u000a are close to

P. Kopperschmidt; G. Kästner; S. Senz; D. Hesse; U. Gösele

1997-01-01

335

Product assurance technology efforts: Technical accomplishments  

NASA Technical Reports Server (NTRS)

Product assurance technology topics addressed include: wafer acceptance procedures, test chips, test structures, test chip methodology, fault models, and the Combined Release and Radiation Effects Satellite test chip.

1985-01-01

336

Technology trends in microcomputer control of electrical machines  

Microsoft Academic Search

A comprehensive review of technology trends in microcomputer control of electrical machines is presented. Although microcomputer control and computer-aided design techniques are the main themes of discussion, motion control as multidisciplinary technology has been reviewed in the broad perspective of electrical machines, power semiconductor devices, converter technology, microcomputers, and VLSI circuits. The concepts discussed are valid not only for small

B. K. Bose

1988-01-01

337

Micro-miniature gas chromatograph column disposed in silicon wafers  

DOEpatents

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, Conrad M. (Antioch, CA)

2000-01-01

338

Field-Programmable Smart-Pixel Arrays: Design, VLSI Implementation, and Applications  

NASA Astrophysics Data System (ADS)

A smart-pixel array is a two-dimensional array of optoelectronic devices that combine optical inputs and outputs with electronic processing circuitry. A field-programmable smart-pixel array (FP-SPA) is a smart-pixel array capable of having its electronic functionality dynamically programmed in the field. Such devices could be used in a diverse range of applications, including optical switching, optical digital signal processing, and optical image processing. We describe the design, VLSI implementation, and applications of a first-generation FP-SPA implemented with the 0.8- m complementary metal-oxide semiconductor self-electro-optic effect device technology made available through the Lucent Technologies Advanced Research Projects Agency Cooperative (Lucent ARPA COOP) program. We report spice simulations and experimental results of two sample applications: In the first application, we configure this FP-SPA as an array of free-space optical binary switches that can be used in optical multistage networks. In the second, we configure the device as an optoelectronic transceiver for a dynamically reconfigurable free-space intelligent optical backplane called the hyperplane. We also describe the testing setup and the electrical and the optical tests that demonstrate the correct functionality of the fabricated device. Such devices have the potential to reduce significantly the need for custom design and fabrication of application-specific optoelectronic devices in the same manner that field-programmable gate arrays have largely eliminated the need for custom design and fabrication of application-specific gate arrays, except in the most demanding applications.

Sherif, Sherif S.; Griebel, Stefan K.; Au, Albert; Hui, Dennis; Szymanski, Ted H.; Hinton, H. Scott

1999-02-01

339

A VLSI decomposition of the deBruijn graph  

NASA Technical Reports Server (NTRS)

A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

Collins, O.; Dolinar, S.; Mceliece, R.; Pollara, F.

1990-01-01

340

Integrated CAD framework linking VLSI layout editors and process simulators  

NASA Astrophysics Data System (ADS)

As feature sizes in VLSI circuits extend into the far sub-micron range, new process techniques, such as using phase shifted masks for photolithography, will be needed. Under these conditions, the only means for the circuit designer to design compact and efficient circuits with good yield capabilities is to be able to see the effect of different design approaches on manufactured silicon, instead of solely relying on conservative general design rules. The integrated CAD framework accomplishes this by providing a link between a layout editor (Magic), advanced photolithographic techniques such as phase shifted masks, and a process simulator (Depict). This paper discusses some applications of this tool. A non- conventional process technique involving interferometric phase shifting and off-axis illumination has been evaluated using the tool. Also, a feature of the CAD framework which allows representation of a phase shifted mask, together with its layout analysis capability has been used to compact a piece of layout by inserting phase shifted elements into it.

Sengupta, Chaitali; Erdelyi, Miklos; Bor, Zsolt; Cavallaro, Joseph R.; Smayling, Michael C.; Szabo, Gabor; Tittel, Frank K.; Wilson, William L., Jr.

1996-06-01

341

Fabrication of miniaturized fluidic devices using SU8 based lithography and low temperature wafer bonding  

Microsoft Academic Search

In this paper, we present a technology for the batch-fabrication of fluidic devices which combines polymer and metal layers. The structures are fabricated by means of two-layer lithography and SU-8-based wafer bonding technique. The combination of SU-8 and metal layers allows the fabrication of “2(1\\/2)”-dimensional fluidic structures. We realized different types of micromixers for the investigation of chemical reactions by

P. Svasek; E. Svasek; B. Lendl; M. Vellekoop

2004-01-01

342

TECHNICAL NOTE: Deep etching of glass wafers using sputtered molybdenum masks  

NASA Astrophysics Data System (ADS)

This note presents a simple, low-cost technology to fabricate very deep isotropically etched features in glass wafers. A process based on fast etching glass combined with a stress-optimized molybdenum mask layer and a photoresist was found to be very suitable for such purposes. The obtained performance, up to 1.2 mm deep etching, rivals the best existing techniques while being more cost-competitive and using widely available equipment.

Ceyssens, Frederik; Puers, Robert

2009-06-01

343

Drop impact life prediction model for wafer level chip scale packages  

Microsoft Academic Search

The demand for small, portable handheld electronic devices has led OEMs to reduce packaging sizes of all types and to create many choices to meet market demand. Wafer-level chip scale package (WL-CSP) is the newest technology to compete with CSP and near-CSP packaging, and has evolved under JEDEC MO-211 standard. This bare-die bumped package is able to reduce single-gate logic

Kim Yong Goh; Jing-en Luan; Tong Yan Tee

2005-01-01

344

A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations  

Microsoft Academic Search

\\u000a Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to\\u000a robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a\\u000a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose a VLSI\\u000a architecture based on this algorithm. We have designed and

Osamu Nomura; Takashi Morie; Masakazu Matsugu; Atsushi Iwata

2005-01-01

345

Fundamental characteristics of electrostatic wafer chuck with insulating sealant  

Microsoft Academic Search

The electrostatic wafer chuck is the most preferable handling method in advanced semiconductor manufacture. Even in a vacuum environment, it enables not only the ability to retain a wafer flat, but also to enhance heat transfer through the whole surface area because of firm contact. We have investigated the fundamental characteristics of an electrostatic chuck consisting of a pair of

Kyoko Yatsuzuka; Fumikazu Hatakeyama; Kazutoshi Asano; Shinichiro Aonuma

2000-01-01

346

FEA Thermal Investigation of Wafer Thinning by Plasma Etching  

Microsoft Academic Search

In this work, finite element analysis (FEA) was used to predict transient heating and temperature distribution on the wafer surface during plasma etching process as backgrind (BG) tape degradation after plasma stress relief was observed. The wafer surface temperature during plasma process was measured using temperature indicator strips and used as input temperature for FEA analysis. Parametric studies were performed

Foo Lam Wong; Radimin; M. Teo; C. Lee

2006-01-01

347

Submicron defect detection standard for patterned wafer inspection systems  

Microsoft Academic Search

Automated defect detection equipment have been used extensively for patterned wafer inspection in the semiconductor industry. These systems are used to find a variety of patterning and process defects on silicon wafers, before device completion, so that action may be directed toward eliminating the cause of the defects. The method of detection that each type of inspection system uses varies

Daniel V. Grelinger

1992-01-01

348

Alternative facility layouts for semiconductor wafer fabrication facilities  

Microsoft Academic Search

Semiconductor wafer fabrication facilities are widely acknowledged to be among the most complicated industrial systems from a production planning and control point of view. The design of most wafer fabrication facilities has followed the process layout, where similar machines are located together. This feeds to complex, reentrant product flows through the facility. In this paper, we examine the effects on

Christopher D. Geiger; Rieko Hase; Christos G. Takoudis; Reha Uzsoy

1997-01-01

349

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Selwyn, Gary S. (Los Alamos, NM)

1998-01-01

350

ORIGINAL ARTICLE Wafer-scale fabricated thermo-pneumatically tunable  

E-print Network

ORIGINAL ARTICLE Wafer-scale fabricated thermo-pneumatically tunable microlenses Wei Zhang, Hans on polyacrylate membranes integrated with compact on-chip thermo-pneumatic actuation fabricated using full Keywords: optofluidics; thermo-pneumatic actuation; tunable microlens; wafer-scale fabrication INTRODUCTION

Cai, Long

351

Piezoelectric Wafer Active Sensor Embedded Ultrasonics in Beams and Plates  

E-print Network

Piezoelectric Wafer Active Sensor Embedded Ultrasonics in Beams and Plates by V. Giurgiutiu, J. Bao and experimental investigation of the fun- damental aspects of using piezoelectric wafer active sensors (PWASs of these results to in situ structural health monitoring using embedded ultrasonics. KEY WORDS--Piezoelectric

Giurgiutiu, Victor

352

Wafer-Scale Microtensile Testing of Thin Films  

Microsoft Academic Search

This paper reports on the mechanical characterization of thin films using the microtensile technique performed for the first time at the wafer scale. Multiple test structures are processed and sequentially measured on the same silicon substrate, thus eliminating delicate handling of individual samples. The current layout uses 26 test structures evenly distributed over a 4-in wafer, each of them carrying

JoÃo Gaspar; Marek E. Schmidt; Jochen Held; Oliver Paul

2009-01-01

353

Heterodyne polarimetry for measuring critical dimensions on semiconductor wafers  

Microsoft Academic Search

A new optical technique based on heterodyne polarimetry is developed for fast measurement of critical dimensions on semiconductor wafers, particularly on those of memory chips. Sub-wavelength periodical structure of a sample acts as a wire-grid polarizer, making both the amplitude and phase of the reflected laser beam dependent on geometrical dimensions and optical properties of the wafer pattern. The heterodyne

Vladimir V. Protopopov

2008-01-01

354

Development and implementation of an automated wafer transport system  

Microsoft Academic Search

The move to 300 mm wafers has prompted IC manufacturers to demand a reliable automated material handling system (AMHS). Hewlett Packard's Inkjet Supplies Business Unit has worked with a supplier to develop a system using overhead rails and vehicles with hoist mechanisms to perform direct-to-tool delivery of 200 mm podded wafers. The system is intended to increase throughput by providing

J. Sikich

1998-01-01

355

Piezoresistive stress sensors on (110) silicon wafers  

NASA Technical Reports Server (NTRS)

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

1992-01-01

356

A novel wafer baking system using hot air streams  

NASA Astrophysics Data System (ADS)

This paper presents a novel wafer baking system that uses hot air streams as heating media and achieves good temperature uniformity across the entire wafer surfaces during the baking process. Wind tunnel experiments have been carried out to verify the concept of using hot air streams for wafer baking. A simple prototyping wafer baking system has been designed and fabricated, and experiments of the baking process have been conducted. Good temperature uniformity across the wafer surface has been achieved. The experimental results match well with the computer fluid dynamics (CFD) simulation results. It is observed that the velocity of the airflow has significant influence on the temperature transient responses. Further optimization of the parameters of the baking system and analytical modelling studies are currently under way.

Wang, Lan; Chow, Siew Loong; Loh, Ai Poh; Gong, Zhi Ming; Tan, Woei Wan; Tay, Arthur E. B.; Ho, Weng Khuen

2004-05-01

357

Approaching new metrics for wafer flatness: an investigation of the lithographic consequences of wafer non-flatness  

NASA Astrophysics Data System (ADS)

Flatness of the incoming silicon wafer is one major contributor to the ultimate focusing limitation of modern exposure tools. Exposure tools are designed to chuck wafers without creating non-flatness and then use focus control to follow as closely as possible the chucked wafer front surface topography. The smaller size of the exposure slit in a step-and-scan exposure tool, as compared to the previous generation full-field stepper tool, helps minimize the impact of chucked wafer non-flat topography. However, to maintain high throughput and improve critical dimension uniformity (CDU) at sub-wavelength line-widths requires continuous improvement in the incoming silicon wafer flatness. In this paper we report extensive experimental results that review existing wafer flatness metrics and propose the addition of a new metric. The new metric emulates the scanning motion of exposure by integrating the defocus that each point on the wafer experiences during exposure. We show that this method is in better spatial agreement with measured defocus in step-and-scan exposure tools. Simple metrics of moving average (MA) defocus prediction analysis will be defined and shown to correlate very well to post exposure defocus data. These experiments were enabled by the creation of special 300-nm wafers by MEMC. These special wafers include sites with a wide variation in flatness. Prior to exposure the wafers were measured with a high-resolution optical flatness metrology tool (WaferSight by ADE) to obtain industry standard thickness variation (flatness) data. Incoming wafer flatness data is used to predict wafer suitability for lithography at the desired device geometry node (e.g., 90 nm). The flatness data was processed and characterized using both standard metrics (SFQR) and the new MA analysis. The relationship between the industry standard metric (SFQR) and similar metrics applied to MA analysis will be presented. Full two-dimensional maps are used to present spatial correlations and permit simple physical insights into the flatness data sets. Measurements of chucked wafer flatness were made on the same wafers using ASML TWINSCAN in-line metrology. These measurements correlate very well to thickness-based flatness. Un-chucked wafer flatness metrics (SFQR and MA) are shown to correlate well to post exposure defocus data when an appropriate site size is used. This result is discussed in relationship to the industry-accepted practice of specifying un-chucked wafer flatness. Lithography performance tests were made to prove the relevance of the different flatness metrics. The same special wafers are used for lithography performance tests. These tests achieve excellent correlation between post-exposure full-wafer focus control results and predictions based on both SFQ (industry standard) and MA re-mapping of the flatness data. The relationship between measured critical dimension (CD) and defocus is also explored. Point-by-point analysis of CD residual versus measured defocus data nicely follows a Bossung curve. We also show that residual CD values predicted from defocus correlate well with measured values. These experiments confirm the application of industry standard wafer flatness measurements to step-and-scan lithography when appropriately using current metrics. They also present the potential for improved metrics based on the MA defocus prediction analysis to help drive continuous improvement of wafer flatness for advanced step-and-scan lithography.

Valley, John F.; Poduje, Noel; Sinha, Jaydeep; Judell, Neil; Wu, Jie; Boonman, Marc; Tempelaars, Sjef; van Dommelen, Youri; Kattouw, Hans; Hauschild, Jan; Hughes, William; Grabbe, Alexis; Stanton, Les

2004-05-01

358

The investigation on research opportunities for the applications of the Internet of Things in semiconductor wafer fabrication  

Microsoft Academic Search

Based on the state-of-the-art technologies of the Internet of Things (IOT) and Radio Frequency Identifier (RFID) this paper introduces the concepts of IOT\\/RFID and investigates its open research opportunity and potential applications in real-time monitoring and dispatch controls for semiconductor wafer fabrication (FAB).

Yong-Zai Lu

2010-01-01

359

Top-down fabricated silicon-nanowire-based field-effect transistor device on a (111) silicon wafer.  

PubMed

The unique anisotropic wet-etching mechanism of a (111) silicon wafer facilitates the highly controllable top-down fabrication of silicon nanowires (SiNWs) with conventional microfabrication technology. The fabrication process is compatible with the surface manufacturing technique, which is employed to build a nanowire-based field-effect transistor structure on the fabricated SiNW. PMID:23143874

Yu, Xiao; Wang, Yuchen; Zhou, Hong; Liu, Yanxiang; Wang, Yi; Li, Tie; Wang, Yuelin

2013-02-25

360

A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.  

PubMed

This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time. PMID:24110095

Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

2013-01-01

361

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

362

VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design  

E-print Network

VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design Saraju P of a Secure Digital Still Camera Several software based watermarking schemes have been presented camera that includes a watermarking module in Fig. 1, and call such a camera as a "secure digital still

Mohanty, Saraju P.

363

VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication  

E-print Network

VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication and security mechanism for images produced by it. Since the proposal of the trustworthy digital camera Watermarking Unit Flash Memory Compression Unit Encryption Unit Fig. 1. Secure digital camera for image

Mohanty, Saraju P.

364

VLSI ARCHITECTURE FOR ENCRYPTION AND WATERMARKING UNITS TOWARDS THE MAKING OF A SECURE CAMERA  

E-print Network

VLSI ARCHITECTURE FOR ENCRYPTION AND WATERMARKING UNITS TOWARDS THE MAKING OF A SECURE CAMERA O. B and architecture in the framework of a digital cam- era, conceptualized as a "Secure Digital Camera (SDC)". The SDC uses watermarking and encryption processes for image security and authentication. The Rijndael AES

Mohanty, Saraju P.

365

Biophysical Synaptic Dynamics in an Analog VLSI Network of Hodgkin-Huxley Neurons  

E-print Network

Biophysical Synaptic Dynamics in an Analog VLSI Network of Hodgkin-Huxley Neurons Theodore Yu1--We study synaptic dynamics in a biophysical net- work of four coupled spiking neurons implemented from a biophysical origin basis for the model implementation of the neurons and synapses coupled

Cauwenberghs, Gert

366

System Implementations of Analog VLSI Velocity Sensors Giacomo Indiveri, Jorg Kramer and Christof Koch  

E-print Network

of analog VLSI velocity sensors for detecting the focus of expansion, time to contact and motion dis of magnitude in light irradiance have been proposed 13, 11 . These sensors being extremely compact, we for the rotational component of motion using lateral accelerometer measurements from other sensors often already

367

Compact real-time 2-D gradient-based analog VLSI motion sensor  

Microsoft Academic Search

In this work we present the first working focal plane analog VLSI sensor for the spatially resolved computationof the 2-D motion field based on temporal and spatial derivatives. Using an adaptive CMOS photoreceptor thetemporal derivative and a function of the spatial derivative of the local light intensity are computed. By multiplyingthese values separately for both spatial dimensions a vector is

Rainer A. Deutschmann; Christof Koch Walter Schottky

1998-01-01

368

A New VLSI Architecture of a Hierarchical Motion Estimator for Low Bit-Rate Video Coding  

Microsoft Academic Search

We propose a new hierarchical motion estimator architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a systematic and small sized motion estimator. Also, since the memory bank of the proposed architecture

Jae Hun Lee; Sung Deuk Kim; Sung Kyu Jang; Jong Beom Ra

1999-01-01

369

A bitonic-sorter based VLSI implementation of the M-algorithm  

Microsoft Academic Search

An implementation of the M-algorithm based on a bitonic sorter is proposed for VLSI implementation. The sorting network is already proven. The sorting architecture is well matched to the use of a few high-speed pipelined path extender units. Such units are highly specific to the trellis being decoded, but it is generally possible to fit several on one chip. The

Stanley J. Simmons

1989-01-01

370

CAN SPIKE TIMING DEPENDENT PLASTICITY COMPENSATE FOR PROCESS MISMATCH IN NEUROMORPHIC ANALOGUE VLSI?  

E-print Network

? Katherine Cameron and Alan Murray School of Engineering and Electronics The University of Edinburgh Edinburgh, EH9 3JL, UK k.l.cameron@sms.ed.ac.uk, alan.murray@ee.ed.ac.uk ABSTRACT Analogue VLSI can be used

Cameron, Katherine

371

Analog VLSI motion projects at Caltech Jorg Kramer and Giacomo Indiveri  

E-print Network

in automotive navigation, robot- ics, and remote sensing require devices for processing visual motion compact analog VLSI motion sensors that compute the 1-D velocity of optical stimuli over a large range and are suitable for integration in fo- cal plane arrays. They have been extensively tested and optimized

372

ECE/CS 5710/6710 Digital VLSI Design Guest Lecture  

E-print Network

on design validation: Simulation, coverage metrics, property verification, model checking, among others.. 5-understanding, incorrect modeling, oversight... ­ How to ascertain validity of the specs? ­ Simulate (randomly and Verification fit-in? · Validation v/s Verification v/s Testing 3 #12;VLSI Circuit Realization Process

Kalla, Priyank

373

Designing VLSI Network Nodes to Reduce Memory Traffic in a Shared Memory Parallel Computer  

Microsoft Academic Search

Serialization of memory access can be a critical bottleneck in shared memory parallel computers. The NYU Ultracomputer, a large-scale MIMD (Multiple Instruction stream, Multiple Data stream) shared memory architec- ture, may be viewed as a column of processors and a column of memory modules connected by a rectangular net- work of enhanced two by two buffered crossbars. These VLSI nodes

Susan Dickey; Allan Gottlieb; Richard Kenner; Yue-Sheng Liu

1986-01-01

374

ANALOG VLSI DESIGN OF MULTI-PHASE VOLTAGE DOUBLERS WITH FREQUENCY REGULATION  

E-print Network

ANALOG VLSI DESIGN OF MULTI-PHASE VOLTAGE DOUBLERS WITH FREQUENCY REGULATION Fengjing Qiu, Janusz A show that the output voltage is 3.995 times the power supply. By using the frequency regulator@bobcat.ent.ohiou.edu ABSTRACT This paper proposes a new organization of charge pump circuits based on a voltage doubler [2

Starzyk, Janusz A.

375

To appear in IEEE Transactions on VLSI Systems 1 Dynamic Voltage and Frequency Scheduling  

E-print Network

To appear in IEEE Transactions on VLSI Systems 1 Dynamic Voltage and Frequency Scheduling@ceng.usc.edu). Abstract-- An adaptive method to perform dynamic voltage and frequency scheduling (DVFS) for minimizing, the proposed DVFS system makes use of adaptive update intervals for optimal frequency and voltage scheduling

Pedram, Massoud

376

An effective congestion-based integer programming model for VLSI global routing  

Microsoft Academic Search

Global routing is a fundamental problem in VLSI physical design in which approximate paths for the interconnect (wires) of a circuit are decided. In this paper, a fast, order-free global routing technique is proposed by formulating the global routing problem as an integer linear programming (ILP) problem. A small set of high quality trees, in terms of congestion and length,

Laleh Behjat; Andy Chiang; Logan Rakai; Jianhua Li

2008-01-01

377

AdOpt: Analog VLSI Stochastic Optimization for Adaptive Optics Marc Cohen Mikhail Vorontsov  

E-print Network

AdOpt: Analog VLSI Stochastic Optimization for Adaptive Optics Marc Cohen Mikhail Vorontsov R). This as- sumption of a point source is the foundation of the most widely used adaptive optics control Electrical and Computer Engineering Intelligent Optics Laboratory Baltimore, MD 21218 Adelphi, MD 20783 fmarc

Cauwenberghs, Gert

378

Microscale adaptive optics: wave-front control with a -mirror array and a VLSI stochastic  

E-print Network

Microscale adaptive optics: wave-front control with a -mirror array and a VLSI stochastic gradient, further increasing the adaptation rate. © 2001 Optical Society of America OCIS codes: 010.0010, 010 for resolving several obstacles that adaptive optics has faced during the past decade: system complexity, high

Cauwenberghs, Gert

379

VLSI implementation for Epileptic Seizure Prediction System based on wavelet and chaos theory  

Microsoft Academic Search

This paper presents a very large scale integration (VLSI) circuit implementation for Epileptic Seizure Prediction System based combination of wavelet and chaos theory. The system consists with operation units of discrete wavelet transform (DWT), correlation dimension (CD), and correlation coefficient. This work discovered by certain bandwidth of signal extraction with DWT, and the combination with Chaotic features analysis, it can

Shao-Hang Hung; Chih-Feng Chao; Shu-Kai Wang; Bor-Shyh Lin; Chin-Teng Lin

2010-01-01

380

Initial Beam Test Results from a Silicon-Strip Detector with VLSI Readout  

Microsoft Academic Search

Silicon detectors with 256 strips, having a pitch of 25 ¿m, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 ¿m and a single multiplexed output which provides voltages proportional to

Chris Adolphsen; Alan Litke; Andreas Schwarz; Michal Turala; Giuseppina Anzivino; Roland Horisberger; Leonardus Hubbeling; Bernard Hyams; Alan Breakstone; Robert Cence; Sherwood Parker; James T. Walker

1986-01-01

381

Application of FDTD method to analysis of electromagnetic radiation from VLSI heatsink configurations  

Microsoft Academic Search

The electromagnetic radiation from a VLSI chip package and heatsink structure is analyzed by means of the finite-difference-time-domain (FDTD) technique. The dimensions of a typical configuration call for a multizone gridding scheme in the FDTD algorithm to accommodate fine grid cells in the vicinity of the heatsink and package cavity and sparse gridding in the remainder of the computational domain.

Kevin Li; C. F. Lee; Soon Y. Poh; R. T. Shin; J. A. Kong

1993-01-01

382

SIGNAL INTEGRITY AND LOW POWER ISSUES IN DEEP SUBMICRON VLSI DESIGN  

E-print Network

Copyright by Hai Zhou 1999 #12; SIGNAL INTEGRITY AND LOW POWER ISSUES IN DEEP SUB­MICRON VLSI of Philosophy The University of Texas at Austin May 1999 #12; SIGNAL INTEGRITY AND LOW POWER ISSUES IN DEEP SUB very satisfying for me to work with a supervisor who shared my love for mathematical and algorithmic

Zhou, Hai

383

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform  

Microsoft Academic Search

Using the lifting scheme to construct VLSI architectures for discrete wavelet transforms outperforms using convolution in many aspects, such as computation complexity and boundary extension. Nevertheless, the critical path of the lifting scheme is potentially longer than that of convolution. Although pipelining can reduce the critical path, it will prolong the latency and require more registers for a 1D architecture

Chao-tsung Huang; Po-chih Tseng; Liang-gee Chen

2002-01-01

384

Fault Diagnosis of VLSI Circuits with Cellular Automata based Pattern Classifier  

E-print Network

Fault Diagnosis of VLSI Circuits with Cellular Automata based Pattern Classifier Biplab K Sikdar 1, India 700094 palchau@vsnl.net Abstract---This paper reports a fault diagnosis scheme for V LSI circuits dictionary used for diagnosis of V LSI circuits. The proposed diagnosis scheme employs significantly lesser

Ganguly, Niloy

385

An efficient approach to pipeline scheme for concurrent testing of VLSI circuits  

Microsoft Academic Search

Presents a unifying procedure, called implicit tree search algorithm (ITSA), for automated allocation of test events in a pipeline scheme for concurrent testing of VLSI circuits. The procedure fully exploits the test parallelism where the test intervals of compatible test events are overlaid so that the system can test as many of them as possible concurrently. Moreover, the utilization of

Chien-In Henry Chen; Joel Yuen

1992-01-01

386

Change Diagram : A behavioural model for very speed VLSI circuit\\/highly parallel systems  

Microsoft Academic Search

The paper proposes a formal moded, named change diagram, for analysis and synthesis of the very high speed complex VLSI circuitslsystems. The CD allows f o r unambiguous expression of concurrent activities riot only of distributive processes, but also those of serni-modular. The equivalence of CDs and Petri Nets is investigated too. Possible usage of CDs in new generation simulators

A. Kondratyev; A. Taubin; V. Varshavskyl; M. Kishinevsky; E. E. Pissaloux

1994-01-01

387

Computational Modeling of Negative Bias Temperature Instability (NBTI) for Reliability-aware VLSI Design  

E-print Network

reliability of circuits for NBTI. II. NBTI THEORY AND MODELING In CMOS circuits, NBTI affects the PMOSFETs and translates into reduced speed at the circuit level. A. Reaction-Diffusion (R-D) Model The interface trap1 Computational Modeling of Negative Bias Temperature Instability (NBTI) for Reliability-aware VLSI

Alam, Muhammad A.

388

Wafer-level Au-Au bonding in the 350-450 °C temperature range  

NASA Astrophysics Data System (ADS)

Metal thermocompression bonding is a hermetic wafer-level packaging technology that facilitates vertical integration and shrinks the area used for device sealing. In this paper, Au-Au bonding at 350, 400 and 450 °C has been investigated, bonding wafers with 1 µm Au on top of 200 nm TiW. Test Si laminates with device sealing frames of 100, 200, and 400 µm in width were realized. Bond strengths measured by pull tests ranged from 8 to 102 MPa and showed that the bond strength increased with higher bonding temperatures and decreased with increasing frame width. Effects of eutectic reactions, grain growth in the Au film and stress relaxation causing buckles in the TiW film were most pronounced at 450 °C and negligible at 350 °C. Bond temperature below the Au-Si eutectic temperature 363 °C is recommended.

Tofteberg, Hannah R.; Schjølberg-Henriksen, Kari; Fasting, Eivind J.; Moen, Alexander S.; Taklo, Maaike M. V.; Poppe, Erik U.; Simensen, Christian J.

2014-08-01

389

Three dimensional integration technology using copper wafer bonding  

E-print Network

With 3-D integration, the added vertical component could theoretically increase the device density per footprint ratio of a given chip by n-fold, provide a means of heterogeneous integration of devices fabricated from ...

Fan, Andy, 1976-

2006-01-01

390

Impact of chuck flatness on wafer distortion and stepper overlay  

NASA Astrophysics Data System (ADS)

Overlay accuracy is known as one of the most important subjects for ULSI device production. Significant contributions such as alignment accuracy and mask distortions are well known. By breaking the 100 nm range on overlay accuracy a number of influences have to take into account, which were usually neglected for relaxed design rules. One of these influences to the overlay is directly related to wafer distortions induced by flatness deviations of wafer chucks. This impact was characterized by investigating the elastic behavior of 4' wafers (525 micrometers thick), fixed on a wafer chuck. Induced elastical deformation due to flatness error of the chuck causes strains and elongations in the wafer surface and therefore wafer distortions. The results obtained by exposure experiments and calculations show that even a point size defect has a 30 mm spreading. Therefore the induced distortions arrives about 100 nm in case of a 3 micrometers flatness irregularity. The final result of the investigations induces that the flatness differences between different wafer chucks or steppers should be smaller than 1 micrometers for design rules below quarter micron.

Simon, Klaus; Scheunemann, H.-U.; Huber, Hans L.; Gabeli, F.

1993-06-01

391

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.  

PubMed

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. PMID:24700434

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

392

Direct to digital holography for semiconductor wafer defect detection and review  

NASA Astrophysics Data System (ADS)

A method for recording true holograms directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for dining defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep UV light.

Thomas, C. E., Jr.; Bahm, Tracy M.; Baylor, Larry R.; Bingham, Philip R.; Burns, Steven W.; Chidley, Matt; Dai, Long; Delahanty, Robert J.; Doti, Christopher J.; El-Khashab, Ayman; Fisher, Robert L.; Gilbert, Judd M.; Goddard, James S., Jr.; Hanson, Gregory R.; Hickson, Joel D.; Hunt, Martin A.; Hylton, Kathy W.; John, George C.; Jones, Michael L.; Macdonald, Ken R.; Mayo, Michael W.; McMackin, Ian; Patek, Dave R.; Price, John H.; Rasmussen, David A.; Schaefer, Louis J.; Scheidt, Thomas R.; Schulze, Mark A.; Schumaker, Philip D.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin, Kenneth W., Jr.; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Jones, Paul G.; Owen, Robert W.

2002-07-01

393

Direct to Digital Holography for Semiconductor Wafer Defect Detection and Review  

SciTech Connect

A method for recording true holograms (not holographic interferometry) directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional to wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for finding defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep ultra-violet light.

ThomasJr., C. E. [nLine Corporation, Austin, TX; Bahm, Tracy M. [nLine Corporation, Austin, TX; Baylor, Larry R [ORNL; Bingham, Philip R. [nLine Corporation, Austin, TX; Burns, Steven W. [nLine Corporation, Austin, TX; Chidley, Matthew D [ORNL; Dai, Xiaolong [nLine Corporation, Austin, TX; Delahanty, Robert J. [nLine Corporation, Austin, TX; Doti, Christopher J. [nLine Corporation, Austin, TX; El-Khashab, Ayman [nLine Corporation, Austin, TX; Fisher, Robert L. [nLine Corporation, Austin, TX; Gilbert, Judd M. [nLine Corporation, Austin, TX; Cui, Hongtao [ORNL; Goddard Jr, James Samuel [ORNL; Hanson, Gregory R [ORNL; Hickson, Joel D. [nLine Corporation, Austin, TX; Hunt, Martin A. [nLine Corporation, Austin, TX; Hylton, Kathy W [ORNL; John, George C. [nLine Corporation, Austin, TX; Jones, Michael L. [nLine Corporation, Austin, TX; McDonald, Kenneth R. [nLine Corporation, Austin, TX; Mayo, Michael W. [nLine Corporation, Austin, TX; McMackin, Ian [nLine Corporation, Austin, TX; Patek, David [ORNL; Price, John H. [nLine Corporation, Austin, TX; Rasmussen, David A [ORNL; Schaefer, Louis J. [nLine Corporation, Austin, TX; Scheidt, Thomas R. [nLine Corporation, Austin, TX; Schulze, Mark A. [nLine Corporation, Austin, TX; Schumaker, Philip D. [nLine Corporation, Austin, TX; Shen, Bichuan [nLine Corporation, Austin, TX; Smith, Randall G. [nLine Corporation, Austin, TX; Su, Allen N. [nLine Corporation, Austin, TX; Tobin Jr, Kenneth William [ORNL; Usry, William R. [nLine Corporation, Austin, TX; Voelkl, Edgar [nLine Corporation, Austin, TX; Weber, Karsten S. [nLine Corporation, Austin, TX; Jones, Paul G. [nLine Corporation, Austin, TX; Owen, Robert W. [nLine Corporation, Austin, TX

2002-01-01

394

A Wafer scale active pixel CMOS image sensor for generic x-ray radiology  

NASA Astrophysics Data System (ADS)

This paper describes a CMOS Active Pixel Image Sensor developed for generic X-ray imaging systems using standard CMOS technology and an active pixel architecture featuring low noise and a high sensitivity. The image sensor has been manufactured in a standard 0.35 ?m technology using 8" wafers. The resolution of the sensor is 3360x3348 pixels of 40x40 ?m2 each. The diagonal of the sensor measures little over 190 mm. The paper discusses the floor planning, stitching diagram, and the electro-optical performance of the sensor that has been developed.

Scheffer, Danny

2007-03-01

395

The uses of Man-Made diamond in wafering applications  

NASA Technical Reports Server (NTRS)

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Fallon, D. B.

1982-01-01

396

On-Wafer Testing of Circuits Through 220 GHz  

NASA Technical Reports Server (NTRS)

We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.

Gaier, Todd; Samoska, Lorene; Oleson, Charles; Boll, Greg

1999-01-01

397

Arthroscopic Wafer Procedure for Ulnar Impaction Syndrome  

PubMed Central

Ulnar impaction syndrome is abutment of the ulna on the lunate and triquetrum that increases stress and load, causing ulnar-sided wrist pain. Typically, ulnar-positive or -neutral variance is seen on a posteroanterior radiograph of the wrist. The management of ulnar impaction syndrome varies from conservative, symptomatic treatment to open procedures to shorten the ulna. Arthroscopic management has become increasingly popular for management of ulnar impaction with ulnar-positive variance of less than 3 mm and concomitant central triangular fibrocartilage complex tears. This method avoids complications associated with open procedures, such as nonunion and symptomatic hardware. The arthroscopic wafer procedure involves debridement of the central triangular fibrocartilage complex tear, along with debridement of the distal pole of the ulna causing the impaction. Debridement of the ulna arthroscopically is taken down to a level at which the patient is ulnar neutral or slightly ulnar negative. Previous studies have shown good results with relief of patient symptoms while avoiding complications seen with open procedures. PMID:24749031

Colantoni, Julie; Chadderdon, Christopher; Gaston, R. Glenn

2014-01-01

398

Development of thin edgeless silicon pixel sensors on epitaxial wafers  

NASA Astrophysics Data System (ADS)

The paper reports on the development of novel p-on-n thin edgeless planar pixel sensors, compatible with ALICE front-end electronics, fabricated by FBK on epitaxial material. The focus of the activity is the minimization of the material budget required for hybrid pixel detectors. This goal has been addressed in two different stages. In the first one, planar pixel detectors fabricated on epitaxial wafers have been thinned and bonded to the readout chips. The second stage is described by the present paper: the `active edge' concept has been studied for the reduction of the dead area at the periphery of the devices. An overview of the key technological steps and of the electrical characterization of the fabricated sensors is given. In addition, the preliminary results on the static behavior of test sensors after neutron irradiation at different fluences (up to 2.5 × 1015 1 MeV-neq/cm2) are reported. The results demonstrate that these kinds of devices are a viable solution for the reduction of the material budget while maintaining the typical electrical characteristics expected from radiation silicon sensors.

Boscardin, M.; Bosisio, L.; Contin, G.; Giacomini, G.; Manzari, V.; Orzan, G.; Rashevskaya, I.; Ronchin, S.; Zorzi, N.

2014-09-01

399

Experimental Evaluation of Ternary Systems for VLSI Microelectronics.  

NASA Astrophysics Data System (ADS)

This work contains both theoretical and experimental results for ternary systems. The theoretical part starts with a compilation of bulk data. Group VIII metals such as Fe, Co, Ni, Pd and Pt form stable ternary phases with other transition metals. This tendency is explained using an empirical approach where parameters affecting phase formation and solubility are electron affinity, atomic radii and valency. Metal -dopant compound formation is also reviewed for Metal-Boron -Si systems. Following the literature review, the validity of other models is discussed. Experimentally, thin film growth of Ti _{rm 4}Ni_4 Si_7, Ti_ {0.75}Co_{0.25} Si_2, TiCoSi, Ti _4Co_4Si_7 and ZrCuSi_2 is observed for the first time. Crystallographic structures and electrical properties of selected compounds are presented. Samples are prepared by Rapid Thermal Processing (RTP) in vacuum. RTP is shown to be also advantageous to form smooth low resistivity silicides such as TiSi_2, CoSi _2 (15-18 muOmega.cm) and ZrSi_2 (34 mu Omega.cm). The ternary phases can be prepared either by reacting bilayers on Si or by processing a metal overlayer on a silicide. For metal bilayers, the sequence of evolution usually starts with the formation of intermetallic compounds. Above 550^circC, Si becomes mobile leading to the growth of ternary phases. The metal in excess with respect to the stoichiometry of the ternary reacts with Si yielding binary silicide which is segregated in a separate layer only if the diffusing metal is involved. The formation of Cu_3Si and its instability in contact with O are analyzed. Decomposition of the silicide is accompanied by room temperature oxidation of Si related to the surface catalytic action of Cu atoms in dissociating O_2 molecules. Small atoms such as Co, Ni and Cu are fast diffusers in silicides, but preliminary results indicate that Cu might be an interesting alternative to Al. For Cu/ZrSi _2 structures, three stages of insertion of Cu atoms into twin habit planes exist. For all the experiments performed, Auger Electron Spectroscopy reflects modifications of the density of states caused by metal d-Si 3p bonding. The global approach combining thin film and bulk samples offers new insights for the future use of multilevel metallizations in submicron VLSI manufacturing processes.

Setton, Michael

1990-01-01

400

VLSI sensor/processor circuitry for autonomous robots  

NASA Astrophysics Data System (ADS)

A CMOS circuit has been developed which integrates sensors and processing circuitry aimed at implementing autonomous robot perception and control functions. The sensors are an array of photodetectors and the processing circuitry analyzes the array data to extract a basic set of sensory primitives. In addition, the processing circuitry provides a low-resolution determination of the location of any brightness edges which cross the array. Ultimately, this sensor-processor circuitry will be used as part of an overall integrated sensorimotor system for autonomous robots. In the complete system, individual sensorimotor units will produce motion requests for the robot as a whole and an operating system, serving in part as a motion request handler, will arbitrate among suggested motions. The nature of the motion requests will be dependent both on sensor input and on the current goals of the robot. Ideally, the entire set of sensors, the processing circuitry, and the operating system will reside on a single VLSI chip. The current chip achieves many of the objectives of the complete integrated sensorimotor system, namely, it acquires sensory information, manipulates that data, and ultimately provides a digital output signal set which could serve as a motor signal set. Much of the on- chip processing is done by sensory primitive modules which calculate spatial convolutions of the sensor array data. Convolution kernels which were actually implemented were chosen based primarily on their usefulness in solving low-level vision problems. Specific kernels on the current chip include discrete approximations to the x-direction first derivative operator, the y-direction first derivative operator, and the laplacian operator. The spatial convolution function is achieved using current mode analog signal processing techniques. The output of the spatial convolution modules is piped into a higher level module which generates an estimate of the location of brightness edges which cross the array. This location estimate, which takes the form of a set of digital signals, can be readily translated into a (motor system dependent) motion request format, if indeed it cannot be used directly for this purpose. Location estimation, although it is the only higher level function implemented on the current chip, is just one example of a useful sensory primitive-based function. Additional higher level modules could be used to implement alternate functions which estimate other important environmental properties.

Friedman, Daniel J.; Clark, James J.

1992-03-01

401

Journal of VLSI Signal Processing 28, 727, 2001 c 2001 Kluwer Academic Publishers. Manufactured in The Netherlands.  

E-print Network

Journal of VLSI Signal Processing 28, 7­27, 2001 c 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Reconfigurable Computing for Digital Signal Processing: A Survey RUSSELL TESSIER AND WAYNE

Tessier, Russell

402

Survey and comparison of various sample preparation techniques for the heavy ions backside irradiation of COTS VLSI  

Microsoft Academic Search

Taking into account current and future encapsulation techniques of COTS VLSI components, a survey of state-of-the-art sample preparation techniques for heavy ions backside irradiation has been performed and then evaluated on a SDRAM test vehicle.

F. Courtade; F. Bezerra; S. Duzellier

2005-01-01

403

Monolithic silicon waveguides in bulk silicon wafers  

NASA Astrophysics Data System (ADS)

We demonstrate two silicon photonic technologies for fabrication of monolithic photonic devices in standard silicon. Using these technologies, we demonstrate low-loss silicon waveguides (2.34 dB/cm), double-layer 3D waveguides, and waveguide Bragg reflectors in standard silicon for optical interconnects and sensing applications. These technologies simplify integration of electronics and photonics and are possible alternatives to SOI-based technology for implementation of silicon-photonic devices and systems for optical interconnects and sensing.

Chang, Chia-Ming; Solgaard, Olav

2014-02-01

404

9nm node wafer defect inspection using visible light  

NASA Astrophysics Data System (ADS)

Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

2014-04-01

405

Laser induced stress wave thermometry applied to silicon wafer processing  

E-print Network

-mechanical properties of single crystal silicon wafers, specifically with respect to ultrasound propagation in the waveguide. The objective is to identify and quantify characteristics of interrogating ultrasonic waves which can be used as a temperature diagnostic...

Rabroker, George Andrew

2012-06-07

406

Wafer cooling for a high current serial ion implantation system  

Microsoft Academic Search

This paper investigates performance of a gas-cooled, low temperature electrostatic chuck and the effects of gas injection radius change on the wafer cooling efficiency. Wafer temperature measurements were taken for two new electro-static chuck designs at different gas cooling pressures during high current ion implantation. Typical input beam power density was 1.3 W\\/cm2. An improvement in cooling performance was achieved

Svetlana B. Radovanov; Steven R. Walther; Edward Evans; Jon Ballou; Nicholas R. White; William Frutiger

1999-01-01

407

ESFI-SOS transistors on as-grown sapphire wafers  

Microsoft Academic Search

The possibility to grow the silicon film on an as-grown substrate rather than on a mechanically processed substrate is considered. The concept is implemented with the aid of sapphire wafers obtained by the edge-defined film-fed growth (EFG) technique. The wafers are ground on one side only, the other side remaining as an as-grown substrate. The principal advantage of the use

H. Splittgerber; D. Takacs; H. Schloetterer

1977-01-01

408

Thermal stresses in 3D IC inter-wafer interconnects  

Microsoft Academic Search

We present a finite element based analysis to determine if thermally induced stresses in inter-wafer Cu via structures in 3D ICs using BCB-bonded wafers is a potential reliability problem. Experimental information on thermal stresses or stress-induced failures of 3D ICs is not available in the literature. Therefore we first partially validate our approach by comparing computed results against experimental data

Jing Zhang; Max O. Bloomfield; Jian-Qiang Lu; Ronald J. Gutmann; Timothy S. Cale

2005-01-01

409

Characterization of acoustomigration with on-wafer measurement system  

Microsoft Academic Search

Developed an automated on-wafer measurement system and a suitable test device for the design-independent characterization of different metallization layers on piezoelectric substrates with respect to acoustomigration. With the measurement system we are able to measure the devices on the wafer without any additional manual handling. The test devices were fabricated on LiTaO3 with Al and AlCu electrodes. The temperature and

G. Raml; W. Ruile; A. Springer; R. Weigel

2001-01-01

410

An air-flow based wafer bake system for improved temperature uniformity  

Microsoft Academic Search

This paper presents an innovative apparatus for wafer baking\\/chilling using a stream of temperature controlled air-flow. This apparatus takes the form of a baking chamber on which the wafer is placed. A stream of hot air is passed through the chamber below the wafer. Heat is transferred from the hot air to the wafer from the bottom surface of the

Lan Wang; Ai Poh Loh; Zhi Ming Gong; Siew Loong Chow

2008-01-01

411

Electrochemical method for defect delineation in silicon-on-insulator wafers  

SciTech Connect

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, T.R.; Jones, D.T.H.; Kelly, M.J.; Medernach, J.W.; Stevenson, J.O.; Tsao, S.S.

1990-01-01

412

Electrochemical method for defect delineation in silicon-on-insulator wafers  

SciTech Connect

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, T.R.; Jones, D.T.H.; Kelly, M.J.; Medernach, J.W.; Stevenson, J.O.; Tsao, S.S.

1990-12-31

413

Strategy and metrics for wafer handling automation in legacy semiconductor fab  

Microsoft Academic Search

We present a systematic approach for converting a legacy wafer fab from manual wafer handling to fully automatic wafer handling. Our strategy began by quantifying the need for automation in terms of impact on die yield, identifying a seven percent die loss associated with scratches from wafer handling. We then addressed the fundamental changes in production equipment and processes as

R. L. Guldi; D. E. Paradis; M. T. Whitfield; F. D. Poag; D. P. Jensen

1999-01-01

414

Micro-nano photonic biosensors scalable at the wafer level  

NASA Astrophysics Data System (ADS)

We present a potential high sensitive label-free optical bio-sensing system based on biophotonic sensing cells, which can be fabricated and interrogated at wafer or disposable chip level. The key benefits rely on the holistic approach that combines bio-photonic resonant micro-nano cavities and advanced sub-micron spot size optical interrogation technologies. The proposed optical sensing system will be tremendously sensitive to refractive index variations by means of the observation of the reflectivity profile of three complementary enhanced sub-micron spot size optical technologies simultaneously (Reflectometry, Spectrometry and Ellipsometry based techniques), and the magnification due to the biophotonics resonant sensing cells, making possible to determine with more reliability and sensitivity the biomolecular interaction with the receptor biomolecules. This novel sensing system also offers an inexpensive solution for integration and packaging because it overcomes the need for using complex systems for light coupling such as inverted tapers or grating couplers, usually used in planar micro-nano photonic devices, because the sensor evaluation is done measuring vertically collecting the reflected light of the bio-photonic resonant sensing cells. The sensing system may use a tightly focused beam which allows measuring in situ micron/sub-micron size geometries, making the routine screening more cost-effective and suitable to perform hundreds of measurements on a single or several samples for multi-single or multiparameter measurements. The simultaneous used of the three different optical techniques will allow the systems to achieve a high throughput and productivity in comparison with other established analytical techniques. The levels of sensitivity expected are in the order of 10-6/10-7 refractive index units (RIU).

Holgado, M.; Casquel, R.; Lagunas, María-Fe

2009-02-01

415

Fabrication of a mechanically aligned single-wafer MEMS turbine with turbocharger  

NASA Astrophysics Data System (ADS)

We describe the fabrication of a turbocharged, microelectromechanical system (MEMS) turbine. The turbine will be part of a standalone power unit and includes extra layers to connect the turbine to a generator. The project goal is to demonstrate the successful combination of several features, namely: silicon fusion bonding (SFB), a micro turbocharger [2], two rotors, mechanical alignment between two wafers [1], and the use of only one 5" silicon wafer. The dimension of the actual turbine casing will be 14mm. The turbine rotor will have a diameter of 8mm. Given these dimensions, MEMS processes are an adequate way to fabricate the device, but it will be necessary to stack up seven different layers to build the turbine, as it is not possible to construct it out of one thick wafer. SFB will be used for bonding because it permits the great precision necessary for high quality alignment. Yet a more precise alignment will be necessary between the layers that contain the turbine rotor, to decrease imbalance and guarantee operation at a very high rpm. To achieve these tight tolerances, a mechanical alignment feature announced by Liudi Jiang [1] is used. The alignment accuracy is expected to be around 200nm. Despite the fact that the turbine consists of multiple layers, it will be fabricated on only one silicon-on-insulator (SOI) wafer. As a result, all layers are exposed to the same process flow. The fabrication process includes MEMS technology as photolithography, nine deep reactive ion etching (DRIE) steps, and six SFB operations. A total of 14 masks are necessary for the fabrication.

Pelekies, S. O.; Schuhmann, T.; Gardner, W. G.; Camacho, A.; Protz, J. M.

2010-10-01

416

1144 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 10, OCTOBER 2007 Wafer-Level Modular Testing of Core-Based SoCs  

E-print Network

in the semicon- ductor industry to screen defective dies. However, since test time is a major practical limit on the SoC test time. We also present a heuristic method to handle large next-generation So of the testing of core-based SoCs [3]. A standardized 1500 wrapper can either be provided by the core vendor

Chakrabarty, Krishnendu

417

Analytic modeling, optimization, and realization of cooling devices in silicon technology  

Microsoft Academic Search

A novel cooling device fully built in silicon technology is presented. The new concept developed in this work consists of micromachining the bottom side of the circuit wafer in order to embed heat sinking microchannels directly into the silicon material. These microchannels are then sealed, by a direct wafer bonding procedure, with another silicon wafer where microchannels and inlet-outlet nozzles

Corinne Perret; Jumana Boussey; Christian Schaeffer; Martin Coyaud

2000-01-01

418

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays  

NASA Astrophysics Data System (ADS)

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 ?m is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 ?m × 25 ?m that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

2013-09-01

419

Performance Evaluation for Electrical Plate Lead-free Solder Bumping on Sapphire Wafers  

Microsoft Academic Search

Electrical plating lead-free solder bumping process is quite common for silicon wafers in semiconductor industry, while for sapphire wafers there are still some technical issues to be encountered. Bumped wafer of unreasonable bumping structure has always been found bumps knocked-off after wafer singulation process which is a three-point breaking. Triple higher residual stress may be accumulated on sapphire wafer surface

Y. J. Zhiyuan

2007-01-01

420

Evaluating the 300 mm wafer-handling task in semiconductor industry  

Microsoft Academic Search

The semiconductor industry is moving from the production of 200mm wafers to 300mm wafers. With the increase in wafer size, the workload of wafer handling tasks is also increasing. This study evaluated the operator's handling capability, and the risk of having musculoskeletal disorders (MSDs) for handling 300mm wafers. Twenty-four female operators from a semiconductor manufacturing company participated in the experiment.

Mao-Jiun J. Wang; Hsiu-Chen Chung; Hsin-Chieh Wu

2004-01-01

421

"Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step  

NASA Astrophysics Data System (ADS)

During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

2013-04-01

422

Gate-Oxide-Integrity Characteristics of Vacancy-rich Wafer Compared with Crystal-Originated-Pits-free Wafer as a Function of Oxide Thickness  

Microsoft Academic Search

The dielectric breakdown of oxides with various thickness between 5-70 nm on Czochralski (CZ)-grown silicon wafer had been investigated. To observe the effects of crystal-originated-particle (COP), vacancy-rich wafers and COP-free wafers were compared. In breakdown voltage (BV) measurement, breakdown fractions of vacancy-rich wafers were increased with the increase of oxide thickness (tOX) and showed a maximum value at the tOX

Ki-Sang Lee; Won-Ju Cho; Bo-Young Lee; Hak-Do Yoo

2000-01-01

423

Mixed-Signal VLSI Circuits for Particle Detector Instrumentation in High-Energy Physics Experiments  

NASA Astrophysics Data System (ADS)

This research is concerned with the circuit design challenges presented by the electronics requirements at future colliding beam facilitates for high-energy physics research. The particle detectors to be used in the next generation of experiments depend on the realization of sophisticated instrumentation electronics that will enable the identification and characterization of the fundamental constituents of matter. The work presented here focuses on the monolithic VLSI integration of multiple, mixed-signal, front-end electronics channels for detector-mounted instrumentation. The use of high levels of integration is driven by the need for compactness, low cost, high reliability, and low power dissipation in the implementation of the hundreds of thousands of sensory channels required for future experiments. The specific application considered in this work is the front -end electronics for straw tube drift chambers. In this context, the function of the front-end electronics is to measure the occurrence time of an input pulse in relation to a system clock. Each front-end channel includes analog circuits that provide amplification and signal conditioning for input pulses as small as 1mV, a timing discriminator, and a time interval digitizer to measure input pulse arrival times with respect to the system clock. Performance requirements for the channel include a timing error less than 0.75ns RMS, average power dissipation in the tens of milliwatts, and event rates in the 50-100MHz range. Circuits must be designed to allow the implementation of high-sensitivity analog and fast digital functions on the same chip. Unwanted coupling between digital and analog circuits must be minimized along with channel-to-channel crosstalk. A multi-channel circuit that measures the occurrence times of input pulses with peak values in the 1-10mV range relative to a 62.5-MHz clock has been monolithically integrated in a 1.2-?m CMOS technology. Each channel includes a wideband amplifier, a tail-cancellation filter, a timing discriminator with time walk compensation, and a time digitizer. A timing error of 0.46ns RMS has been achieved, with negligible channel-to-channel crosstalk, at a power dissipation of 50mW/channel from a 3.3-V supply.

Loinaz, Marc Joseph

424

High Density Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications  

Microsoft Academic Search

A novel direct wafer bonding technology capable of forming a very high density of electrical interconnections across the bond interface integral to the bond process is described. Results presented include an 8 um interconnection pitch, die-to-wafer and wafer-to-wafer bonding formats, temperature cycling reliability x10 greater than the JEDEC requirement, connection yield ~ 99.999, > 50% part yield on parts with

Paul Enquist

2007-01-01

425

An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV  

Microsoft Academic Search

Fractional Motion Estimation (FME) in high-definition H.264 presents a significant design challenge in terms of memory bandwidth,\\u000a latency and area cost as there are various modes and complex mode decision flow, which require over 45% of the computation\\u000a complexity in the H.264 encoding process. In this paper, a new high-performance VLSI architecture for Fractional Motion Estimation\\u000a (FME) in H.264\\/AVC based

Gustavo A. Ruiz; Juan A. Michell

2011-01-01

426

A low power VLSI architecture for mesh-based video motion tracking  

Microsoft Academic Search

This paper proposes a low-power very large-scale integration (VLSI) architecture for motion tracking. It uses a hierarchical adaptive structured mesh that generates a content-based video representation. The proposed mesh is a coarse-to-fine hierarchical two-dimensional mesh that is formed by recursive triangulation of the initial coarse mesh geometry. The structured mesh offers a significant reduction in the number of bits that

Wael Badawy; Magdy A. Bayoumi

2002-01-01

427

Switch-level simulation of VLSI using a special-purpose data-driven computer  

Microsoft Academic Search

In this paper I present the algorithms, architecture, and performance of the FAST-1, a special-purpose data-driven computer for switch-level simulation of VLSI circuits. The FAST-1 algorithm computes the same steady state as Bryant's Mossimll algorithm, using a similar network model. The architecture of the simulation machine follows directly from the simulation algorithm and, like the algorithm, is very simple. While

Edward H. Frank

1985-01-01

428

A VLSI sigma delta A\\/D converter for audio and signal processing applications  

Microsoft Academic Search

The use of sigma-delta has inherent advantages over other techniques and lends itself well to VLSI integration. A sigma-delta modulator for analog\\/digital conversion featuring third-order noise shaping and a two-stage multirate digital decimation filter is discussed. Design goals included 16-bit resolution and 100-kHz output sample rate. Die area has been kept to a minimum using a 1.5-?m CMOS process, and

C. D. Thompson

1989-01-01

429

Toward terabit\\/s input to silicon VLSI: a demonstrator experiment  

Microsoft Academic Search

The physical limit on electronic data communication rates between silicon chips is projected to be of the order of Tbit\\/s over cm-scale connections. The semiconductor industry predicts that this level of i\\/o is likely to be required in the near future. Free-space optical connections to silicon VLSI are potentially able to offer much higher data-rates than electrical interconnects and are

Andrew C. Walker; Stuart J. Fancey; M. G. Forbes; Gerald S. Buller; Mohammad R. Taghizadeh; Marc P. Desmulliez; Julian A. Dines; C. R. Stanley; G. Pennelli; A. Boyd; J. L. Pearson; Paul G. Horan; Declan Byrne; John Hegarty; S. Eitel; Hans-Peter Gauggel; Karlheinz H. Gulden; A. Gauthier; P. Benabes; J. L. Gutzwiller; Michel Goetz

2000-01-01

430

Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages  

Microsoft Academic Search

Recently VLSI IC design is concerned with the large temperature non-uniformity in high power chips. Thus far, thermal simulations have been limited to steady-state worst case conditions, which have caused the use of conservative margins in thermal designs. Transient temperature characteristics were not simulated in prior art chip-level simulations due to the high computational expense. To drastically reduce the time

Je-Hyoung Park; A. Shakouri; Sung-Mo Kang

2008-01-01

431

A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends  

Microsoft Academic Search

Next-generation bionic ears or cochlear implants will be fully implanted inside the body of the patient and consequently have very stringent requirements on the power consumption used for signal processing. We describe a low-power programmable analog VLSI processing channel that implements bandpass filtering, envelope detection, logarithmic mapping and analog-to-digital conversion. A bionic ear processor may be implemented through the use

Timothy Kuan-ta Lu; Michael W. Baker; Christopher D. Salthouse; Ji-jon Sit; Serhii M. Zhak; Rahul Sarpeshkar

2003-01-01

432

An accurate AC characteristic table look-up model for VLSI analog circuit simulation applications  

Microsoft Academic Search

A new accurate table look-up method is presented for modeling both I-V characteristics and C-V and\\/or Q-V characteristics of deep submicron MOSFETs for VLSI analog circuit simulation. Based on the linear and quadratic isoparametric shape functions, the proposed table lookup approach can accurately model complicated AC characteristics of MOSFETs. The charges and capacitances derived through integration of C-V characteristics and

D.-H. Cho; S. M. Kang

1993-01-01

433

First results from a silicon-strip detector with VLSI readout  

Microsoft Academic Search

A 256-strip silicon detector with 25 mum strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 mum. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals

Giuseppina Anzivino; Roland Horisberger; Leonardus Hubbeling; Bernard Hyams; Sherwood Parker; Alan Breakstone; Alan M. Litke; James T. Walker; Nils Bingefors

1986-01-01

434

A new fluorescent and Photoemission Microscope for submicron VLSI IC failure analysis  

Microsoft Academic Search

Photoemission Microscopy (PEM) has been widely used in modern VLSI IC failure analysis. As its camera normally detects the emissions from visible to near infrared light, it is more sensitive to non-heat-related failure such as junction related defect, gate oxide related defect, etc. As a complimentary technique, infrared photoemission microscope was developed by different companies or FA labs for heat-related

Oh Chong Khiam; Wu Zong Min; Shailesh Redkar; Christopher Cheong; Thomas Yang

2002-01-01

435

A restructurable VLSI robotics vector processor architecture for real-time control  

Microsoft Academic Search

The authors propose a restructurable architecture based on a VLSI robotics vector processor (RVP) chip. It is specially tailored to exploit parallelism in the low-level matrix\\/vector operations characteristic of the kinematics and dynamics computations required for real-time control. The RVP is composed of three tightly synchronized 32-bit floating-point processors to provide adequate computational power. Besides adder and multiplier units in

PONNUSWAMY SADAYAPPAN; YONG-LONG CALVIN LING; KARL W. OLSON; DAVID E. ORIN

1989-01-01

436

Efficient approaches to low-cost high-fault coverage VLSI BIST designs  

Microsoft Academic Search

This work introduces a built-in self-test (BIST) design methodology that can sequentially test large very large scale integrated (VLSI) circuits with very high fault coverage. The proposed techniques, circular BIST ((BIST) and (BIST with pseudopartial scan (PPSCAN), are modeled after the principles of the circular self-test path (CSTP). The basis of this method is to trade a minimal increase in

CHIEN-IN HENRY CHEN

1998-01-01

437

Development of a wafer positioning system for the Sandia extreme ultraviolet lithography tool  

SciTech Connect

A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

Wronosky, J.B.; Smith, T.G.; Darnold, J.R.

1995-12-01

438

Development of a Wafer Positioning System for the Sandia Extreme Ultraviolet Lithography Tool  

NASA Technical Reports Server (NTRS)

A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

Wronosky, John B.; Smith, Tony G.; Darnold, Joel R.

1996-01-01

439

100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices  

SciTech Connect

A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

OLIVER,ANDREW D.; MATZKE,CAROLYN M.

2000-04-06

440

Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.  

PubMed

Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices. PMID:21031027

Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

2010-01-01

441

Supply and power optimization in leakage-dominant technologies  

Microsoft Academic Search

In this paper, we present a methodology for systematically optimizing the power-supply voltage for either maximizing the performance of very large scale integration (VLSI) circuits or minimizing the power dissipation in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations that describe the transistor behavior as a

Man Lung Mui; Kaustav Banerjee; Amit Mehrotra

2005-01-01

442

Neural Networks In High Energy Physics Royal Institute of Technology  

NSDL National Science Digital Library

Neural Networks in High Energy Physics Royal Institute of Technology, Stockholm, Sweden. From the Dept. of Physics-Frescati comes this comprehensive list of references, recent developments in the field, upcoming conferences, etc. Of most general interest is the extensive list of commercial neural network hardware, including VLSI chips, PC accelerator cards, and neurocomputers.

443

Characterizing SOI Wafers By Use Of AOTF-PHI  

NASA Technical Reports Server (NTRS)

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

444

CSCE 612: VLSI System Design Instructor: Dr. Jason D. Bakos  

E-print Network

in the face of changing physical phenomena resulting from chip feature sizes shrinking to only a handful years. No other technology in history has sustained such a high growth rate for so long. In 2003. This course will begin by presenting students will the fundamentals in integrated circuit technology

Bakos, Jason D.

445

1.5- to 0.8-?m optical upconversion by wafer fusion  

NASA Astrophysics Data System (ADS)

An InGaAs photodetector array interconnected with a silicon readout IC is the industry standard for 1.2-1.6 ?m imaging applications. However, the indium-bump technique it employs for interconnection makes it expensive. An alternative approach is to combine a CCD with a device that upconverts 1.2-1.6 ?m radiation to a wavelength below 1 ?m. Here we report the realization of a 1.5 ?m to 0.87 ?m optical upconversion device using wafer fusion technology. The device consists of an InGaAs/InP PIN photodetector and an AlGaAs/GaAs light emitting diode (LED). Incoming 1.5 ?m light is absorbed by the InGaAs photodetector. The resulting photocurrent drives the GaAs LED, which emits at 0.87 ?m. The PIN and LED structures are epitaxially grown on an InP and a GaAs substrate, respectively. The two wafers are wafer fused together, the GaAs substrate is removed, and the sample is processed using conventional microfabrication technology. In this paper, we first present the design and fabrication process of the device. We then discuss the approaches to increase device efficiency. We show, both experimentally and theoretically, that the active layer doping affects the LED internal quantum efficiency, especially under low current injection. An optimum doping value is obtained. The LED extraction efficiency is increased using several approaches, including micro-lens and surface scattering. Overall device efficiency is further improved by introducing a gain mechanism into the photodetector. Our results show the potentials of this integrated photodetector-LED device for 1.2-1.6 ?m imaging applications.

Luo, Hui; Ban, Dayan; Liu, Huichun C.; SpringThorpe, Anthony J.; Wasilewski, Zbigniew R.; Buchanan, Margaret

2004-12-01

446

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 52, NO. 3, MARCH 2005 489 Analog VLSI Implementation of Spatio-Temporal  

E-print Network

responses to low contrast and low-speed visual motion stimuli. We describe analog VLSI implementations of layout for focal plane vision processing arrays. The presented sensors are capable of distinguishing consumption, size, and weight are crucial. Index Terms--Analog very large-scale integration (VLSI), biomimetic

Deutschmann, Rainer

447

Wafer heating mechanisms in a molecular gas, inductively coupled plasma: in situ, real time wafer surface measurements and three-dimensional thermal modeling  

SciTech Connect

The authors report measurements and modeling of wafer heating mechanisms in an Ar/O{sub 2} inductively coupled plasma (ICP). The authors employed a commercially available on-wafer sensor system (PlasmaTemp developed by KLA-Tencor) consisting of an on-board electronics module housing battery power and data storage with 30 temperature sensors embedded onto the wafer at different radial positions. This system allows for real time, in situ wafer temperature measurements. Wafer heating mechanisms were investigated by combining temperature measurements from the PlasmaTemp sensor wafer with a three-dimensional heat transfer model of the wafer and a model of the ICP. Comparisons between pure Ar and Ar/O{sub 2} discharges demonstrated that two additional wafer heating mechanisms can be important in molecular gas plasmas compared to atomic gas discharges. The two mechanisms are heating from the gas phase and O-atom surface recombination. These mechanisms were shown to contribute as much as 60% to wafer heating under conditions of low bias power. This study demonstrated how the 'on-wafer' temperature sensor not only yields a temperature profile distribution across the wafer, but can be used to help determine plasma characteristics, such as ion flux profiles or plasma processing temperatures.

Titus, M. J.; Graves, D. B. [Department of Chemical Engineering, University of California, Berkeley, California 94720 (United States)

2008-09-15

448

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning  

NASA Astrophysics Data System (ADS)

In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

2005-06-01

449

DARPA's advanced technology GPS chipset  

NASA Astrophysics Data System (ADS)

Technology advances have made possible substantial reductions in size, weight, power, and cost of GPS receivers over the last decade. This trend continues with the exploitation of cutting-edge device technologies, most notably VLSI and MMIC. Five new chips based on these technologies are defined and described in detail. With mix-and-match techniques these chips can be used to implement a variety of GPS sets from single channel through multiple channel. The implementation status of the chips is presented, and their integration into a demonstration receiver is discussed.

Hemesath, N. B.; Bruckner, J. M. H.

450

Wafer and reticle positioning system for the Extreme Ultraviolet Lithography Engineering Test Stand  

SciTech Connect

This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EUVL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100nm. EUVL research and development includes development of capabilities for demonstrating key EUV technologies. The ETS is under development at the EUV Virtual National Laboratory, to demonstrate EUV full-field imaging and provide data that supports production-tool development. The stages and their associated metrology operated in a vacuum environment and must meet stringent outgassing specifications. A tight tolerance is placed on the stage tracking performance to minimize image distortion and provide high position repeatability. The wafer must track the reticle with less than {+-}3nm of position error and jitter must not exceed 10nm rms. To meet these performance requirements, magnetically levitated positioning stages utilizing a system of sophisticated control electronics will be used. System modeling and experimentation have contributed to the development of the positioning system and results indicate that desired ETS performance is achievable.

WRONOSKY,JOHN B.; SMITH,TONY G.; CRAIG,MARCUS J.; STURGIS,BEVERLY R.; DARNOLD,JOEL R.; WERLING,DAVID K.; KINCY,MARK A.; TICHENOR,DANIEL A.; WILLIAMS,MARK E.; BISCHOFF,PAUL

2000-01-27

451

A new low-temperature high-aspect-ratio MEMS process using plasma activated wafer bonding  

NASA Astrophysics Data System (ADS)

This paper presents the development and characterization of a new high-aspect-ratio MEMS process. The silicon-on-silicon (SOS) process utilizes dielectric barrier discharge surface activated low-temperature wafer bonding and deep reactive ion etching to achieve a high aspect ratio (feature width reduction-to-depth ratio of 1:31), while allowing for the fabrication of devices with a very high anchor-to-anchor thermal impedance (>0.19 × 106 K W-1). The SOS process technology is based on bonding two silicon wafers with an intermediate silicon dioxide layer at 400 °C. This SOS process requires three masks and provided numerous advantages in fabricating several MEMS devices, as compared with silicon-on-glass (SOG) and silicon-on-insulator (SOI) technology, including better dimensional and etch profile control of narrow and slender MEMS structures. Additionally, by patterning the intermediate SiO2 insulation layer before bonding, footing is reduced without any extra processing, as compared to both SOG and SOI. All SOS process steps are CMOS compatible.

Galchev, T. V.; Welch, W. C., III; Najafi, K.

2011-04-01

452

Wafer and reticle positioning system for the extreme ultraviolet lithography engineering test stand  

NASA Astrophysics Data System (ADS)

This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EUVL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100 nm. EUVL research and development includes development of capabilities for demonstrating key EUV technologies. The ETS is under development at the EUV Virtual National Laboratory, to demonstrate EUV full-field imaging and provide data that supports production-tool development. The stages and their associated metrology operate in a vacuum environment and must meet stringent outgassing specifications. A tight tolerance is placed on the stage tracking performance to minimize image distortion and provide high position repeatability. The wafer must track the reticle with less than +/- 3 nm of position error and jitter must not exceed 10 nm rms. To meet these performance requirements, magnetically levitated positioning stages utilizing a system of sophisticated control electronics will be used. System modeling and experimentation have contributed to the development of the positioning system and results indicate that desired ETS performance is achievable.

Wronosky, John B.; Smith, Tony G.; Craig, Marcus J.; Sturgis, Beverly R.; Darnold, Joel R.; Werling, David K.; Kincy, Mark A.; Tichenor, Daniel A.; Williams, Mark E.; Bischoff, Paul M.

2000-07-01

453

A through-wafer interconnect in silicon for RFICs  

Microsoft Academic Search

In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight.

Joyce H. Wu; Jörg Scholvin; Jesús A. del Alamo

2004-01-01

454

Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence  

E-print Network

Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence H. C. Sio, Z-mediated nonclassical crystal growth of sodium fluorosilicate nanowires and nanoplates AIP Advances 1, 042165 (2011) Crystal phase and growth orientation dependence of GaAs nanowires on NixGay seeds via vapor

455

The effect of various wafer thicknesses on hot spot temperature  

Microsoft Academic Search

Hot spots on thin wafers of IC packages are becoming an important issue in thermal and electrical engineering. To investigate these hot spots, we developed a diode temperature sensor array (DTSA) that consists of an array of 32 times 32 diodes (1,024 diodes) in an 8 mm x 8 mm surface area. We used chemical-mechanical planarization to make DTSA chips

Kyo Sung Choo; Il Young Han; Sung Jin Kim

2008-01-01

456

Wafer yield prediction by the Mahalanobis-Taguchi system  

Microsoft Academic Search

The distribution of yield from the production lines is concentrated at a high-yield area and tapers down to the lower-yield area. Production management would find it useful if the yield of individual wafers could be forecast. The yield is determined by the variability of electrical characteristics and dust. In this study, only the variability of electrical characteristics was discussed. One

M. Asada

2001-01-01

457

Wafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition  

E-print Network

are fabricated using mechanical exfoliation of graphite,15-18 which have limited sizes of µm2 and are certainlyWafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition Seunghyun Lee gap opening in bilayer graphene opens a new door for making semiconducting graphene without aggressive

Zhong, Zhaohui

458

Fabricating a Microcomputer on a Single Silicon Wafer  

NASA Technical Reports Server (NTRS)

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Evanchuk, V. L.

1983-01-01

459

Ultra-Gradient Test Cavity for Testing SRF Wafer Samples  

SciTech Connect

A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

2010-11-01

460

Multi-wafer slicing with a fixed abrasive  

NASA Technical Reports Server (NTRS)

A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

1988-01-01

461

Crack propagation and fracture in silicon wafers under thermal stress  

PubMed Central

The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M. Reyes; Baumbach, Tilo; Tanner, Brian K.

2013-01-01

462

Steel Bridge Fatigue Crack Detection with Piezoelectric Wafer Active Sensors  

E-print Network

Steel Bridge Fatigue Crack Detection with Piezoelectric Wafer Active Sensors Lingyu Yu1 , Victor acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since of the fatigue life for these details is consumed while the fatigue crack is too small to be detected. Hence

Giurgiutiu, Victor

463

InP based photonic crystal microlasers on silicon wafer  

Microsoft Academic Search

We report on 2D photonic crystal InP membrane micro-lasers transferred onto a silicon wafer. Two types of lasers are investigated: microcavities and defect-free structures, exploiting either conventional defect modes, or DFB-like modes. Room temperature low threshold laser operation has been performed for low sized devices.

C. Monat; C. Seassal; X. Letartre; P. Regreny; P. Rojo-Romeo; P. Viktorovitch; M. Le Vassor d'Yerville; D. Cassagne; J. P. Albert; E. Jalaguier; S. Pocas; B. Aspar

2003-01-01

464

Detection and classification of defect patterns on semiconductor wafers  

Microsoft Academic Search

The detection of process problems and parameter drift at an early stage is crucial to successful semiconductor manufacture. The defect patterns on the wafer can act as an important source of information for quality engineers allowing them to isolate production problems. Traditionally, defect recognition is performed by quality engineers using a scanning electron microscope. This manual approach is not only

Chih-Hsuan Wang; Halima Bensmail

2006-01-01

465

Localized induction heating solder bonding for wafer level MEMS packaging  

Microsoft Academic Search

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 °C during bonding, thus

Hsueh-An Yang; Mingching Wu; Weileun Fang

2005-01-01

466

ion-implantation energy dependence of electronic transport properties in the MeV range in n-type silicon wafers using frequency-domain  

E-print Network

Technologies, Suzhou University, Suzhou, Jiangsu 215006, People's Republic of China Andreas Mandelis and Jordan of view because it allows changing the doping profile of a power device down to considerable depth. How-type silicon wafers using frequency-domain photocarrier radiometry Chinhua Wanga Institute of Modern Optical

Mandelis, Andreas

467

Ericsson's VLSI mini-fab strategy; low volume VLSI fab to ensure short time to market for Ericsson telecom systems and products  

Microsoft Academic Search

Ericsson adopted a rather different approach when it planned a submicron fab at its Kista site in Sweden. Wafer manufacturing volumes were less important than time factors, since the principal role of the fab is to reduce the design and manufacturing lead times for the complex ASICs needed in the company's telecommunications products and systems. In this paper, the author

K.-I. Engde

1995-01-01

468

A study of defects on EUV masks using blank inspection, patterned mask inspection, and wafer inspection  

E-print Network

-701 5 ASML, 25 Corporate Circle, Albany, NY 12203 ABSTRACT The availability of defect-free masks remains) in Albany. After exposure, the wafers were inspected with a wafer inspection tool (KLA 28XX) at CNSE

469

Kinematical and mechanical aspects of wafer slicing  

NASA Astrophysics Data System (ADS)

Some recently achieved results concerning the technological fundamentals of slurry sawing are presented. The specific material removal process and the related kinematic and geometric contact conditions between workpiece and saw blade are described. The result of a functional description of the slurry sawing process is presented, expressing the main process criteria, such as infeed per stroke, specific removal rate, specific tool wear, and vertical stroke intensity, in terms of the dominating process parameters, such as stroke length, width of workpiece, stroke frequency, specific cutting force and slurry specification.

Werner, P. G.

1982-02-01

470

Modeling and testing of PZT and PVDF piezoelectric wafer active sensors  

NASA Astrophysics Data System (ADS)

Piezoelectric wafer active sensors (PWAS) used in structural health monitoring (SHM) applications are able to detect structural damage using Lamb waves. PWAS are small, lightweight, unobtrusive and inexpensive. They achieve direct transduction between electric and elastic wave energies. PWAS are charge mode sensors and can be used as both transmitters and receivers. The focus of this paper is to find a suitable in situ piezoelectric active sensor for sending and receiving Lamb waves to be used in the SHM of structures with a curved surface. Current SHM technology uses brittle piezoceramic (PZT) wafer active sensors. Since piezoceramics are brittle, this approach could only be used on flat surfaces. The motivation of our research was to explore the use of flexible piezoelectric materials, e.g. piezoelastic polymers such as PVDF. However, PVDF stiffness is orders of magnitude lower than the PZT stiffness, and hence PVDF Lamb wave transmitters are much weaker than PZT transmitters. Thus, our research proceeded in two main directions: (a) to model and understand how piezoelectric material properties affect the behaviour of piezoelectric wafer active sensors; and (b) to perform experiments to test the capabilities of the flexible PVDF PWAS in comparison with those of stiffer but brittle PZT PWAS. We have shown that, with appropriate signal amplification, PVDF PWAS can perform the same Lamb wave transmission and reception functions currently performed by PZT PWAS. The experimental results of PZT-PWAS and PVDF-PWAS have been compared with a conventional strain gauge. The theoretical and experimental results in this study gave a basic demonstration of the piezoelectricity of PZT-PWAS and PVDF-PWAS.

Lin, B.; Giurgiutiu, V.

2006-08-01

471

Wafer bonding process for building MEMS devices  

NASA Astrophysics Data System (ADS)

The technology for the measurement of colour rendering and colour quality is not new, but many parameters related to this issue are currently changing. A number of standard methods were developed and are used by different specialty areas of the lighting industry. CIE 13.3 has been the accepted standard implemented by many users and used for many years. Light-emitting Diode (LED) technology moves at a rapid pace and, as this lighting source finds wider acceptance, it appears that traditional colour-rendering measurement methods produce inconsistent results. Practical application of various types of LEDs yielded results that challenged conventional thinking regarding colour measurement of light sources. Recent studies have shown that the anatomy and physiology of the human eye is more complex than formerly accepted. Therefore, the development of updated measurement methodology also forces a fresh look at functioning and colour perception of the human eye, especially with regard to LEDs. This paper includes a short description of the history and need for the measurement of colour rendering. Some of the traditional measurement methods are presented and inadequacies are discussed. The latest discoveries regarding the functioning of the human eye and the perception of colour, especially when LEDs are used as light sources, are discussed. The unique properties of LEDs when used in practical applications such as luminaires are highlighted.

Pabo, Eric F.; Meiler, Josef; Matthias, Thorsten

2014-06-01

472

Technology.  

ERIC Educational Resources Information Center

Discussion of technology focuses on instructional technology. Topics include inquiry and technology; curriculum development; reflection and curriculum evaluation; criteria for technological innovations that will increase student motivation; standards; impact of new technologies on library media centers; software; and future trends. (LRW)

Callison, Daniel

2002-01-01

473

Wafer temperature measurement in PVD systems using the Co–Si reaction  

Microsoft Academic Search

It is becoming increasingly important to control the wafer temperature during IC processing, e.g. PVD. To measure the wafer temperature in PVD systems it is possible to use the Co–Si reaction. The difference in sheet resistance of the Co–Si phases, which form at different temperatures, is used to measure maximum wafer temperature in a PVD chamber. The maximum wafer temperature

A. M. van Graven; R. A. M. Wolters

2000-01-01

474

Characterization, modeling, and design of an electrostatic chuck with improved wafer temperature uniformity  

NASA Astrophysics Data System (ADS)

The resulting temperature distribution of a silicon wafer held by an electrostatic chuck (ESC) in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor is characterized and modeled. The effects of the clamping voltage VESC, pressure between the ESC and wafer PHe, and the surface finish and pattern on the ESC are investigated. Heat transfer coefficients between the wafer and various ESCs are determined experimentally. A model is developed to predict the temperature distribution at the surface of the wafer, and used to explain the experimentally observed temperature variations both within wafer and between different chucks. The model is then used to aid in the design of an ESC which provides improved temperature uniformity at the wafer surface. The results of this study indicate: (a) the thermal resistances across the interface between the wafer and ESC control both the absolute wafer temperature and the wafer temperature uniformity; (b) the surface roughness of the ESC and the size of the ``contact'' regions are major design factors controlling the absolute temperature of the wafer—the temperature can be adjusted by varying the value of VESC and fine tuned by adjusting the value of PHe; (c) the nonuniform temperature distribution across the wafer surface is dictated by the surface pattern on the ESC, the variation in surface roughness, and the size of the ESC relative to the wafer; (d) wafer temperature variations from chuck to chuck are reduced by controlling the surface finish of the ESC and by ensuring that PHe is a dominant heat transfer mechanism; and (e) maximum uniformity in the temperature of the wafer is obtained when the radius of the ESC is matched as closely as possible to that of the wafer. We have shown that numerical heat transfer models can be used to optimize the geometry of the ESC to provide a uniform distribution of temperature across the surface of the wafer.

Olson, Kurt A.; Kotecki, David E.; Ricci, Anthony J.; Lassig, Stephan E.; Husain, Anwar

1995-02-01

475

Electrochemical method for defect delineation in silicon-on-insulator wafers  

SciTech Connect

This patent describes an electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, T.R.; Jones, H.D.T.; Kelly, M.J.; Medernach, J.W.; Stevenson, J.O.; Tsao, S.S.

1991-05-14

476

A novel VLSI architecture of motion compensation for multiple standards  

Microsoft Academic Search

Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264 and the Chinese AVS, many efficient coding tools have been introduced into MC, such as new motion vector prediction, bi-directional matching, quarter precision interpolation, etc. However, these new

Junhao Zheng; Wen Gao; David Wu; Don Xie

2008-01-01

477

Testing On-Die Process Variation in Nanometer VLSI  

Microsoft Academic Search

As device technology progresses toward 45 nm and beyond, the fidelity of process parameter modeling becomes questionable. The authors propose the concept of process variation (PV) testing, which involves applying an innovative fault model and test methodology that uses PV sensing circuitry and frequency domain analysis. Rather than pinpointing the variation of different parameters, the architecture proposed by the authors

Mehrdad Nourani; Arun Radhakrishnan

2006-01-01

478

Influence of a lift hole-equipped pin chuck on wafer flatness  

Microsoft Academic Search

A site flatness of less than 32nm will be required when fabricating next-generation devices. A pin chuck is used to flatten a warped wafer. This chuck has three lift holes that are utilized when loading and unloading wafers. These holes deteriorate local flatness. This paper describes the influence of wafer thickness and the diameters of lift holes and chuck pins

Atsunobu Une; Nagahisa Ogasawara; Tetsuo Fukuda; Masanori Yoshise; Ping Xin

2009-01-01

479

Effects of wafer impedance on the monitoring and control of ion energy in plasma reactors  

Microsoft Academic Search

Ion kinetic energy in plasma reactors is controlled by applying radio-frequency (rf) substrate bias, but the efficiency and reproducibility of such control will be affected if the wafer being processed has a significant electrical impedance. Here, the effects of wafer impedance were studied by modeling and electrical measurements. Models of wafer impedance were proposed and tested by comparing model predictions

Mark A. Sobolewski

2006-01-01

480

Enhanced Growth of Thermal Oxide Due to Impurity Absorption from Adjoining Contaminated Silicon Wafers  

Microsoft Academic Search

Enhanced growth of thermal oxide at high temperature is investigated when a silicon wafer is situated behind an adjoining contaminated one. Impurities reside on the back surface of the wafer due to chucking with a stainless steel plate, depending on the surface roughness. During oxidation, the impurities spread to the adjoining wafers, causing enhanced oxide growth with the convex side

Hirofumi Shimizu; Masashi Yamamoto

1992-01-01

481

Dynamic deformation of a wafer above a lift hole and influence on flatness due to chucking  

Microsoft Academic Search

A site flatness of less than 26nm will be required when fabricating next-generation devices. A pin chuck is used to flatten warped wafers. This chuck has lift holes for loading and unloading wafers and a ring seal around its periphery. The lift holes and seal deteriorate the local flatness. This paper describes the influence of local dynamic deformation on wafer

Atsunobu Une; Kenichiro Yoshitomi; Masaaki Mochida

2011-01-01

482

Beam test results of ion-implanted silicon strip detectors on a 100 mm wafer  

Microsoft Academic Search

The use of planar silicons trip detectors in both position sensitive and energy dispersive applications has rapidly increased. Detector systems of large angular coverage unavoidably consist of a large number of individual detector plates traditionally processed on 3 inch silicon wafers. The effective wafer processing area is almost doubled by the use of 100 mm wafers, enabling detector designs with

Iiro Hietanen; Jukka Lindgren; Risto Orava; Tuure Tuuva; R. Brenner; Mikael Andersson; Kari Leinonen; Hannu Ronkainen; L. Hubbeling; Michal Turala; W. Dulinski; D. Husson; A. Lounis; M. Schaeffer; R. Turchetta; J. Chauveau

1991-01-01

483

Evaluating different sampling techniques for process control using automated patterned wafer inspection systems  

Microsoft Academic Search

To evaluate sampling for automated defect inspections, a series of four inspection areas ranging from <1 cm2 to >4 cm2 were performed. Using an automated patterned wafer inspection system, 20 wafers were inspected for each of the sample sizes. Inspected die were selected in a random pattern across the wafer and remained the same for each inspection. The inspected area

Dennis Lazaroff; David Bakker; Derek R. Granath

1991-01-01

484

Optimized wafer-probe and assembled package test design for analog circuits  

Microsoft Academic Search

It is well known that wafer-probe test costs of analog ICs are an order of magnitude less than the corresponding test costs of assembled packages. It is therefore natural to push as much of the testing process into wafer-probe testing as possible to reduce the scope of assembled package testing. However, the signal drive and response observation capabilities during wafer

Soumendu Bhattacharya; Abhijit Chatterjee

2005-01-01

485

Automation of wafer handling in legacy semiconductor faba true cultural change  

Microsoft Academic Search

When yield analysis revealed extensive die losses associated with wafer scratches, our fab management commissioned a comprehensive program to completely eliminate manual handling of wafers during manufacturing. This experience constituted a true cultural change for our legacy fab, which throughout a 15-year history had excelled at low cost, low cycle time manufacturing but had neglected fundamental improvements in wafer handling

R. L. Guldi; M. T. Whitfield; D. E. Paradis; F. D. Poag; D. P. Jensen

1997-01-01

486

Technology platform for hybrid integration of MOEMS on reconfigurable silicon micro-optical table  

E-print Network

Technology platform for hybrid integration of MOEMS on reconfigurable silicon micro-optical table S micromachining of standard silicon wafer (baseplate) or SOI wafer (holders). The design and technology of RFS. In this paper we present technological platform to build MOEMS devices on reconfigurable silicon free

Paris-Sud XI, Université de

487

Studies of 100 um-thick silicon strip detector with analog VLSI readout  

E-print Network

We evaluate the performances of a 100 um-thick silicon strip detector (SSD) with a 300 MeV proton beam and a 90Sr beta-ray source. Signals from the SSD have been read out using a VLSI chip. Common-mode noise, signal separation efficiency and energy resolution are compared with those for the SSD's with a thickness of 300 um and 500 um. Energy resolution for minimum ionizing particles (MIP's) is improved by fitting the non-constant component in a common-mode noise with a linear function.

T. Hotta; M. Fujiwara; T. Kinashi; Y. Kuno; M. Kuss; T. Matsumura; T. Nakano; S. Sekikawa; H. Tajima

1998-12-18

488

A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition  

Microsoft Academic Search

\\u000a Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to\\u000a robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a\\u000a new algorithm for reducing multiply-and-accumulation operation by thresholding in a projection field and by performing weight\\u000a decomposition in a 2-D neuron array. We also propose a

Osamu Nomura; Takashi Morie; Keisuke Korekado; Masakazu Matsugu; Atsushi Iwata

2004-01-01

489

Thermal transport properties of organic films for advanced VLSI systems  

Microsoft Academic Search

Polymer films play an important role in the development of fast integrated circuits and novel electronic and optoelectronic devices. A wide variety of polymer films are being developed for application as low-dielectric-constant passivation for multilevel metallization in highly-integrated circuits. A new trend in novel electronic device technologies employs electrically-conducting polymer films as active layers because of the ease with which

Katsuo Kurabayashi

1998-01-01

490

Light scatter from defects on chemically-mechanically polished wafers  

NASA Astrophysics Data System (ADS)

Detection and reduction of defects on chemically-mechanically polished (CMP) wafers are important concerns in semiconductor manufacturing. The physical and light scattering characteristics of typical CMP wafer surface defects including roughness, dishing, particles, and scratches are investigated in this dissertation. A new scatterometer is developed for the light scattering study. The system measured "true" bidirectional reflectance distribution functions (BRDF) and differential scattering cross sections (DSC) in plane of incidence. Through comparing experimental results with modeling and with expected values from standard samples, the system is proven to be able to deliver accurate scattering measurements on small features and wafer surfaces. The physical characteristics of metal roughness, metal dishing, contaminants, and scratches on tungsten (W) and copper (Cu) CMP wafers are studied. The power spectral density of W and Cu, the metal dishing's dependency on linewidth and pattern density, the different compositions of various contaminants, and the appearances of scratches are investigated. The scattering characteristics of the patterned W and Cu CMP wafer substrates are studied. A light scattering scheme which measures metal roughness on a patterned wafer is developed based on the Rayleigh-Rice vector perturbation theory. The dishing's dependency on pattern density is characterized using light scattering, and the scatter from Cu line-edges is measured and compared to the scatter from a step simulated using the Kirchhoff approximation method. The angle-resolved scatter from individual 0.305 mum and 0.482 mum polystyrene latex spheres on blanket silicon (Si), silicon dioxide (SiO 2) film, and W film surfaces is measured and the effects of roughness and a dielectric film on particle scatter are investigated. The scattering characteristics of diamond-tip scribed scratches on a filmed surface, which are long linear scratches and are about 0.8 mum wide and 90 nm deep, are studied as a function of incident angle and polarization. Finally, a light scattering scheme that classifies particles and scratches is developed using their different dependency of differential scattering cross sections on beam diameter.

Ding, Ping

2000-10-01

491

Liquid crystal lens auto-focus extended to optical image stabilization for wafer level camera  

NASA Astrophysics Data System (ADS)

Miniaturization and reduction of production cost of optical components in consumer electronics leads to wafer level optics. This miniaturization, associated with the increase of CMOS sensors resolution, generates new needs such as auto-focus (AF) and optical image stabilization (OIS) in order to reduce the blurring caused by hand jitter. In this paper, we propose a wafer scale technology to perform AF and introduce OIS functionality. We managed to create a tunable focal lens by filling with nematic liquid crystal (LC) an assembly of two glass substrates coated with circular hole patterned chromium electrodes and resistive transparent layers of Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT-PSS). When a voltage with tunable magnitude and frequency is applied to the electrodes, the resistive layer creates a non-uniform voltage distribution from the edge to the center of the aperture which depends on electrical parameters of PEDOT-PSS and LC. The resultant electric field generates a gradient orientation of the nematic director which allows to focus light polarized along the director. It is also possible to shift the optical axis of the lens by dividing the hole patterned electrodes in several sectors and to apply different voltages on each sectors. The principle of the shifting effect has been demonstrated but its magnitude has to be increased by using more adapted electrode structure to ensure the OIS function. Finally, we characterised the dynamical behaviour of the lens in both focus and shifting modes.

Fraval, Nicolas; Berier, Frédéric

2011-03-01

492

A hermetic and room-temperature wafer bonding technique based on integrated reactive multilayer systems  

NASA Astrophysics Data System (ADS)

This paper focuses on direct deposition and patterning of reactive and nano-scale multilayer films at wafer level. These multilayer structures are called integrated reactive material systems (iRMS). In contrast to the typically used nickel (Ni)/ aluminum (Al) systems, in this work we needed to have our total multilayer film thicknesses smaller than 2.5?µm to reduce stress within the multilayer as well as deposition costs. Thus, we introduced new high energetic iRMS. These films were deposited by using alternating magnetron sputtering from high purity Al- and palladium (Pd)-targets to obtain films with a defined Al:Pd atomic ratio. In this paper, we present the result for reaction characteristics and reaction velocities which were up to 72.5?m?s?1 for bond frames with lateral dimensions as low as 20?µm. Furthermore, the feasibility of silicon (Si)–Si, Si–glass as well as Si–ceramic hermetic and metallic wafer bonding at room temperature is presented. We show that by using this bond technology, strong (maximum shear strengths of 235?MPa) and hermetically sealed bond interfaces can be achieved without any additional solder material.

Braeuer, J.; Gessner, T.

2014-11-01

493

CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties  

PubMed Central

This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 ?m standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive. PMID:23235449

Chuang, Wan-Chun; Hu, Yuh-Chung; Chang, Pei-Zen

2012-01-01

494

Cartilage-retaining Wafer Resection Osteotomy of the Distal Ulna  

PubMed Central

Ulnar-sided wrist pain resulting from ulnar impaction is common. We describe a new cartilage-retaining wafer resection osteotomy designed to keep the cartilage intact and decompress the ulnocarpal articulation without requiring internal fixation. We retrospectively reviewed seven patients with ulnar impaction who had the procedure. The minimum followup was 14 months (mean, 30 months; range, 14–38 months). The mean change in ulnar variance was ?1.29 mm. Patients showed radiographic healing by a mean of 11 weeks. Our preliminary results suggest the cartilage-retaining wafer resection osteotomy may be an effective way to unload the ulnocarpal joint without requiring internal fixation or destruction of the distal ulna cartilage. Level of Evidence: Level IV, therapeutic study. See the Guidelines for Authors for a complete description of levels of evidence. PMID:18196423

Macksoud, Wadih S.

2008-01-01

495

JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES  

SciTech Connect

There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup