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1

High speed synchronizer card utilizing VLSI technology  

NASA Technical Reports Server (NTRS)

A generic synchronizer card capable of providing standard NASA communication block telemetry frame synchronization and quality control was fabricated using VLSI technology. Four VLSI chip sets are utilized to shrink all the required functions into a single synchronizer card. The application of VLSI technology to telemetry systems resulted in an increase in performance and a decrease in cost and size.

Speciale, Nicholas; Wunderlich, Kristin

1988-01-01

2

MEMS Wafer-level Packaging Technology Using LTCC Wafer  

NASA Astrophysics Data System (ADS)

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40C30min/+125C30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

3

Advancements in bipolar VLSI circuits and technologies  

NASA Astrophysics Data System (ADS)

This paper gives an overview on bipolar circuit/device techniques for VLSI logic and memories. Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic (TTL) and emitter-coupled logic (ECL) are still mainly applied, but also new circuit technologies such as integrated injection logic or merged transistor logic (I2L/MTL) and Schottky transistor logic (STL) or integrated Schottky logic (ISL) have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected by technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 micron dimensions or below. Some experimental data and projections indicate the strong potentials of bipolar VLSI.

Wiedmann, S. K.

1984-06-01

4

Potential impact of VLSI technologies on guided missile design  

Microsoft Academic Search

Some aspects of the anticipated impact of emerging VLSI technologies on tactical missiles, present and future generations are discussed. VLSI evolution represents a unique example of a very dynamic and pervasive trend in commercial and military applications. It is our opinion, however, that the characteristics of this trend are quite different in tactical missiles, not only compared to commercial electronics

H. A. Maurer; K. S. Kongelbeck

1985-01-01

5

A wafer-scale 3-D circuit integration technology  

Microsoft Academic Search

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.

James A. Burns; Brian F. Aull; Chenson K. Chen; Chang-Lee Chen; Craig L. Keast; Jeffrey M. Knecht; V. Suntharalingam; K. Warner; P. W. Wyatt; D.-R. W. Yost

2006-01-01

6

VLSI and optical technologies for mass data processing  

Microsoft Academic Search

The authors discuss several technologies that can improve the performance of database systems. They identify several issues that must be addressed for the commercialization of these technologies. The study is summarized as follows: (i) VLSI circuits are not the bottleneck for associative search and aggregation operations; (ii) holographical technology is promising for high-density, high-speed, and nonvolatile random access storage (further

K. C. Lee; W. Mansfield; E. G. Paek; A. Von Lehmen; L. A. Wang

1991-01-01

7

Through wafer via technology for 3-D packaging  

Microsoft Academic Search

Through wafer via fabrication has been one of the key technologies for 3-D packaging and microsystem packaging. Four different through wafer via fabrication technologies and applications are reviewed, such as laser drilling, deep reactive ion etching (DRIE), photo assisted electro chemical etching (PAECE) and KOH etching. Especially, KOH etching is widely used in bulk micromachining of microelectromechanical system (MEMS) fabrication

Guoqiang Feng; Xiao Peng; Jian Cai; Shuidi Wang

2005-01-01

8

Advanced plasma etching processes for dielectric materials in VLSI technology  

NASA Astrophysics Data System (ADS)

Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the etch processes included measurement of the etch rates, etch profiles, etch depth, top-down images, selectivity and etch margin. The cross-section images were taken on the Hitachi S-4500 Scanning Electron Microscope (SEM, Tokyo, Japan) tool.

Wang, Juan Juan

9

Potential impact of VLSI technologies on guided missile design  

NASA Astrophysics Data System (ADS)

Some aspects of the anticipated impact of emerging VLSI technologies on tactical missiles, present and future generations are discussed. VLSI evolution represents a unique example of a very dynamic and pervasive trend in commercial and military applications. It is our opinion, however, that the characteristics of this trend are quite different in tactical missiles, not only compared to commercial electronics but even to strategic or space missiles. Considering the particular objectives and constraints as they seem common to most tactical guided missiles and smart munitions, the VLSI technologies should be almost tailored to this application. However, there are some perequisites to be considered to make the introduction of VLSIs successful. Here are some examples: careful planning to be in step with the maturity of the VLSI technology, sensible selection of targets for insertion or new designs and - quite importantly - consideration of program stability in terms of volume, rates, and changes. From a technical viewpoint alone, the current trend to light and small, 4- to 8-inch-diameter configuration whether ground or air-launched encourages an early insertion of VLSIs. Electronic packaging with unusual form factors, e.g., having a central hole for warhead effectiveness, high density and low weight, and low power dissipation, poses conflicting requirements to the missile designer. With very few exceptions, such as in magnetics or battery chemistry, the electronics sections cannot benefit from other technological breakthroughs. It is the evolution of monolithic large scale integration of circuits on Silicon and to a lesser degree on Gallium Arsenide which bears the main load to meeting these criteria of processing density at minimum power dissipation, and of providing an ever-increasing functional throughput. Those VLSI embodiments which appear to be most likely to influence missile electronics are defined. They may be divided into four categories, with some ranking indicated regarding their maturity and avaliability, as well as nonrecurring cost weight: (1) Memories (RAM and ROM); (2) Catalog special devices (ADC, DAC, (CP); (3) Semicustom (CGAs); and (4) Full custom.

Maurer, H. A.; Kongelbeck, K. S.

1985-08-01

10

Wafer-level vacuum/hermetic packaging technologies for MEMS  

NASA Astrophysics Data System (ADS)

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

11

VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.  

ERIC Educational Resources Information Center

As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications

Bayoumi, Magdy

12

9.1 MICROSYSTEMS TECHNOLOGY LABORATORIES ANNUAL RESEARCH REPORT 2009 VLSI MeMo SerIeS VLSI MeMo SerIeS  

E-print Network

9.1 MICROSYSTEMS TECHNOLOGY LABORATORIES ANNUAL RESEARCH REPORT 2009 VLSI MeMo SerIeS VLSI MeMo SerIeS and Robust Optimization of Analog Circuits D. Lim 08-2046 Advanced Materials, Process, and Designs. M. Zhak 09-2053 Circuit Design for Logic Automata K. Chen 09-2054 Nanofluidic System for Single

Reif, Rafael

13

VLSI technology for smaller, cheaper, faster return link systems  

NASA Technical Reports Server (NTRS)

Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

1994-01-01

14

GaAs VLSI technology and circuit elements for DSP  

NASA Astrophysics Data System (ADS)

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Mikkelson, James M.

1990-10-01

15

Computer-Aided Design of Mixed-Technology VLSI Systems  

E-print Network

Capacitor Fabrication · Grants from SRC, Intel, TI, DARPA #12;Outline F Thermal VLSI Engineering ­ Cell. Optimal Temp. Dist. #12;Substrate Temperature Calculation by Finite Difference Method (FDM) · Model

Shanbhag, Naresh R.

16

A LOW COST WAFER-LEVEL MEMS PACKAGING TECHNOLOGY Pejman Monajemi, Paul J. Joseph*  

E-print Network

A LOW COST WAFER-LEVEL MEMS PACKAGING TECHNOLOGY Pejman Monajemi, Paul J. Joseph* , Paul A. Kohl-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied

Ayazi, Farrokh

17

Wafer-level manufacturing technology of glass microlenses  

NASA Astrophysics Data System (ADS)

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

18

A Wafer Transfer Technology for MEMS Adaptive Optics  

NASA Technical Reports Server (NTRS)

Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

Yang, Eui-Hyeok; Wiberg, Dean V.

2001-01-01

19

Advances in bipolar VLSI  

NASA Astrophysics Data System (ADS)

Bipolar IC processes are reviewed, and the impact of BiCMOS technology on bipolar VLSI is discussed. The discussion covers standard emitter-coupled-logic (ECL) circuit configuration, on-chip line driving, output circuitry, series gating, ECL versus CML (current-mode logic), differential logic, noise margins, interconnect capacitance, bipolar VLSI transistor design and scaling, and processes for ECL VLSI.

Wilson, George R.

1990-11-01

20

Current technologies for very high performance VLSI IC's  

NASA Astrophysics Data System (ADS)

A review is given of III-V device performances with specific references to their use in high-speed signal processing and communications. Application-specific integrated circuits (ICs) are compared to emitter coupled logic (ECL) gate arrays in terms of density and speed, and specific attention is given to semicustom GaAs ICs. Performance and cost comparisons are presented in the form of critical path analyses and device sizes. The data-conversion applications for the III-V devices are set forth indicating that self-aligned GaAs MESFET technologies can be used for high-resolution flash ADCs because of their very low short-distance dispersions. GaAs is shown to be a viable alternative for silicon ECL and to be more useful in the fabrication of larger wafers of four inches. GaAs devices are more effective than silicon ECL if they can provide a gain of not less than a factor of five in the power-delay product.

Perea, Ernesto H.

1991-06-01

21

Advanced Dicing Technology for Semiconductor WaferStealth Dicing  

Microsoft Academic Search

ldquoStealth dicing (SD)rdquo was developed to solve inherent problems of a dicing process such as debris contaminants and unnecessary thermal damages on a work wafer. A completely dry process is another big advantage over other dicing methods. In SD, the laser beam power of transmissible wavelength is absorbed only around focal point in the wafer by utilizing the temperature dependence

Masayoshi Kumagai; Naoki Uchiyama; Etusji Ohmura; Ryuji Sugiura; Kazuhiro Atsumi; Kenshi Fukumitsu

2007-01-01

22

A VLSI implementation of DCT using pass transistor technology  

NASA Technical Reports Server (NTRS)

A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

Kamath, S.; Lynn, Douglas; Whitaker, Sterling

1992-01-01

23

Bonding pad models for silicon VLSI technologies and their effects on the noise figure of RF NPNs  

Microsoft Academic Search

VLSI technologies such as BiCMOS and high speed ECL Bipolar are candidates for mixed mode applications which include RF receiver functions. In order for these silicon technologies to achieve low noise characteristics one needs to optimize both the active device and the signal path to the IC interface. Studies in the bonding pad parasitics indicate that these path losses can

Natalino Camilleri; J. Kirschgessner; Julio Costa; David Ngo; David Lovelace

1994-01-01

24

Micromanipulator vision for wafer probing  

Microsoft Academic Search

An overview is presented of a micromanipulator vision system for use in automating various functions during the testing of a wafer for semiconductor parameters and inspection of VLSI circuits. It is assumed that the wafer under test is not necessarily in its proper orientation. It is required that certain probes be lowered automatically onto certain pads to inject test vectors

R. V. Dantu; N. J. Dimopoulos; R. V. Patel; A. J. Al-Khalili

1989-01-01

25

SEMICONDUCTOR TECHNOLOGY: Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology  

NASA Astrophysics Data System (ADS)

A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E.

Yuhan, Cao; Le, Luo

2009-08-01

26

Product assurance technology for custom LSI/VLSI electronics  

NASA Technical Reports Server (NTRS)

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

1985-01-01

27

Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors  

NASA Astrophysics Data System (ADS)

Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm2/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

Kim, SangHyeon; Ikku, Yuki; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung; Takenaka, Mitsuru; Takagi, Shinichi

2014-07-01

28

Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias  

NASA Astrophysics Data System (ADS)

The presented wafer-level packaging technology enables the direct integration of electrical interconnects during low-temperature wafer bonding of a cap substrate featuring through silicon vias (TSVs) onto a MEMS device wafer. The hybrid bonding process is based on hydrophilic direct bonding of plasma-activated Si/SiO2 surfaces and the simultaneous interconnection of the device metallization layers with Cu TSVs by transient liquid phase (TLP) bonding of ultra-thin AuSn connects. The direct bond enables precise geometry definition between device and cap substrate, whereas the TLP bonding does not require a planarization of the interconnect metallization before bonding. The complete process flow is successfully validated and the fabricated devices' characterization evidenced ohmic interconnects without interfacial voids in the TLP bond.

Khne, Stphane; Hierold, Christofer

2011-08-01

29

NASA VLSI 2007 Mohanty, Vadlamudi and  

E-print Network

NASA VLSI 2007 Mohanty, Vadlamudi and Kougianos 1 A Universal Voltage Level Converter for Multi University of North Texas dhruva@unt.edu #12;NASA VLSI 2007 Mohanty, Vadlamudi and Kougianos 2 Agenda Custom layout design at 90nm technology Conclusion and future works #12;NASA VLSI 2007 Mohanty, Vadlamudi

Mohanty, Saraju P.

30

VLSI neuroprocessors  

NASA Technical Reports Server (NTRS)

Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional techniques and enables multiple assignments, (many to many), not achievable with standard statistical approaches. Tactical movement planning (finding the best path from A to B) is accomplished with a digital two-dimensional concurrent processor array. By exploiting the natural parallel decomposition of the problem in silicon, a four order of magnitude speed-up over optimized software approaches has been demonstrated.

Kemeny, Sabrina E.

1994-01-01

31

Wafer mapping of total dose failure thresholds in a bipolar recessed field oxide technology  

SciTech Connect

Ionizing radiation failure thresholds were measured across a silicon wafer using 10 KeV x-rays to determine the success of hardened process modifications and to examine wafer level hardness assurance screening techniques. Topological wafer maps of the total dose failure response for Signetics 74F00 circuits are presented.

Titus, J.L.; Platteter, D.G.

1987-12-01

32

Process integration of single-wafer technology in a 300-mm fab, realizing drastic cycle time reduction with high yield and excellent reliability  

Microsoft Academic Search

In this paper, we discuss a new technology implemented with single-wafer processing for a 300-mm fab. Newly developed equipment and chemicals reduce the process time and provide cost savings. The combination of fully automated systems and single-wafer processing significantly reduces queuing time. The process has been re-integrated to eliminate long time processes and make it suitable for single-wafer technologies. As

Shuji Ikeda; Kazunori Nemoto; Michimasa Funabashi; Toshiyuki Uchino; Hirohiko Yamamoto; Noriyuki Yabuoshi; Yasushi Sasaki; Kazuhiro Komori; Norio Suzuki; Shinji Nishihara; Shunji Sasabe; Atsuyoshi Koike

2003-01-01

33

Multimedia systems play a central part in many human activities. Due to the significant advances in the VLSI technology, there is an  

E-print Network

advances in the VLSI technology, there is an increasing demand for portable multimedia appliances capableAbstract Multimedia systems play a central part in many human activities. Due to the significant a steady move from stand- alone (or desktop) multimedia to deeply distributed multimedia systems. Whereas

Pedram, Massoud

34

Thin-film encapsulation technology for above-IC MEMS wafer-level packaging  

NASA Astrophysics Data System (ADS)

This work presents a low-cost and low-temperature wafer-level packaging solution for microelectromechanical systems (MEMS) devices. Heat-sensitive polymer poly(propylene carbonate) is used as the sacrificial material to release the capping layer in a clean and fast manner. Free-standing caps made of amorphous silicon carbide films and as large as 450 m in diameter are successfully fabricated. To demonstrate the validity of this technology, surface-micromachined Pirani vacuum gauges are fabricated as an example of MEMS devices and encapsulated. Capped Pirani gauges respond to pressure between 1 mTorr and 1 atm. The Pirani gauges are sealed with Parylene C films that exhibit near-hermetic properties and the initial sealing pressure for 300 m diameter cavities is characterized to be in the range of tens of torr.

Zhang, Qing; Cicek, Paul-Vah; Nabki, Frederic; El-Gamal, Mourad

2013-12-01

35

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics  

NASA Technical Reports Server (NTRS)

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

36

2236 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 16, NO. 12, DECEMBER 1998 Wafer-Fused Optoelectronics for Switching  

E-print Network

2236 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 16, NO. 12, DECEMBER 1998 Wafer-Fused Optoelectronics be compatible for coupling with fiber ribbon cables and should incorporate integrated optical amplifiers. In the following, after discussion of various design issues for fused vertical couplers, their fabrication

37

Plate-like structure health monitoring based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers  

NASA Astrophysics Data System (ADS)

Piezoelectric ceramic wafers are applied for the excitation and detection of ultrasonic guided waves to determine the health state of plate-like structures. Two PZT wafers, whose diameter is 11mm and thickness is 0.4mm respectively, are bonded permanently on the surface of a 1mm thick aluminum plate. One of these wafers is actuated by sinusoidal tone burst at various frequencies ranging from 100kHz to 500kHz, the other one is used as a receiver for acquiring ultrasonic guided wave signals. According to the amplitudes and shapes of these received signals, guided wave modes and their proper frequency range by using these wafers are determined. For the improvement of the signal-to-noise ratio, the Daubechies wavelet of order 40 is used for signal denoising as the mother wavelet. Furthermore, the detection of an artificial cylindrical through-hole defect is achieved by using S0 at 300kHz. Experimental results show that it is feasible and effective to detect defects in plate-like structures based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers.

Liu, Zenghua; Zhao, Jichen; He, Cunfu; Wu, Bin

2008-11-01

38

Across wafer focus mapping and its applications in advanced technology nodes  

Microsoft Academic Search

The understanding of focus variation across a wafer is crucial to CD control (both ACLV and AWLV) and pattern fidelity on the wafer and chip levels. This is particularly true for the 65nm node and beyond, where focus margin is shrinking with the design rules, and is turning out to be one of the key process variables that directly impact

Gary Zhang; Stephen DeMoor; Scott Jessen; Qizhi He; Winston Yan; Sopa Chevacharoenkul; Venugopal Vellanki; Patrick Reynolds; Joe Ganeshan; Jan Hauschild; Marco Pieters

2006-01-01

39

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories  

NASA Astrophysics Data System (ADS)

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

40

Wafer scale nano-membranes supported on a silicon microsieve using thin-film transfer technology  

Microsoft Academic Search

A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independent of the thin film, which is later transferred onto it by fusion bonding, thus providing flexibility in design and processing steps. Using this thin-film transfer technique, nano-membranes down

Sandeep Unnikrishnan; Henri Jansen; Erwin Berenschot; Miko Elwenspoek

2008-01-01

41

Laser wafering for silicon solar  

Microsoft Academic Search

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g\\/W{sub p} (grams\\/peak watt) polysilicon usage

Thomas Aquinas Friedmann; William C. Sweatt; Bradley Howell Jared

2011-01-01

42

Optical interconnections for VLSI systems  

Microsoft Academic Search

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The

S.-Y. Kung; R. A. Athale; Sun-Yuan Kung

1984-01-01

43

Optical interconnects for neural and reconfigurable VLSI architectures  

Microsoft Academic Search

The increasing transistor density in very large-scale integrated (VLSI) circuits and the limited pin member in the off-chip communication lead to a situation described as interconnect crisis in micro-electronics. Optoelectronic VLSI (OE-VLSI) circuits using short-distance optical interconnects and optoelectronic devices like microlaser, modulator, and detector arrays for optical off-chip sending and receiving offer a technology to overcome this crisis. However,

DIETMAR FEY; WERNER ERHARD; MATTHIAS GRUBER; JRGEN JAHNS; HARTMUT BARTELT; GUIDO GRIMM; LUTZ HOPPE; STEFAN SINZINGER

2000-01-01

44

Toward 300 mm wafer-scalable high-performance polycrystalline chemical vapor deposited graphene transistors.  

PubMed

The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26,000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ? 74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ? 40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available. PMID:25198884

Rahimi, Somayyeh; Tao, Li; Chowdhury, Sk Fahad; Park, Saungeun; Jouvray, Alex; Buttress, Simon; Rupesinghe, Nalin; Teo, Ken; Akinwande, Deji

2014-10-28

45

Bondability of processed glass wafers  

NASA Astrophysics Data System (ADS)

The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness will result in small real area of contact, and therefore yield voids in the bonding interface. Usually, the root mean square roughness (RMS) or the mean roughness (Ra) are used as parameters to evaluate the wafer bondability. It was found from experience that for a bondable wafer surface the mean roughness must be in the subnanometer range, preferentially less than 0.5 nm. When the surface roughness exceeds a critical value, the wafers will not bond at all. However RMS and Ra were found to be not sufficient for evaluating the wafer bondability. Hence one tried to relate wafer bonding to the spatial spectrum of the wafer surface profile and indeed some empirical relations that have been found. The first, who proposed a theory on the problem of the closing gaps between contacted wafers was Stengl. This gap-closing theory was then further developed by Tong and Gosele. The elastomechanics theory was used to study the balance between the decrease of surface energy due to the bonding and the increase of elastic energy due to the distortion of the wafer. They considered the worst case by assuming that both wafers have a waviness, with a wavelength (lambda) and a height amplitude h, resulting in a gap height of 2h in a head to head position. This theory is simple and can be used in practice, for studying the formation of the voids, or for constructing design rules for the bonding of deliberately structured wafers. But it is insufficient to know what is the real area of contact in the wafer interface after contact at room temperature because the wafer surface always possesses a random distribution of the surface topography. Therefore Gui developed a continuous model on the influence of the surface roughness to wafer bonding, that is based on a statistical surface roughness model Pandraud demonstrated experimentally that direct bonding between processed glass wafers is possible. This result cannot be explained by considering the RMS value of the surfaces only, because the wafers used show a RMS value larger than 1 nm. Based on the approach exposed in reference six, a rigorous analysis of wafer bonding of these processed glass wafers is presented. We will discuss the relation between the bonding process and different waveguide technologies used for implementing optical waveguides into one or both glass wafers, and give examples of optical devices benefiting from such a bonding process.

Pandraud, Gregory; Gui, Cheng-Qun; Pigeon, Florent; Lambeck, Paul V.; Parriaux, Olivier M.

1999-09-01

46

Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies  

NASA Astrophysics Data System (ADS)

We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of InP/Si substrates for bulk InP in the fabrication of such a four-junction solar cell could significantly reduce the substrate cost since the current prices for commercial InP substrates are much higher than those for Si substrates by two orders of magnitude. Direct heteroepitaxial growth of InP thin films on Si substrates has not produced the low dislocation-density high quality layers required for active InGaAs/InP in optoelectronic devices due to the 8% lattice mismatch between InP and Si. We successfully fabricated InP/Si substrates by He implantation of InP prior to bonding to a thermally oxidized Si substrate and annealing to exfoliate an InP thin film. The thickness of the exfoliated InP films was only 900 nm, which means hundreds of the InP/Si substrates could be prepared from a single InP wafer in principle. The photovoltaic current-voltage characteristics of the In0.53Ga0.47As cells fabricated on the wafer-bonded InP/Si substrates were comparable to those synthesized on commercially available epi-ready InP substrates, and had a 20% higher short-circuit current which we attribute to the high reflectivity of the InP/SiO2/Si bonding interface. This work provides an initial demonstration of wafer-bonded InP/Si substrates as an alternative to bulk InP substrates for solar cell applications. We have observed photocurrent enhancements up to 260% at 900 nm for a GaAs cell with a dense array of Ag nanoparticles with 150 nm diameter and 20 nm height deposited through porous alumina membranes by thermal evaporation on top of the cell, relative to reference GaAs cells with no metal nanoparticle array. This dramatic photocurrent enhancement is attributed to the effect of metal nanoparticles to scatter the incident light into photovoltaic layers with a wide range of angles to increase the optical path length in the absorber layer. GaAs solar cells with metallic structures at the bottom of the photovoltaic active layers, not only at the top, using semiconductor-metal direct bonding have been fabricated. These metallic back structures could incouple the incident

Tanake, Katsuaki

47

A novel technology for fabricating customizable VLSI artificial neural network chips  

SciTech Connect

This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems. These neural networks are programmed using precision laser cutting and deposition. The fast turnaround of laser-based customization allows us to explore different neural network architectures and to rapidly program the synaptic weights. Our customizable chip allows us to expand an artificial network laterally and vertically. This flexibility permits us to build very large neural network systems.

Fu, C.Y.; Law, B.; Chapline, G. [Lawrence Livermore National Lab., CA (United States); Swenson, D. [Naval Air Warfare Center, China Lake, CA (United States)

1992-02-05

48

Behavioural EMI Models of Complex Digital VLSI Circuits Thomas Steinecke  

E-print Network

Behavioural EMI Models of Complex Digital VLSI Circuits Thomas Steinecke Infineon Technologies AG-Meyer-Allee 25, 13355 Berlin Germany 1. ABSTRACT Increasing EMI potential of high-performance digital circuits-based EMI simulations. A promising modelling approach for digital VLSI circuits is presented and a silicon

Paris-Sud XI, Université de

49

Algorithms and methodologies for routability-driven VLSI placement  

Microsoft Academic Search

Very large scale integration (VLSI) has been a central technology for the realization of modern-day systems. The number of components in a VLSI design may run in the billions and it continues to grow, while the advantages associated with these advances are realized in multiple fields. However, the increased complexity of the designs poses new challenges for today's electronic design

Kalliopi Tsota

2011-01-01

50

APPLIED PHYSICS REVIEWSFOCUSED REVIEW Adhesive wafer bonding  

E-print Network

APPLIED PHYSICS REVIEWS­FOCUSED REVIEW Adhesive wafer bonding F. Niklausa Microsystem Technology 9 February 2006 Wafer bonding with intermediate polymer adhesives is an important fabrication-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive

Salama, Khaled

51

Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding  

E-print Network

Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

Spearing, S. Mark

52

Innovative design methodology for implementing heterogeneous multiprocessor architectures in VLSI  

SciTech Connect

Considering the design cost of today's VLSI systems, advanced VLSI technology may not be cost-effective for implementing complex computer systems. In the paper, an innovative design approach which can drastically reduce the cost of implementing heterogeneous multiprocessor architectures in VLSI is presented. The author introduces high-level architectural design tools for assisting the design of multiprocessor systems with distributed memory modules and communication networks, and presents a logic/firmware synthesis scheme for automatically implementing multitasking structures and system service functions for multiprocessor architectures. Furthermore, the importance of the firmware synthesis aspect of VLSI system design is emphasized. Most logic of complex VLSI systems can be implemented very easily in firmware using the design approach introduced here. 10 references.

Tientien Li

1983-01-01

53

Case studies on lithography-friendly vlsi circuit layout  

E-print Network

Moores Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered by lithography hardware. Currently, a light wavelength of 193nm is being used...

Shah, Pratik Jitendra

2009-05-15

54

VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.  

PubMed

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (?1 /s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology. PMID:24628497

Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip

2014-01-01

55

SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface  

NASA Astrophysics Data System (ADS)

This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

2010-10-01

56

The 1992 4th NASA SERC Symposium on VLSI Design  

NASA Technical Reports Server (NTRS)

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

Whitaker, Sterling R.

1992-01-01

57

NASA Space Engineering Research Center for VLSI System Design  

NASA Technical Reports Server (NTRS)

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

1993-01-01

58

SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers  

NASA Astrophysics Data System (ADS)

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

2010-02-01

59

Silicon Wafer Epitaxy  

NSDL National Science Digital Library

This Quicktime animation shows an optional process for creating silicon epitaxial wafers. The animations shows a trichlorosilane gas being injected which creates a monocrystaline film atop the preexisting wafer. This is the seventh animation in a series of how silicon wafers are created. The previous animation showing silicon wafer polishing can be seen here.The next and final animation in this sequence about silicon wafer laser inspection can be seen here.

2009-10-19

60

Analog VLSI Implementation of Artificial Neural Networks with Supervised On-Chip Learning  

Microsoft Academic Search

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and\\/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities

Maurizio Valle

2002-01-01

61

Parallel VLSI Architecture  

NASA Technical Reports Server (NTRS)

Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

1985-01-01

62

Scheduling semiconductor wafer fabrication  

Microsoft Academic Search

The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

LAWRENCE M. WEIN

1988-01-01

63

Silicon Wafer Polishing  

NSDL National Science Digital Library

This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

2009-10-21

64

Silicon Wafer Lapping  

NSDL National Science Digital Library

This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

2010-02-08

65

Dictionary machine (for VLSI)  

SciTech Connect

The authors present the design of a dictionary machine that is suitable for VLSI implementation, and discusses how to realize this implementation efficiently. The machine supports the operations of search, insert, delete, and extractment on an arbitrary ordered set. Each of these operations takes time o(logn), where n is the number of entries present when the operation is performed. Moreover, arbitrary sequences of these instructions can be pipelined through the machine at a constant rate (i.e. independent of n and the capacity of the machine). The time o(logn) is an improvement over previous VLSI designs of dictionary machines which require time o(log n) per operation, where n is the maximum number of keys that can be stored. 10 references.

Ottmann, T.A.; Rosenberg, A.L.; Stockmeyer, L.J.

1982-09-01

66

C. T.-C. Nguyen, "Integrated micromechanical radio front-ends (invited plenary)," Proceedings of Tech. Program, 2008 IEEE Int. Symp. On VLSI Technolo-gy, Systems, and Applications (VLSI-TSA'08), Hsinchu, Taiwan, April 21-23, 2008, pp. 3-4.  

E-print Network

C. T.-C. Nguyen, "Integrated micromechanical radio front-ends (invited plenary)," Proceedings of Tech. Program, 2008 IEEE Int. Symp. On VLSI Technolo- gy, Systems, and Applications (VLSI-TSA'08), Hsinchu, Taiwan, April 21-23, 2008, pp. 3-4. Integrated Micromechanical Radio Front-Ends Clark T

Nguyen, Clark T.-C.

67

Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics  

SciTech Connect

Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020from $0.15 per kilowatt hour to less than $0.07. 1366s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with todays state-of-the-art technologies. 1366s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366s technology, the cost of silicon wafers could be reduced by 80%.

None

2010-01-15

68

Three wafer stacking for 3D integration.  

SciTech Connect

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

2011-11-01

69

Application Specific Wafer Stepper  

NASA Astrophysics Data System (ADS)

Overlay, throughput and lens performance are three critical parameters of optical alignment equipment. High overlay accuracy will give high die yields for alignment sensitive parts or can allow designers to use tighter design rules which will allow a shrink of the chip and more chips per wafer. This work contains high overlay accuracy data obtained during the processing of production wafer lots of a 64K HRAM (Hierarchical RAM) device using an ASM Lithography PAS 2000 Wafer Stepper.

Fallon, Dick; Shih, James R.

1987-01-01

70

Assembly and Hermetic Encapsulation of Wafer Level Secondary Batteries  

Microsoft Academic Search

A new technology was developed for the construction and hermetic encapsulation of chip-size secondary lithium-ion batteries on a wafer-level plane. To reduce the size of the package and improve the handling and assembly of miniature batteries, we established a wafer-level process that combines foil processing of Li batteries and wafer technologies for battery contacts and encapsulation. Parylene and thin-film metal

K. Marquardt; R. Hahn; T. Luger; H. Reichl

2006-01-01

71

Optical interconnections for VLSI systems  

NASA Astrophysics Data System (ADS)

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The origins of the communication crisis are discussed. Those aspects of electrooptic technology that are applicable to the generation, routing, and detection of light at the level of chips and boards are reviewed. Algorithmic implications of interconnections are discussed, with emphasis on the definition of a hierarchy of interconnection problems from the signal-processing area having an increasing level of complexity. One potential application of optical interconnections is to the problem of clock distribution, for which a single signal must be routed to many parts of a chip or board. More complex is the problem of supplying data interconnections via optical technology. Areas in need of future research are identified.

Goodman, J. W.; Leonberger, F. J.; Kung, S.-Y.; Athale, R. A.

1984-07-01

72

New VLSI architectures for three-level correlators  

Microsoft Academic Search

This paper presents the VLSI architectures for three-level correlator design based on 1-m CMOS technology. The architecture performs very high speed, real-time, three-level cross-correlation of signals. Two architectures, one for serial incoming samples of signals (serial data) and the other for stored signal samples (parallel data), are described in the paper.

Rana Ejaz Ahmed; Saleh A. Alshebeili

1996-01-01

73

High-speed parallel CRC circuits in VLSI  

Microsoft Academic Search

The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should

Tong-Bi Pei; Charles Zukowski

1992-01-01

74

ARPA/CSTO rapid VLSI implementation  

NASA Astrophysics Data System (ADS)

The task objective was to provide rapid access to cost effective, state-of-the-art U.S. microelectronics industry fabrication technology for DoD customers and the educational community. This access was provided through the establishment of a prototyping service for use by the DARPA and NSF research communities which offered access to a variety of technologies unobtainable from a single fabrication source. The Defense Advanced Research Projects Agency (DARPA) had the goal of providing state-of-the-art VLSI fabrication services and electronic systems assembly technology to DoD customers and the educational community to ensure that DoD has access to low-cost, advanced electronic assemblies and to ensure that the country's newly emerging engineers will be able to support military needs in the area of electronics. The first task was to provide VLSI fabrication to DoD and DARPA supported contractors who have need of custom chips and assemblies. The second task was to provide this same technology to NSF-sponsored activities, under DARPA guidance.

Pina, Cesar A.

1993-07-01

75

Mixed voltage VLSI design  

NASA Technical Reports Server (NTRS)

A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

Panwar, Ramesh; Rennels, David; Alkalaj, Leon

1993-01-01

76

VLSI Architectures for Computing DFT's  

NASA Technical Reports Server (NTRS)

Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

1986-01-01

77

Analysis and Design of Resilient VLSI Circuits  

E-print Network

frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiation-induced soft errors. Among these noise sources, soft errors...

Garg, Rajesh

2010-07-14

78

Wafer level reliability testing: An idea whose time has come  

NASA Technical Reports Server (NTRS)

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Trapp, O. D.

1987-01-01

79

Wafer characteristics via reflectometry  

DOEpatents

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

80

Scriber for silicon wafers  

NASA Technical Reports Server (NTRS)

A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

Yamakawa, K. A.; Fortier, E. P. (inventors)

1981-01-01

81

Reciprocating Saw for Silicon Wafers  

NASA Technical Reports Server (NTRS)

Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

Morrison, A. D.; Collins, E. R., Jr.

1985-01-01

82

Compressive Computation in Analog VLSI Motion Sensors  

E-print Network

Compressive Computation in Analog VLSI Motion Sensors Rainer A. Deutschmann1 and Oliver G. Wenisch2 analog VLSI mo- tion sensors developed in the past. We show how their pixel-parallel architecture can is best suited to perform the algorithm even at high noise levels. 1 Analog VLSI Motion Sensors Inthe past

Deutschmann, Rainer

83

Toward a general-purpose analog VLSI neural network with on-chip learning  

Microsoft Academic Search

This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 ?m2 in a 2-?m technology, includes a hybrid of nonvolatile and dynamic

Antonio J. Montalvo; Ronald S. Gyurcsik; John J. Paulos

1997-01-01

84

Integration of RF-MEMS, passives and CMOS-IC on silicon substrate by low temperature wafer to wafer bonding technique  

Microsoft Academic Search

In this paper, a novel platform technology for system level integration of RF-MEMS, RF passives and CMOS-IC on silicon substrate is reported. The RF passives and RF MEMS devices are fabricated on a low resistivity silicon wafer using Cu damascene process. After bonding the wafer to a CMOS wafer with recesses using benzocyclobutene (BCB) as intermediate layer and subsequently removal

Q. X. Zhang; H. Y. Li; M. Tang; A. B. Yu; E. B. Liao; Rong Yang; G. Q. Lo; N. Balasubramanian; D. L. Kwong

2008-01-01

85

Stable wafer-carrier system  

DOEpatents

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

86

Wafer screening device and methods for wafer screening  

DOEpatents

Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

Sopori, Bhushan; Rupnowski, Przemyslaw

2014-07-15

87

Hypervelocity impact on silicon wafers with metallic and polymeric coatings  

Microsoft Academic Search

Current and near future developments in microsystem technologies (MST, also known as MEMS) are defining a new trend towards lower mass, smaller volume spacecraft, without loss of functionality. The MST spacecraft components are etched onto silicon wafers coated with different metallic or polymeric material layers (typically 1-2 microns in thickness). These silicon wafers are then integrated to provide the spacecraft

E. A. Taylor; H. J. Scott; M. Abraham; A. T. Kearsley

2001-01-01

88

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness  

SciTech Connect

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

Fong, Theodore E.

2013-05-06

89

AWV: high-throughput cross-array cross-wafer variation mapping  

NASA Astrophysics Data System (ADS)

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

2008-03-01

90

Structured wafer for device processing  

DOEpatents

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Okandan, Murat; Nielson, Gregory N

2014-05-20

91

Structured wafer for device processing  

DOEpatents

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Okandan, Murat; Nielson, Gregory N

2014-11-25

92

VLSI Reed-Solomon decoder  

NASA Astrophysics Data System (ADS)

In this paper, a VLSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provides both erasure and error correcting capability. In order to reduce the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed. And the overall architecture features parallel and pipelined structure, making a real time decoding possible. It is shown that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the architecture based on the recursive Euclid algorithm.

Kim, Yong H.; Chung, Young Mo; Lee, Sang Uk

1992-11-01

93

Wafer-level package interconnect options  

Microsoft Academic Search

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare

Jayaprakash Balachandran; Steven Brebels; Geert Carchon; Maarten Kuijk; Walter De Raedt; Bart K. J. C. Nauwelaers; Eric Beyne

2006-01-01

94

Silicon waveguides produced by wafer bonding  

SciTech Connect

X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 {mu}m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides to excite single guided modes at typical x-ray energies.

Poulsen, M.; Jensen, F.; Bunk, O.; Feidenhans'l, R.; Breiby, D.W. [Department of Micro and Nanotechnology, Technical University of Denmark, Oersteds Plads, DK-2800 Kgs. Lyngby (Denmark) and Materials Research Department, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark); DANCHIP, Technical University of Denmark, Oersteds Plads, DK-2800 Kgs. Lyngby (Denmark); Materials Research Department, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark); Danish Polymer Centre, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark)

2005-12-26

95

GaAs-Wafer Dicing Using the Water jet Guided Laser  

Microsoft Academic Search

Semiconductor wafers are getting thinner and thinner. GaAs wafers are not excluded by this trend. Since new dicing technologies are required for wafer thicknesses less than 150 m. Significant differences are noted among existing dicing methods. Abrasive sawing does not provide the desired cutting speed and yield because of mechanical damage (cracking, chipping). Cutting with conventional lasers should be avoided

Delphine Perrottet; Akos Spiegel; Simone Amorosi; Bernold Richerzhagen

96

VLSI scaling methods and low power CMOS buffer circuit  

NASA Astrophysics Data System (ADS)

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Sharma, Vijay Kumar; Pattanaik, Manisha

2013-09-01

97

Etching Of Semiconductor Wafer Edges  

DOEpatents

A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

2003-12-09

98

Diagnosis and reconfiguration of VLSI/WSI array processors  

SciTech Connect

Some fault-tolerant techniques and analytical methods are presented for linear, mesh, and tree array processors which are implemented in Very Large Scale Integration (VLSI) circuits or Wafer Scale Integration (WSI) circuits. Several techniques are developed for testing, diagnosis, on-line fault detection and reconfiguration of array processors. A testing strategy, built-in self-test, is presented for array processors to achieve the C-testability by which the test length is independent of the size of the array. The signature comparison approach is used for diagnostic algorithms. Reconfiguration schemes with two-level redundancy for mesh and tree arrays are described. An on-line fault detection scheme by using redundant cells and blocks are developed. Analytical tools for reliability are given for evaluating the proposed schemes. A yield estimation model for WSI mesh array processors with two-level redundancy is presented. Distributed as well as clustered defects are considered in this model.

Wang, M.

1988-01-01

99

Closed-loop electroosmotic microchannel cooling system for VLSI circuits  

Microsoft Academic Search

The increasing heat generation rates in VLSI circuits motivate research on compact cooling technologies with low thermal resistance. This paper develops a closed-loop two-phase microchannel cooling system using electroosmotic pumping for the working fluid. The design, fabrication, and open-loop performance of the heat exchanger and pump are summarized. The silicon heat exchanger, which attaches to the test chip (1 cm2),

Linan Jiang; James Mikkelsen; Jae-Mo Koo; David Huber; Shuhuai Yao; Lian Zhang; Peng Zhou; James G. Maveety; Ravi Prasher; Juan G. Santiago; Thomas W. Kenny; Kenneth E. Goodson

2002-01-01

100

VLSI architecture design of MPEG4 shape coding  

Microsoft Academic Search

This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 video standard. The real-time constraint of MPEG-4 shape coding leads to a heavy computational bottleneck on today's computer architectures. To overcome this problem, design analysis and optimization of MPEG-4 shape coding are addressed. By utilizing

Hao-chieh Chang; Yung-chi Chang; Yi-chu Wang; Wei-ming Chao; Liang-gee Chen

2002-01-01

101

Proceedings of the Low-Cost Solar Array Wafering Workshop  

NASA Technical Reports Server (NTRS)

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

Morrison, A. D.

1982-01-01

102

A Dictionary Machine (for VLSI)  

Microsoft Academic Search

The authors present the design of a dictionary machine that is suitable for VLSI implementation, and discusses how to realize this implementation efficiently. The machine supports the operations of search, insert, delete, and extractment on an arbitrary ordered set. Each of these operations takes time o(logn), where n is the number of entries present when the operation is performed. Moreover,

Thomas Ottmann; Arnold L. Rosenberg; Larry J. Stockmeyer

1982-01-01

103

Thin Film Encapsulation for Secondary Batteries on Wafer Level  

Microsoft Academic Search

This paper presents results concerning the realization and characterization of thin film encapsulated wafer-level batteries. Initially, the technology concept for the construction and hermetic encapsulation of chip-size lithium-ion secondary batteries on wafer level is introduced. Parylene and thin-film metal deposition was used for hermetic encapsulation of the batteries. With this technology, battery sizes between 1 mm2 and 1 cm2, and

K. Marquardt; R. Hahn; T. Lugerl; H. Reichl

2006-01-01

104

The Fifth NASA Symposium on VLSI Design  

NASA Technical Reports Server (NTRS)

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

1993-01-01

105

A second generation 50 Mbps VLSI level zero processing system prototype  

NASA Technical Reports Server (NTRS)

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

1994-01-01

106

Pulse mode VLSI asynchronous circuits  

NASA Technical Reports Server (NTRS)

A new basic VLSI circuit element is presented that can be used to realize pulse mode asynchronous sequential circuits. A synthesis procedure is developed along with an unconventional state assignment procedure. Level input asynchronous sequential circuits can be realized by converting a regular flow table into a differential mode flow table, thereby allowing the new synthesis technique to be general. The new circuits tolerate 1-1 crossovers. This circuit also provides a means for state sequence detection and real time fault detection.

Chen, Q.; Maki, G.

1991-01-01

107

Teaching processor architecture with a VLSI perspective  

Microsoft Academic Search

This paper proposes a new approach to teaching computer architecture by placing an explicit emphasis on circuit and VLSI aspects. This approach has the potential to enhance the teaching of both architecture and VLSI classes, to improve collaboration between CS and ECE departments and to lead to a better understanding of the current difficulties faced by microprocessor designers in industry.

Mircea R. Stan; Kevin Skadron

2002-01-01

108

Improved self arbitrated VLSI asynchronous circuits  

NASA Technical Reports Server (NTRS)

This paper introduces an improved method for designing the class of CMOS VLSI asynchronous sequential circuits introduced in the paper by Sterling R. Whitaker and Gary K. Maki, 'Self Arbitrated VLSI Asynchronous Circuits.' Of main interest here is the simple design by inspection rules that arise from these circuits. This paper presents a variation on these circuits which reduces the number of transistors required.

Winterrowd, P.

1991-01-01

109

Gettering Silicon Wafers with Phosphorus  

NASA Technical Reports Server (NTRS)

Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

Daiello, R. V.

1983-01-01

110

Silicon cast wafer recrystallization for photovoltaic applications  

E-print Network

Current industry-standard methods of manufacturing silicon wafers for photovoltaic (PV) cells define the electrical properties of the wafer in a first step, and then the geometry of the wafer in a subsequent step. The ...

Hantsoo, Eerik T. (Eerik Torm)

2008-01-01

111

Constant fan-in digital neural networks are VLSI-optimal  

SciTech Connect

The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

Beiu, V.

1995-12-31

112

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

2009-03-01

113

The VLSI design of an error-trellis syndrome decoder for certain convolutional codes  

NASA Technical Reports Server (NTRS)

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

1986-01-01

114

The VLSI design of error-trellis syndrome decoding for convolutional codes  

NASA Technical Reports Server (NTRS)

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

1985-01-01

115

Analysis of Application of the IDDQ Technique to the Deep SubMicron VLSI Testing  

Microsoft Academic Search

In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the

Chih-wen Lu; Chung-len Lee; Chauchin Su; Jwu-e Chen

2002-01-01

116

Further investigation of EUV process sensitivities for wafer track processing  

NASA Astrophysics Data System (ADS)

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

Bradon, Neil; Nafus, K.; Shite, H.; Kitano, J.; Kosugi, H.; Goethals, M.; Cheng, S.; Hermans, J.; Hendrickx, E.; Baudemprez, B.; Van Den Heuvel, D.

2010-04-01

117

Systolic VLSI for Kalman filters  

NASA Technical Reports Server (NTRS)

A novel two-dimensional parallel computing method for real-time Kalman filtering is presented. The mathematical formulation of a Kalman filter algorithm is rearranged to be the type of Faddeev algorithm for generalizing signal processing. The data flow mapping from the Faddeev algorithm to a two-dimensional concurrent computing structure is developed. The architecture of the resulting processor cells is regular, simple, expandable, and therefore naturally suitable for VLSI chip implementation. The computing methodology and the two-dimensional systolic arrays are useful for Kalman filter applications as well as other matrix/vector based algebraic computations.

Yeh, H.-G.; Chang, J. J.

1986-01-01

118

Adhesive wafer-to-wafer bonding using contact imprinting  

NASA Astrophysics Data System (ADS)

The present work proposes an adhesive bonding technique, at wafer level, using SU-8 negative photoresist as intermediate layer. The adhesive was selective imprint on one of the bonding surface. The main applications are in microfluidic area where a low temperature bonding is required. The method consists of three major steps. First the adhesive layer is deposited on one of the bonding surface by contact imprinting from a dummy wafer where the SU-8 photoresist was initially spun, or from a Teflon cylinder. Second, the wafers to be bonded are placed in contact and aligned. In the last step, the bonding process is performed at temperatures between 100C and 200C, a pressure of 1000 N in vacuum on a classical wafer bonding system. The results indicate a low stress value induced by the bonding technique. In the same time the process presents a high yield: 95-100%. The technique was successfully tested in the fabrication process of a dielectrophoretic device.

Yu, Liming; Pang, Ah Ju; Chen, Bangtao; Tay, Francis E. H.; Iliescu, Ciprian

2006-12-01

119

Novel adhesive development for CMOS-compatible thin wafer handling  

Microsoft Academic Search

3D integration is a promising technology for advancing the performance of semiconductors since it can provide higher density, faster speed and better power efficiency in a smaller form factor [13]. The Through Silicon Via (TSV) is an important component for achieving the benefits of 3D integrated semiconductors. However, depending on the temporary wafer bonding technology's behavior during processing at temperatures

K. Tamura; K. Nakada; N. Taneichi; P. Andry; J. Knickerbocker; C. Rosenthal

2010-01-01

120

Application of network coding for VLSI routing  

E-print Network

This thesis studies the applications of the network coding technique for intercon- nect optimization and improving the routability of Very-large-scale integration (VLSI) designs. The goal of the routing process is to connect the required sets...

Nemade, Nikhil Pandit

2009-05-15

121

Wafer-Level Thermocompression Bonds  

E-print Network

Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding without the application of an electric field or complicated pre-bond cleaning procedure. The presence of a ductile ...

Tsau, Christine H.

122

Wafer handling and placement tool  

DOEpatents

A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

Witherspoon, Linda L. (22 Cottonwood La., Los Lunas, NM 87031)

1988-01-05

123

Development of Megasonic cleaning for silicon wafers. Final report  

SciTech Connect

The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

Mayer, A.

1980-09-01

124

VLSI circuits and systems for microphotonic applications  

NASA Astrophysics Data System (ADS)

This paper describes various VLSI systems for microphotonic applications. The first project investigates an optimum phase design implementing a multi phase Opto-ULSI processor for multi-function capable optical networks. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering (BS) Opto-ULSI processor (OUP) for integrated intelligent photonic system (IIPS), while investigating the optimal phase characteristics and developing compensation for the nonlinearity of liquid crystal. The second part provides an insight into realisation of a novel 3-D configurable chip based on "sea-of-pixels" architecture, which is highly suitable for applications in multimedia systems as well as for computation of coefficients for generation of holograms required in optical switches. The paper explores strategies for implementation of distributed primitives for arithmetic processing. This entails optimisation of basic cells that would allow using these primitives as part of a 3-D "sea-of-pixel" configurable processing array. The concept of 3-D Soft-Chip Technology (SCT) entails integration of "Soft-Processing Circuits" with "Soft-Configurable Circuits", which effectively manipulates hardware primitives through vertical integration of control and data. Thus the notion of 3-D Soft-Chip emerges as a new design paradigm for content-rich multimedia, telecommunication and photonic-based networking system applications. Combined with the effective manipulation of configurable hardware arithmetic primitives, highly efficient and powerful soft configurable processing systems can be realized.

Lachowicz, S.; Rassau, A.; Kim, C.; Lee, S.-M.

2005-12-01

125

The 1991 3rd NASA Symposium on VLSI Design  

NASA Technical Reports Server (NTRS)

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

Maki, Gary K.

1991-01-01

126

Wafer characteristics via reflectometry and wafer processing apparatus and method  

DOEpatents

An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

Sopori, Bhushan L. (Denver, CO)

2007-07-03

127

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.  

PubMed

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

2014-08-15

128

Sub-micron, planarized, Nb-AlO(x)-Nb Josephson process for 125 mm wafers developed in partnership with Si technology  

NASA Astrophysics Data System (ADS)

A new planarized all-refractory technology was demonstrated for low-Tc superconductivity (PARTS). With the exception of the Nb-AlO(x)-Nb trilayer preparation, the processing is done almost exclusively within an advanced Si technology fabrication facility. This approach made it possible to leverage highly off of existing state-of-the-art lithography, metal etching, materials deposition, and planarization capabilities. Using chemical-mechanical polish as the planarization technique Josephson junctions ranging in size from 0.5-100 sq microns were fabricated. Junction quality is excellent with the figure of merit Vm typically exceeding 70 mV. PARTS has yielded fully functional integrated Josephson devices including magnetometers, gradiometers, and soliton oscillators.

Ketchen, M. B.; Pearson, D.; Kleinsasser, A. W.; Hu, C.-K.; Smyth, M.; Logan, J.; Stawiasz, K.; Baran, E.; Jaso, M.; Ross, T.

1991-11-01

129

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

130

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Vosen, Steven R. (Berkeley, CA)

1999-01-01

131

450mm wafer patterning with jet and flash imprint lithography  

NASA Astrophysics Data System (ADS)

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

132

Wafer-scale process for fabricating arrays of nanopore devices  

E-print Network

Wafer-scale process for fabricating arrays of nanopore devices Amir G. Ahmadi Georgia Institute.nair@chbe.gatech.edu Abstract. Nanopore-based single-molecule analysis is a subject of strong scientific and technological chemistry. Previously demonstrated methods have been confined to the production of single nanopore de- vices

Nair, Sankar

133

High-performance VLSI architecture for video processing  

NASA Astrophysics Data System (ADS)

Real time image processing is a key issue in nowadays multimedia applications. Image filtering and video coding are two basic applications in image processing. Their algorithms are computationally expensive due to both, the number of points of each frame to be processed, and the calculation complexity per point. The VLSI implementation of these algorithms leads to special architectures that are based on systolic arrays, and whose implementation is greedy in silicon area. In this paper, we propose a configurable and bidimensional pipelined VLSI architecture that supports mathematical morphology operations and the block matching algorithm. Remarkable advantages include low power consumption, and a regular and compact design (in terms of core active area) versus the traditional systolic architecture. The architecture is adequate for both morphological image filtering and video compression, depending on the hardware resources of the processing elements. The main advantage of this bidimensional pipeline architecture is the area saving compared with the systolic array implementation. Total area saving was presented in terms of the number of bits of the FIFO memories that can be eliminated. The proposed architecture was verified at high level in C++, at RTL level using Verilog and at C++/RTL level using DEMETER. Required cycle times was measured for a real time morphological filter per dilation/erosion operation, as a function of the incoming resolution. Physical layouts were obtained for the basic slice of the processing element and for the systolic array using the technology of 0,35 microns CMOS from AMS.

Navarro, Hector; Montiel-Nelson, Juan A.; Sosa, Javier; Garcia, Jose C.; Sarmiento, Roberto; Nooshabadi, Saeid

2003-04-01

134

Associative Pattern Recognition In Analog VLSI Circuits  

NASA Technical Reports Server (NTRS)

Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

Tawel, Raoul

1995-01-01

135

Silicon Wafer Processing Dr. Seth P. Bates  

E-print Network

Silicon Wafer Processing Dr. Seth P. Bates Applied Materials Summer, 2000 Objective To provide from blank silicon wafers. Goals The Transfer Plan provides a curriculum covering the process of manufacturing integrated circuits from the silicon wafer blanks, using the equipment manufactured by Applied

Colton, Jonathan S.

136

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

137

Platinum-coated probes sliding at up to 100 mm s-1 against coated silicon wafers for AFM probe-based recording technology  

NASA Astrophysics Data System (ADS)

One of the new alternative information storage technologies being researched is based on the probe-based recording technique. In one technique, a phase-change medium is used, and the phase change is accomplished by applying either a high or low magnitude of current which heats the interface to different temperatures. Tip wear is a serious concern. For wear protection of the phase-change chalcogenide medium with a silicon substrate, diamond-like carbon (DLC) film with various lubricant overcoats was deposited on the recording layer surface. Nanowear properties of platinum (Pt)-coated probes with high electrical conductivity have been investigated in sliding against the coated medium using an atomic force microscope (AFM). A silicon grating sample and software to deconvolute tip shape were used to characterize the change in the tip shape and evaluate the tip radius and its wear volume. The nanowear experiments were performed at sliding velocities ranging from 0.1 to 100 mm s-1. Pt-coated tips on the lubricant-coated DLC film surfaces showed less sensitivity to the velocity and the load as compared to the unlubricated DLC film surfaces. In wear life threshold experiments, the threshold reaches a smaller sliding distance at higher loads. In high-temperature experiments at 80 C, the wear rate is higher compared to that at 20 C. The results suggest that the wear mechanism at low velocity appears to be primarily adhesive and abrasive. At high velocity, an additional wear mechanism of the tribochemical reaction is important.

Bhushan, Bharat; Kwak, Kwang Joo

2007-08-01

138

Manufacture and Metrology of 300 mm Silicon Wafers with Ultra-Low Thickness Variation  

NASA Astrophysics Data System (ADS)

With the evolution of exposure tools for optical lithography towards larger numerical apertures, the semiconductor industry expects continued demand for improved wafer flatness at the exposure site. The allowable site flatness for 300 mm wafers is expected to be less than 45 nm by 2010 and it may be as low as 25 nm by 2015 according to the International Technology Roadmap for Semiconductors (ITRS 2006). This requires wafers with low thickness variation and presents a challenge for both wafer polishing and metrology tools, which must be capable of meeting the specifications. We report the results of fabricating 300 mm silicon wafers with very low thickness variation using magnetorheological finishing (MRF), a deterministic subaperture finishing process. The wafer thickness metrology, which guided the finishing process, was provided by an infrared interferometer developed at the National Institute of Standards and Technology (NIST). The finishing method in combination with the interferometric wafer metrology enabled the fabrication of 300 mm silicon wafers with a total thickness variation (TTV) of about 40 nm, and between 10 nm and 15 nm thickness variation at 25 mm25 mm exposure sites.

Griesmann, Ulf; Wang, Quandou; Tricard, Marc; Dumas, Paul; Hall, Christopher

2007-09-01

139

Low-Power Equalizer VLSI Implementation for xDSL Jun-Dong Cho and Jin-Woo Kim  

E-print Network

FEQ and Low Power FEQ 4 Simulation of Low-Power Equalizer and Comparison ADSL system is simulated 1000Low-Power Equalizer VLSI Implementation for xDSL Jun-Dong Cho and Jin-Woo Kim Dept. of ECE Subscriber Line (DSL) technologies [1]. xDSL service promises to dramatically increase the speed of copper

Cho, Jun Dong

140

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers  

E-print Network

RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens ...

Keast, Craig L.

141

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress  

NASA Astrophysics Data System (ADS)

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Brunner, Timothy A.; Menon, Vinayan C.; Wong, Cheuk Wun; Gluschenkov, Oleg; Belyansky, Michael P.; Felix, Nelson M.; Ausschnitt, Christopher P.; Vukkadala, Pradeep; Veeraraghavan, Sathish; Sinha, Jaydeep K.

2013-10-01

142

Design Of An Optical Linewidth Standard Reference Material For Wafers  

NASA Astrophysics Data System (ADS)

Optical linewidth measurements on patterned wafers are complicated by the wide variety of materials and correspondingly wide variation in optical parameters, complex refractive index and thickness, used in the manufacture of integrated circuits. It has been shown that in addition to linewidth, two key parameters, the normalized local reflectance R and the optical phase difference ? at the line edge, determine the characteristics of the optical image and, therefore, affect the accuracy and precision of linewidth measurements. Both of these parameters, R and ?, are dependent upon the illuminating wavelength or spectral bandpass and the coherence parameter of the optical system. To achieve the measurement precision and accuracy required for VLSI dimensions (e.g., 10% tolerance for 1-?m linewidths), it is necessary to control coherence, spectral bandpass, and image integrity as well as to achieve reproducible edge detection and focus criteria. When a system can be operated without further operator intervention despite changes in the materials being mea-sured, it is possible to calibrate the linewidth measurement system using a standard fabri-cated from only a few materials representing a range of image characteristics. The desirable characteristics of such a standard are discussed with respect to durability, edge definition, and equivalence of the image characteristics to materials used in the manufacture of ICs. A prototype design consisting of combinations of SiO2 and chromium layers on a silicon substrate is presented.

Nyyssonen, Diana

1982-10-01

143

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Technical Reports Server (NTRS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

144

The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics  

Microsoft Academic Search

Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect

W. Stephen Lacy; Jos L. Cruz-Rivera; D. Scott Wills

1998-01-01

145

A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases  

NASA Technical Reports Server (NTRS)

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to Berlekamp; the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in different areas. Finally, they are implemented on silicon chips with nitride metal oxide semiconductor technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.

Hsu, I. S.; Truong, T. K.; Deutsch, L. J.; Reed, I. S.

1988-01-01

146

The VLSI implementation of a Reed-Solomon encoder using Berlekamp's bit-serial multiplier algorithm  

NASA Technical Reports Server (NTRS)

Realization of a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes on a single VLSI chip using NMOS technology is demonstrated to be feasible. A dual basis (255, 223) over a Galois field is used. The conventional RS encoder for long codes often requires look-up tables to perform the multiplication of two field elements. Berlekamp's algorithm requires only shifting and exclusive-OR operations.

Hsu, I.-S.; Reed, I. S.; Wang, K.; Yeh, C.-S.; Truong, T. K.; Deutsch, L. J.

1984-01-01

147

A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases  

NASA Astrophysics Data System (ADS)

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to Berlekamp; the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in different areas. Finally, they are implemented on silicon chips with nitride metal oxide semiconductor technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.

Hsu, I. S.; Truong, T. K.; Deutsch, L. J.; Reed, I. S.

1988-06-01

148

The VLSI implementation of a Reed-Solomon encoder using Berlekamp's bit-serial multiplier algorithm  

NASA Astrophysics Data System (ADS)

Realization of a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes on a single VLSI chip using NMOS technology is demonstrated to be feasible. A dual basis (255, 223) over a Galois field is used. The conventional RS encoder for long codes often requires look-up tables to perform the multiplication of two field elements. Berlekamp's algorithm requires only shifting and exclusive-OR operations.

Hsu, I.-S.; Reed, I. S.; Wang, K.; Yeh, C.-S.; Truong, T. K.; Deutsch, L. J.

1984-10-01

149

Analog VLSI Architecture for Computing Heading Direction  

E-print Network

circuits. Since analog circuits are limited by low precision in the values of the state variables, we@klab.caltech.edu Abstract| We describe a parallel analog VLSI architec- ture that integrates optical ow data obtained from arise from noise in the input images e.g. due to bad lighting conditions or extreme speeds or noise

150

Delay and power optimization in VLSI circuits  

Microsoft Academic Search

The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macromodels are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.

Lance A. Glasser; Lennox P. J. Hoyte

1984-01-01

151

SSI/MSI/LSI/VLSI/ULSI.  

ERIC Educational Resources Information Center

Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future

Alexander, George

1984-01-01

152

Deposition uniformity inspection in IC wafer surface  

NASA Astrophysics Data System (ADS)

This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

2014-03-01

153

High performance LWIR microbolometer with Si/SiGe quantum well thermistor and wafer level packaging  

NASA Astrophysics Data System (ADS)

An uncooled microbolometer with peak responsivity in the long wave infrared region of the electromagnetic radiation is developed at Sensonor Technologies. It is a 384 x 288 focal plane array with a pixel pitch of 25?m, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The high sensitivity (TCR) and low 1/f noise are the main performance characteristics of the product. The frame rate is maximum 60Hz and the output interface is digital (LVDS). The quantum well thermistor material is transferred to the read-out integrated circuit (ROIC) by direct wafer bonding. The ROIC wafer containing the released pixels is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. The resulting wafer stack is mounted in a standard ceramic package. In this paper the architecture of the pixels and the ROIC, the wafer packaging and the electro-optical measurement results are presented.

Roer, Audun; Lapadatu, Adriana; Bring, Martin; Wolla, Erik; Hohler, Erling; Kittilsland, Gjermund

2011-11-01

154

Thermal modeling and simulation of a package-on-package embedded micro wafer level package (EMWLP) structure at the package and system-level  

Microsoft Academic Search

In the embedded wafer-level packaging field, the embedded micro wafer level package (EMWLP) technology leverages on fan-out redistribution connections, keeping the reliance on wire-bonding and flip-chip bump connections to a minimum, thus streamlining the packaging process. As the embedded micro wafer level packaging (EMWLP) technology evolves to capitalize on package-on-package (POP) technology, this study's parametric thermal modeling focuses on analyzing

Y. Y. G. Hoe; Chong Ser Choong; V. S. Rao; G. Sharma; Zhang Xiaowu; D. Pinjala

2010-01-01

155

Wafer Inspection in the Photolithography Process  

NSDL National Science Digital Library

This is a description for a learning module from Maricopa Advanced Technology Education Center. This PDF describes the module; access may be purchased by visiting the MATEC website. In this module, your learners begin to master the sensitive after develop inspection (ADI) methods that follow photolithography. MATEC describes macro- and micro-inspection techniques and distinguishes qualitative (inspection) from quantitative (metrology) methods. The chief focus is on teaching learners to examine wafers under an optical microscope; a simulated microscope is also provided in a computer-based training (CBT) format. The module covers edge bead inspection and provides extensive practice in flash boundary inspection, including evaluating Nikon crosses, overlay boxes, scanning electronic microscope features, resolution bars, Verniers, and product identification numbers.

156

Architecture for VLSI design of Reed-Solomon encoders  

NASA Technical Reports Server (NTRS)

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

Liu, K. Y.

1981-01-01

157

Cascaded VLSI Chips Help Neural Network To Learn  

NASA Technical Reports Server (NTRS)

Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

1993-01-01

158

Wafer bonding for three dimensional (3D) integration  

NASA Astrophysics Data System (ADS)

Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 Gtip t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400C. Thermal cycling performed at a temperature 450C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

Kwon, Yongchai

2003-10-01

159

Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis  

SciTech Connect

This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

Tobin, K.W.

2003-05-22

160

Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010  

SciTech Connect

1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

Lorenz, A.

2011-06-01

161

Full wafer metrology for chemically graded thin films  

NASA Astrophysics Data System (ADS)

Combinatorial CBVD (Chemical Beam Vapor Deposition) is a thin film deposition technology which has the ability to produce multi-element thin films with large controlled composition spread gradients. If functional characterizations can be carried out systematically and rapidly on such graded films over full wafers, they enable to identify precisely the best film composition for a given application, and CBVD then easily allows for the deposition of the optimized film homogeneously on large wafers. In this article, we demonstrate the efficiency of such a process development based on the optimization of new Transparent Conductive Oxide thin films (TCO) of few % Nb doped TiO2. We have developed a full wafer metrology instrument which maps the optical thickness and the sheet resistance with a lateral resolution below 400um. We discuss the performance of various algorithms to extract the optical thickness from the white light reflectance measurement in the case of very small thickness. The sheet resistance is measured with an array of four AFM-like conductive cantilevers, allowing accurate sheet resistance (R) measurement where the standard tungsten four probes destroy porous thin oxide films. Application of these measurements to several Nb doped TiO2 films deposited on 4" wafer by CBVD is presented.

Jobin, Marc; Jotterand, Stphane; Pellodi, Cdric; dos Santos, Sergio; Sandu, Cosmin Silviu; Wagner, Estelle; Benvenuti, Giacomo

2012-04-01

162

Macroporous-based micromachining on full wafers  

Microsoft Academic Search

This paper reports on a technique of macroporous-based micromachining for full wafers. A 3.6kW xenon lamp of whose intensity can be varied is employed to generate electronic holes during the etching. In order to apply a uniform electric field to whole 3in. wafer, a mesh electrode is formed on the backside of the wafer after implantation of an n+ layer.

H. Ohji; S. Izuo; P. J. French; K. Tsutsumi

2001-01-01

163

Strength of Silicon Wafers: Fracture Mechanics Approach  

SciTech Connect

This paper describes a model to predict mechanical strength distribution of silicon wafers. A generalized expression, based on a multimodal Weibull distribution, is proposed to describe the strength of a brittle material with surface, edge, and bulk flaws. The specific case of a cast, unpolished photovoltaic (PV) wafer is further analyzed. Assuming that surface microcracks constitute the dominant mechanism of wafer breakage, this model predicts the strength distribution of PV silicon that matches well the experimental results available in the literature.

Rupnowski, P.; Sopori, B.

2009-01-01

164

DCT algorithms for VLSI parallel implementations  

SciTech Connect

This paper presents two different algorithms for computing the discrete cosine transform (DCT) on the existing VLSI structures. First, it is shown that the N-point DCT can be implemented on the existing systolic architecture for N-point discrete Fourier transform (DFT), by introducing some modifications. Second, a new prime factor DCT algorithm is presented for the class of DCT's of length N = N{sub 1} {times} N{sub 2}, where N{sub 1}, and N{sub 2} are relatively prime and odd numbers. It is shown that the proposed algorithm can be implemented on the already existing VLSI structures for prime factor DFT such as in (10) and (13). Moreover, the number of multipliers required for the proposed algorithm is comparable to the other fast DCT algorithms. Also in this paper, it is shown that the discrete sine transform (DST) can be computed by the same structure.

Cho, N.I.; Lee, S.U. (Seoul National Univ. (Republic of Korea))

1990-01-01

165

Systolic VLSI Reed-Solomon Decoder  

NASA Technical Reports Server (NTRS)

Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.

1986-01-01

166

Leak detection utilizing analog binaural (VLSI) techniques  

NASA Technical Reports Server (NTRS)

A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

Hartley, Frank T. (inventor)

1995-01-01

167

DCT algorithms for VLSI parallel implementations  

Microsoft Academic Search

Two algorithms are presented for computing the discrete cosine transform (DCT) on existing VLSI structures. First, it is shown that the N-point DCT can be implemented on the existing systolic architecture for the N-point discrete Fourier transform (DFT) by introducing some modifications. Second, a new prime factor DCT algorithm is presented for the class of DCTs of length N=N 1N2,

Nam Ik Cho; Sang Uk Lee

1990-01-01

168

Parallel analog VLSI architectures for computation of heading direction and  

E-print Network

analog VLSI architectures that integrate optical ow data obtained from arrays of elementary velocity sen simulations to evaluate the most important qualitative properties of the optical ow eld and determine the best possible errors. 1 Introduction We have designed analog VLSI velocity sensors invariant to absolute

169

CDU improvement with wafer warpage control oven for high-volume manufacturing  

NASA Astrophysics Data System (ADS)

Immersion lithography has been developed for 45nm technology node generation during the last several years. Currently, IC manufacturers are moving to high volume production using immersion lithography. Due to the demand of IC manufactures, as the critical dimension (CD) target size is shrinking, there are more stringent requirements for CD control. Post Exposure Bake (PEB) process, which is the polymer de-protection process after exposure, is one of the important processes to control the CD in the 193nm immersion lithography cluster. Because of the importance of the PEB process for CD uniformity, accurate temperature control is a high priority. Tokyo Electron LTD (TEL) has been studying the temperature control of PEB plates. From our investigation, total thermal history during the PEB process is a key point for controlling intra wafer and inter wafer CD [1]. Further, production wafers are usually warped, which leads to a nonuniform thermal energy distribution during the PEB process. So, it is necessary to correct wafer warpage during the baking process in order to achieve accurate CD control on production wafers. TEL has developed a new PEB plate for 45nm technology node mass production, which is able to correct wafer warpage. The new PEB plate succeeded in controlling the wafer temperature on production wafers using its warpage control function. In this work, we evaluated CD process capability using the wafer warpage control PEB plate, which is mounted on a CLEAN TRACKTM LITHIUS ProTM-i (TEL) linked with the latest immersion exposure tool. The evaluation was performed together with an IC manufacturer on their 45nm production substrates in order to determine the true performance in production.

Tomita, T.; Weichert, H.; Hornig, S.; Trepte, S.; Shite, H.; Uemura, R.; Kitano, J.

2009-03-01

170

Endpoint detectable plating through femtosecond laser drilled glass wafers for electrical interconnections  

Microsoft Academic Search

An endpoint detectable plating process to avoid over-electroplating was proposed and performed in this work. The technology was developed for fabrication of Pyrex glass wafer with electrical feed-throughs. Thin film of gold was deposited on the glass wafer prior to the femtosecond laser drilling. When the growing metal in the through-holes was contacted to the metal, a resistance between the

Takashi Abe; Xinghua Li; Masayoshi Esashi

2003-01-01

171

Stress Voiding During Wafer Processing  

SciTech Connect

Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

Yost, F.G.

1999-03-01

172

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits  

NASA Astrophysics Data System (ADS)

A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed for effective use of the hardware resources. In logic-in-control architecture, the control circuits can be merged with the arithmetic/logic circuits, where the control and arithmetic/logic circuits are constructed by using one or multiple logic blocks. To implement the control circuit, only one state in a state transition diagram is allocated to one logic block, which leads to reduction of the complexity of interconnections between logic blocks. The fine-grain logic block is implemented based on multiple-valued current-mode circuit technology. In the fine-grain logic block, an arbitrary 3-variable binary function can be programmed by using one multiplexer and two universal literal circuits. Three-variable binary functions are used to implement the control circuit. Moreover, the hardware resources can be utilized to construct a bit-serial adder, because full-adder sum and carry can be realized by programming in the universal literal circuit. Therefore, the logic block can be effectively reconfigured for arithmetic/logic and control circuits. It is made clear that the hardware complexity of the control circuit in the proposed reconfigurable VLSI can be reduced in comparison with that of the control circuit based on a typically sequential circuit in the conventional FPGA and the fine-grain field-programmable VLSI reported until now.

Okada, Nobuaki; Kameyama, Michitaka

173

A self-priming, high performance, check valve diaphragm micropump made from SOI wafers  

NASA Astrophysics Data System (ADS)

In this paper, we describe a self-priming high performance piezoelectrically actuated check valve diaphragm micropump. The micropump was fabricated from three wafers: two silicon-on-insulator (SOI) wafers and one silicon wafer. A process named 'SOI/SOI wafer bonding and etching back followed by a second wafer bonding' was developed in order to make the core components of this device which included an inlet check valve, an outlet check valve, a diaphragm and a chamber. The movable structures of this device, i.e. the check valves and the diaphragm, were fabricated from the device layers of the two bonded SOI wafers. Taking advantages of SOI wafer technology and etch-stop layers, the vertical parameters of the movable structures were precisely controlled in fabrication. The micropump was self-priming without any pre-filling process. The pumping rate of the micropump was linearly adjustable from 0 to 650l m min-1 by adjusting frequency. The maximum pumping rate was 860 l min-1 and the maximum pumping pressure was approximately 10.5 psi. The power consumption of the device was less than 1.2 mW.

Kang, Jianke; Mantese, Joseph V.; Auner, Gregory W.

2008-12-01

174

Electrostatic Wafer Chuck for Electron Beam Microfabrication  

Microsoft Academic Search

Vacuum wafer chucks are useless for electron beam microfabrication. An analysis of the required electrostatic forces and frequency response of a specimen wafer on a field plate is made. An experimental electrostatic chuck and its high voltage square wave power supply have been fabricated. Full clamping action has been provided by electrostatic pressures of 1?6 atm, and 1 atm pressures

George A. Wardly

1973-01-01

175

Methane production using resin-wafer electrodeionization  

SciTech Connect

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

176

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

Kim, Dae Jong; Yoo, Hyung Won; Kim, Chul Hong; Lee, Hak Kwon; Kim, Sung Su; Bae, Koon Ho; Spielberg, Hedvi; Lee, Yun Ho; Levi, Shimon; Bustan, Yariv; Rozentsvige, Moshe

2010-03-01

177

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 3, MARCH 2014 631 Mapping Loop Structures onto Parametrized  

E-print Network

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 3, MARCH 2014 631 Mapping Loop Structures onto Parametrized Hardware Pipelines Adrien Le Masle and Wayne Luk, Fellow, IEEE with pipelining and replication features. A technology-independent parametric model of the proposed design

Luk, Wayne

178

Wavelength-encoded OCDMA system using opto-VLSI processors.  

PubMed

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram. PMID:17603568

Aljada, Muhsen; Alameh, Kamal

2007-07-01

179

VLSI Reed-Solomon Encoder With Interleaver  

NASA Technical Reports Server (NTRS)

Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).

Hsu, In-Shek; Deutsch, L. J.; Truong, Trieu-Kie; Reed, I. S.

1990-01-01

180

Development of megasonic cleaning for silicon wafers  

NASA Technical Reports Server (NTRS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-01-01

181

Wafer and reticle positioning system for the extreme ultraviolet lithography engineering test stand  

Microsoft Academic Search

This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EUVL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100 nm. EUVL research and development includes development of capabilities for demonstrating key EUV technologies. The ETS

John B. Wronosky; Tony G. Smith; Marcus J. Craig; Beverly R. Sturgis; Joel R. Darnold; David K. Werling; Mark A. Kincy; Daniel A. Tichenor; Mark E. Williams; Paul M. Bischoff

2000-01-01

182

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers  

NASA Technical Reports Server (NTRS)

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.

Truong, T. K.; Hsu, I. S.; Chang, J. J.; Shyu, H. C.; Reed, I. S.

1986-01-01

183

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers  

NASA Technical Reports Server (NTRS)

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

1987-01-01

184

Critical dimension control for prevention of wafer-to-wafer and module-to-module difference  

NASA Astrophysics Data System (ADS)

In recent years, the worldwide semiconductor market has changed drastically, and it is expected that the digital device market will continue to expand towards general consumer electronics and away from the personal computers that have been the core of the market. To accommodate this shift, the new devices will be diversified with improved productivity, higher process yield, and higher precision. Clean Track (LITHIUS) design also has been changed drastically to maintain equal productivity with new high throughput exposure equipment. Design changes include increasing the number of processing chambers by stacking reduced size modules in order to meet high throughput and small footprint requirements. However, this design change concept raises concerns about increased wafer-to-wafer difference (WtW) and module-to-module different (MtM). These variations can result in lower process yield and have a negative effect on design rule shrinkage. The primary causes of WtW difference and MtM difference stem from minute module hardware variations, module height differences, and module parameter adjustment differences during the installation of the tool. Previous Clean Track development focused mainly on reduction of module hardware difference as an approach to reduce WtW variation. However, to further improve lot level uniformity, it is necessary to reduce module height difference factors within the system and module adjustment disparities such as plate temperature calibrations. Highly temperature sensitive ArF processes have necessitated precise manual PEB temperature adjustments. These calibrations are labor intensive and require many field hours to ensure optimal CD uniformity. Therefore, an auto temperature measurement and adjustment tool is developed to eliminate the human error due to manual adjustment and minimize adjustment time. In order to meet demands for design rules shrinkage and increased process uniformity we minimized the WtW and MtM difference by using thermal history adjustment and transfer time control. This method is also used to improve within wafer CD control technology resulting in a more stable process. In this report, we introduce improved features to reduce WtW and MtM variation and their effect on CD uniformity with 193nm (ArF) resist and 248nm (KrF) resist.

Deguchi, Masatoshi; Tanaka, Kouichirou; Nagatani, Naohiko; Miyata, Yuichiro; Yamashita, Mitsuo; Minami, Yoshiaki; Matsuyama, Yuji

2004-05-01

185

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

186

Modelling deformation and fracture in confectionery wafers  

NASA Astrophysics Data System (ADS)

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

2015-01-01

187

VLSI implementable parallel stochastic learning algorithm  

NASA Astrophysics Data System (ADS)

A VLSI implementable, massively parallel, digital, stochastic neural network architecture with on-chip learning is described which can be used to address video/image compression applications. Color information in images is usually encoded as a means to reduce the data needed to transmit high resolution video images over a lower bandwidth communication system. A neural net approach can be used for such a compression scheme since it can be trained to map a set of patterns from a k-dimensional space to a 1D space very easily. The training algorithm is implemented as a cross correlation between previously calculated weights and global errors. These simple calculations are performed by each processing unit with information available in their local memories, thus, no transfer of information between neurons is necessary. This feature allows for the synchronous updating of all the weights, which optimizes the inherent parallel nature of the neural network architecture, making the design an excellent candidate for VLSI implementation as an SIMD architecture. By incorporating the learning portion on-chip, an appreciable reduction in computing time is possible. The stochastic nature of the learning algorithm, and a simulated 'annealing' process, allows it to convergence to a global minimum. The architecture is synthesized from an HDL description using powerful design and analysis tools which allow for many performance trade- offs and fault coverage to be done by the compiler before the final design is sent for fabrication.

Ruiz, Laura V.; Pandya, Abhijit S.

1995-08-01

188

Relationship between coefficient of friction and surface roughness of wafer in nanomachining process  

NASA Astrophysics Data System (ADS)

Fixed abrasive polishing technology can obtain a nanoscale surface and is one of the future nano machining directions. The coefficient of friction between the pad and the wafer in the polishing process can influence on the surface quality of the wafer. The relationship between the coefficient of friction and surface roughness of the wafer was investigated to improve the efficiency and surface quality. Based on the Florida model, the adhesion, asperity plough and abrasive plough from the pad in the polishing process was analyzed. The friction force per unit area was calculated by the properties of the pad and wafer. Based on the rod model, the actual contact area was calculated by the surface roughness and the properties of the pad and wafer. The relational model between the surface roughness of the wafer and the friction coefficient was established. The model was verified by the experiments of fixed abrasive polishing of BK7 glass. When the friction coefficient is less than 1.9, the data of the experiment and theory match very well in the comparison process.

Li, Jun; Xia, Lei; Li, Pengpeng; Zhu, Yongwei; Sun, Yuli; Zuo, Dunwen

2013-08-01

189

Porous solid ion exchange wafer for immobilizing biomolecules  

SciTech Connect

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

2007-12-11

190

Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001  

SciTech Connect

The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.

Beetz, C.P.; Steinbeck, J.; Hsueh, K.L.

2001-03-31

191

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays  

NASA Technical Reports Server (NTRS)

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

2009-01-01

192

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder  

NASA Technical Reports Server (NTRS)

A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

193

Four-Terminal FinFET Device Technology  

Microsoft Academic Search

One of the biggest challenges for the VLSI circuits with 32-nm-technology nodes and beyond is to overcome the issue of catastrophic increases in power consumption due to short-channel effects (SCEs). Fortunately, \\

M. Masahara; K. Endo; Y. X. Liu; S. O'uchi; T. Matsukawa; R. Surdeanu; L. Witters; G. Doornbos; V. H. Nguyen; G. Van den bosch; C. Vrancken; M. Jurczak; S. Biesemans; E. Suzuki

2007-01-01

194

Hierarchical Design and Verification for VLSI  

NASA Technical Reports Server (NTRS)

The specification and verification work is described in detail, and some of the problems and issues to be resolved in their application to Very Large Scale Integration VLSI systems are examined. The hierarchical design methodologies enable a system architect or design team to decompose a complex design into a formal hierarchy of levels of abstraction. The first step inprogram verification is tree formation. The next step after tree formation is the generation from the trees of the verification conditions themselves. The approach taken here is similar in spirit to the corresponding step in program verification but requires modeling of the semantics of circuit elements rather than program statements. The last step is that of proving the verification conditions using a mechanical theorem-prover.

Shostak, R. E.; Elliott, W. D.; Levitt, K. N.

1983-01-01

195

Periodic binary sequence generators: VLSI circuits considerations  

NASA Technical Reports Server (NTRS)

Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

Perlman, M.

1984-01-01

196

VLSI processors for signal detection in SETI  

NASA Technical Reports Server (NTRS)

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

197

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

198

Laser furnace and method for zone refining of semiconductor wafers  

NASA Technical Reports Server (NTRS)

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

1988-01-01

199

VLSI architecture for computer vision based on neurobiological principles of organization  

SciTech Connect

Biological and technological (wide-field-of-view) vision systems are confronted with the formidable task of managing data sets at a rate in excess of 10/sup 0/10 bits per second. In both cases, however, considering the required tasks, it appears that the data are highly redundant, and therefore must be reorganized before any type of higher level processing is applied to them. Reorganizations may include compression, and dimensional reduction according to the various relevant parameters. Biological processing at both the retinal and cortical levels often consists of repetitive simple operations applied to spatial and/or temporal neighborhoods, limited in their extend and duration. These are most adequate for the very high image data rates, in spite of the fact that those neurobiological systems actually consists of simple components which are several orders of magnitude slower than electronic components. It is the authors' goal to follow biological algorithms and principles of organization in the design of VLSI architectures, and to achieve similar or better performance in image processing and machine vision. Their efforts have yielded the following families of VLSI devices and systems. A highly parallel Intelligent Scan Image Acquisition VLSI sensing device has been constructed. It selectively scans only the relevant areas of interest in each image, thus effectively providing a compressed image for later processing stages. The device is controlled by an algorithm which is highly sensitive to image content. This sensor imitates the capability of the eye to concentrate on (attend) certain parts of the image, and even extends this by processing multiple focal points simultaneously. This is an example of how we applied the nonuniform sample-and-process algorithm, characteristic of biological vision, in a highly parallel architecture which surpasses the performance of the human eye.

Ginosar, R.; Zeevi, Y.Y.

1988-09-01

200

Biocompatible "click" wafer bonding for microfluidic devices.  

PubMed

We introduce a novel dry wafer bonding concept designed for permanent attachment of micromolded polymer structures to surface functionalized silicon substrates. The method, designed for simultaneous fabrication of many lab-on-chip devices, utilizes a chemically reactive polymer microfluidic structure, which rapidly bonds to a functionalized substrate via"click" chemistry reactions. The microfluidic structure consists of an off-stoichiometry thiol-ene (OSTE) polymer with a very high density of surface bound thiol groups and the substrate is a silicon wafer that has been functionalized with common bio-linker molecules. We demonstrate here void free, and low temperature (< 37 C) bonding of a batch of OSTE microfluidic layers to a silane functionalized silicon wafer. PMID:22760578

Saharil, Farizah; Carlborg, Carl Fredrik; Haraldsson, Tommy; van der Wijngaart, Wouter

2012-09-01

201

FPGA-realization of a motion control IC for wafer-handling robot  

Microsoft Academic Search

The work studies to apply a novel FPGA (Field Programmable Gate Arrays) technology to realize a motion control IC for wafer-handling robot which has three-DOF (Degree of freedom) and each axis is driven by PMSM (Permanent Magnet Synchronous Motor). The motion control IC proposed in this paper has two modules. The first module is a Nios II processor which is

Ying-Shieh Kung; Cheng-Ting Hsu; Hsin-Hung Chou; Tai-Wei Tsui

2010-01-01

202

Board level drop impact reliability analysis for compliant wafer level package through modeling approaches  

Microsoft Academic Search

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. In this paper, a new compliant Wafer Level Package technology is proposed which can accommodate the CTE mismatch between the chip and PCB substrate and consequently should be more reliable without the application of underfill. The purpose of this study is

Chaoping Yuan; K. L. Pan; Weiyang Qiu; Jing Liu

2009-01-01

203

Electrical performances and structural designs of copper bonding in wafer-level three-dimensional integration.  

PubMed

The integrity of bonded Cu interconnects in wafer-level three-dimensional integration has been investigated as the function of pattern size and density, as well as bonding process parameter. The desired pattern density coupled with the application of bonding process profile we developed gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and contact resistance through the entire wafer. This result is a key milestone in establishing the manufacturability of Cu-based interconnections for 3D integration technology. PMID:21770156

Chen, K N; Young, A M; Lee, S H; Lu, J Q

2011-06-01

204

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment  

NASA Technical Reports Server (NTRS)

Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

2013-01-01

205

Geometry control of recrystallized silicon wafers for solar applications  

E-print Network

The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

Ruggiero, Christopher W

2009-01-01

206

Bubble-domain circuit wafer evaluation coil set  

NASA Technical Reports Server (NTRS)

Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

Chen, T. T.; Williams, J. L.

1975-01-01

207

First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies  

NASA Technical Reports Server (NTRS)

Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

2008-01-01

208

Integratible process for fabrication of fluidic microduct networks on a single wafer  

NASA Astrophysics Data System (ADS)

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 mm, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectric materials.

Matzke, Carolyn M.; Ashby, Carol I. H.; Bridges, Monica M.; Griego, Leonardo; Wong, C. Channy

1999-08-01

209

Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer  

SciTech Connect

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

1999-09-07

210

Wafer Backside Anisotropic Wet Etching of Silicon  

NSDL National Science Digital Library

This animation, created by Southwest Center for Microsystems Education (SCME), illustrates how the "wafer backside anisotropic wet etching of silicon is used to form the pressure sensor chamber." Further information and resources can be found on the SCME website.

2014-07-30

211

REDUCING MANUFACTURING CYCLE TIME OF WAFER FAB WITH SIMULATION  

Microsoft Academic Search

Wafer Fabrication process is the starting point of making any computers or integrated circuit (IC) products. It is complex. On average, a wafer needs to go through more than 300 operational steps before shipping for assembly and test. It requires high investment. This makes the control of wafer fab very challenging and the results can be very encouraging. A simulation

Giam Kim Toh; Ui Wei Teck; Alimin Lie; George Sun; Wang Ming; Kelvin Kok

212

Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)  

SciTech Connect

A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

Rupnowski, P.; Sopori, B.

2008-05-01

213

Defect detection in patterned wafers using multichannel Scanning Electron Microscope  

E-print Network

Defect detection in patterned wafers using multichannel Scanning Electron Microscope Maria Zontak using Scanning Electron Microscope (SEM) images. A wafer is irradiated with a focused beam of electrons s t r a c t Recent computational methods of wafer defect detection often inspect Scanning Electron

Cohen, Israel

214

On VLSI Design of Rank-Order Filtering using DCRAM Architecture  

PubMed Central

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 ?m 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 427.7?m2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply. PMID:19865599

Lin, Meng-Chun; Dung, Lan-Rong

2009-01-01

215

VLSI architecture for variable-block-size motion estimation with luminance correction  

NASA Astrophysics Data System (ADS)

This paper describes the architecture and application of a flexible 100 GOPS (giga operations per second) exhaustive search segment matching VLSI architecture to support evolving motion estimation algorithms as well as block matching algorithms of established video coding standards. The architecture is based on a 32 by 32 processor element (PE) array and a 10240 byte on-chip search area RAM and allows concurrent calculation of motion vectors for 32 by 32, 16 by 16, 8 by 8 and 4 by 4 blocks and partial quadtrees (called segments) for a plus or minus 32 pel search range with 100% PE utilization. This architecture supports object based algorithms by excluding pixels outside of video objects from the segment matching process as well as advanced algorithms like variable block-size segment matching with luminance correction. The VLSI has been designed using VHDL synthesis and a 0.35 micrometer CMOS technology and will have a clock rate of 100 Mhz (min.) allowing the processing of 23668 32 by 32 blocks per second with a maximum of plus or minus 32 pel search area.

Kuhn, Peter M.; Stechele, Walter

1997-10-01

216

NASA Space Engineering Research Center for VLSI systems design  

NASA Technical Reports Server (NTRS)

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

1991-01-01

217

Advanced technologies for Mission Control Centers  

NASA Technical Reports Server (NTRS)

Advance technologies for Mission Control Centers are presented in the form of the viewgraphs. The following subject areas are covered: technology needs; current technology efforts at GSFC (human-machine interface development, object oriented software development, expert systems, knowledge-based software engineering environments, and high performance VLSI telemetry systems); and test beds.

Dalton, John T.; Hughes, Peter M.

1991-01-01

218

Development of GaN wafers via the ammonothermal method  

NASA Astrophysics Data System (ADS)

This paper reviews the current progress of ammonothermal growth at SixPoint Materials and discusses some of the remaining challenges to commercialize the technology. The mass production of the ammonothermal grown wafers of GaN for high power devices has substantial commercial potential but is currently limited by two problems: impurities which lead to semitransparent coloration and stress in the crystals which leads to cracking. To improve the coloration, it is important to understand and reduce the impurities in the crystal. Oxygen impurities were found to be the primary source of coloration. By reducing the oxygen impurities the absorption coefficient at 450 nm was improved to 3.9 cm-1 yielding semitransparent crystals. The second and more serious issue is a cracking that occurs when thick boules are produced. Currently we routinely produce ammonothermal growth over a millimeter in thickness without any cracking. However, as the thickness increases cracks develop. From a production viewpoint, the production of thick crystals is beneficial since it allows a single wafer to be processed into many. By improving a variety of parameters, the crack density was reduced and the maximum crack-free growth increased from 1 mm to 2.6 mm.

Letts, Edward; Hashimoto, Tadao; Hoff, Sierra; Key, Daryl; Male, Keith; Michaels, Mathew

2014-10-01

219

Wafer-scale fabrication of nanoapertures using corner lithography.  

PubMed

Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated--based on a theoretical foundation including a statistical analysis--with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures. PMID:23792365

Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

2013-07-19

220

Low cost camera modules using integration of wafer-scale optics and wafer-level packaging of image sensors  

NASA Astrophysics Data System (ADS)

Using wafer scale optics, wafer scale integration, and wafer level packaging of image sensor, we developed small form factor (3.3mmx3.3mmx2.5mm), low manufacturing cost, Pb-free solder reflow compatible digital camera modules which are suitable for many applications including mobile electronic devices, automotives, security, and medical applications.

Han, Hongtao; Main, Keith

2009-11-01

221

Performance optimization of digital VLSI circuits  

SciTech Connect

Designers of digital VLSI circuits have virtually no computer tools available for the optimization of circuit performance. Instead, a designer relies extensively on circuit-analysis tools, such as circuit simulation (SPICE) and/or critical-delay-path analysis. A circuit-analysis approach to digital design is very labor-intensive and seldom produces a circuit with optimum area/delay or power/delay trade off. The goal of this research is to provide a synthesis approach to the design of digital circuits by finding the sizes of transistors that optimize circuits by finding the sizes of transistors that optimize circuit performance (delay, area, power). Solutions are found that are optimum for all possible delay paths of a given circuit and not for just a single path. The approach of this research is to formulate the problem of area/delay or power/delay optimization as a nonlinear program. Conditions for optimality are then established using graph theory and Kuhn-Tucker conditions. Finally, the use of augmented-Lagrangian and projected-Lagrangian algorithms are reviewed for the solution of the nonlinear programs. Two computer programs, PLATO and COP, were developed by the author to optimize CMOS PLA's (PLATO) and general CMOS circuits (COP). These tools provably find the globally optimum transistor sizes for a given circuit. Results are presented for PLA's and small- to medium-sized cells.

Marple, D.P.

1987-01-01

222

Product assurance technology efforts: Technical accomplishments  

NASA Technical Reports Server (NTRS)

Product assurance technology topics addressed include: wafer acceptance procedures, test chips, test structures, test chip methodology, fault models, and the Combined Release and Radiation Effects Satellite test chip.

1985-01-01

223

Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process  

NASA Astrophysics Data System (ADS)

Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

2013-09-01

224

Optical cavity furnace for semiconductor wafer processing  

DOEpatents

An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

Sopori, Bhushan L.

2014-08-05

225

Devices using resin wafers and applications thereof  

DOEpatents

Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

2009-03-24

226

Macromodeling and Optimization of Digital MOS VLSI Circuits  

Microsoft Academic Search

Power consumption and signal delay are crucial to the design of high-performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based

Mark Douglas Matson; Lance A. Glasser

1986-01-01

227

CSCE 6933/5933 Advanced Topics in VLSI Systems  

E-print Network

technique called Design of Experiments-Monte Carlo (DOE-MC) approach is proposed, offering up to 6.25X computational time savings over traditional Monte-Carlo (TMC). Advanced Topics in VLSI Systems 5 #12;Related: Efficient Design of Current-Starved VCO NOTE: The figures, text etc included in slides are borrowed from

Mohanty, Saraju P.

228

Modeling Selective Attention Using a Neuromorphic Analog VLSI Device  

Microsoft Academic Search

Attentional mechanisms are required to overcome the problem of ood- ing a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for articial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large- scale integration (VLSI) chip, using analog

Giacomo Indiveri

2001-01-01

229

VLSI CAD tool integration using the Ulysses environment  

Microsoft Academic Search

Ulysses is a VLSI CAD environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment

Michael L. Bushnell; Stephen W. Director

1986-01-01

230

Hybrid VLSI/QCA Architecture for Computing FFTs  

NASA Technical Reports Server (NTRS)

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

231

Decentralized Fault-Tolerant Clock Pulse Generation in VLSI Chips  

E-print Network

Decentralized Fault-Tolerant Clock Pulse Generation in VLSI Chips The invention offers a solution for various problems associated with the steady increase of clock rates of chips. It offers a fault of faults; · self generation of clock pulses. Instead of globally distributing the clock produced

Szmolyan, Peter

232

EFFICIENT VLSI IMPLEMENTATION OF BIT PLANE CODER OF JPEG2000  

E-print Network

EFFICIENT VLSI IMPLEMENTATION OF BIT PLANE CODER OF JPEG2000 Kishore Andra* , Tinku Acharya compression, a new standard, JPEG2000, is under development by the International Standard Organization. Embedded bit plane coding is the heart of the JPEG2000 encoder. This encoder is more complex and has

Kambhampati, Subbarao

233

VLSI architecture for computing third-order cumulants  

Microsoft Academic Search

The higher order statistics (HOS) (or cumulants), and their associated Fourier Transforms, have been established as a powerful analytical tool in modern signal processing. This paper presents a computationally efficient VLSI architecture for computing third-order cumulants. The architecture is based on the systolic array implementation and exploits parallelism, pipelining, and regular cell structures. The architecture is designed with 10?m CMOS

RANA EJAZ AHMED; M. A. AL-TURAIGT; SALEH A. ALSHEBEILI

1994-01-01

234

Palmo: pulse-based signal processing for programmable analog VLSI  

Microsoft Academic Search

This paper presents novel signaling and circuit techniques for the implementation of programmable analog and mixed signal very large scale integration (VLSI). The signaling technique uses pulsewidth modulated digital signals to convey analog signal information between programmable analog cells. A circuit for a generic programmable analog cell is introduced and is analyzed for harmonic distortion performance. The equivalence of the

Konstantinos Papathanasiou; Thomas Brandtner; Alister Hamilton

2002-01-01

235

ECE533 Advanced MOS Concepts and VLSI Design Spring 2012  

E-print Network

ECE533 Advanced MOS Concepts and VLSI Design Spring 2012 S.K. Islam, 504 Min Kao Building, 974 on the course website. Lab 1: Introduction Lab 2: Simulation of Inverter using Spectre Lab 3: Schematic Entry Topics: Introduction to CMOS Circuits MOS Transistor Theory CMOS Process Video CMOS Processes CMOS Layout

Tennessee, University of

236

The constrained via minimization problem for PCB and VLSI design  

Microsoft Academic Search

A new via minimization approach is presented for two layer routing of printed circuit boards and VLSI chips. We have analyzed and characterized different aspects of the problem and have derived an equivalent graph model for the problem from the linear programming formulation. Based on the analysis of our unified formulation, we posed a practical heuristic algorithm. The algorithm can

Xiao-Ming Xiong; Ernest S. Kuh

1988-01-01

237

Cycle time and slack optimization for VLSI-chips  

Microsoft Academic Search

We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes all previously considered models. Then we show how to optimize the cycle time and optimally balance slacks on data paths and on clocktree paths.The problem of finding a clock schedule

Christoph Albrecht; Bernhard Korte; Jrgen Schietke; Jens Vygen

1999-01-01

238

A special purpose silicon compiler for designing supercomputing VLSI systems  

NASA Technical Reports Server (NTRS)

Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

1991-01-01

239

The on-chip parallelism of VLSI circuits  

Microsoft Academic Search

Simulation is a bottleneck in VLSI circuit design. Not only are there many simulation runs throughout the design cycle, but each run can take hours or days to complete. One often suggested means of speeding up event-driven simulation is to use multiple processors to exploit the natural parallelism present in the circuit, that is to partition the circuit among multiple

M. L. Bailey

1989-01-01

240

A VLSI architecture of color model-based tonsillitis detection  

Microsoft Academic Search

Tonsillitis disease is the cause of heart attack and pneumonia. It is also a sign of suspected symptom of heart disease. To improve data transfer rates, this paper proposes VLSI architecture by using color model for early-state tonsillitis detection. In this method, input image is divided into 9 blocks. Each block has 3times3 window which send color data and pixel

Pranithan Phensadsaeng; Werapon Chiracharit; Kosin Chamnongthai

2009-01-01

241

Biophysical Neural Spiking and Bursting Dynamics in Reconfigurable Analog VLSI  

E-print Network

Biophysical Neural Spiking and Bursting Dynamics in Reconfigurable Analog VLSI Theodore Yu1 92037 Abstract--We study a range of neural dynamics under varia- tions in biophysical parameters kinetics and biophysical membrane dynamics. We present simulation and measurement results and observe

Cauwenberghs, Gert

242

Etching methodologies in ?111?-oriented silicon wafers  

Microsoft Academic Search

New methodologies in anisotropic wet-chemical etching of ?111?-oriented silicon, allowing useful process designs combined with smart mask-to-crystal-orientation-alignment are presented in this paper. The described methods yield smooth surfaces as well as high-quality plan-parallel beams and membranes. With a combination of pre-etching and wall passivation, structures can be etched at different depths in a wafer. Designs, using the ?111?-crystal orientation, supplemented

R. Edwin Oosterbroek; J. W. Berenschot; H. V. Jansen; A. J. Nijdam; G. Pandraud; A. van den Berg; M. C. Elwenspoek

2000-01-01

243

Precipitating Chromium Impurities in Silicon Wafers  

NASA Technical Reports Server (NTRS)

Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

Salama, A. M.

1982-01-01

244

Optoelectronic interconnects for 3D wafer stacks  

Microsoft Academic Search

Wafer and chip stacking are envisioned as a means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input\\/output communication channels within the layers of

David E. Ludwig; John C. Carson; Louis S. Lome

1996-01-01

245

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.  

PubMed

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-01

246

Fabrication of large-scale monocrystalline silicon micro-mirror arrays using adhesive wafer transfer bonding  

NASA Astrophysics Data System (ADS)

Today, spatial light modulators (SLMs) based on individually addressable micro-mirrors play an important role for use in DUV lithography and adaptive optics. Especially the mirror planarity and stability are important issues for these applications. Mono-crystalline silicon as mirror material offers a great possibility to combine the perfect surface with the good mechanical properties of the crystalline material. Nevertheless, the challenge is the integration of mono-crystalline silicon in a CMOS process with low temperature budget (below 450C) and restricted material options. Thus, standard processes like epitaxial growth or re-crystallization of poly-silicon cannot be used. We will present a CMOS-compatible approach, using adhesive wafer transfer bonding with Benzocyclobutene (BCB) of a 300nm thin silicon membrane, located on a SOI-donor wafer. After the bond process, the SOI-donor wafer is grinded and spin etched to remove the handle silicon and the buried oxide layer, which results in a transfer of the mono-crystalline silicon membrane to the CMOS wafer. This technology is fully compatible for integration in a CMOS process, in order to fabricate SLMs, consisting of one million individually addressable mono-crystalline silicon micro-mirrors. The mirrors, presented here, have a size of 1616 ?m2. Deflection is achieved by applying a voltage between the mirrors and the underlying electrodes of the CMOS electronics. In this paper, we will present the fabrication process as well as first investigations of the mirror properties.

Zimmer, Fabian; Niklaus, Frank; Lapisa, Martin; Ludewig, Thomas; Bring, Martin; Friedrichs, Martin; Bakke, Thor; Schenk, Harald; van der Wijngaart, Wouter

2009-02-01

247

Direct To Digital Holography For High Aspect Ratio Inspection of Semiconductor Wafers  

NASA Astrophysics Data System (ADS)

Direct to Digital Holography (DDH) has been developed as a semiconductor wafer inspection tool and in particular as a tool for seeing defects in high aspect ratio (HAR) structures on semiconductor wafers and also for seeing partial-height defects. While the tool works very well for general wafer inspection, it has unusual capabilities for high aspect ratio inspection (HARI) and for detecting thin residual film defects (partial height defects). Inspection of HAR structures is rated as one of the highest unmet priorities of the member companies of International SEMATECH, and finding residual thin film defects (in some cases called "stringers") is also a very difficult challenge. The capabilities that make DDH unusually sensitive include: 1) the capture of the whole waveboth the classical amplitude captured by traditional optical systems, and the phase of the wave, with phase potentially measured to 1/1000'th of a wavelength or 2 to 3 Angstroms for a deep ultra-violet (DUV) laser; 2) heterodyne detectionthis allows it to capture very low signal levels; and 3) a head-on geometry using a collimated laser beam that allows best penetration of HAR structures. The basic features and methods of this patented technology are presented, along with simple calculations of signal strength and expected noise levels for various circumstances. Full-wave numerical calculations of electromagnetic field penetration into HAR contacts and experimental results from various wafer types and structures are also presented.

Thomas, C. E. (Tommy); Hunt, Martin A.; Bahm, Tracy M.; Baylor, Larry R.; Bingham, Philip R.; Chidley, Matthew D.; Dai, Xiaolong; Delahanty, Robert J.; El-Khashab, Ayman; Gilbert, Judd M.; Goddard, James S.; Hanson, Gregory R.; Hickson, Joel D.; Hylton, Kathy W.; John, George C.; Jones, Michael L.; Mayo, Michael W.; Marek, Christopher; Price, John H.; Rasmussen, David A.; Schaefer, Louis J.; Schulze, Mark A.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin, Kenneth W.; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Owen, Robert W.

2003-09-01

248

Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins  

NASA Astrophysics Data System (ADS)

Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

Mller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

2014-04-01

249

Wafer-Level Membrane-Transfer Process for Fabricating MEMS  

NASA Technical Reports Server (NTRS)

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

250

Electrooptic shutter devices utilizing PLZT ceramic wafers  

SciTech Connect

Optical transparency was achieved in lead zirconate-titanate ferroelectric ceramics by substituting moderate amounts of the element lanthanum (8 to 12%) for lead. These compositions exhibit the quadratic (Kerr) electrooptic effect. The excellent optical qualities of these materials (designated PLZT) has permitted the practical utilization of their electrooptic properties in a number of devices. All of these devices utilize the classic Kerr cell arrangement. A PLZT wafer with optical axis oriented at 45/sup 0/ with respect to the axes of polarization is sandwiched between crossed polarizers. Application of an electric field via an interdigital array of electrodes on opposing wafer surfaces forces the PLZT material into a tetragonal state with the resulting induced birefringence proportional to the square of the applied electric field. Hence, the electrooptic wafer provides a retardation of light so that a component is passed by the second crossed polarizer to achieve an ON or open state. Maximum transmission is achieved when the retardation is half-wave. Shutter devices developed by Sandia and those in continuing development are described with respect to operational characteristics and physical configuration. The devices range in size from very small apertures of 50 ..mu..m x 2 mm with center-to-center repeat dimensions of 125 ..mu..m - to very large - apertures of 15.2 cm in single pieces and mosaics with apertures of 15.2 cm x 20.3 cm. Major efforts have centered on shutter development for the protection of aircrew from eye-damaging weapon effects. Other devices are also described which: provide eye protection for welders, protect vidicon tubes, function as page composers for holographic memories serve as large aperture photographic shutters, provide stereoscopic three-dimensional TV displays, and serve as data links in a fiber-optic transmission path.

Thornton, A.L.

1981-01-01

251

vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM  

ERIC Educational Resources Information Center

This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.

Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

2014-01-01

252

High density circuit technology, part 1  

NASA Technical Reports Server (NTRS)

The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

Wade, T. E.

1982-01-01

253

High density circuit technology, part 3  

NASA Technical Reports Server (NTRS)

Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations.

Wade, T. E.

1982-01-01

254

Wafer-scale aluminum nano-plasmonics  

NASA Astrophysics Data System (ADS)

The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

2014-09-01

255

Wafer-scale charge isolation technique  

SciTech Connect

An apparatus and method are described which improve the performance of charge-coupled devices (CCD) in the presence of ionizing radiation. The invention is a wafer scale charge isolation technique which inhibits or reduces the flow of electrons created by the passage of ionizing radiation in the bulk regions of a silicon CCD. The technique has been tested in a device designed for operating in the infra-red wavelength band. The technique prevents charge from reaching the active charge collection volume of a pixel in a CCD.

Colella, N.J.; Kimbrough, J.R.

1994-12-31

256

Auto Defect Classification (ADC) Value for Patterned Wafer Inspection Systems in PLY Within a High Volume Wafer Manufacturing Fabrication Facility  

E-print Network

silicon wafer and repeats a process of depositing multiple layers of material on the wafer topped with a photo sensitive top layer. Using photo- litholography to expose the wafer, exposed areas will be vulnerable or hardened to the chemical etching...-6 Industry Overview . 7-10 Literary Research 11-13 Challenge 13-14 Project Outline 14 Goals... 14-16 Result 1 - Blocked Etch . 17-20 Moving Median...

Durniak, John

2010-05-14

257

Opto-VLSI-based tunable single-mode fiber laser.  

PubMed

A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature. PMID:20372600

Xiao, Feng; Alameh, Kamal; Lee, Tongtak

2009-10-12

258

Noise-margin limitations on gallium-arsenide VLSI  

NASA Technical Reports Server (NTRS)

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Long, Stephen I.; Sundaram, Mani

1988-01-01

259

Mechanisms for room temperature direct wafer bonding  

NASA Astrophysics Data System (ADS)

Reducing the temperature needed for high strength bonding which was and is driven by the need to reduce effects of coefficient of thermal expansion mismatch, reduce thermal budgets, and increase throughput has led to the development of plasma treatment procedures capable of bonding Si wafers below 300 C with a bond strength equivalent to Si bulk. Despite being widely used, the physical and chemical mechanisms enabling low temperature wafer bonding have remained poorly understood. We developed an understanding of the beneficial surface modifications by plasma and a model based on short range low temperature diffusion through bonding experiments combined with results from spectroscopic ellipsometry, depth resolving Auger electron spectroscopy, and transmission electron microscopy measurements. We also present experimental results showing that even at room temperature reasonable bond strength can be achieved. We conclude that the gap closing mechanism is therefore a process which balances the lowering of the total energy by minimizing the sum of the free surface energy (maximizing the contact area between the surfaces) and strain energy in the oxide at the bond interface.

Plach, T.; Hingerl, K.; Tollabimazraehno, S.; Hesser, G.; Dragoi, V.; Wimplinger, M.

2013-03-01

260

Autonomous Vehicle Guidance Using Analog VLSI Neuromorphic Sensors  

Microsoft Academic Search

Analog VLSI circuits implementing aspects of biological sys- tems are attractive for the construction of compact low-power autonomous systems. We describe such a system, consisting of a mobile robot equipped with a neuromorphic sensor implementing a one dimensional silicon retina. Specically, we demonstrate how the real-time visual pre-processing ca- pabilities of the neuromorphic sensor are instrumental in enabling the system

Giacomo Indiveri; Paul F. M. J. Verschure

1997-01-01

261

A VLSI design of a pipeline Reed-Solomon decoder  

NASA Technical Reports Server (NTRS)

A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

1985-01-01

262

Systolic VLSI and FPGA Realization of Artificial Neural Networks  

Microsoft Academic Search

\\u000a Systolic architectures are established as a widely popular class of VLSI structures for repetitive and computation-intensive\\u000a applications due to the simplicity of their processing elements (PEs), modularity of design, regular and nearest neighbor\\u000a interconnections between the PEs, high-level of pipelinability, small chip-area and low-power consumption. In systolic arrays,\\u000a the desired data is pumped rhythmically in a regular interval across the

Pramod Kumar Meher

263

Drift chamber tracking with a VLSI neural network  

SciTech Connect

We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers.

Lindsey, C.S.; Denby, B.; Haggerty, H. (Fermi National Accelerator Lab., Batavia, IL (United States)); Johns, K. (Arizona Univ., Tucson, AZ (United States). Dept. of Physics)

1992-10-01

264

Opto-VLSI-based N M wavelength selective switch.  

PubMed

In this paper, we propose and experimentally demonstrate a novel N M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB. PMID:23938686

Xiao, Feng; Alameh, Kamal

2013-07-29

265

Parallel Random Number Generation for VLSI Systems Using Cellular Automata  

Microsoft Academic Search

A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in parallel from various cells in the cellular automaton on each

Peter D. Hortensius; Robert D. Mcleod; Howard C. Card

1989-01-01

266

Computing perspectives: the rise of the VLSI processor  

Microsoft Academic Search

Around 1970 Intel discovered it could put 2,000 transistorsor perhaps a few moreon a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), an event which had been long heralded, but had been seemingly slow to come. At the time, it went almost unnoticed in the computer industry. This was partly

Maurice V. Wilkes

1990-01-01

267

A survey of power estimation techniques in VLSI circuits  

Microsoft Academic Search

With the advent of portable and high-density microelectronic devices, the power dissipationof very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate andefficient power estimation during the design phase is required in order to meet the powerspecifications without a costly redesign process. In this paper, we present a review\\/tutorialof the power estimation techniques that have recently been proposed.Invited,

Farid N. Najm

1994-01-01

268

Design and VLSI implementation of an ASK for real-time manipulation of digital colour images  

Microsoft Academic Search

This paper presents the design and VLSI implementation, on a single chip, of a new real-time colour space converter, which performs the transformation of the RCB colour coordinates to the intensity, hue and saturation (IHS) colour space. This high speed VLSI chip is designed to work at 13.3 MHz and can process high resolution colour images of up to 697

I. Andreadis; K. Stavroglou; Ph. Tsalides

1995-01-01

269

Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite  

E-print Network

1 Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite-scale VLSI design demands reliable on- chip power/ground (P/G) supply. Decoupling capacitors effec- tively decoupling capacitor insertion techniques are based on sensitivity analysis and greedy optimization

Liu, Bao

270

Parallel algorithms and VLSI architectures for stack filtering using Fibonacci p-codes  

Microsoft Academic Search

A parallel decompositional algorithm and VLSI architecture is proposed for computation of the output of a stack filter over a single window of input samples using Fibonacci p-codes. For a subclass of positive Boolean functions, a more efficient parallel algorithm and VLSI architecture for running stack filtering is also presented. The area-time complexities of the proposed designs are estimated

David Z. Gevorkian; K. O. Egiazarian; S. S. Agaian; J. T. Astola; O. Vainio

1995-01-01

271

VLSI architecture for HDTV sub-band coding using GQMFs' filterbanks  

Microsoft Academic Search

A VLSI architecture for a low complexity intraframe subband image coding for HDTV signals is presented. The generalized quadrature mirror filters (GQMFs), which have smaller overall delay, are optimized in order to achieve high coding efficiency. The filter design exploits a symmetry property among different filter coefficients which, in turn, reduces the hardware complexity of the VLSI architecture substantially. The

A. K. Al-Asmari; Rana Ejaz Ahmed

1995-01-01

272

VLSI design approach of complex motor control: case of direct torque control of AC machine  

Microsoft Academic Search

This paper presents VLSI design for complex motor control in the case of direct torque control (DTC) algorithm. A specific methodology, using VHDL descriptions and analog-digital simulations in a power and analog context, is applied to study DTC algorithm digital properties, ASIC architecture and VLSI layout

F. Aubepart; Philippe POURE; F. Braun

2000-01-01

273

A Memory Aware Behavioral Synthesis Tool for Real-Time VLSI Circuits  

E-print Network

A Memory Aware Behavioral Synthesis Tool for Real-Time VLSI Circuits Gwenol´e Corre, Eric Senn the mem- ory architecture and the memory mapping in the Behav- ioral Synthesis of Real-Time VLSI circuits. We formalize the memory mapping as a set of constraints for the syn- thesis, and defined a Memory

Paris-Sud XI, Université de

274

An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs  

E-print Network

An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs with a Proposal design. ................ 27 #12; 5.2 Definition of the MCM routing problem. .................. 28 5 demands on these placement and routing algorithms than on VLSI or PCB layouts. However, many

Thornton, Mitchell

275

Ultra-Low Noise HEMT Device Models: Application of On-Wafer Cryogenic Noise Analysis and Improved Parameter Extraction Techniques  

NASA Technical Reports Server (NTRS)

Significant advances in the development of HEMT technology have resulted in high performance cryogenic low noise amplifiers whose noise temperatures are within an order of magnitude of the quantum noise limit. Key to the identification of optimum HEMT structures at cryogenic temperatures is the development of on-wafer noise and device parameter extraction techniques. Techniques and results are described.

Bautista, J. J.; Hamai, M.; Nishimoto, M.; Laskar, J.; Szydlik, P.; Lai, R.

1995-01-01

276

Design and fabrication of a miniature pressure sensor head using direct bonded ultra-thin silicon wafers  

Microsoft Academic Search

We have designed and fabricated a miniature pressure sensor head which is formed using an ultrathin silicon wafer (~5 ?m thick) directly bonded to an excimer laser micromachined silicon substrate. The fabrication process features numerous advantages over existing pressure sensor construction technology including a maskless procedure and no chemical or mechanical thinning required to form the membrane after bonding. The

Chad E. Statler; Elizabeth S. Olson; K. R. Farmer

1996-01-01

277

The investigation on research opportunities for the applications of the Internet of Things in semiconductor wafer fabrication  

Microsoft Academic Search

Based on the state-of-the-art technologies of the Internet of Things (IOT) and Radio Frequency Identifier (RFID) this paper introduces the concepts of IOT\\/RFID and investigates its open research opportunity and potential applications in real-time monitoring and dispatch controls for semiconductor wafer fabrication (FAB).

Yong-Zai Lu

2010-01-01

278

ULYSSES - an expert-system-based VLSI design environment  

SciTech Connect

Ulysses is a VLSI computer-aided design (CAD) environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation (DA) system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment employs artificial intelligence techniques, functions as an interactive expert system, and interprets descriptions of design tasks encoded in the scripts language. An integrated-circuit silicon compilation task is presented as an example of the ability of Ulysses to automatically execute CAD tools to solve a problem where inferencing is required to obtain a viable VLSI layout. The inferencing mechanism, in the form of a controlled production system, allows Ulysses to recover when routing channel congestion or over-constrained leaf-cell boundary conditions make it impossible for CAD tools to complete layouts. Also, Ulysses allows the designer to intervene while design activities are being carried out. Consistency-maintenance rules encoded in the scripts language enforce geometric floor-plan consistency when CAD tools fail and when the designer makes adjustments to a VLSI chip layout.

Bushnell, M.L.

1987-01-01

279

Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards. [Very Large Scale Integration (VLSI)  

SciTech Connect

This paper discusses the sensor-based driving of a car in a-priori unknown environments using human-like'' reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver's aid using the new fuzzy inferencing VLSI hardware and human-like'' reasoning schemes.

Pin, F.G.; Watanabe, Y.

1992-01-01

280

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.  

PubMed

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 m thick Si wafers with about 1 m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale. PMID:24457563

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-01

281

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Selwyn, Gary S. (Los Alamos, NM)

1998-01-01

282

Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint  

SciTech Connect

This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

Rupnowski, P.; Sopori, B.

2008-05-01

283

Near 13% Efficiency Shunt Free Solar Cells on RGS Wafers  

Microsoft Academic Search

Direct casting of silicon into wafers allows to produce wafers much more cheaply than in traditional block casting methods. RGS (ribbon growth on substrate) is such a method. In order for RGS to be cost effective sufficient cell efficiencies must be realized. In this paper we present a 12.9% efficient screen printed RGS cell. This is an increase of 0.6%

Antonius Burgers; Astrid Gutjahr; Leon Laas; Axel Schonecker; Sven Seren; Giso Hahn

2006-01-01

284

High density plasma flood system for wafer charge neutralisation  

Microsoft Academic Search

The Plasma Flood System, a low energy electron generator, has been widely used as an effective tool to neutralise wafer charging induced by ion implantation. Although it has been successful in achieving the full device yield under high current ion implantation, further advancement in device design imposed a need to minimise the wafer charging down to a few volts due

Hiroyuki Ito; Hiroshi Asechia; Yasuhiko Matsunaga; Masahiko Niwayamab; Kenji Yoneda; Michael Vella; Mike Reilly; Walt Hacker

1999-01-01

285

Wafer-Scale Microtensile Testing of Thin Films  

Microsoft Academic Search

This paper reports on the mechanical characterization of thin films using the microtensile technique performed for the first time at the wafer scale. Multiple test structures are processed and sequentially measured on the same silicon substrate, thus eliminating delicate handling of individual samples. The current layout uses 26 test structures evenly distributed over a 4-in wafer, each of them carrying

Joo Gaspar; Marek E. Schmidt; Jochen Held; Oliver Paul

2009-01-01

286

Sacrificial wafer bonding for planarization after very deep etching  

Microsoft Academic Search

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of polymer bonding followed by

Vincent L. Spiering; J. W. Berenschot; Miko Elwenspoek; Jan H. J. Fluitman

1995-01-01

287

Wafer quality analysis of various scribe line mark designs  

NASA Astrophysics Data System (ADS)

Scribe Line Marks (SLM) printed on substrates are a standard method used by modern scanners for wafer alignment. Light reflected from the SLM forms a diffraction pattern which is used to determine the exact position of the wafer. The signal strength of the diffraction order needs to reach a certain threshold for the scanner to detect it. The marks are changed as the wafers go through various processes and are buried underneath complex film stacks. These processes and stacks can severely reduce wafer quality (WQ). Equipment manufactures recommend several variations of the SLM to improve WQ but these variations are not effective for certain advanced processes. This paper discusses theoretical analysis of how SLM designs affect wafer quality, addresses the challenge of self-aligned double patterning (SADP) on SLMs and experimentally verifies results using various structures.

Zhou, Jianming; Hickman, Craig; He, Yuan; Light, Scott; Lamonds, Lucas; deVilliers, Anton

2011-03-01

288

VLSI Analogs of Neuronal Visual Processing  

E-print Network

Institute of Technology Pasadena, California 1992 (Defended 12 May 1992) #12;Acknowledgments my heart has . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 Basic Anatomy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.2 Function

289

200-mm GaN-on-Si Based Blue Light-Emitting Diode Wafer with High Emission Uniformity  

NASA Astrophysics Data System (ADS)

We investigated the emission wavelength uniformity of 200-mm GaN-on-Si based blue light-emitting diode (LED) wafer grown by metalorganic vapor phase epitaxy (MOVPE). The larger the Si substrate diameter becomes, the more difficult to obtain uniform distribution of the emission wavelength because of the larger bow during growth, resulting in larger on-wafer inhomogeneity in growth temperature. Owing to the GaN-on-Si buffer strain management, optimized gas flow condition, and precise control of temperature balance in a reactor, we have achieved high thickness and crystal quality uniformity over the 200-mm GaN-on-Si based blue LED wafer. As a result, excellent blue photoluminescence emission wavelength uniformity from the InGaN-multi-quantum wells can be demonstrated on a 200-mm wafer with a standard deviation of 2.53 nm (0.57%). Less wavelengths binning with these highly uniform emission over the 200-mm wafer show the capability of sustainable cost reduction in LED fabrication based on GaN-on-Si technology.

Nishikawa, Atsushi; Groh, Lars; Solari, William; Lutgen, Stephan

2013-08-01

290

Rapid defect detections of bonded wafer using near infrared polariscope  

NASA Astrophysics Data System (ADS)

In modern field of microelectronics and MEMS, wafer bonding has emerged as an important processing step in wide range of manufacturing applications. During the manufacturing process, even in the modern clean room, small defects result from trapped particles and gas bubbles exist at bonded interface. Defects and trapped particles may exist on the top and bottom of the wafers, or at the interface of bonded wafer pair. These inclusions will generate high stress around debond region at the wafers bonded interface. In this paper, inspection at the bonded interface will be the interest of investigation. Since silicon wafer is opaque to visible light, defect detection at the bonded interface of silicon wafer is not possible. Due to the fact that silicon wafer is transparent to wavelength greater than 1150nm, an Near Infrared Polariscope which has showed some promises on residual stress measurement on silicon devices has been adapted and developed. This method is based on the well known photoelastic principles, where the stress variations are measured based on the changes of light propagation velocity in birefringence material. The results are compared and contrast with conventional Infrared Transmission Imaging tool (IRT) which is widely used to inspect the bonded silicon wafer. In this research, the trapped particles that are not visible via conventional infrared transmission method are identified via the generated residual stress pattern. The magnitude of the residual stress fields associated with each defect is examined qualitatively and quantitatively. The stress field generated at the wafers bonded interface will looks like a 'butterfly' pattern. Wafer pairs Pyrex-Si and Si-Si bonded interface will be examined.

Ng, Chi Seng; Asundi, Anand K.

2011-10-01

291

Design Study of Wafer Seals for Future Hypersonic Vehicles  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

292

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing  

NASA Technical Reports Server (NTRS)

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Aanstoos, J. V.; Snyder, W. E.

1981-01-01

293

Wafer-level vacuum packaging for an optical readout bi-material cantilever infrared FPA  

NASA Astrophysics Data System (ADS)

In this paper, we report the design and fabrication of an uncooled infrared (IR) focal plane array (FPA) on quartz substrate and the wafer-level vacuum packaging for the IR FPA in view of an optical readout method. This FPA is composed of bi-material cantilever array which fabricated by the Micro-Electro Mechanical System (MEMS) technology, and the wafer-level packaging of the IR FPA is realized based on AuSn solder bonding technique. The interface of soldering is observed by scan electron microscope (SEM), which indicates that bonding interface is smooth and with no bubbles. The air leakage rate of packaged FPA is measured to be 1.310-9 atmcc/s.

Li, Shuyu; Zhou, Xiaoxiong; Yu, Xiaomei

2013-12-01

294

Double exposure as a method to correct on-wafer CD variations: a proposal  

NASA Astrophysics Data System (ADS)

Keeping across-field CD variation on the wafer within the tight limits imposed by 28nm and other advanced technologies is a challenge, particularly in a foundry where designs of different customers are realized. We propose a cost-efficient, fast, and flexible method to improve CD uniformity and correct reticle or design-induced variation, by applying a second exposure to the wafer, in the form of a grey scale map created with a low grade correction reticle. Compared to CD correction by subsequent modification of the primary reticle, this method has the potential of much higher spatial resolution and simpler logistics, which make it an attractive alternative especially for prototyping and lowvolume production.

Hotzel, Arthur; Bald, Holger

2012-02-01

295

Fabrication of laterally driven bulk titanium devices on titanium-on-glass wafers  

NASA Astrophysics Data System (ADS)

In this study, a sandwiched titanium-on-glass (TOG) substrate was used to fabricate laterally driven microelectromechanical systems devices with bulk titanium as the structural material. 4? TOG wafers with a titanium device layer of 25 m were fabricated by low temperature SU-8 wafer bonding and chemical mechanical polishing. By using inductively coupled plasma for titanium deep etching as well as dry release, suspended high-aspect-ratio bulk titanium structures were realized with only one mask. A laterally driven electrostatic comb-driven bulk titanium resonator was manufactured as a preliminary demonstration. The resonator achieves a quality factor of 110 at 34 kHz, and survived 10?000 g shock without damage. Due to the high mechanical endurance and excellent corrosion resistance of titanium, TOG technology may open up many new applications in harsh environments.

Zhang, Yiming; Li, Nannan; Yan, Bo; Feng, Xiaoyang; Hu, Jia; He, Shuwei; Hao, Yilong; Chen, Jing

2013-07-01

296

Direct to Digital Holography for Semiconductor Wafer Defect Detection and Review  

SciTech Connect

A method for recording true holograms (not holographic interferometry) directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional to wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for finding defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep ultra-violet light.

ThomasJr., C. E. [nLine Corporation, Austin, TX; Bahm, Tracy M. [nLine Corporation, Austin, TX; Baylor, Larry R [ORNL; Bingham, Philip R. [nLine Corporation, Austin, TX; Burns, Steven W. [nLine Corporation, Austin, TX; Chidley, Matthew D [ORNL; Dai, Xiaolong [nLine Corporation, Austin, TX; Delahanty, Robert J. [nLine Corporation, Austin, TX; Doti, Christopher J. [nLine Corporation, Austin, TX; El-Khashab, Ayman [nLine Corporation, Austin, TX; Fisher, Robert L. [nLine Corporation, Austin, TX; Gilbert, Judd M. [nLine Corporation, Austin, TX; Cui, Hongtao [ORNL; Goddard Jr, James Samuel [ORNL; Hanson, Gregory R [ORNL; Hickson, Joel D. [nLine Corporation, Austin, TX; Hunt, Martin A. [nLine Corporation, Austin, TX; Hylton, Kathy W [ORNL; John, George C. [nLine Corporation, Austin, TX; Jones, Michael L. [nLine Corporation, Austin, TX; McDonald, Kenneth R. [nLine Corporation, Austin, TX; Mayo, Michael W. [nLine Corporation, Austin, TX; McMackin, Ian [nLine Corporation, Austin, TX; Patek, David [ORNL; Price, John H. [nLine Corporation, Austin, TX; Rasmussen, David A [ORNL; Schaefer, Louis J. [nLine Corporation, Austin, TX; Scheidt, Thomas R. [nLine Corporation, Austin, TX; Schulze, Mark A. [nLine Corporation, Austin, TX; Schumaker, Philip D. [nLine Corporation, Austin, TX; Shen, Bichuan [nLine Corporation, Austin, TX; Smith, Randall G. [nLine Corporation, Austin, TX; Su, Allen N. [nLine Corporation, Austin, TX; Tobin Jr, Kenneth William [ORNL; Usry, William R. [nLine Corporation, Austin, TX; Voelkl, Edgar [nLine Corporation, Austin, TX; Weber, Karsten S. [nLine Corporation, Austin, TX; Jones, Paul G. [nLine Corporation, Austin, TX; Owen, Robert W. [nLine Corporation, Austin, TX

2002-01-01

297

Analytic modeling, optimization, and realization of cooling devices in silicon technology  

Microsoft Academic Search

A novel cooling device fully built in silicon technology is presented. The new concept developed in this work consists of micromachining the bottom side of the circuit wafer in order to embed heat sinking microchannels directly into the silicon material. These microchannels are then sealed, by a direct wafer bonding procedure, with another silicon wafer where microchannels and inlet-outlet nozzles

Corinne Perret; Jumana Boussey; Christian Schaeffer; Martin Coyaud

2000-01-01

298

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.  

PubMed

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. PMID:24700434

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

299

Packaging solution for VLSI electronic photonic chips  

E-print Network

As the demand of information capacity grows, the adoption of optical technology will increase. The issue of resistance and capacitance is limiting the electronic transmission bandwidth while fiber optic delivers data at ...

Lee, Chieh-feng

2007-01-01

300

The uses of Man-Made diamond in wafering applications  

NASA Technical Reports Server (NTRS)

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Fallon, D. B.

1982-01-01

301

Techniques for on-wafer reliability testing for MMICs  

NASA Astrophysics Data System (ADS)

Two Compliant Interconnected Structures (CISs) have been designed and fabricated to enable accelerated DC life tests to be performed at the wafer level. The first CIS was fabricated using Kapton polyimide, the second with borosilicate glass. Both structures are capable of providing bias to the GaAs wafers at 24O C for an extended period of time. Three inch wafers that contain process test characterization vehicles, a distribution amplifier, and three stage amplifiers, were used to demonstrate the feasibility of the techniques.

Saito, Yoshio

1995-09-01

302

Development of thin edgeless silicon pixel sensors on epitaxial wafers  

NASA Astrophysics Data System (ADS)

The paper reports on the development of novel p-on-n thin edgeless planar pixel sensors, compatible with ALICE front-end electronics, fabricated by FBK on epitaxial material. The focus of the activity is the minimization of the material budget required for hybrid pixel detectors. This goal has been addressed in two different stages. In the first one, planar pixel detectors fabricated on epitaxial wafers have been thinned and bonded to the readout chips. The second stage is described by the present paper: the `active edge' concept has been studied for the reduction of the dead area at the periphery of the devices. An overview of the key technological steps and of the electrical characterization of the fabricated sensors is given. In addition, the preliminary results on the static behavior of test sensors after neutron irradiation at different fluences (up to 2.5 1015 1 MeV-neq/cm2) are reported. The results demonstrate that these kinds of devices are a viable solution for the reduction of the material budget while maintaining the typical electrical characteristics expected from radiation silicon sensors.

Boscardin, M.; Bosisio, L.; Contin, G.; Giacomini, G.; Manzari, V.; Orzan, G.; Rashevskaya, I.; Ronchin, S.; Zorzi, N.

2014-09-01

303

Wafer-bonded 2-D CMUT arrays incorporating through-wafer trench-isolated interconnects with a supporting frame.  

PubMed

This paper reports on wafer-bonded, fully populated 2-D capacitive micromachined ultrasonic transducer (CMUT) arrays. To date, no successful through-wafer via fabrication technique has been demonstrated that is compatible with the wafer-bonding method of making CMUT arrays. As an alternative to through-wafer vias, trench isolation with a supporting frame is incorporated into the 2-D arrays to provide through-wafer electrical connections. The CMUT arrays are built on a silicon-on-insulator (SOI) wafer, and all electrical connections to the array elements are brought to the back side of the wafer through the highly conductive silicon substrate. Neighboring array elements are separated by trenches on both the device layer and the bulk silicon. A mesh frame structure, providing mechanical support, is embedded between silicon pillars, which electrically connect to individual elements. We successfully fabricated a 16 x 16-element 2-D CMUT array using wafer bonding with a yield of 100%. Across the array, the pulse-echo amplitude distribution is uniform (rho = 6.6% of the mean amplitude). In one design, we measured a center frequency of 7.6 MHz, a peak-to-peak output pressure of 2.9 MPa at the transducer surface, and a 3-dB fractional bandwidth of 95%. Volumetric ultrasound imaging was demonstrated by chip-to-chip bonding one of the fabricated 2-D arrays to a custom-designed integrated circuit (IC). This study shows that through-wafer trench-isolation with a supporting frame is a viable solution for providing electrical interconnects to CMUT elements and that 2-D arrays fabricated using waferbonding deliver good performance. PMID:19213645

Zhuang, Xuefeng; Wygant, Ira O; Lin, Der-Song; Kupnik, Mario; Oralkan, Omer; Khuri-Yakub, Butrus T

2009-01-01

304

A VLSI architecture for simplified arithmetic Fourier transform algorithm  

NASA Technical Reports Server (NTRS)

The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

1992-01-01

305

Low-temperature full wafer adhesive bonding  

NASA Astrophysics Data System (ADS)

We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 m and 18 m. The tested polymer materials were benzocyclobutene (BCB) from Dow Chemical, a negative photoresist (ULTRA-i 300) and a positive photoresist (S1818) from Shipley, a polyimide (HTR3) from Arch Chemical and two different polyimides (PI2555 and PI2610) from DuPont. The polymer material, the bonding pressure and the pre-curing time and temperature for the polymer significantly influence void formation at the bond interface. High bonding pressure and optimum pre-curing times/temperatures counteract void formation. We present the process parameters to achieve void-free bonding with the BCB coating and with the ULTRA-i 300 photoresist coating as adhesive materials. Excellent void-free and strong bonds have been achieved by using BCB as the bonding material which requires a minimum bonding temperature of 180 C.

Niklaus, Frank; Enoksson, Peter; Klvesten, Edvard; Stemme, Gran

2001-03-01

306

Contactless Characterization of Silicon Wafers Dieter K. Schroder  

E-print Network

strength thin film. The sensor electrode is held above the wafer by a porous ceramic air bearing, which Surface scattering, SEM/EDS, Raman Bulk Impurities Microwave-photoconductance decay, surface photovoltage

Schroder, Dieter K.

307

A ultra-high-vacuum wafer-fusion-bonding system.  

PubMed

The design of heterojunction devices is typically limited by material integration constraints and the energy band alignment. Wafer bonding can be used to integrate material pairs that cannot be epitaxially grown together due to large lattice mismatch. Control of the energy band alignment can be provided by formation of interface dipoles through control of the surface chemistry. We have developed an ultra-high-vacuum system for wafer-fusion-bonding semiconductors with in situ control and measurement of surface properties relevant to interface dipoles. A wafer-fusion-bonding chamber with annealing capabilities was integrated into an ultra-high-vacuum system with a sputtering chamber and an x-ray photoelectron spectroscopy system for preparing and measuring the surface chemistry of wafers prior to bonding. The design of the system along with initial results for the fusion-bonded InGaAs/Si heterojunction is presented. PMID:22667658

McKay, Kyle; Wolter, Scott; Kim, Jungsang

2012-05-01

308

Photoelastic characterization of Si wafers by scanning infrared polariscope  

NASA Astrophysics Data System (ADS)

A small amount of birefringence caused by the photoelastic effect from residual strains, crystal-defects-induced strains, and process-induced strains in Si wafers has been measured by using an improved version of a scanning infrared polariscope (SIRP). The SIRP presented here has high sensitivity sufficient to detect the small amount of strain induced near the wafer-supporting finger by the wafer weight itself. It is found that an anomalous amount of strain is induced by slip-line generation during the thermal process and also that a concentric ring pattern of strain is induced by OSF rings. From these results, it is suggested that SIRP is very useful for Si wafer inspection and Si process evaluation in various phases.

Fukuzawa, M.; Yamada, M.

2001-07-01

309

A ultra-high-vacuum wafer-fusion-bonding system  

NASA Astrophysics Data System (ADS)

The design of heterojunction devices is typically limited by material integration constraints and the energy band alignment. Wafer bonding can be used to integrate material pairs that cannot be epitaxially grown together due to large lattice mismatch. Control of the energy band alignment can be provided by formation of interface dipoles through control of the surface chemistry. We have developed an ultra-high-vacuum system for wafer-fusion-bonding semiconductors with in situ control and measurement of surface properties relevant to interface dipoles. A wafer-fusion-bonding chamber with annealing capabilities was integrated into an ultra-high-vacuum system with a sputtering chamber and an x-ray photoelectron spectroscopy system for preparing and measuring the surface chemistry of wafers prior to bonding. The design of the system along with initial results for the fusion-bonded InGaAs/Si heterojunction is presented.

McKay, Kyle; Wolter, Scott; Kim, Jungsang

2012-05-01

310

Electrochemical method for defect delineation in silicon-on-insulator wafers  

DOEpatents

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

1991-01-01

311

Design and electrical characterization of a novel wafer level package for RF MEMS applications  

Microsoft Academic Search

This paper describes the electrical design and characterization through modeling of a novel wafer level package for RF MEMS applications (RF switches, micro antennas, micro-machined passives, resonators, etc). The package consists of a bottom wafer, which is MEMS wafer and a cap wafer that has a micro-machined cavity for the space necessary for the movement of the MEMS device. The

N. D. Rotaru; C. S. Premachandran; M. K. Iyer

2003-01-01

312

A VLSI Neural Monitoring System With Ultra-Wideband Telemetry for Awake Behaving Subjects.  

PubMed

Long-term monitoring of neuronal activity in awake behaving subjects can provide fundamental information about brain dynamics for neuroscience and neuroengineering applications. Here, we present a miniature, lightweight, and low-power recording system for monitoring neural activity in awake behaving animals. The system integrates two custom designed very-large-scale integrated chips, a neural interface module fabricated in 0.5 ?m complementary metal-oxide semiconductor technology and an ultra-wideband transmitter module fabricated in a 0.5 ?m silicon-on-sapphire (SOS) technology. The system amplifies, filters, digitizes, and transmits 16 channels of neural data at a rate of 1 Mb/s. The entire system, which includes the VLSI circuits, a digital interface board, a battery, and a custom housing, is small and lightweight (24 g) and, thus, can be chronically mounted on small animals. The system consumes 4.8 mA and records continuously for up to 40 h powered by a 3.7-V, 200-mAh rechargeable lithium-ion battery. Experimental benchtop characterizations as well as in vivo multichannel neural recordings from awake behaving rats are presented here. PMID:23851199

Greenwald, E; Mollazadeh, M; Hu, C; Wei Tang; Culurciello, E; Thakor, V

2011-04-01

313

Novel on chip-interconnection structures for giga-scale integration VLSI ICS  

NASA Astrophysics Data System (ADS)

Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

Nelakuditi, Usha R.; Reddy, S. N.

2013-01-01

314

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

315

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

316

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays  

NASA Astrophysics Data System (ADS)

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 ?m is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 ?m 25 ?m that are arranged on read-out-wafers in arrays with 320 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Bjrn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Gran; Niklaus, Frank

2013-09-01

317

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.  

PubMed

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging. PMID:22966554

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

318

Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons  

NASA Technical Reports Server (NTRS)

The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

1986-01-01

319

Voltage and Timing Adaptation for Variation and Aging Tolerance in Nanometer VLSI Circuits  

E-print Network

Process variations and circuit aging continue to be main challenges to the power-efficiency of VLSI circuits, as considerable power budget must be allocated at design time to mitigate timing variations. Modern designs incorporate adaptive techniques...

Shim, Kyu-Nam 1978-

2012-09-10

320

Parallel VLSI architecture emulation and the organization of APSA/MPP  

NASA Technical Reports Server (NTRS)

The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.

Odonnell, John T.

1987-01-01

321

VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number  

NASA Technical Reports Server (NTRS)

Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

1984-01-01

322

A VLSI architecture for fast computation of third-order cumulants for two-dimensional signals  

Microsoft Academic Search

Higher-order statistics or cumulants, and their associated Fourier transforms, have been established as powerful analytical tools in modern signal processing. To achieve real-time performance in estimating cumulants directly from the incoming time-series data, it is necessary to design a VLSI implementable parallel architecture that speeds up the estimation process. This paper presents a computationally efficient VLSI architecture for computing third-order

Z. H. Musallam; R. E. Ahmed; S. A. Alshebeili

2000-01-01

323

Nanoscale Transistors: Advanced VLSI Devices (Introductory Lecture)  

NSDL National Science Digital Library

Contributed by Mark Lundstrom of Purdue University, this introductory lecture to nanoscale transistors is available both as a Flash video with audio and as presentation slides in PDF form (the links to these are on the right hand side of the page). The lecture introduces the course, which "examines the device physics of advanced transistors and the process, device, circuit, and systems considerations that enter into the development of new integrated circuit technologies." This is a helpful resource for nanotechnology instructors looking to introduce the concept of nanoscale transistors into their classrooms. For more from this course (lectures, assignments, etc.) click the Course Information Website link.

Lundstrom, Mark

324

Development of a wafer positioning system for the Sandia extreme ultraviolet lithography tool  

SciTech Connect

A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

Wronosky, J.B.; Smith, T.G.; Darnold, J.R.

1995-12-01

325

Development of a Wafer Positioning System for the Sandia Extreme Ultraviolet Lithography Tool  

NASA Technical Reports Server (NTRS)

A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

Wronosky, John B.; Smith, Tony G.; Darnold, Joel R.

1996-01-01

326

VLSI processor with a configurable processing element array for balanced feature extraction in high-resolution images  

NASA Astrophysics Data System (ADS)

A VLSI processor employing a configurable processing element array (PEA) is developed for a newly proposed balanced feature extraction algorithm. In the algorithm, the input image is divided into square regions and the number of features is determined by noise effect analysis in each region. Regions of different sizes are used according to the resolutions and contents of input images. Therefore, inside the PEA, processing elements are hierarchically grouped for feature extraction in regions of different sizes. A proof-of-concept chip is fabricated using a 0.18 m CMOS technology with a 32 32 PEA. From measurement results, a speed of 7.5 kfps is achieved for feature extraction in 128 128 pixel regions when operating the chip at 45 MHz, and a speed of 55 fps is also achieved for feature extraction in 1920 1080 pixel images.

Zhu, Hongbo; Shibata, Tadashi

2014-01-01

327

Design and development of wafer-level short wave infrared micro-camera  

NASA Astrophysics Data System (ADS)

Low cost IR Sensors are needed for a variety of Defense and Commercial Applications as low cost imagers for various Army and Marine missions. SiGe based IR Focal Planes offers a low cost alternative for developing wafer-level shortwave infrared micro-camera that will not require any cooling and can operate in the Visible-NIR band. The attractive features of SiGe based IRFPA's will take advantage of Silicon based technology, that promises small feature size and compatibility with the low power silicon CMOS circuits for signal processing. SiGe technology offers a low cost alternative for developing Visible-NIR sensors that will not require any cooling and can operate from 0.4- 1.7 microns. The attractive features of SiGe based IRFPA's will take advantage of Silicon based technology that can be processed on 12-inch silicon substrates, that can promise small feature size and compatibility with the Silicon CMOS circuit for signal processing. In this paper, we will discuss the design and development of Wafer-Level Short Wave Infrared (SWIR) Micro-Camera. We will discuss manufacturing approaches and sensor configurations for short wave infrared (SWIR) focal plane arrays (FPAs) that significantly reduce the cost of SWIR FPA packaging, optics and integration into micro-systems.

Sood, Ashok K.; Richwine, Robert A.; Pethuraja, Gopal; Puri, Yash R.; Lee, Je-Ung; Haldar, Pradeep; Dhar, Nibir K.

2013-06-01

328

Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease  

PubMed Central

The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365 faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the HodgkinHuxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365 real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems. PMID:25538613

Niu, Chuanxin M.; Nandyala, Sirish K.; Sanger, Terence D.

2014-01-01

329

Durham Music Technology: Activity Report  

Microsoft Academic Search

Durham Music Technology is an ongoing collaboration between the Concurrent Digital Signal Processing group in the School of Engineering and the Electroacoustic Music Studio in the Department of Music at Durham University. In this activity report, we present current research interests in multi-processor architectures for real-time synthesis, VLSI implementation of synthesis algorithms, sound analysis-resynthesis, and works in the electroacoustic studio.

Takebumi ITAGAKI; Simon JOHNSON; Peter D. MANNING; Douglas J. E. NUNN; Desmond K. PHILLIPS; Alan PURVIS; Jonathan R. SPANIER

330

Low-temperature titanium-based wafer bonding  

NASA Astrophysics Data System (ADS)

This thesis presents novel methods of metal-based wafer bonding at back-end-of-the-line (BEOL) compatible conditions (?450C). For the first time to our knowledge, 200 mm diameter oxidized Si wafers are bonded with prime Si wafers using 10-300 nm thick Ti as bonding intermediate at 300-450C. Nearly void-free bonding with strong mechanical integrity has been confirmed. Moreover, microcavity formation has been demonstrated by bonding of patterned wafers. Both Rutherford backscattering spectroscopy (RBS) and Auger electron spectroscopy (AES) show clear evidence of Si and Ti interdiffusion, whereas high-resolution transmission electron microscopy (HRTEM) reveals an approximately 8 nm thick amorphous layer at the bonding interface. Those results indicate that the strong adhesion at the Ti/Si bonding interface is attributed to a solid-state amorphization (SSA) assisted by interdiffusion. A key effort is devoted to fundamental investigation of low-temperature transition metal(TM)/Si-based wafer bonding. With the extensive work on Ti/Si system, additional experiments are performed with six other TM/Si systems, namely Ni/Si, Co/Si, Pd/Si, Hf/Si, Au/Si and Ta/Si. The results indicate there are two principal requirements for TM/Si-based wafer bonding: (1) intimate contact (able to break through kinetic barriers), and (2) adequate chemical bonding. Three kinetic barriers addressed in this thesis are: (1) enclosed microvoids due to surface roughness, (2) gas molecules at the bonding interface, and (3) interfacial oxides. Presence of these barriers can prevent formation of intimate contact, consequently retarding or even blocking interfacial interactions for chemical bonding. The unique properties of Group IVA metals (e.g., Ti and Hf) to reduce native SiO2 on Si surfaces and their exceptionally large solid solubility for O2 and N2, help overcome those issues. Once kinetic barriers are surmounted, the key for strong metal/Si-based wafer bonding is formation of chemical bonds, aided primarily by interdiffusion. According to their principal bonding mechanisms, the examined seven TM/Si-based wafer bonding can be divided into three groups: (1) silicidation bonding (Ni/Si, Co/Si and Pd/Si), (2) solid-state amorphization bonding (Ti/Si and Hf/Si), and (3) eutectic bonding (Au/Si). One of the major thesis contributions is the development and identification of a new type of metal-based wafer bonding, i.e. SSA bonding.

Yu, Jian

331

A novel VLSI processor for high-rate, high resolution spectroscopy  

NASA Astrophysics Data System (ADS)

A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 ?s) quasi-optimal weight function, an ultra-low-level energy discrimination (150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

Pullia, A.; Fiorini, C.; Gatti, E.; Longoni, A.; Buttler, W.

2000-01-01

332

Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers  

NASA Technical Reports Server (NTRS)

An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

Simons, Rainee N.

2004-01-01

333

Simulation-based optimization of dispatching rules for semiconductor wafer fabrication system scheduling by the response surface methodology  

Microsoft Academic Search

Scheduling of a semiconductor wafer fabrication system (SWFS) is complicated due to its re-entrant product flow, high uncertainties\\u000a in operations, and rapidly changing products and technologies; thus dispatching rules have been widely used for real-time\\u000a scheduling because they can provide a very quick and pretty good solution. However, deciding how to select appropriate rules\\u000a is very difficult and seldom tackled.

Huai Zhang; Zhibin Jiang; Chengtao Guo

2009-01-01

334

VLSI-based Video Event Triggering for Image Data Compression  

NASA Technical Reports Server (NTRS)

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

Williams, Glenn L.

1994-01-01

335

A novel VLSI architecture for pixel purity index algorithm  

NASA Astrophysics Data System (ADS)

The Pixel Purity Index (PPI) algorithm is one of the most successful algorithms for hyperspectral image endmembers extraction. But it has high computational complexity so it is hard to meet the real-time processing demands of some onboard application. In this paper, we present a novel Very-Large-Scale Integration (VLSI) architecture for PPI algorithm to meet the on-board demands. With parallelism and improved I/O communication strategy, our implementation is significantly time saving than other architectures in the same hardware resources. We evaluate our implementation using the well-known "Cuprite" scene and assess endmembers signature purity using the U.S. Geological Survey (USGS) library. It demonstrates that our hardware implementation can get endmembers in less processing time to meet the onboard demands.

Yi, Fang; Guo, Jie; Li, Yunsong; Huang, Bormin

2013-09-01

336

Efficient VLSI Architecture for Training Radial Basis Function Networks  

PubMed Central

This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

Fan, Zhe-Cheng; Hwang, Wen-Jyi

2013-01-01

337

Aspects of full-custom VLSI microprocessor design and implementation  

SciTech Connect

There is a broad spectrum of design styles that have proven successful for the construction of VLSI circuits and systems. Semi-custom to full-custom design styles offer a wide range of resulting performance, expected turn-around time, and required design effort. Implementation alternatives, such as replacing dynamic memory for static memory to implement a denser on-chip memory, also exist at all levels of design hierarchy. To make the best use of scarce resources on a single chip microprocessor and to make the emerging CAD tools truly useful, alternatives in the implementation of a microprocessor must be carefully evaluated. The research reported in this thesis focuses on issues concerning these alternatives, especially in the areas of on-chip memory design and automated control logic design.

Lee, Daebum.

1989-01-01

338

Event-driven neural integration and synchronicity in analog VLSI.  

PubMed

Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics. PMID:23366007

Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

2012-01-01

339

Nano-particle laser removal from silicon wafers  

NASA Astrophysics Data System (ADS)

A laser shock cleaning (LSC) technique as a new dry cleaning methodology has been applied to remove micro and nano-scale inorganic particulate contaminants. Shock wave is generated in the air just above the wafer surface by focusing intensive laser beam. The velocity of shock wave can be controlled to 10,000 m/sec. The sub-micron sized silica and alumina particles are attempted to remove from bare silicon wafer surfaces. More than 95% of removal efficiency of the both particles are carried out by the laser-induced airborne shock waves. In the final, a removal of nano-scale slurry particles from real patterned wafers are successfully demonstrated by LSC after chemical-mechanical polishing (CMP) process.

Lee, J. M.; Cho, S. H.; Kim, T. H.; Park, Jin-Goo; Busnaina, Ahmed A.

2003-11-01

340

Characterizing SOI Wafers By Use Of AOTF-PHI  

NASA Technical Reports Server (NTRS)

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

341

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers  

NASA Technical Reports Server (NTRS)

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

342

Multichip module technology at MCC  

Microsoft Academic Search

Wafer-scale interconnect problems and technological and cost objectives for multichip modules are examined. The performance potential of multichip packaging is discussed. Cu polyimide interconnect technology is discussed. Some problems and limitations in multichip packaging are described. Module connectors and cooling technology are discussed

Dennis Herrell

1990-01-01

343

A Review of 3-D Packaging Technology  

Microsoft Academic Search

This paper reviews the state-of-the-art in three- dimensional (3-D) packaging technology for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in details. Technical issues such as silicon efficiency, complexity,

Said F. Al-sarawi; Derek Abbott; Paul D. Franzon

1998-01-01

344

Wafer and reticle positioning system for the Extreme Ultraviolet Lithography Engineering Test Stand  

SciTech Connect

This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EUVL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100nm. EUVL research and development includes development of capabilities for demonstrating key EUV technologies. The ETS is under development at the EUV Virtual National Laboratory, to demonstrate EUV full-field imaging and provide data that supports production-tool development. The stages and their associated metrology operated in a vacuum environment and must meet stringent outgassing specifications. A tight tolerance is placed on the stage tracking performance to minimize image distortion and provide high position repeatability. The wafer must track the reticle with less than {+-}3nm of position error and jitter must not exceed 10nm rms. To meet these performance requirements, magnetically levitated positioning stages utilizing a system of sophisticated control electronics will be used. System modeling and experimentation have contributed to the development of the positioning system and results indicate that desired ETS performance is achievable.

WRONOSKY,JOHN B.; SMITH,TONY G.; CRAIG,MARCUS J.; STURGIS,BEVERLY R.; DARNOLD,JOEL R.; WERLING,DAVID K.; KINCY,MARK A.; TICHENOR,DANIEL A.; WILLIAMS,MARK E.; BISCHOFF,PAUL

2000-01-27

345

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking  

PubMed Central

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 m larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 m CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 m and 0.5 m, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-01-01

346

An application of selective electrochemical wafer thinning for silicon characterization  

SciTech Connect

A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

1990-01-01

347

Face-to-face transfer of wafer-scale graphene films.  

PubMed

Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene. PMID:24336218

Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

2014-01-01

348

Face-to-face transfer of wafer-scale graphene films  

NASA Astrophysics Data System (ADS)

Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

2014-01-01

349

A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion  

E-print Network

155 A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion, University of Maryland, College Park, MD 20742, USA ABSTRACT A low-power parallel VLSI structure for DCT for DCT). The property of BCR is also used to compute the DCT/IDCT through the down-sampled even and odd

Liu, K. J. Ray

350

Influence of gas composition on wafer temperature in a tungsten chemical vapor deposition reactor: Experimental measurements, model  

E-print Network

include a gas phase transport submodel and a wafer submodel to account for the interactions between/wafer boundary condition solved simultaneously with the wafer dy- namical submodel can provide insightful

Rubloff, Gary W.

351

Neural Networks In High Energy Physics Royal Institute of Technology  

NSDL National Science Digital Library

Neural Networks in High Energy Physics Royal Institute of Technology, Stockholm, Sweden. From the Dept. of Physics-Frescati comes this comprehensive list of references, recent developments in the field, upcoming conferences, etc. Of most general interest is the extensive list of commercial neural network hardware, including VLSI chips, PC accelerator cards, and neurocomputers.

352

Modeling modern bipolar technologies to insure design for manufacturability  

Microsoft Academic Search

A description is given of an integrated empirical modeling methodology which has been successfully applied in modeling the ASPECT process (Advanced Single Poly Emitter Coupled Technology) to ensure manufacturable circuit designs. The accuracy which has been achieved with this degree of modeling has contributed significantly to realizing `right the first time' designs on a number of standard cell VLSI ECL

James Lyle Bouknight; Steven M. Leibiger; Kyle S. Yakabu; Hem K. Hingarh

1988-01-01

353

Wafer bonding with low-temperature-grown (Ga,P) as an adhesive material  

NASA Astrophysics Data System (ADS)

Amorphous and polycrystalline (Ga,P) grown with the molecular beam epitaxy technique at low temperatures were developed as adhesive materials for wafer bonding technology. The microstructure and V/III incorporation ratio in (Ga,P) were studied with transmission electron microscopy (TEM) and Auger electron spectroscopy. The crystallinity of the low-temperature-grown (LTG) (Ga,P), amorphous or polycrystalline, is controlled by the phosphorus overpressure during growth. The n-type GaP substrates, each with LTG (Ga,P) material on top, were strongly bonded face-to-face at 600 C for several hours. TEM shows that along the bonded interface recrystallization of the (Ga,P) layer has taken place during high-temperature annealing and hence helped the two wafers bond together. In comparison, direct wafer bonding of GaP substrates without LTG (Ga,P) requires high bonding temperatures above 750 C. The current-voltage (I-V) characteristics of the bonded samples were also investigated. Samples bonded with Ga-rich polycrystalline (Ga,P) exhibit linear I-V dependence across the bonded interface. In contrast, samples bonded with P-rich amorphous (Ga,P) show back-to-back Schottky I-V characteristics with a breakdown of about 11-13 V. The two bonded interfaces show great similarity in microstructure except that gallium clusters are present only at the interface of the sample bonded with Ga-rich polycrystalline (Ga,P). We attribute the linear ohmic I-V dependence to the presence of Ga-clusters.

Chang, K. L.; Pickrell, G. W.; Cheng, K. Y.; Hsieh, K. C.

2004-07-01

354

Wafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition  

E-print Network

oxide. (b) Optical microscopy image showing the edge of a bilayer graphene film. (c) AFM imageWafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition Seunghyun Lee gap opening in bilayer graphene opens a new door for making semiconducting graphene without aggressive

Zhong, Zhaohui

355

Wafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition  

Microsoft Academic Search

The discovery of electric field induced bandgap opening in bilayer graphene opens new door for making semiconducting graphene without aggressive size scaling or using expensive substrates. However, bilayer graphene samples have been limited to um size scale thus far, and synthesis of wafer scale bilayer graphene posts tremendous challenge. Here we report homogeneous bilayer graphene films over at least 2

Seunghyun Lee; Kyunghoon Lee; Zhaohui Zhong

2010-01-01

356

Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence  

E-print Network

) Crystal phase and growth orientation dependence of GaAs nanowires on NixGay seeds via vaporImaging crystal orientations in multicrystalline silicon wafers via photoluminescence H. C. Sio, Z-mediated nonclassical crystal growth of sodium fluorosilicate nanowires and nanoplates AIP Advances 1, 042165 (2011

357

Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements  

E-print Network

effects on the manufacturing processes. In addition, vibration analysis of wiresaw can leadVibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements I. Kao (PI), S the yield per crystal and to reduce the cost. In this paper, the vibration model of wiresaw system

Kao, Imin

358

THIN GLASS OPTIC AND SILICON WAFER DEFORMATION AND KINEMATIC CONSTRAINT  

Microsoft Academic Search

To meet these assembly and metrology challenges, we present how thin materials such as silicon and glass wafers deform and how they can be constrained to minimize these effects. Both analytical calculations and finite element analyses (FEA) are utilized to understand the effects of gravity on foil deformation while varying parameters such as foil thickness and angle of inclination. Friction

Craig R. Forest; Mireille Akilian; Guillaume Vincent; Alexandre Lamure; Mark L. Schattenburg

2003-01-01

359

Reducing Cycle Time at an Ibm Wafer Fabrication Facility  

Microsoft Academic Search

In 1991, IBM San Jose decided to produce and sell magnetic heads for computer disk drives on the open market to original equipment manufacturers. However, as IBM's wafer fabrication facility increased the number of products it manufactured, its manufacturing cycle time lengthened. Since cycle time is important in competing in the open market, IBM San Jose formed a study team

Lieven DEMEESTER; C. S. Tang

1996-01-01

360

Crack propagation and fracture in silicon wafers under thermal stress  

PubMed Central

The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M. Reyes; Baumbach, Tilo; Tanner, Brian K.

2013-01-01

361

Scatterometry on pelliclized masks: an option for wafer fabs  

NASA Astrophysics Data System (ADS)

Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

2007-03-01

362

Acoustic emission monitoring during laser shock cleaning of silicon wafers  

Microsoft Academic Search

A laser shock cleaning is a new dry cleaning methodology for the effective removal of submicron sized particles from solid surfaces. This technique uses a plasma shock wave produced by laser-induced air breakdown, which has applied to remove nano-scale silica particles from silicon wafer surfaces in this work. In order to characterize the laser shock cleaning process, acoustic waves generated

T. Kim; J. M. Lee; S. H. Cho; T. H. Kim

2005-01-01

363

Nanomechanical optical devices fabricated with aligned wafer bonding  

Microsoft Academic Search

This paper reports on a new method for making some types of integrated optical nanomechanical devices. Intensity modulators as well as phase modulators were fabricated using several silicon micromachining techniques, including chemical mechanical polishing and aligned wafer bonding. This new method enables batch fabrication of the nanomechanical optical devices, and enhances their performance

C. Gui; G. J. Veldhuis; T. M. Koster; P. V. Lambeck; J. W. Berenschot; J. G. E. Gardeniers; M. Elwenspoek

1998-01-01

364

Localized induction heating solder bonding for wafer level MEMS packaging  

Microsoft Academic Search

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 C during bonding, thus

Hsueh-An Yang; Mingching Wu; Weileun Fang

2005-01-01

365

Crack propagation and fracture in silicon wafers under thermal stress.  

PubMed

The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M Reyes; Baumbach, Tilo; Tanner, Brian K

2013-08-01

366

Steel Bridge Fatigue Crack Detection with Piezoelectric Wafer Active Sensors  

E-print Network

Steel Bridge Fatigue Crack Detection with Piezoelectric Wafer Active Sensors Lingyu Yu1 , Victor acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since primarily on history of past performance. In this study, extensive laboratory investigation is performed

Giurgiutiu, Victor

367

Ultraviolet laser removal of small metallic particles from silicon wafers  

Microsoft Academic Search

Laser removal of small 1?m sized copper, gold and tungsten particles from silicon wafer surfaces was carried out using ultraviolet radiation at 266nm generated by Nd:YAG harmonic generation. Successful removal of both copper and gold particles from the surface was achieved whereas tungsten particles proved to be difficult to remove. The cleaning efficiency was increased with an increase of laser

C. Curran; J. M. Lee; K. G. Watkins

2002-01-01

368

Characterization, modeling, and design of an electrostatic chuck with improved wafer temperature uniformity  

NASA Astrophysics Data System (ADS)

The resulting temperature distribution of a silicon wafer held by an electrostatic chuck (ESC) in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor is characterized and modeled. The effects of the clamping voltage VESC, pressure between the ESC and wafer PHe, and the surface finish and pattern on the ESC are investigated. Heat transfer coefficients between the wafer and various ESCs are determined experimentally. A model is developed to predict the temperature distribution at the surface of the wafer, and used to explain the experimentally observed temperature variations both within wafer and between different chucks. The model is then used to aid in the design of an ESC which provides improved temperature uniformity at the wafer surface. The results of this study indicate: (a) the thermal resistances across the interface between the wafer and ESC control both the absolute wafer temperature and the wafer temperature uniformity; (b) the surface roughness of the ESC and the size of the ``contact'' regions are major design factors controlling the absolute temperature of the waferthe temperature can be adjusted by varying the value of VESC and fine tuned by adjusting the value of PHe; (c) the nonuniform temperature distribution across the wafer surface is dictated by the surface pattern on the ESC, the variation in surface roughness, and the size of the ESC relative to the wafer; (d) wafer temperature variations from chuck to chuck are reduced by controlling the surface finish of the ESC and by ensuring that PHe is a dominant heat transfer mechanism; and (e) maximum uniformity in the temperature of the wafer is obtained when the radius of the ESC is matched as closely as possible to that of the wafer. We have shown that numerical heat transfer models can be used to optimize the geometry of the ESC to provide a uniform distribution of temperature across the surface of the wafer.

Olson, Kurt A.; Kotecki, David E.; Ricci, Anthony J.; Lassig, Stephan E.; Husain, Anwar

1995-02-01

369

Fine Keyed Alignment and Bonding for Wafer-Level 3D ICs  

Microsoft Academic Search

Precise wafer-to-wafer alignment accuracy is crucial to interconnecting circuits on different wafers in three dimensional integrated circuits. We discuss the use of fabricated structures on wafer surfaces to mechanically achieve higher alignment accuracy than can be achieved with our existing (baseline) alignment protocol. The keyed alignment structures rely on structures with tapered side-walls that can slide into each after two

Sang Hwui Lee; Frank Niklaus; J. Jay McMahon; Jian Yu; Ravi J. Kumar; Hui-feng Li; Ronald J. Gutmann; Timothy S. Cale; J.-Q. Lu

370

Damascene patterned metal/adhesive wafer bonding for three-dimensional integration  

NASA Astrophysics Data System (ADS)

Wafer bonding of damascene patterned metal/adhesive surfaces is explored for a new three-dimensional (3D) integration technology platform. By bonding a pair of damascene patterned metal/adhesive layers, high density micron-sized vias can be formed for interconnection of fully fabricated integrated circuit (IC) dies at the wafer-level. Such via dimensions increase the areal interconnect density by at least two orders of magnitude over current package and die-stacking approaches to 3D integration. The adhesive field-dielectric produces a high critical adhesion energy bond and has the potential to produce void-free bonded interfaces. This new technology platform has been demonstrated by fabricating and characterizing inter-wafer via-chains on 200 mm diameter Si wafers. Copper and partially cured divinylsiloxane bis-benzocyclobutene (BCB) are selected as the metal and adhesive, respectively, and unit processes for this demonstration are described. Typical alignment tolerance is 2 mum, and baseline bonding conditions include vacuum of 5x10-4 mbar, bonding force of 10 kN, and two step bonding temperature of 250C for 60 min followed by 350C for 60 min. Integration issues associated with the damascene patterning and the wafer bonding processes are discussed, particularly the resulting topography of damascene patterned Cu/BCB. Cross-sectional investigation of bonded and annealed inter-wafer interconnections provides insight into the Cu-Cu and BCB-BCB bonding interfaces. Inter-wafer specific contact resistance is measured to be on the order of 10-7 O-cm 2 for these via-chains. Several material characterization techniques have been explored to evaluate partially cured BCB as an adhesive field-dielectric. To investigate the critical adhesion energy, Gc, four-point bending is utilized to compare surfaces bonded after chemical-mechanical planarization (CMP) and various post-CMP treatments. The Gc of bonded 50% partially cured BCB is measured to be in the range of 32--44 J/m2. The elastic modulus of the BCB is investigated by monitoring film stress behavior for temperatures just below that needed for crosslinking (i.e. the temperature where BCB-BCB bonding begins). The film-stress temperature dependence is then used as an indicator for phase transitions in the BCB that affect elastic modulus. Surface analysis techniques are used to explore the surface chemistry of the BCB and measure its surface energy over the temperature range required for bonding. The surface energy of partially cured BCB at both 50 and 90% crosslinking is measured to decrease by 30% when the temperature is raised from 35C to 230C. The surface analysis and mechanical properties studies provide insight into the capability of BCB to close gaps when in contact during bonding, a necessary condition for forming void-free bonding interfaces. One important aspect for implementing wafer-level 3D integration is the ability of a technology platform to accommodate topography on fully fabricated wafers. The aforementioned metal/adhesive 3D platform has strict requirements in this regard if void-free surfaces are to be attained. A bonding protocol that eliminates the copper and tantalum interconnect structure is utilized to investigate the deformation capability of partially cured BCB during bonding. The results indicate that the defect density of such BCB-BCB bonds depends on material parameters such as the degree of crosslinking and surface energy, the pitch of the features, and the depth of the topography to be accommodated. For 70--90% crosslinked BCB, accommodation was observed for lines 120 nm deep and 100 mum in pitch. Furthermore, 70--90% crosslinked BCB lines with pitch 1 mum and depth 12 nm were accommodated during bonding. When the BCB crosslinking is reduced to 50%, additional accommodation is observed. In such cases, lines with pitch 100 mum and depth 500 nm, and those with pitch 1 mum and depth 50 nm were accommodated. Additional work has shown that accommodation of some topography is possible even with zero down-force during bonding. Th

McMahon, J. Jay

371

Formation of Surface Microcrack for Separation of Nonmetallic Wafers Into Chips  

Microsoft Academic Search

High quality separation of wafers into chips is important to the electronic industry. Since chips often operate at a high power level ~Bar-Cohen @1#, Suhir @2#! wafers with high quality edges are required. Most of the defects, e.g., microcracks, dislocations, etc., form during cutting. During heating, the defects at the edge of a wafer ~with a size larger than some

T. Elperin; A. Kornilov; G. Rudin

2009-01-01

372

System analysis of wafer logistics information management for IC packaging foundry in Taiwan  

Microsoft Academic Search

The IC manufacturing related business had been remarkably developed for the past decade in Taiwan. In addition to the well-known wafer fabrication industries, the IC design house and IC packaging\\/testing business together form a contiguous supply chain form material to system in Taiwan. Logistics and information management of the wafer is the key linkage in the wafer foundry process. The

Yu-Chuan Liu

2008-01-01

373

Antenna technologies for 60 GHz applications  

Microsoft Academic Search

In this paper, the wafer transfer technology (WTT) and the low-temperature co-fired ceramic (LTCC) technology are employed for 60 GHz antenna designs. A coplanar waveguide (CPW) fed coplanar strip (CPS) dipole antenna using the WTT technology is presented. Meanwhile, two antenna arrays using the LTCC technology are reported.

Yong-Xin Guo; Siew Bee Yeap; Zhi Ning Chen

2009-01-01

374

Optically augmented 3-D computer: technology and architecture  

Microsoft Academic Search

In order to achieve high performance parallel computing in terms of bandwidth versus power consumption and volume, denser and faster means of implementing interconnections while minimizing power and crosstalk are required. Global interconnections can be implemented using free-space interconnect technology and can be coupled to the wafer to wafer connection system developed at Hughes Research laboratories to obtain an optoelectronic

Philippe J. Marchand; Ashok V. Krishnamoorthy; S. C. Esener; Uzi Efron

1994-01-01

375

Wafer bonding process for building MEMS devices  

NASA Astrophysics Data System (ADS)

The technology for the measurement of colour rendering and colour quality is not new, but many parameters related to this issue are currently changing. A number of standard methods were developed and are used by different specialty areas of the lighting industry. CIE 13.3 has been the accepted standard implemented by many users and used for many years. Light-emitting Diode (LED) technology moves at a rapid pace and, as this lighting source finds wider acceptance, it appears that traditional colour-rendering measurement methods produce inconsistent results. Practical application of various types of LEDs yielded results that challenged conventional thinking regarding colour measurement of light sources. Recent studies have shown that the anatomy and physiology of the human eye is more complex than formerly accepted. Therefore, the development of updated measurement methodology also forces a fresh look at functioning and colour perception of the human eye, especially with regard to LEDs. This paper includes a short description of the history and need for the measurement of colour rendering. Some of the traditional measurement methods are presented and inadequacies are discussed. The latest discoveries regarding the functioning of the human eye and the perception of colour, especially when LEDs are used as light sources, are discussed. The unique properties of LEDs when used in practical applications such as luminaires are highlighted.

Pabo, Eric F.; Meiler, Josef; Matthias, Thorsten

2014-06-01

376

CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties  

PubMed Central

This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Youngs modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Eulers beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Youngs modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 ?m standard CMOS process, and the experimental results refer to Osterbergs work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive. PMID:23235449

Chuang, Wan-Chun; Hu, Yuh-Chung; Chang, Pei-Zen

2012-01-01

377

Modelling the reaction behavior in reactive multilayer systems on substrates used for wafer bonding  

NASA Astrophysics Data System (ADS)

Exothermic self-propagating high-temperature synthesis of intermetallic compounds attain increasing interest in the field of wafer bonding in microelectronics and microsystems technology due to local heat generation. Numerical models of self-sustaining reactions in thin multilayer films can be used to predict velocity and shape of the reaction front. This work deals with heat losses to various substrate materials and material compounds used for wafer bonding as well as the prediction of minimal numbers of bilayers required for a self-propagating reaction front. We introduced a cylindrically symmetric finite element approach. In addition to that, the effect of temperature-dependent specific heat capacities was investigated. Numerical computations were performed for Pd/Al multilayers and are compared to experimental data. It was found that the developed formalism is suitable to determine the mutual influence of heat losses and reaction properties. Furthermore, it was demonstrated that minimal numbers of bilayers can be determined more precisely by including temperature-dependent specific heat capacities.

Masser, Robin; Braeuer, Joerg; Gessner, Thomas

2014-06-01

378

Elastic Softening of Surface Acoustic Wave Caused by Vacancy Orbital in Silicon Wafer  

NASA Astrophysics Data System (ADS)

We have performed surface acoustic wave (SAW) measurements to examine vacancies in a surface layer of a boron-doped silicon wafer currently used in semiconductor industry. A SAW with a frequency of fs = 517 MHz was optimally generated by an interdigital transducer with a comb gap of w=2.5 m on a piezoelectric ZnO film deposited on the (001) silicon surface. The SAW propagating along the [100] axis with a velocity of vtext{s}=4.967 km/s is in agreement with the Rayleigh wave, which shows an ellipsoidal trajectory motion in the displacement components ux and uz within a penetration depth of ?p = 3.5 m. The elastic constant Cs of the SAW revealed the softening of ?Cs/Cs = 1.9 10?4 below 2 K down to 23 mK. Applied magnetic fields of up to 2 T completely suppress the softening. The quadrupole susceptibilities based on the coupling between the electric quadrupoles Ou, Ov, and Ozx of the vacancy orbital consisting of ?8?7 states and the symmetry strains ?u, ?v, and ?zx associated with the SAW account for the softening and its field dependence on Cs. We deduced a low vacancy concentration N = 3.1 1012/cm3 in the surface layer within ?p = 3.5 m of the silicon wafer. This result promises an innovative technology for vacancy evaluation in the fabrication of high-density semiconductor devices in industry.

Mitsumoto, Keisuke; Akatsu, Mitsuhiro; Baba, Shotaro; Takasu, Rie; Nemoto, Yuichi; Goto, Terutaka; Yamada-Kaneta, Hiroshi; Furumura, Yuji; Saito, Hiroyuki; Kashima, Kazuhiko; Saito, Yoshihiko

2014-03-01

379

Wafer level fabrication of single cell dispenser chips with integrated electrodes for particle detection  

NASA Astrophysics Data System (ADS)

This work presents the microfabrication and experimental evaluation of a dispenser chip, designed for isolation and printing of single cells by combining impedance sensing and drop-on-demand dispensing. The dispenser chip features 50? ?55?m (width height) microchannels, a droplet generator and microelectrodes for impedance measurements. The chip is fabricated by sandwiching a dry film photopolymer (TMMF) between a silicon and a Pyrex wafer. TMMF has been used to define microfluidic channels, to serve as low temperature (75?C) bonding adhesive and as etch mask during 300?m deep HF etching of the Pyrex wafer. Due to the novel fabrication technology involving the dry film resist, it became possible to fabricate facing electrodes at the top and bottom of the channel and to apply electrical impedance sensing for particle detection with improved performance. The presented microchip is capable of dispensing liquid and detecting microparticles via impedance measurement. Single polystyrene particles of 10?m size could be detected with a mean signal amplitude of 0.39? ?0.13?V (n=439 ) at particle velocities of up to 9.6?mm?s?1 inside the chip.

Schoendube, Jonas; Yusof, Azmi; Kalkandjiev, Kiril; Zengerle, Roland; Koltay, Peter

2015-02-01

380

Liquid crystal lens auto-focus extended to optical image stabilization for wafer level camera  

NASA Astrophysics Data System (ADS)

Miniaturization and reduction of production cost of optical components in consumer electronics leads to wafer level optics. This miniaturization, associated with the increase of CMOS sensors resolution, generates new needs such as auto-focus (AF) and optical image stabilization (OIS) in order to reduce the blurring caused by hand jitter. In this paper, we propose a wafer scale technology to perform AF and introduce OIS functionality. We managed to create a tunable focal lens by filling with nematic liquid crystal (LC) an assembly of two glass substrates coated with circular hole patterned chromium electrodes and resistive transparent layers of Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT-PSS). When a voltage with tunable magnitude and frequency is applied to the electrodes, the resistive layer creates a non-uniform voltage distribution from the edge to the center of the aperture which depends on electrical parameters of PEDOT-PSS and LC. The resultant electric field generates a gradient orientation of the nematic director which allows to focus light polarized along the director. It is also possible to shift the optical axis of the lens by dividing the hole patterned electrodes in several sectors and to apply different voltages on each sectors. The principle of the shifting effect has been demonstrated but its magnitude has to be increased by using more adapted electrode structure to ensure the OIS function. Finally, we characterised the dynamical behaviour of the lens in both focus and shifting modes.

Fraval, Nicolas; Berier, Frdric

2011-03-01

381

A hermetic and room-temperature wafer bonding technique based on integrated reactive multilayer systems  

NASA Astrophysics Data System (ADS)

This paper focuses on direct deposition and patterning of reactive and nano-scale multilayer films at wafer level. These multilayer structures are called integrated reactive material systems (iRMS). In contrast to the typically used nickel (Ni)/ aluminum (Al) systems, in this work we needed to have our total multilayer film thicknesses smaller than 2.5?m to reduce stress within the multilayer as well as deposition costs. Thus, we introduced new high energetic iRMS. These films were deposited by using alternating magnetron sputtering from high purity Al- and palladium (Pd)-targets to obtain films with a defined Al:Pd atomic ratio. In this paper, we present the result for reaction characteristics and reaction velocities which were up to 72.5?m?s?1 for bond frames with lateral dimensions as low as 20?m. Furthermore, the feasibility of silicon (Si)Si, Siglass as well as Siceramic hermetic and metallic wafer bonding at room temperature is presented. We show that by using this bond technology, strong (maximum shear strengths of 235?MPa) and hermetically sealed bond interfaces can be achieved without any additional solder material.

Braeuer, J.; Gessner, T.

2014-11-01

382

Wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible biomedical platform.  

PubMed

We present wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible parylene platform, as progress toward sustainably powering biomedical microsystems suitable for implantable and wearable applications. All-solid-state, low-profile (<30?m), and high-density (up to ~500?F/mm(2)) micro-supercapacitors are formed on an ultrathin (~20?m) freestanding parylene film by a wafer-scale parylene packaging process in combination with a polyaniline (PANI) nanowire growth technique assisted by surface plasma treatment. These micro-supercapacitors are highly flexible and shown to be resilient toward flexural stress. Further, direct integration of micro-supercapacitors into a radio frequency (RF) rectifying circuit is achieved on a single parylene platform, yielding a complete RF energy harvesting microsystem. The system discharging rate is shown to improve by ~17 times in the presence of the integrated micro-supercapacitors. This result suggests that the integrated micro-supercapacitor technology described herein is a promising strategy for sustainably powering biomedical microsystems dedicated to implantable and wearable applications. PMID:25653069

Maeng, Jimin; Meng, Chuizhou; Irazoqui, Pedro P

2015-02-01

383

Enhanced capture rate for haze defects in production wafer inspection  

NASA Astrophysics Data System (ADS)

Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

2010-03-01

384

On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays  

NASA Technical Reports Server (NTRS)

A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

Shao, H. M.; Deutsch, L. J.; Reed, I. S.

1987-01-01

385

On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays  

NASA Technical Reports Server (NTRS)

A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

Shao, Howard M.; Reed, Irving S.

1988-01-01

386

A parallel VLSI architecture for a digital filter using a number theoretic transform  

NASA Technical Reports Server (NTRS)

The advantages of a very large scalee integration (VLSI) architecture for implementing a digital filter using fermat number transforms (FNT) are the following: It requires no multiplication. Only additions and bit rotations are needed. It alleviates the usual dynamic range limitation for long sequence FNT's. It utilizes the FNT and inverse FNT circuits 100% of the time. The lengths of the input data and filter sequences can be arbitraty and different. It is regular, simple, and expandable, and as a consequence suitable for VLSI implementation.

Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

1983-01-01

387

Wafer-level packaging with compression-controlled seal ring bonding  

DOEpatents

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Farino, Anthony J

2013-11-05

388

VLSI Datapath Choices: Cell-Based Versus Full-Custom  

E-print Network

Traditionally, VLSI architects and designers have acknowledged the area, performance, and effort tradeoffs between cell-based and full-custom implementations of the same datapath function. However, few attempts have been made to characterize these tradeoffs in the context of contemporary fabrication processes and area place and route tools. More importantly, few attempts have been made to determine how to enable cell-based implementations to approach the density and speed of full-custom designs. This work quantifies the limits of cell-based datapath implementations based on results derived from a detailed analysis of the density and performance tradeoffs in the implementation of two full-custom datapaths, the Integer Register-Read Datapath (IRRDP) and the 64-bit adder/subtracter (ADDSUB), employed in the multi-ALU Processor (MAP) chip. A cell-based implementation of the IRRDP is 1.64x larger than the full-custom original. The critical timing path for the cell-based implementation is 11...

Andrew Liang Ping Chang; Andrew Liang; Andrew Liang; Ping Chang; Ping Chang

1998-01-01

389

A photo-sensor on thin polysilicon membrane embedded in wafer level package LED  

NASA Astrophysics Data System (ADS)

A wafer level packaging LED with photo-sensor which is fabricated on thin poly-silicon membrane located on the corner of silicon cavity is presented in this paper. The wafer substrate was fabricated with (100) orientation silicon wafer and a cavity was etched on the top of the wafer with wet chemical anisotropic etching process for mounting a LED chip. A thin polysilicon membrane was fabricated on the corner of the cavity and a MSM (Metal Semiconductor Metal) type photo-sensor was fabricated on the thin polysilicon membrane. The photo-sensor fabrication and LED packaging were completed on wafer level. The embedded photo-sensor in a wafer level packaging LED is designed to measure light intensity of a LED. The membrane structure photo-sensor can sense the light of the mounted LED directly, so it can measure accurate light intensity of the wafer level packing LED.

Kim, Jin Kwan; Lee, Hee Chul

2012-06-01

390

Influence of the bonding front propagation on the wafer stack curvature  

NASA Astrophysics Data System (ADS)

The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

Navarro, E.; Brchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

2014-08-01

391

Slumping of Si wafers at high temperature  

NASA Astrophysics Data System (ADS)

Space X-ray imaging telescopes have delivered unique observations that have been significantly contributing to many important discoveries of current astrophysics. For future telescopes with a larger collecting area and a better angular resolution, the limiting factor is their X-ray reflecting mirror array. Therefore, for a successful construction of future lightweight and highly reflecting X-ray mirrors, new cost-effective technologies and progressive materials are needed. Currently, the very promising materials are silicon foils which are commercially produced on a large scale. We focused on the plastic deformation of thin monocrystalline silicon foils, which was necessary for the precise thermal forming of the foils to 3D shapes. To achieve the plastic deformation, we applied forced slumping at temperatures from 1200 to 1400C. The final shapes and the surface quality of the foils were measured using a Taylor Hobson contact profilometer and examined with an Atomic Forced Microscopy. We studied the effects of temperature, applied slumping force, heattreatment time, crystal orientation, and furnace atmosphere on the shape and surface quality of the formed foils.

Mika, M.; Jankovsky, O.; Simek, P.; Lutyakov, O.; Havlikova, R.; Sofer, Z.; Hudec, R.; Pina, L.; Inneman, A.; Sveda, L.; Marsikova, V.

2013-05-01

392

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si  

NASA Astrophysics Data System (ADS)

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

2014-08-01

393

Wafer-fused VECSELs emitting in the 1310nm waveband  

NASA Astrophysics Data System (ADS)

Optically pumped wafer fused 1310 nm VECSELs have the advantage of high output power and wavelength agility. Gain mirrors in these lasers are formed by direct bonding of InAlGaAs/InP active cavities to Al(Ga)As/GaAs DBRs. We present for the first time Watt-level 1310 nm wafer-fused VCSELs based on gain mirrors with heat dissipation in the "flip-chip" configuration. Even though output power levels in this approach is lower than with intra-cavity diamond heat-spreaders, the "flip-chip configuration demonstrates higher quality optical emission and is preferable for industrial applications in optical amplifiers, intra-cavity doubled lasers, etc.

Sirbu, A.; Pierscinski, K.; Mereuta, A.; Iakovlev, V.; Caliman, A.; Micovic, Z.; Volet, N.; Rautiainen, J.; Heikkinen, J.; Lyytikainen, J.; Rantamki, A.; Okhotnikov, O.; Kapon, E.

2014-03-01

394

Chemical method for producing smooth surfaces on silicon wafers  

DOEpatents

An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

Yu, Conrad (Antioch, CA)

2003-01-01

395

Electrophoretic Photoresist Application for High Topography Wafer Surfaces  

Microsoft Academic Search

As wafer surfaces become topographically more challenging, achieving uniform resist coatings in deep vias, over high mesas, and three-dimensional (3-D) features may no longer be possible using conventional, solvent based, spin-coated liquid photoresist (LPR). Thinning of the resist on the high areas and pooling of the resist in the deep areas are common problems. Electrophoretic photoresist (EPR) may be used

James Tajadod; Henry Hendriks; John Klocke; Antonio Morales; Heather Rapuano

396

100GHz Transistors from Wafer-Scale Epitaxial Graphene  

Microsoft Academic Search

The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon

Y.-M. Lin; C. Dimitrakopoulos; K. A. Jenkins; D. B. Farmer; H.-Y. Chiu; A. Grill; Ph. Avouris

2010-01-01

397

Wafer-level radiometric performance testing of uncooled microbolometer arrays  

NASA Astrophysics Data System (ADS)

A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 ?m AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 ?m pixel size and 160x120, 52 ?m pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

2014-03-01

398

On-wafer calibration using space-conservative (SOLT) standards  

Microsoft Academic Search

In this paper the accuracy of on-wafer calibration using space-conservative (SOLT) standards is evaluated. The calibration approach relies on measurement-based standard definitions. Results are presented using CPW standards with 50 and 300 micron offsets, over the range from .045-65 GHz. In comparing to a multi-line TRL, the magnitude of the difference between the S-parameters is less than 0.05 up to

M. Imparato; T. Weller; L. Dunleavy

1999-01-01

399

Wafer-scale Reduced Graphene Oxide Films for Nanomechanical Devices  

Microsoft Academic Search

We report a process to form large-area, few-monolayer graphene oxide films and then recover the outstanding mechanical properties found in graphene to fabricate high Young's modulus ( ) 185 GPa), low-density nanomechanical resonators. Wafer-scale films as thin as 4 nm are sufficiently robust that they can be delaminated intact and resuspended on a bed of pillars or field of holes.

Jeremy T. Robinson; Maxim Zalalutdinov; Jeffrey W. Baldwin; Eric S. Snow; Zhongqing Wei; Paul Sheehan; Brian H. Houston

2008-01-01

400

Performance limiting micropipe defects in silicon carbide wafers  

Microsoft Academic Search

Reports on the characteristics of a major defect in mass-produced silicon carbide wafers which severely limits the performance of silicon carbide power devices. Micropipe defects originating in 4H- and 6H-SiC substrates were found to cause pre-avalanche reverse-bias point failures in most epitaxially-grown pn junction devices of 1 mm2 or larger in area. Until such defects are significantly reduced from their

Philip G. Neudeck; Anthony J. Powell

1994-01-01

401

Reduction of electrostatically adhered particles on wafer backside using ionizers  

Microsoft Academic Search

In this paper we provide results and discussion on the positive impact of ionizer(s) used in multiple configurations on wafer back-side and front-side particle adders in PVD processing tools. We present a hypothesis, followed by testing, that establishes a relationship between electrical surface charge collection data and particle data obtained in a laboratory setting and real world fabrication facility (fab)

Viraj Pandit; Emery Kuo

2010-01-01

402

Material electronic quality specification factors for polycrystalline silicon wafers  

SciTech Connect

The authors present a scheme to monitor quality (diffusion length) improvement, or upgrading, for inhomogeneous polycrystalline silicon wafers. Statistically-based parameters and scaling factors are defined to represent individual regions of varying diffusion length, and are used to follow material electronic property changes from crystal growth through upgrading steps, including phosphorus diffusion, hydrogen passivation and aluminum firing. Measurements of diffusion length using two different methods, SPV and IRPC are used.

Bailey, J. [Univ. of California, Berkeley, CA (United States). Dept. of Materials Science and Mineral Engineering; Kalejs, J.P.; Keaveny, C. [ASE Americas, Billerica, MA (United States)

1994-12-31

403

Method for making circular tubular channels with two silicon wafers  

DOEpatents

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

Yu, Conrad M. (Antioch, CA); Hui, Wing C. (Campbell, CA)

1996-01-01

404

Method for making circular tubular channels with two silicon wafers  

DOEpatents

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

Yu, C.M.; Hui, W.C.

1996-11-19

405

Adhesive wafer bonding using a molded thick benzocyclobutene layer for wafer-level integration of MEMS and LSI  

NASA Astrophysics Data System (ADS)

This paper describes a wafer bonding process using a 50 m thick benzocyclobutene (BCB) layer which has vias and metal electrodes. The vias were fabricated by molding BCB using a glass mold. During the molding, worm-like voids grew between BCB and the mold due to the shrinkage of polymerizing BCB. They were completely removed by subsequent reflowing in N2. After patterning Al on the reflowed BCB for the electrodes and via connections, bonding with a glass substrate was performed. Voidless bonding without damage in the vias and electrodes was achieved. Through the process, the control of the polymerization degree of BCB is important, and thus the polymerization degree was evaluated by Fourier transform infrared spectroscopy. The developed process is useful for the wafer-bonding-based integration of different devices, e.g. micro electro mechanical systems and large-scale integrated circuits.

Makihata, M.; Tanaka, S.; Muroyama, M.; Matsuzaki, S.; Yamada, H.; Nakayama, T.; Yamaguchi, U.; Mima, K.; Nonomura, Y.; Fujiyoshi, M.; Esashi, M.

2011-08-01

406

Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers  

E-print Network

Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive advantage of copper-to-copper (Cu-to-Cu) bonding with the increased adhesion strength and robustness of dielectric adhesive bonding using benzocyclobutene (BCB) is discussed. Critical processing challenges

Salama, Khaled

407

Ant Colony Optimization and its Application to Boolean Satisfiability for Digital VLSI Circuits  

E-print Network

Ant Colony Optimization and its Application to Boolean Satisfiability for Digital VLSI Circuits and Computer Engineering Dept., Rutgers University Piscataway, NJ 08854, USA Abstract Ant Colony Optimization (ACO) [8] is a non- deterministic algorithm framework that mimics the forag- ing behavior of ants

Parashar, Manish

408

VLSI POTENTIOSTAT FOR AMPEROMETRIC MEASUREMENTS FOR ELECTROLYTIC Harpreet S. Narula and John G. Harris  

E-print Network

VLSI POTENTIOSTAT FOR AMPEROMETRIC MEASUREMENTS FOR ELECTROLYTIC REACTIONS Harpreet S. Narula and John G. Harris Computational Neuro-Engineering Lab University of Florida, Gainesville, FL, USA harpreet,harris@cnel.ufl.edu 1. ABSTRACT This paper describes a CMOS integrated potentiostatic con- trol circuit. The design

Harris, John G.

409

Integrated VLSI Potentiostat For Cyclic Voltammetry In Electrolytic Reactions Harpreet S. Narula and John G. Harris  

E-print Network

Integrated VLSI Potentiostat For Cyclic Voltammetry In Electrolytic Reactions Harpreet S. Narula and John G. Harris Computational Neuro-Engineering Lab University of Florida, Gainesville, FL, USA harpreet. The design maintains a constant bias po- tential between the reference and working electrodes

Harris, John G.

410

Application of FDTD method to analysis of electromagnetic radiation from VLSI heatsink configurations  

Microsoft Academic Search

The electromagnetic radiation from a VLSI chip package and heatsink structure is analyzed by means of the finite-difference-time-domain (FDTD) technique. The dimensions of a typical configuration call for a multizone gridding scheme in the FDTD algorithm to accommodate fine grid cells in the vicinity of the heatsink and package cavity and sparse gridding in the remainder of the computational domain.

Kevin Li; C. F. Lee; Soon Y. Poh; R. T. Shin; J. A. Kong

1993-01-01

411

The VLSI design of a single chip for the multiplication of integers modulo a Fermat number  

Microsoft Academic Search

Multiplication is central in the implementation of Fermat number transforms (FNT) and other residue number algorithms. There is need for a good multiplication algorithm which can be realized easily on a VLSI chip. In this paper, the Leibowitz multiplier [1] is modified to realize multiplication in the ring of integers modulo a Fermat number. The advantage of this new algorithm

Jaw Chang; T. Truong; H. Shao; I. Reed; In-Shek Hsu

1985-01-01

412

An analog VLSI model of the jamming avoidance response in electric fish  

Microsoft Academic Search

The author describes an analog VLSI model of the jamming avoidance response (JAR) in the electric fish Eigenmannia. The fish uses the JAR to change the frequency of its electric organ discharge (EOD) so that interfering signals do not impair its ability to detect and locate objects with its electric field. This system, although behaviorally simple, comprises many levels of

John E. LeMoncheck

1992-01-01

413

A VLSI implementation of a correlator/digital-filter based on distributed arithmetic  

NASA Technical Reports Server (NTRS)

The design of a VLSI chip which applies the ideas of distributed arithmetic to a nonrecursive digital filter is described. The main features of this design are very high precision and a high degree of flexibility, which allows one chip to implement a large number of quite different digital filters and correlators.

Zohar, Shalhav

1989-01-01

414

A BIOMIMETIC VLSI ARCHITECTURE FOR SMALL TARGET TRACKING Vivek Pant1  

E-print Network

A BIOMIMETIC VLSI ARCHITECTURE FOR SMALL TARGET TRACKING Vivek Pant1 and Charles M. Higgins1,2 1 extensive computational architecture. However, even a small housefly is adept at pursuing its prey was supported by the Office of Naval Research under Agreement N68936-00-2-0002. Fig. 1. Spatial integration

415

AdOpt: Analog VLSI Stochastic Optimization for Adaptive Optics Marc Cohen Mikhail Vorontsov  

E-print Network

in optical imaging and laser optics applications. We present a hybrid VLSI and optical system for real-time). This as- sumption of a point source is the foundation of the most widely used adaptive optics control that prevent real-time phase compensation and significantly in- crease adaptive system cost and complexity

Cauwenberghs, Gert

416

VLSI Architecture for a Low Complexity Algorithm for Intraframe SubBand Coding of HDTV Images  

Microsoft Academic Search

A VLSI architecture for a low complexity intraframe subband image coding for HDTV signals is presented. The Generalized Quadrature Mirror Filters (GQMFs), which have smaller overall delay, are optimized in order to achieve high coding efficiency. The filter design exploits a symmetry property among different filter coefficients which, in turn, reduces the hardware complexity of the architecture substantially. The architecture

A. Kh. Al-Asmari; Rana Ejaz Ahmed

1994-01-01

417

A System Demonstration of Progressive Deadlock Recovery Routing Using Optoelectronic/VLSI Chips  

E-print Network

1 A System Demonstration of Progressive Deadlock Recovery Routing Using Optoelectronic/VLSI Chips Mongkol Raksapatcharawong Timothy Mark Pinkston SMART Interconnects Group EE-Systems Dept., University of Southern California Los Angeles, CA 90089-2562 {http://www.usc.edu/dept/ceng/pinkston/SMART.html} Abstract

Pinkston, Timothy M.

418

VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design  

E-print Network

VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design Saraju P of a Secure Digital Still Camera Several software based watermarking schemes have been presented camera that includes a watermarking module in Fig. 1, and call such a camera as a "secure digital still

Mohanty, Saraju P.

419

VLSI ARCHITECTURE FOR ENCRYPTION AND WATERMARKING UNITS TOWARDS THE MAKING OF A SECURE CAMERA  

E-print Network

VLSI ARCHITECTURE FOR ENCRYPTION AND WATERMARKING UNITS TOWARDS THE MAKING OF A SECURE CAMERA O. B and architecture in the framework of a digital cam- era, conceptualized as a "Secure Digital Camera (SDC)". The SDC uses watermarking and encryption processes for image security and authentication. The Rijndael AES

Mohanty, Saraju P.

420

VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication  

E-print Network

VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication and security mechanism for images produced by it. Since the proposal of the trustworthy digital camera Watermarking Unit Flash Memory Compression Unit Encryption Unit Fig. 1. Secure digital camera for image

Mohanty, Saraju P.

421

The Microprocessor as a Microcosm: A Hands-On Approach to VLSI Design Education  

E-print Network

The Microprocessor as a Microcosm: A Hands-On Approach to VLSI Design Education David Harris David_Harris@hmc.edu November 2002 Harvey Mudd College Claremont, CA #12;Microprocessor as Microcosm David Harris Page 2 of 19 Conclusion #12;Microprocessor as Microcosm David Harris Page 3 of 19 Introduction Changing face of Very Large

Harris, David Money

422

Sequential/Parallel Global Routing Algorithms for VLSI Standard Presented to  

E-print Network

. . . . . . . . . . . 33 2.4.3 Amdahl's Law and Parallel Speedup . . . . . . . . . . . . . 33 2.5 MCNC Benchmarks#12;Sequential/Parallel Global Routing Algorithms for VLSI Standard Cells A Thesis Presented for the degree of Masters of Science April, 2004 c Hao Sun, 2004 #12;2 #12;ABSTRACT Sequential/Parallel Global

Areibi, Shawki M

423

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Compact Current Source Models  

E-print Network

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Compact Current Source Models tables for each cell. We propose a new approach to compactly capture body bias and temperature effects within a mainstream CSM framework. Our approach features a table reduction method for compaction

Sapatnekar, Sachin

424

A real-time face recognition system using custom VLSI hardware  

Microsoft Academic Search

A real-time face recognition system has been implemented on an IBM compatible personal computer with a video camera, image digitizer, and custom VLSI image correlator chip. With a single frontal facial image under semicontrolled lighting conditions, the system performs (i) image preprocessing and template extraction, (ii) template correlation with a database of 173 images, and (iii) postprocessing of correlation results

Jeffrey M. Gilbert; Woodward Yang

1993-01-01

425

Modeling of two-phase microchannel heat sinks for VLSI chips  

Microsoft Academic Search

Microchannel heat sinks with forced convective boiling can satisfy the increasing heat removal requirements of VLSI chips. But little is known about two-phase boiling flow in channels with cross-sectional dimensions below 100 ?m. This work develops and experimentally verifies microchannel simulations, which relate the temperature field to the applied power and flowrate. The simulations consider silicon conduction and assume an

Jae-Mo Koo; Linan Jiang; Lian Zhang; Peng Zhou; Shilajeet S. Banerjee; Thomas W. Kenny; Juan G. Santiago; Kenneth E. Goodson

2001-01-01

426

LOW POWER DCT IMPLEMENTATION APPROACH FOR VLSI DSP PROCESSORS S. Masupe and T. Arslan  

E-print Network

LOW POWER DCT IMPLEMENTATION APPROACH FOR VLSI DSP PROCESSORS S. Masupe and T. Arslan in the low power implementation of the Discrete Cosine Transform (DCT). This is mainly due to the DCT being implement- ation of the DCT have targeted reducing the compu- tational complexity of the design or modifying

Arslan, Tughrul

427

Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders  

E-print Network

fan-out and wiring density thus influencing design decisions and yielding better area/power than known with simulated data. 1. Introduction In the course of VLSI processor design it is very important to choose will be known only after the design is finished. Therefore a lingering question remains: could we have achieved

California at Davis, University of

428

VLSI module placement based on rectangle-packing by the sequence-pair  

Microsoft Academic Search

The earliest and the most critical stage in VLSI layout design is the placement. The background of which is the rectangle packing problem: Given set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is

Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani

1996-01-01

429

Biophysical Synaptic Dynamics in an Analog VLSI Network of Hodgkin-Huxley Neurons  

E-print Network

Biophysical Synaptic Dynamics in an Analog VLSI Network of Hodgkin-Huxley Neurons Theodore Yu1--We study synaptic dynamics in a biophysical net- work of four coupled spiking neurons implemented from a biophysical origin basis for the model implementation of the neurons and synapses coupled

Cauwenberghs, Gert

430

Multi-Layer Parallel Decoding Algorithm and VLSI Architecture for Quasi-Cyclic LDPC Codes  

E-print Network

Multi-Layer Parallel Decoding Algorithm and VLSI Architecture for Quasi-Cyclic LDPC Codes Yang Sun, Houston, TX 77005 Email: {ysun, gw2, cavallar}@rice.edu Abstract--We propose a multi-layer parallel-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix

Mellor-Crummey, John

431

VLSI chip-set for data compression using the Rice algorithm  

NASA Technical Reports Server (NTRS)

A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

Venbrux, J.; Liu, N.

1990-01-01

432

Wafer shape compensation at the track PEB for improved CD uniformity  

NASA Astrophysics Data System (ADS)

This paper investigates the feasibility of using an electrostatic chuck (ESC) on a post exposure bake (PEB) plate in the track to improve the critical dimension uniformity (CDU) for bowed wafers. Although it is more conventional to consider vacuum chucking during PEB, electrostatic chucking offers some potential advantages, chief among which is the fact that electrostatic chucking does not require any type of a seal between the wafer and the PEB plate whereas vacuum chucking does. Such a seal requires contact and therefore has the potential to generate backside particles on the wafer. Electrostatic chucking therefore has the potential for a cleaner overall process. Three different PEB plates were tested in the course of this investigation, a non-chucking PEB plate (SRHP), a PEB plate equipped with a vacuum chuck (VRHP), and a PEB plate equipped with an ESC (eBHP). It was found that CD uniformities were up to 84 percent lower for bowed wafers that were chucked during PEB relative to wafers that were not chucked. In every case tested, wafers processed through chucking PEB plates showed lower CDUs than wafers processed through the non-chucking plate. CDU results were similar between vacuum chucked wafers and electrostatic chucked wafers. Based on the results presented in this paper, it can be concluded that electrostatic chucking during PEB is a feasible method for controlling CD uniformities on bowed wafers.

Michaelson, Timothy; Dai, Junyan; Chen, Lu; Cervera, Hiram; Lue, Brian; Herchen, Harald; Vellore, Kim; Bekiaris, Nikolaos

2008-03-01

433

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage  

NASA Astrophysics Data System (ADS)

This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ?50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (? 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III

Kulshreshtha, Prashant Kumar

434

A fast lightstripe rangefinding system with smart VLSI sensor  

NASA Technical Reports Server (NTRS)

The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

1989-01-01

435

High contrast reflection modulation near 1.55mum in InP 2D photonic crystals on silicon wafer.  

PubMed

We report on reflection modulation results near 1.55 mum in InP-based two-dimensional photonic crystals. The fabrication technology uses a polymeric bonding technique to integrate the InP thin-slab onto a Silicon wafer. Reflectivity modulation greater than 90% is obtained by pumping at 810 nm with optical excitation densities of 15 muJ/cm(2). The resulting optical broadband modulation is based on the saturation of absorption of InGaAs quantum wells at a photonic mode frequency tunable by lithography. PMID:19532354

Vecchi, Gabriele; Raineri, Fabrice; Sagnes, Isabelle; Lee, Ko-Hsin; Guilet, Stphane; Le Gratiet, Luc; Talneau, Anne; Levenson, Ariel; Raj, Rama; Van Laere, Frederik; Roelkens, Gunther; Van Thourhout, Dries; Baets, Roel

2007-02-01

436

A Scalable Wavelet Transform VLSI Architecture for Real-Time Signal Processing in High-Density Intra-Cortical Implants  

Microsoft Academic Search

This paper describes an area and power-efficient VLSI approach for implementing the discrete wavelet transform on streaming multielectrode neurophysiological data in real time. The VLSI implementation is based on the lifting scheme for wavelet computation using the symmlet4 basis with quantized coefficients and integer fixed-point data precision to minimize hardware demands. The proposed design is driven by the need to

Karim G. Oweiss; Andrew Mason; Yasir Suhail; Awais M. Kamboh; Kyle E. Thomson

2007-01-01

437

Technology.  

ERIC Educational Resources Information Center

Focuses on technology, on advances in such areas as aeronautics, electronics, physics, the space sciences, as well as computers and the attendant progress in medicine, robotics, and artificial intelligence. Describes educational resources for elementary and middle school students, including Web sites, CD-ROMs and software, videotapes, books,

Online-Offline, 1998

1998-01-01

438

An improved calibration technique for on-wafer large-signal transistor characterization  

Microsoft Academic Search

The on-wafer measurement of complex quantities and absolute power levels of active devices is truly significant for nonlinear device characterization and modeling. An original procedure, which allows one to perform both the vector and the power calibrations at the RF wafer probe tips used for on-wafer measurement of two-port devices, is presented. The measurement system is based on an automatic

Andrea Ferrero; Umberto Pisani

1993-01-01

439

Alternative fabrication process for edgeless detectors on 6 in. wafers  

NASA Astrophysics Data System (ADS)

VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 ?m thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 55 and 11 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.41.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 ?m from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

Kalliopuska, Juha; Ernen, Simo; Virolainen, Tuula

2011-05-01

440

THz quantum cascade lasers with wafer bonded active regions.  

PubMed

We demonstrate terahertz quantum-cascade lasers with a 30 ?m thick double-metal waveguide, which are fabricated by stacking two 15 ?m thick active regions using a wafer bonding process. By increasing the active region thickness more optical power is generated inside the cavity, the waveguide losses are decreased and the far-field is improved due to a larger facet aperture. In this way the output power is increased by significantly more than a factor of 2 without reducing the maximum operating temperature and without increasing the threshold current. PMID:23188348

Brandstetter, M; Deutsch, C; Benz, A; Cole, G D; Detz, H; Andrews, A M; Schrenk, W; Strasser, G; Unterrainer, K

2012-10-01

441

Propagation of Nd-laser pulses through crystalline silicon wafers  

SciTech Connect

Propagation of pulses from an Nd:YAG laser (wavelength, 1.064 {mu}m; pulse duration, 270 ns; pulse energy, 225 {mu}J) through crystalline silicon wafers is studied experimentally. Mathematical modelling of the process is performed: the heat conduction equation is solved numerically, the temperature dependences of the absorption and refraction of a substance, as well as generation of nonequilibrium carriers by radiation are taken into account. The constructed model satisfactorily explains the experimentally observed intensity oscillations of transmitted radiation. (interaction of laser radiation with matter)

Kirichenko, N A; Kuzmin, P G; Shcherbina, M E [Wave Research Center, A.M. Prokhorov General Physics Institute, Russian Academy of Sciences, Moscow (Russian Federation)

2011-07-31

442

Network analyzer calibration for cryogenic on-wafer measurements  

SciTech Connect

A cryogenic probe station for on-wafer microwave measurements has been developed at Sandia National Laboratories to explore the basic device physics and characterize advanced components for low-temperature applications. The station was designed to operate over a temperature range of 20 to 300 K with a frequency range of DC to 50 GHz. Due to the vacuum and the low temperature environment, the use of microwave probes and the calibration of network analyzer measurements are somewhat elaborate. This paper presents guidelines for probe use and calibration in this environment.

Hietala, V.M.; Housel, M.S.; Caldwell, R.B.

1994-04-01

443

Addressable Inverter Matrix Tests Integrated-Circuit Wafer  

NASA Technical Reports Server (NTRS)

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Buehler, Martin G.

1988-01-01

444

Characterization of wafer charging mechanisms and oxide survival prediction methodology  

SciTech Connect

Unipolar, EEPROM-based peak potential sensors and current sensors have been used to characterize the I-V relationship of charging transients which devices normally experience during the course of ion implantation. The results indicate that the charging sources may appear to behave like current-sources or voltage-sources, depending on the impedance of the load. This behavior may be understood in terms of plasma concepts. The ability to empirically characterize the I-V characteristics of charging sources using the CHARM-2 monitor wafers opens the way for prediction of failure rates of oxides subjected to specific processes, if the oxide Q{sub bd} distributions are known.

Lukaszek, W.; Dixon, W. [Stanford Univ., CA (United States). Center for Integrated Systems; Vella, M. [Lawrence Berkeley Lab., CA (United States). Accelerator and Fusion Research Div.; Messick, C.; Reno, S.; Shideler, J. [National Semiconductor, West Jordan, UT (United States)

1994-04-01

445

Pressureless wafer bonding by turning hillocks into abnormal grain growths in Ag films  

NASA Astrophysics Data System (ADS)

We demonstrate pressureless wafer bonding using silver abnormal grain growth caused by stress migration at 250 C, which is very low for a direct solid-state bonding temperature. The bonding achieved a die-shear strength of more than 50 MPa, which exceeds the fracture toughness of Si wafer. Various deposition temperatures for the silver films, i.e., initial residual stress, reveal that the bonding process is driven by thermomechanical stress. Abnormal grain growth is induced at the contact interface instead of hillocks growing on the film surface. Pressureless wafer bonding can be applied to advanced devices such as thin-wafer multi-chip integrations.

Oh, Chulmin; Nagao, Shijo; Kunimune, Teppei; Suganuma, Katsuaki

2014-04-01

446

Improved quality control of silicon wafers using novel off-line air pocket image analysis  

NASA Astrophysics Data System (ADS)

Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

Valley, John F.; Sanna, M. Cristina

2014-08-01

447

The optimization of CD uniformity and measurement on mask and wafer  

NASA Astrophysics Data System (ADS)

As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) is used to represent global CD variation on mask. These methods are removing local CD variation on mask. Because local CD variation on wafer is large compared with the effect of local CD variation of mask, global CD uniformity can be measured with suppressed local CD variation [1]. In this paper, local CD variation of mask and wafer is evaluated, and area CD and smoothing methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. By these methods, CD measurement repeatability can be enhanced to get closer correlation of mask and wafer. Close correlation makes fine CD correction on mask to get better field CD uniformity on wafer. And the repeatability of field to field CD uniformity of wafer is evaluated according to measurement tool of CD-SEM and scatterometry.

Choi, Yongkyoo; Kim, Munsik; Han, Oscar

2007-05-01

448

True wafer temperature during metallization in physical vapor deposition cluster tools  

NASA Astrophysics Data System (ADS)

Aluminum metallization is an important process for planarization and interconnect applications. Wafer temperature during deposition is one of the key parameter determining film properties such as reflectivity and resistivity. Results of experiments carried out in order to characterize the thermal behavior of product wafers during physical vapor deposition, primarily aluminum and wafer degas will be presented. The effects of back and front side depositions, backside gas pressure and plasma power level on deposition temperature are all investigated. The utility of real time in-situ temperature monitoring on every product wafer in all deposition chambers within a cluster tool and the advantages provided in terms of process monitoring are discussed.

Adel, Michael E.; Mangan, Shmuel; Grunes, Howard; Parkhe, Vijay

1994-09-01

449

Determination of wafer center position during the transfer process by using the beam-breaking method  

NASA Astrophysics Data System (ADS)

A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

2014-09-01

450

Through pellicle management of haze formation in a wafer fabrication environment  

NASA Astrophysics Data System (ADS)

The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been shown to suppress or minimize the propensity for haze formation, but none of these technologies has stopped every instance of haze. Additionally, the management of photo-induced defects during lithography exposure is expensive, so some capability will always be needed to remove haze on photomasks for long term maintenance over a mask's lifetime. A novel technology is reviewed here which uses a dry (no chemical effluents) removal system to safely sweep the entire printable region of a pelliclized photomask to eliminate all removable haze. This process is safe regardless of the mask substrate materials or the presence of small critical patterns such as SRAF's that may represent damage problems for traditional cleaning methods. Operational process techniques for this system and performance in removal will be shown for haze located on the mask pattern surface. This paper will also discuss the theory of operation for the system, including expected chemical reactions and address the reformation rate of haze crystals. Data from tool acceptance and preliminary production use will also be reviewed including analysis of process window through a focus-exposure matrix, repair durability, CD performance, and sort yield.

Figliolini, Alexander; Archuletta, Michael; LeClaire, Jeff; Brinkley, David; Doerr, David; White, Roy; Bozak, Ron; Lee, David A.

2012-02-01

451

Development of a multi-electrode system for non-destructive and contactless wafer evaluation  

NASA Astrophysics Data System (ADS)

With the miniaturization of CMOS, the gate insulator has extremely become thin until reaching the EOT (equivalent oxide thickness) of less than 1nm in order to keep maintaining high-speed performances of devices and low electric energy consumption. Since the gate insulator is so thin, leakage current increases and the gate dielectric breakdown can easily occur. This affects the reliability of semiconductor devices. To make good devices, it is necessary to use technologies for the evaluation of the gate insulator reliability. TDDB (Time Dependent Dielectric Breakdown) lifetime has been one of the main factors for this evaluation. In this case, a wafer is destroyed in order to be evaluated, which reduces the semiconductor yield. To solve this problem, we propose a new technique for the evaluation of the gate insulator which is a non-destructive and contactless measurement method, and thus an appropriate method for inline processes. A voltage is applied on a Si/SiO2 specimen. A voltage source electrode and the specimen are not in contact (10micron gap). After it is charged, the specimen is irradiated by a xenon-flash-lamp. Since the energy of this pulsed light is beyond 4eV, electrons are emitted and move from Si to SiO2. It is possible to estimate the condition (the electrical conductivity) of the insulator using this phenomenon. A multi-electrode system was developed for mass production. With this system, one is able to evaluate 10 thousand points over a 12-inch wafer in 1 minute.

Ndagijmana, Justin; Soh, Yuki; Fukashi, Junpei; Kobayashi, K.; Furuta, Masaaki; Kubota, Hiroshi

2013-12-01

452

Mixed-Dimensionality VLSI-Type Configurable Tools for Virtual Prototyping of Biomicrofluidic Devices and Integrated Systems  

NASA Astrophysics Data System (ADS)

This report presents results of a DARPA/MTO Composite CAD Project aimed to develop a comprehensive microsystem CAD environment, CFD-ACE+ Multiphysics, for bio and microfluidic devices and complete microsystems. The project began in July 1998, and was a three-year team effort between CFD Research Corporation, California Institute of Technology (CalTech), University of California, Berkeley (UCB), and Tanner Research, with Mr. Don Verlee from Abbott Labs participating as a consultant on the project. The overall objective of this project was to develop, validate and demonstrate several applications of a user-configurable VLSI-type mixed-dimensionality software tool for design of biomicrofluidics devices and integrated systems. The developed tool would provide high fidelity 3-D multiphysics modeling capability, l-D fluidic circuits modeling, and SPICE interface for system level simulations, and mixed-dimensionality design. It would combine tools for layouts and process fabrication, geometric modeling, and automated grid generation, and interfaces to EDA tools (e.g. Cadence) and MCAD tools (e.g. ProE).

Makhijani, Vinod B.; Przekwas, Andrzej J.

2002-10-01

453

Experimental Evaluation of Ternary Systems for VLSI Microelectronics.  

NASA Astrophysics Data System (ADS)

This work contains both theoretical and experimental results for ternary systems. The theoretical part starts with a compilation of bulk data. Group VIII metals such as Fe, Co, Ni, Pd and Pt form stable ternary phases with other transition metals. This tendency is explained using an empirical approach where parameters affecting phase formation and solubility are electron affinity, atomic radii and valency. Metal -dopant compound formation is also reviewed for Metal-Boron -Si systems. Following the literature review, the validity of other models is discussed. Experimentally, thin film growth of Ti _{rm 4}Ni_4 Si_7, Ti_ {0.75}Co_{0.25} Si_2, TiCoSi, Ti _4Co_4Si_7 and ZrCuSi_2 is observed for the first time. Crystallographic structures and electrical properties of selected compounds are presented. Samples are prepared by Rapid Thermal Processing (RTP) in vacuum. RTP is shown to be also advantageous to form smooth low resistivity silicides such as TiSi_2, CoSi _2 (15-18 muOmega.cm) and ZrSi_2 (34 mu Omega.cm). The ternary phases can be prepared either by reacting bilayers on Si or by processing a metal overlayer on a silicide. For metal bilayers, the sequence of evolution usually starts with the formation of intermetallic compounds. Above 550^circC, Si becomes mobile leading to the growth of ternary phases. The metal in excess with respect to the stoichiometry of the ternary reacts with Si yielding binary silicide which is segregated in a separate layer only if the diffusing metal is involved. The formation of Cu_3Si and its instability in contact with O are analyzed. Decomposition of the silicide is accompanied by room temperature oxidation of Si related to the surface catalytic action of Cu atoms in dissociating O_2 molecules. Small atoms such as Co, Ni and Cu are fast diffusers in silicides, but preliminary results indicate that Cu might be an interesting alternative to Al. For Cu/ZrSi _2 structures, three stages of insertion of Cu atoms into twin habit planes exist. For all the experiments performed, Auger Electron Spectroscopy reflects modifications of the density of states caused by metal d-Si 3p bonding. The global approach combining thin film and bulk samples offers new insights for the future use of multilevel metallizations in submicron VLSI manufacturing processes.

Setton, Michael

1990-01-01

454

CMOS VLSI Active-Pixel Sensor for Tracking  

NASA Technical Reports Server (NTRS)

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

455

Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding  

SciTech Connect

The single twin boundary with crystallographic orientation relationship (1{sup }1{sup }1{sup })//(111) [01{sup }1]//[011{sup }] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Kim, Moon J., E-mail: moonkim@utdallas.edu [Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, Texas 75080 (United States); Klie, Robert F. [Department of Physics, University of Illinois at Chicago, Chicago, Illinois 60607 (United States)] [Department of Physics, University of Illinois at Chicago, Chicago, Illinois 60607 (United States)

2013-12-16

456

Process Performance of Optima XEx Single Wafer High Energy Implanter  

NASA Astrophysics Data System (ADS)

To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstream dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.

Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.; David, J.; Rubin, L. M.; Jang, I. S.; Cha, J. C.; Joo, Y. H.; Lee, A. B.; Jin, S. W.

2011-01-01

457

Optical Cluster Eye fabricated on wafer-level.  

PubMed

Wafer-level optics is considered as a cost-effective approach to miniaturized cameras, because fabrication and assembly are carried out for thousands of lenses in parallel. However, in most cases the micro-optical fabrication process is not mature enough to reach the required accuracy of the optical elements, which may have complex profiles and sags in the mm-scale. Contrary, the creation of microlens arrays is well controllable so that we propose a multi aperture system called "Optical Cluster Eye" which is based on conventional micro-optical fabrication techniques. The proposed multi aperture camera consists of many optical channels each transmitting a segment of the whole field of view. The design of the system provides the stitching of the partial images, so that a seamless image is formed and a commercially available image sensor can be used. The system can be fabricated on wafer-level with high yield due to small aperture diameters and low sags. The realized optics has a lateral size of 2.2 2.9 mm2, a total track length of 1.86 mm, and captures images at VGA video resolution. PMID:21935117

Meyer, Julia; Brckner, Andreas; Leitel, Robert; Dannberg, Peter; Bruer, Andreas; Tnnermann, Andreas

2011-08-29

458

Patterning of photocleavable zwitterionic polymer brush fabricated on silicon wafer.  

PubMed

Brushes of a polymer, namely poly(carboxymethylbetaine) (PCMB), were fabricated on silicon wafers by reversible addition-fragmentation chain-transfer (RAFT) polymerization using a surface-confined RAFT agent having an aromatic group at its bottom. The polymer brush showed effective suppression of the non-specific adsorption of bovine serum albumin (BSA) and adhesion of fibroblasts (3T3 cells). In contrast, BSA and 3T3 cells significantly adsorbed on and adhered to positively or negatively charged polymer brushes fabricated by the same procedure. Upon UV irradiation at 193nm, the thickness of the PCMB brush with an aromatic group at its bottom decreased significantly whereas PCMB prepared using a surface-confined RAFT agent without an aromatic group needed a much higher irradiation dose to afford a comparable decrease in thickness. These results indicate a preferential cleavage of the PCMB brush due to photodecomposition of the phenyl group at the bottom. BSA and 3T3 cells non-specifically adsorbed on and adhered to the UV irradiation-induced hollow spaces, respectively. Furthermore, a designed pattern with a resolution of 5?m was successfully made on the PCMB brush above the silicon wafer by simple UV irradiation. These results suggest that the surface-confined aromatic RAFT agent will be quite useful for simple photolithography in biomedical fields. PMID:25466462

Kamada, Tomohiro; Yamazawa, Yuka; Nakaji-Hirabayashi, Tadashi; Kitano, Hiromi; Usui, Yuki; Hiroi, Yoshiomi; Kishioka, Takahiro

2014-11-01

459

On the generation of bulk microdefects in phosphorus-diffused monocrystalline silicon solar wafers after a high-thermal treatment studied by X-ray topography  

NASA Astrophysics Data System (ADS)

Oxygen is the most important impurity in free dislocation Czochralski silicon single crystals incorporated interstitially during the growth. The knowledge of oxygen behavior after thermal processes is of great technological importance, since different kinds of bulk microdefects such us SiO2 precipitates, dislocation loops and stacking faults can be generated. In monocrystalline silicon solar cell manufacturing fabrication, there are several high-thermal treatments. The first is the diffusion process at 850-900 C. Three different kinds of phosphorus diffusion wafers, standard PO3Cl liquid, spray-on and screen printing, were comparatively studied by X-ray topography showing that phosphorus diffusion improves the crystal quality by a gettering process whose best efficiency is in PO3Cl-diffused wafers. Later, another fabrication high-thermal step is for instance the rear surface passivation taking place at temperatures from 800 to 1,050 C. For this reason, it is important to study how a high-thermal treatment at 1,000 C affects the different phosphorus-diffused wafers mentioned above. To evaluate and characterize the possible defects induced by the oxygen precipitation, X-ray topography has been employed. Results show that annealed wafers are not perfect crystals; the oxygen precipitation induces the generation of bulk microdefects whose kind, size and density depend on the diffusion method employed. In PO3Cl and spray-on diffused wafers, retardation in the oxygen precipitation process takes place after annealing, while in screen printing this process is recovered and a kind of mixed defects between dislocation loops and platelet precipitates is generated.

Gonzlez-Maas, M.; Vallejo, B.; Caballero, M. A.

2014-09-01

460

Resist deposition without spinning by using novel inkjet technology and direct lithography for MEMS  

E-print Network

Resist deposition without spinning by using novel inkjet technology and direct lithography for MEMS spinning. Drop-on-demand coating of the wafer reduces waste and the cost of coating wafers. The novel and development is uniform. In the literature, several types of photoresist coating methods are reported1'2: spin

Khuri-Yakub, Butrus T. "Pierre"

461

Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace  

Microsoft Academic Search

Early production results are reviewed for IBM's integrated SiGe HBT technology. With a sample size of over 200 wafers, statistical control of key HBT parameters (F T, F max, R bb, R bi, ?) and other supporting devices, and benchmark circuit performance are shown. HBT device yield and reliability on 200 mm wafers are presented, demonstrating that the SiGe HBT

D. C. Ahlgren; M. Gilbert; D. Greenberg; J. Jeng; J. Malinowski; D. Nguyen-Ngoc; K. Schonenberg; K. Stein; R. Groves; K. Walter; G. Hueckel; D. Colavito; G. Freeman; D. Sunderland; D. L. Harame; B. Meyersori

1996-01-01

462

Mixed-Signal VLSI Circuits for Particle Detector Instrumentation in High-Energy Physics Experiments  

NASA Astrophysics Data System (ADS)

This research is concerned with the circuit design challenges presented by the electronics requirements at future colliding beam facilitates for high-energy physics research. The particle detectors to be used in the next generation of experiments depend on the realization of sophisticated instrumentation electronics that will enable the identification and characterization of the fundamental constituents of matter. The work presented here focuses on the monolithic VLSI integration of multiple, mixed-signal, front-end electronics channels for detector-mounted instrumentation. The use of high levels of integration is driven by the need for compactness, low cost, high reliability, and low power dissipation in the implementation of the hundreds of thousands of sensory channels required for future experiments. The specific application considered in this work is the front -end electronics for straw tube drift chambers. In this context, the function of the front-end electronics is to measure the occurrence time of an input pulse in relation to a system clock. Each front-end channel includes analog circuits that provide amplification and signal conditioning for input pulses as small as 1mV, a timing discriminator, and a time interval digitizer to measure input pulse arrival times with respect to the system clock. Performance requirements for the channel include a timing error less than 0.75ns RMS, average power dissipation in the tens of milliwatts, and event rates in the 50-100MHz range. Circuits must be designed to allow the implementation of high-sensitivity analog and fast digital functions on the same chip. Unwanted coupling between digital and analog circuits must be minimized along with channel-to-channel crosstalk. A multi-channel circuit that measures the occurrence times of input pulses with peak values in the 1-10mV range relative to a 62.5-MHz clock has been monolithically integrated in a 1.2-?m CMOS technology. Each channel includes a wideband amplifier, a tail-cancellation filter, a timing discriminator with time walk compensation, and a time digitizer. A timing error of 0.46ns RMS has been achieved, with negligible channel-to-channel crosstalk, at a power dissipation of 50mW/channel from a 3.3-V supply.

Loinaz, Marc Joseph

1995-11-01

463

Wafer bonded 4-junction GaInP/GaAs//GaInAsP/GaInAs concentrator solar cells  

NASA Astrophysics Data System (ADS)

Multiple-junction solar cells made from III-V compound semiconductors are delivering the highest solar-electric conversion efficiencies. Increasing the number of junctions offers the potential to reach higher efficiencies. Direct wafer bonding offers a unique opportunity to combine lattice mismatched materials through a permanent, electrically conductive and optically transparent interface. In addition, the use of Smart Cut technology, associated with its material recycling capabilities allows from a cost perspective the use of expensive bulk material such as InP. Combination of both technologies opens new opportunities to deliver cost effective high efficiency solar cells. In this respect, we have been able to demonstrate a record efficiency of 44,7% with a wafer bonded 4-junction GaInP/GaAs//GaInAsP/GaInAs concentrator solar cell with bandgap energies of 1.88/1.44//1.11/0.70 eV respectively. The bandgaps are chosen to be close to optimal for conversion under concentrated sunlight [1]. This paper presents the improvements made to achieve the world record result leading to higher efficiencies and lower cost.

Krause, Rainer; Piccin, Matteo; Blanc, Nicolas; Rico, Miguel Muoz; Charles-Alfred, Cedric; Drazek, Charlotte; Guiot, Eric; Dimroth, Frank; Bett, Andreas; Grave, Matthias; Beutel, Paul; Karcher, Christian; Tibbits, Tom; Oliva, Eduard; Siefer, Gerald; Schachtner, Michael; Wekkeli, Alexander; Signamarcheix, Thomas

2014-09-01

464

A new VLSI architecture for a single-chip-type Reed-Solomon decoder  

NASA Technical Reports Server (NTRS)

A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.

Hsu, I. S.; Truong, T. K.

1989-01-01

465

Learning and optimization with cascaded VLSI neural network building-block chips  

NASA Technical Reports Server (NTRS)

To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

1992-01-01

466

VLSI architectures for computing multiplications and inverses in GF(2m)  

NASA Technical Reports Server (NTRS)

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

1985-01-01

467

VLSI architectures for computing multiplications and inverses in GF(2m).  

PubMed

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation. PMID:11539660

Wang, C C; Truong, T K; Shao, H M; Deutsch, L J; Omura, J K; Reed, I S

1985-08-01

468

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours  

NASA Astrophysics Data System (ADS)

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

469

A Progl-am for Simulation of Semiconductol-Wafer Fabrication  

E-print Network

to analyze issues such as fak-'out design. capacity analysis, production forecasts. and fab start in a clean room environmenl since even the smallest dust particle can e on a chip. Wafers follow e s c i s e q u e n c e of process ;teps. which transform a blank wafer

Resende, Mauricio G. C.

470

Damage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors  

E-print Network

and increases safety and availability of military and commercial aircraft. Although the incor- poration of IVHMDamage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors VICTOR: Piezoelectric wafer active sensors can be applied to aging aircraft structures to monitor the onset and progress

Giurgiutiu, Victor

471

Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication  

Microsoft Academic Search

This paper concerns performance modeling of semiconductor manufacturing operations. More specifically, it focuses on queueing network models for an analysis of wafer fabrication facilities. The congestion problems that plague wafer fabrication facilities are described in general terms, and several years' operating data from one particular facility are summarized. A simple queueing network model of that facility is constructed, and the

HONG CHEN; J. MICHAEL HARRISON; AVI MANDELBAUM; ANN VAN ACKERE; LAWRENCE M. WEIN

1988-01-01

472

3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces.  

E-print Network

3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces. Journal: 2008 Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces Jian-Qiang Lu1 , J. Jay Mc approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces

Salama, Khaled

473

Power and energy transduction analysis of piezoelectric wafer-active sensors for  

E-print Network

the damage of the structure is inferred from the changes in load and strain distributions measuredArticle Power and energy transduction analysis of piezoelectric wafer-active sensors for structural of power and energy transduction in piezoelectric wafer-active sensors (PWAS) for structural health

Giurgiutiu, Victor

474

Absolute micro-encoder using image obtained by ball lens assembled inside wafer  

Microsoft Academic Search

An absolute micro-encoder based on code imaging is demonstrated. As the lens for the code imaging, a ? 300 m ball lens is assembled inside the cavity between wafer-bonded Pyrex glass and suspensions inside a Si wafer. By designing the appropriate lens holder, the assembling accuracy of the ball lens can be of the same level as that of the

Minoru Sasaki; Fuki Nakai; Kazuhiro Hane; Kanji Yokomizo; Kazuhito Hori

2006-01-01

475

Micro crack detection of multi-crystalline silicon solar wafer using machine vision techniques  

Microsoft Academic Search

Purpose The detection of invisible micro cracks (?-cracks) in multi-crystalline silicon (mc-si) solar wafers is difficult because of the wafers' heterogeneously textured backgrounds. The difficulty is twofold. First, invisible ?-cracks must be visualized to imaging devices. Second, an image processing sequence capable of extracting ?-cracks from the captured images must be developed. The purpose of this paper is to

Yih-Chih Chiou; Jian-Zong Liu; Yu-Teng Liang

2011-01-01

476

Detection of Cracks in Single-Crystalline Silicon Wafers Using Impact Testing  

Microsoft Academic Search

This thesis is about detection of cracks in single-crystalline silicon wafers by using a vibration method in the form of an impact test. The goal to detect cracks from vibration measurements introduced by striking the silicon wafer with an impact hammer. Such a method would reduce costs in the production of solar cells. It is an inexpensive, relatively simple method

Christina Hilmersson

2006-01-01

477

Crack detection in single-crystalline silicon wafers using impact testing  

Microsoft Academic Search

This paper presents acoustic measurements obtained by mechanically exciting vibratory modes in single-crystalline silicon wafers with hairline periphery cracks of different type and location. The data presented shows a dependence of natural frequencies, peak amplitudes and damping levels of four audio vibration modes in the frequency range up to 1000Hz on crack type and crack location. Data from defective wafers

C. Hilmersson; D. P. Hess; W. Dallas; S. Ostapenko

2008-01-01

478

Low temperature sacrificial wafer bonding for planarization after very deep etching  

Microsoft Academic Search

A new technique, at temperatures of 150C or 450C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of (1) polymer bonding

V. L. Spiering; J. W. Berenschot; M. Elwenspoek; J. H. J. Fluitman

1994-01-01

479

A Study of Lean Production Management in the Crystal Wafer Processing at TXC  

E-print Network

A Study of Lean Production Management in the Crystal Wafer Processing at TXC 032 034090324 2007-5-17 #12; "" #12; ABSTRACT Lean production mode is a management method at applying the lean production management principle in the crystal wafer process of TXC. Combining the lean

Wang, Ji

480

Wafer based aberration metrology for lithographic systems using overlay measurements on targets  

E-print Network

Wafer based aberration metrology for lithographic systems using overlay measurements on targets projection system from wafer metrology data. For this, new types of phase-shift gratings (PSG) are introduced metrology tool. In this way, the overlay error can be used as a measurand based on which the phase

481

Characterization of Piezoelectric Wafer Active Sensors Victor Giurgiutiu* and Andrei N. Zagrai  

E-print Network

, these piezoelectric wafers act as both sensors and actuators. In addition, their frequency bandwidth is orders of magnitude larger than that of conventional modal analysis equipment. They can form sensor and actuator wafer to excite the structure and an array of PVDF film sensors to pick up the forced vibration response

Giurgiutiu, Victor

482

A full wafer dicing free dry release process for MEMS devices  

Microsoft Academic Search

This paper presents a full wafer, dicing free, dry release process using hydrofluoric acid (HF) vapour phase etching (VPE) for MEMS sensors and actuators fabricated using silicon on insulator (SOI) wafers. It is particularly beneficial to MEMS sensors whose performance benefits from a large proof mass, for example accelerometers and gyroscopes. Such a fabrication method was first proposed by Overstolz

I. Sari; I. Zeimpekis; M. Kraft

2010-01-01

483

A clean wafer-scale chip-release process without dicing based on vapor phase etching  

Microsoft Academic Search

A new method to release MEMS chips from a wafer without dicing is presented. It can be applied whenever SOI wafers are used that are structured from both the device and the handle side using DRIE. This method enables the release of extremely fragile structures without any mechanical impact on the chips. No more dicing residues or debris are created

T. Overstolz; P. A. Clerc; W. Noell; M. Zickar; N. F. de Rooij

2004-01-01

484

Computationally efficient modeling of wafer temperatures in a low-pressure chemical vapor deposition furnace  

Microsoft Academic Search

A new thermal model is developed to predict wafer temperatures within a hot-wall low pressure chemical vapor deposition furnace based on the furnace wall temperatures as measured by thermocouples. Based on an energy balance of the furnace system, this model is a transformed linear model which captures the nonlinear relationship between the furnace wall temperature distribution and the wafer temperature

Qinghua He; S. Joe Qin; Anthony J. Toprac

2003-01-01

485

Iron detection in polished and epitaxial silicon wafers using generation lifetime measurements  

Microsoft Academic Search

For iron detection in silicon, minority carrier diffusion length measurements are often used. These methods analyze only the bulk properties of the wafer and therefore failed in the case of epitaxial wafers due to the disturbing influence of the highly doped substrate. A technique is presented for the determination of the iron content in epitaxial as well as in polished

Guenther Obermeier; Diethard Huber