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1

Overlay Tolerances For VLSI Using Wafer Steppers  

NASA Astrophysics Data System (ADS)

In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

Levinson, Harry J.; Rice, Rory

1988-01-01

2

SOD wafer technology  

Microsoft Academic Search

Silicon-on-diamond (SOD) structured wafer with 4-inch diameter was fabricated by the technologies of CVD diamond deposition, Si wafer bonding and thinning. Diamond thin film with high quality and low interface state density was uniformly deposited on Silicon (001) substrate, continuous H+ ion bombardment to as-grown film surface under DC bias was performed to decrease the intrinsic tensile stress in the

C. Z. Gu; Y. Sun; J. K. Jia; Z. S. Jin

2003-01-01

3

High speed synchronizer card utilizing VLSI technology  

NASA Technical Reports Server (NTRS)

A generic synchronizer card capable of providing standard NASA communication block telemetry frame synchronization and quality control was fabricated using VLSI technology. Four VLSI chip sets are utilized to shrink all the required functions into a single synchronizer card. The application of VLSI technology to telemetry systems resulted in an increase in performance and a decrease in cost and size.

Speciale, Nicholas; Wunderlich, Kristin

1988-01-01

4

The evolution of silicon wafer cleaning technology  

Microsoft Academic Search

The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as RCA Standard Clean. This is still the primary method used in the industry. What

Werner Kern

1990-01-01

5

Various Applications Of An Automated Wafer Inspection System In VLSI Manufacturing  

NASA Astrophysics Data System (ADS)

Although the VLSI products produced in our manufacturing lines are mostly designed with 1 micron geometries, we expect the majority of products will shift to sub-micron design very soon. This article discusses results of our experiments to releaf human operators from the already difficult visual inspection tasks with a fully automated equipment. We have two groups of visual inspection tasks necessary on the VLSI manufacturing floor. One is Engineering Analysis and the other is in-line monitor, or Product Wafer Auditing. The former, Engineering Analysis, demands a variety of different measurements and inspections, such as line width, contact area, multilayer alignment precision and defect density. On the otherhand, Product Wafer Auditing, will need only one or two such functions per mo-nitoring point in the process, but will use the function more extensively, continuously, and repeatedly. In the manufacturing environment, where the ever pressing demand to increase yield is para-mount, it is crucial to reduce defect finding and analysing time. For that purpose, we need higher speed and accuracy for production wafer inspection than can be obtained with human inspectors. In this context, our experience on the KLA-2020, fully automated wafer inspection equipment has proven to be truely beneficial in the area of the following five different cases of evaluation of the KLA-2020, conducted in our plant. Case: 1. Visual inspection of the VLSI production wafer after aluminum dry-etching was studied in comparison with human operators. The result is that not only was the KLA-2020 much more thorough in detecting defects but also was much faster than any of the operators, by far. Case: 2. We applied the KLA-2020 to identify the cause of die, lost at probe test. We traced the killer defect, which was originated from the reticle. KLA-2020 is effective in reticle qualification. Case: 3. We found that the line-width instruments based upon laser scatterology cannot properly measure most of the dense 1 micron geometry of our VLSI devices. However, the KLA-2020 has provided excellent data of such Case: 4. During the course of process development, where the objective was to improve the LW uniformity within a production wafer, we found the efficiency and accuracy of the KLA-2020 were so good that the objective was met successfully in a very short time. In addition, the yield was improved remarkably. Case: 5. There have been no practical and simple methods to measure a small area in a pro-duction VLSI wafer. We will show the experimental results of measuring the area of contact holes in dropouts using the KLA-2020.

Matsuda, Kimihiro; Takashima, Isamu; Aoki, Yasuo; Araki, Junichi

1988-01-01

6

Full custom VLSI - A technology for high performance computing  

NASA Technical Reports Server (NTRS)

Full custom VLSI is presented as a viable technology for addressing the need for the computing capabilities required for the real-time health monitoring of spacecraft systems. This technology presents solutions that cannot be realized with stored program computers or semicustom VLSI; also, it is not dependent on current IC processes. It is argued that, while design time is longer, full custom VLSI produces the fastest and densest VLSI solution and that high density normally also yields low manufacturing costs.

Maki, Gary K.; Whitaker, Sterling R.

1990-01-01

7

Wafer level reliability for high-performance VLSI design  

NASA Technical Reports Server (NTRS)

As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

Root, Bryan J.; Seefeldt, James D.

1987-01-01

8

MEMS Wafer-level Packaging Technology Using LTCC Wafer  

NASA Astrophysics Data System (ADS)

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

9

Potential impact of VLSI technologies on guided missile design  

Microsoft Academic Search

Some aspects of the anticipated impact of emerging VLSI technologies on tactical missiles, present and future generations are discussed. VLSI evolution represents a unique example of a very dynamic and pervasive trend in commercial and military applications. It is our opinion, however, that the characteristics of this trend are quite different in tactical missiles, not only compared to commercial electronics

H. A. Maurer; K. S. Kongelbeck

1985-01-01

10

GaAs VLSI technology and circuit elements for DSP  

NASA Astrophysics Data System (ADS)

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Mikkelson, James M.

1990-10-01

11

Characterization and management of wafer stress for various pattern densities in 3D integration technology  

Microsoft Academic Search

In the current 3D integration technology, the control of wafer warp is needed to ensure uniform photolithography, good bonding areas and other major processes that requires flat wafer surface. In this paper, we found out that the wafer warpage was increased with increasing TSV density. The highest wafer warpage was observed after Cu annealing base on step by step warpage

X. F. Pang; T. T. Chua; H. Y. Li; E. B. Liao; W. S. Lee; F. X. Che

2010-01-01

12

Electro Energy Bipolar Wafer Cell Battery Technology for PHEV Applications  

Microsoft Academic Search

Electro Energy, Inc. (EEI) has developed a bipolar battery utilizing a patented wafer cell design, applicable to both NiMH and Li-Ion chemistries. This battery is particularly suitable for meeting the high-voltage, high- energy demands of modern and emerging plug-in hybrid vehicles (PHEVs). EEI's battery technology has the potential to provide a rebuttal to the most common argument for not developing

J. Dailey; K. M. Abraham; R. Plivelich; J. Landi; M. Klein

2007-01-01

13

Development of a novel Wafer-Level-Packaging technology using laminating process  

Microsoft Academic Search

We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some Jisso techniques to WLP manufacturing processes. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the developed

Yoshio Okayama; Yasuyuki Yanase; Kouichi Saitou; Hajime Kobayashi; Mayumi Nakasato; Tetsuya Yamamoto; Ryosuke Usui; Yasunori Inoue

2009-01-01

14

Semiconductor thin film transfer by wafer bonding and advanced ion implantation layer splitting technologies  

Microsoft Academic Search

Wafer bonding is an attractive technology for modern semiconductor and microelectronic industry due to its variability in allowing combination of materials. Initially, the bonding of wafers of the same material, such as silicon-silicon wafer bonding has been major interest. In the meantime, research interest has shifted to the bonding of dissimilar materials such as silicon to quartz or to sapphire.

Tien-Hsi Lee

1998-01-01

15

Wafer-level manufacturing technology of glass microlenses  

NASA Astrophysics Data System (ADS)

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

16

Wafer dicing process optimization and characterization for C90 low-k wafer technology  

Microsoft Academic Search

This paper presents an investigation on the effect and optimization of machining parameters for 90 nm low-k wafer topside peeling improvement in mechanical dicing operation. It is part of the continuous improvement that performed based on current established dicing recipe. The resulted outcomes to achieve are cut quality improvement, dicing yield loss reduction and device reliability enhancement for low-k wafer

Koh Wen Shi; K. Y. Yow; K. Rachel; L. Calvin

2009-01-01

17

Interconnection technologies for multichip assemblies (ITMA)-A UK Information Technology Engineering Directorate hybrid wafer scale project  

Microsoft Academic Search

The Interconnection technology for multichip assemblies (ITMA) project is addressing the application of a silicon-substrate-based multichip module (MCM) technology to the requirements of parallel computing applications in the UK. The program involves activities on MCM design methodology, silicon substrate process technology, device assembly, module packaging technology, the design of VLSI devices specifically for MCM applications, and the implementation of advanced

D. J. Pedder

1993-01-01

18

Science and technology of plasma activated direct wafer bonding  

NASA Astrophysics Data System (ADS)

This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

Roberds, Brian Edward

19

A Wafer Transfer Technology for MEMS Adaptive Optics  

NASA Technical Reports Server (NTRS)

Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

Yang, Eui-Hyeok; Wiberg, Dean V.

2001-01-01

20

A VLSI implementation of DCT using pass transistor technology  

NASA Technical Reports Server (NTRS)

A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

Kamath, S.; Lynn, Douglas; Whitaker, Sterling

1992-01-01

21

Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies  

NASA Astrophysics Data System (ADS)

Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a consequence, computational lithography solutions are currently under development in order to correct wafer topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer stack. In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC flow for chip scale mask correction is presented with quality and run time penalty analysis.

Michel, J.-C.; Le Denmat, J.-C.; Sungauer, E.; Robert, F.; Yesilada, E.; Armeanu, A.-M.; Entradas, J.; Sturtevant, J. L.; Do, T.; Granik, Y.

2013-09-01

22

Versatile wafer-level hermetic packaging technology using anodically-bondable LTCC wafer with compliant porous gold bumps spontaneously formed in wet-etched cavities  

Microsoft Academic Search

This paper reports simple and versatile technology for hermetically capping MEMS with a wet-etched LTCC (low temperature cofired ceramic) wafer by standard anodic bonding process, in which the MEMS and Au vias in the LTCC wafer are electrically connected by porous Au bumps. The porous Au bump is spontaneously formed from a part of the Au via by wet-etching the

Shuji Tanaka; Mamoru Mohri; Atsushi Okada; Hideyuki Fukushi; Masayoshi Esashi

2012-01-01

23

Bonding pad models for silicon VLSI technologies and their effects on the noise figure of RF NPNs  

Microsoft Academic Search

VLSI technologies such as BiCMOS and high speed ECL Bipolar are candidates for mixed mode applications which include RF receiver functions. In order for these silicon technologies to achieve low noise characteristics one needs to optimize both the active device and the signal path to the IC interface. Studies in the bonding pad parasitics indicate that these path losses can

Natalino Camilleri; J. Kirschgessner; Julio Costa; David Ngo; David Lovelace

1994-01-01

24

Wafer Slicing and Wire Saw Manufacturing Technology I. Kao (PI)  

E-print Network

this abrasive slurry cutting process and to optimize it. As a sequel to this understanding, control tools can applications than the traditional use of the process. An evaluation of wire saw cutting process has shown to cut very thin wafers from large diameter crystalline ingots of semiconductor materials, has emerged

Kao, Imin

25

Fine pitch connection and thermal stress analysis of a novel Wafer Level Packaging technology using laminating process  

Microsoft Academic Search

We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some JISSO techniques to WLP manufacturing processes [1]. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the

Yoshio Okayama; Mayumi Nakasato; Kouichi Saitou; Yasuyuki Yanase; Hajime Kobayashi; Tetsuya Yamamoto; Ryosuke Usui; Yasunori Inoue

2010-01-01

26

Single-wafer-processed nano-positioning XY-stages with trench-sidewall micromachining technology  

Microsoft Academic Search

For operation and manipulation with nanometric positioning precision, a single crystalline silicon micro XY-stage is developed by using double-sided bulk-micromachining technology. Front-side deep reactive ion etching combined with backside anisotropic etching constructs the high-aspect-ratio comb-driven XY-stage in a single standard silicon wafer (i.e., no silicon on insulator wafer is used). For integrating several electrostatic actuators in one silicon chip, different

Lei Gu; Xinxin Li; Haifei Bao; Bin Liu; Yuelin Wang; Min Liu; Zunxian Yang; Baoluo Cheng

2006-01-01

27

3D micro-optical lens scanner made by multi-wafer bonding technology  

NASA Astrophysics Data System (ADS)

We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

Bargiel, S.; Gorecki, C.; Bara?ski, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frömel, J.

2013-03-01

28

Wafer level reliability assessment of stress-induced voiding  

Microsoft Academic Search

As device technology advances toward submicron geometry, the linewidth of VLSI metallization interconnects continues to scale down and stress-induced migration becomes an increasingly important issue. Wafer level stress-induced migration testing of metallization was introduced as a technique for obtaining greater levels of quality assurance with a shorter feedback time at an affordable cost. Slit-like voids are typically formed causing catastrophic

H. H. Hoang; R. B. MacNaughton; Y. S. Lin; M. Zamanian; F. S. Chen; E. Carpenter; L. Tullos; S. Tso; F. T. Liou

1991-01-01

29

Material and process limits in silicon VLSI technology  

Microsoft Academic Search

The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely believed that this process will continue for at least another ten years. However there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur, and beyond ten years

JAMES D. PLUMMER; PETER B. GRIFFIN

2001-01-01

30

Product assurance technology for custom LSI/VLSI electronics  

NASA Technical Reports Server (NTRS)

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

1985-01-01

31

Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors  

SciTech Connect

Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300?mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700?cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

Kim, SangHyeon, E-mail: dadembyora@mosfet.t.u-tokyo.ac.jp, E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); JST-CREST, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Yokoyama, Masafumi; Nakane, Ryosho [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Li, Jian; Kao, Yung-Chung [IntelliEPI, Inc., 1250 E. Collins Blvd., Richardson, Texas 75081 (United States)

2014-07-28

32

Inertial sensor technology using DRIE and wafer bonding with connecting capability  

Microsoft Academic Search

A novel device structure utilizing deep reactive ion etching (DRIE) technology and aligned wafer bonding was developed. In this structure, an interconnecting scheme for electrical signal routing with signal crossovers is realized. Also, the `footing effect' and the `bowing effect,' which are inherent in DRIE processes, were investigated in detail. A mask layout strategy for solving the footing effect was

Kei Ishihara; Chi-Fan Yung; A. A. Ayon; Martin A. Schmidt

1999-01-01

33

Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology  

NASA Astrophysics Data System (ADS)

Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

Shi, Fang Frank

34

Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias  

NASA Astrophysics Data System (ADS)

The presented wafer-level packaging technology enables the direct integration of electrical interconnects during low-temperature wafer bonding of a cap substrate featuring through silicon vias (TSVs) onto a MEMS device wafer. The hybrid bonding process is based on hydrophilic direct bonding of plasma-activated Si/SiO2 surfaces and the simultaneous interconnection of the device metallization layers with Cu TSVs by transient liquid phase (TLP) bonding of ultra-thin AuSn connects. The direct bond enables precise geometry definition between device and cap substrate, whereas the TLP bonding does not require a planarization of the interconnect metallization before bonding. The complete process flow is successfully validated and the fabricated devices' characterization evidenced ohmic interconnects without interfacial voids in the TLP bond.

Kühne, Stéphane; Hierold, Christofer

2011-08-01

35

Ultra-Low Resistance, Through-Wafer Via (TWV) Technology and Its Applications in Three Dimensional Structures on Silicon  

Microsoft Academic Search

This paper presents an ultra-low resistance, high wiring density, through-wafer via (TWV) technology that is compatible with standard silicon wafer processing. Vias as small as 30 µm by 30 µm are fabricated through a 525 µm thick wafer. This results in an aspect ratio for the via that is greater than 17:1. Furthermore, the dc resistance of a single via

Hyongsok T. Soh; C. Patrick Yue; Anthony McCarthy; Changsup Ryu; Thomas H. Lee; S. Simon Wong; Calvin F. Quate

1999-01-01

36

A Novel VLSI Technology to Manufacture High-Density Thermoelectric Cooling Devices  

E-print Network

This paper describes a novel integrated circuit technology to manufacture high-density thermoelectric devices on a semiconductor wafer. With no moving parts, a thermoelectric cooler operates quietly, allows cooling below ambient temperature, and may be used for temperature control or heating if the direction of current flow is reversed. By using a monolithic process to increase the number of thermoelectric couples, the proposed solid-state cooling technology can be combined with traditional air cooling, liquid cooling, and phase-change cooling to yield greater heat flux and provide better cooling capability.

H. Chen; L. Hsu; X. Wei

2008-01-07

37

Robust hermetic wafer level thin-film encapsulation technology for stacked MEMS \\/ IC package  

Microsoft Academic Search

This paper reports a thin-film encapsulation technology for wafer level micro-electro-mechanical systems (MEMS) package, using poly-benzo-oxazole (PBO) sacrificial material and plasma enhanced chemical vapor deposited silicon oxide (PECVD SiO) cap layer. This technique, which is applicable for MEMS technologies, saves die size and enables conventional package processes such as dicing, picking, mounting and bonding. Besides the fabrication processes of the

Y. Shimooka; M. Inoue; M. Endo; S. Obata; A. Kojima; T. Miyagi; Y. Sugizaki; I. Mori; H. Shibata

2008-01-01

38

On-Chip High Variable Inductor Using Wafer-Level Chip-Scale Package Technology  

Microsoft Academic Search

In this paper, the authors propose an on-chip high-Q variable inductor embedded in wafer-level chip-scale package (WL-CSP). The variable inductor has a metal plate and a spiral inductor fabricated by the WL-CSP technology. The metal plate can be moved by a microelectromechanical systems (MEMS) actuator, and the inductance is varied according to the position of the metal plate. At the

Kenichi Okada; Hirotaka Sugawara; Hiroyuki Ito; Kazuhisa Itoi; Masakazu Sato; Hiroshi Abe; Tatsuya Ito; Kazuya Masu

2006-01-01

39

NASA VLSI 2007 Mohanty, Vadlamudi and  

E-print Network

NASA VLSI 2007 Mohanty, Vadlamudi and Kougianos 1 A Universal Voltage Level Converter for Multi University of North Texas dhruva@unt.edu #12;NASA VLSI 2007 Mohanty, Vadlamudi and Kougianos 2 Agenda Custom layout design at 90nm technology Conclusion and future works #12;NASA VLSI 2007 Mohanty, Vadlamudi

Mohanty, Saraju P.

40

978-1-4244-6455-5/10/$26.00 2010 IEEE 38 11th Int'l Symposium on Quality Electronic Design VLSI circuits of 45nm technology and beyond are  

E-print Network

Abstract VLSI circuits of 45nm technology and beyond are increasingly affected by process variations with conventional ASV through SPICE simulations on benchmark circuits. The results indicate that the dual-ASV system. Introduction As the VLSI technology scales to 45nm and beyond, manufacturing process variations and aging

Hu, Jiang

41

Wafer warpage analysis of stacked wafers for 3D integration  

Microsoft Academic Search

The demand for wafer stacking technology has been increasing significantly. Although many technical challenges of wafer stacking have improved greatly, there are still many processing issues to be resolved. One of them is wafer warpage since it causes process and product failures such as delamination, cracking, mechanical stresses, and even electrical failure. In this study the warpage of multi-stacked wafers

Youngrae Kim; Sung-Keun Kang; Sung-Dong Kim; Sarah Eunkyung Kim

42

1IUCEE Workshop: VLSI Design, Day 2 Today's Topic: Revised Course Content  

E-print Network

, labs Research: MEMS & Sensors Introduction; VLSI Curriculum; Course Content Overview Course content: Session B BOG: Session A BOG: New Technology Lectures BOG: VLSI Course Content Lectures Components of VLSI: technology & device models Teaching skills; effective lectures #12;2IUCEE Workshop: VLSI Design, Day 2 A

Mason, Andrew

43

1IUCEE Workshop: VLSI Design, Day 5 Today's Topic: Research Topics  

E-print Network

, labs Research: MEMS & Sensors Introduction; VLSI Curriculum; Course Content Overview Course content: Session B BOG: Session A BOG: New Technology Lectures BOG: VLSI Course Content Lectures Components of VLSI: technology & device models Teaching skills; effective lectures #12;2IUCEE Workshop: VLSI Design, Day 5 A

Mason, Andrew

44

1IUCEE Workshop: VLSI Design, Day 3 Today's Topic: Effective Teaching  

E-print Network

, labs Research: MEMS & Sensors Introduction; VLSI Curriculum; Course Content Overview Course content: Session B BOG: Session A BOG: New Technology Lectures BOG: VLSI Course Content Lectures Components of VLSI: technology & device models Teaching skills; effective lectures #12;2IUCEE Workshop: VLSI Design, Day 3 A

Mason, Andrew

45

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics  

NASA Technical Reports Server (NTRS)

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

46

New dynamic FET logic and serial memory circuits for VLSI GaAs technology  

NASA Technical Reports Server (NTRS)

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

Eldin, A. G.

1991-01-01

47

Thin-film encapsulation technology for above-IC MEMS wafer-level packaging  

NASA Astrophysics Data System (ADS)

This work presents a low-cost and low-temperature wafer-level packaging solution for microelectromechanical systems (MEMS) devices. Heat-sensitive polymer poly(propylene carbonate) is used as the sacrificial material to release the capping layer in a clean and fast manner. Free-standing caps made of amorphous silicon carbide films and as large as 450 µm in diameter are successfully fabricated. To demonstrate the validity of this technology, surface-micromachined Pirani vacuum gauges are fabricated as an example of MEMS devices and encapsulated. Capped Pirani gauges respond to pressure between 1 mTorr and 1 atm. The Pirani gauges are sealed with Parylene C films that exhibit near-hermetic properties and the initial sealing pressure for 300 µm diameter cavities is characterized to be in the range of tens of torr.

Zhang, Qing; Cicek, Paul-Vahé; Nabki, Frederic; El-Gamal, Mourad

2013-12-01

48

Sensitivity analysis of add-on price estimate for select silicon wafering technologies  

NASA Technical Reports Server (NTRS)

The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

Mokashi, A. R.

1982-01-01

49

A new VLSI compatible rapid thermal processing system  

NASA Astrophysics Data System (ADS)

Rapid thermal processing (RTP) is increasingly becoming a significant tool to meet the challenge of fabricating miniaturized MOS and bipolar devices. The primary advantages of RTP over conventional furnace annealing include the shorter heat cycle, well-controlled soak times at peak temperatures and the capability to rapidly change anneal ambients, thereby enhancing its flexibility as a process tool. The major applications of RTP in VLSI technology that are presently being pursued include: (i) implant-damage annealing/dopant activation, (ii) silicide formation, (iii) glass reflow, (iv) thin film growth/deposition (oxides, nitrides, oxy-nitrides) and (v) contact alloying. This paper discusses a new rapid thermal processor, RTP-800/8000, recently introduced by Varian. The discussion will include mechanical and electrical design, software, heating process compatibility, process uniformity and repeatability, process setup and noncontact temperature measurement. The heating system consists of a tungsten lamp array surrounded by a highly reflective mirror system designed to provide good temperature uniformity for wafer sizes up to 200 mm. The RTP-8000 has a serial cassette-to-cassette automatic wafer handling system. The RTP-800 possesses a single wafer, operator-assisted wafer handling system. The RTP-800/8000 has an automated multiple gas flow control and also has the optional capability of processing wafers in vacuum. An infrared optical pyrometer measures the wafer temperature from the backside of the wafer. In the RTP-8000, touch screen operation of the menu-driven recipes is easy with user-friendly software. A separate electroluminescent flat panel display provides information for maintenance and servicing and reports the system status. Process information is provided on this display in the RTP-800.

Aitken, D.; Mehta, S.; Parisi, N.; Russo, C. J.; Schwartz, V.

50

Single-wafer-processed nano-positioning XY-stages with trench-sidewall micromachining technology  

NASA Astrophysics Data System (ADS)

For operation and manipulation with nanometric positioning precision, a single crystalline silicon micro XY-stage is developed by using double-sided bulk-micromachining technology. Front-side deep reactive ion etching combined with backside anisotropic etching constructs the high-aspect-ratio comb-driven XY-stage in a single standard silicon wafer (i.e., no silicon on insulator wafer is used). For integrating several electrostatic actuators in one silicon chip, different actuators are electrically isolated from each other using a trench-sidewall insulating technique. SiO2-refilled trench bars are formed on vertical trench sidewalls to isolate adjacent comb-drive elements. Combined with the reverse-biased p-n junction along the boron-diffused trench sidewall for comb driving, individual actuators can be operated independently. The developed XY-stage of 1600 × 1600 µm2 is suspended by four sets of folded-beam and bending-flexure composite springs. To maximize the moving distance, a two-segment comb finger with a gently curved transition is used for both improving the actuation efficiency and avoiding side instability of the stage. The experimental results verify the stage design including the gentle transition of a two-segment comb-drive scheme. Under 23 V driving voltage, a 10 µm moving stroke is measured in each of the four directions. Compared with a conventional comb structure, the two-segment comb fingers contribute 70% improvement in actuating amplitude. The positioning precision of the stage is evaluated with a nano-mechanical indenting experiment. A scanning probe microscopy probe with an electrical-heated nano tip is put in contact with the surface of a polymethyl methacrylate film that is coated on the stage surface. Along with the movement of the stage, pulsed heating on the nano tip produces serial nano-pitches. With the nano-indenting experiment, better than 18 nm positioning precision is obtained for the XY-stage.

Gu, Lei; Li, Xinxin; Bao, Haifei; Liu, Bin; Wang, Yuelin; Liu, Min; Yang, Zunxian; Cheng, Baoluo

2006-07-01

51

Numerically Controlled Dry Etching Technology for Flattening of Si Wafer which Employs SF6/H2 Downstream Plasma  

NASA Astrophysics Data System (ADS)

Technology for the damage-free flattening of a Si wafer that employs a numerically controlled local dry etching (NC-LDE) technology has been developed to meet the requirement for achieving an extremely flat-surface wafer for the downscaling of ULSI feature size. In this technology, fluorine atoms which are generated in a localized SF6/H2 downstream plasma are exposed at a local area of a Si wafer, thereby generating a high etch rate of 130 ?m/min at the bottom of the etched profile and a volume removal rate of 45.9 mm3/min. The flattening process was carried out by numerically controlled scan etching according to previously measured thickness data and consequently site flatness was improved from 0.51 ?m to 0.08 ?m within 150 s for a 200-mm-diameter Si wafer. This level of flatness will be the value required after 2005. Damage-free characteristics were also confirmed by minority carrier recombination lifetime and sub-surface defect measurements.

Yanagisawa, Michihiko; Iida, Shinya; Horiike, Yasuhiro

2002-05-01

52

Mixed-Mode VLSI Implementation of Fuzzy ART Marc Cohen, Pamela Abshire and Gert Cauwenberghs  

E-print Network

Mixed-Mode VLSI Implementation of Fuzzy ART Marc Cohen, Pamela Abshire and Gert Cauwenberghs to issues of VLSI architec- ture and technology in the context of our mixed-mode VLSI hardware every alternative; we have chosen a scheme which seems natural and flexiblefor mixed-modeVLSI circuit

Maryland at College Park, University of

53

Impact of Wafer and Technology Selection on Liner Stress Mobility Enhancement  

Microsoft Academic Search

For the first time, the drain current enhancement effect of stressed contact liner applied to various wafer material is discussed in this paper. The enhancement is larger in SOI and SOQ device than in bulk MOSFET. Thinner SOI film causes more enhancement, but saturation current fluctuation sensitive to SOI thickness variation increases drastically. In case of SOS wafer, enhancement is

M. Mochizuki; K. Fukuda

2006-01-01

54

VLSI Architecture: Past, Present, and Future  

Microsoft Academic Search

This paper examines the impact of VLSI technology on the evolution of computer architecture and projects the future of this evolution. We see that over the past 20 years, the increased den- sity of VLSI chips was applied to close the gap between microprocessors and high-end CPUs. Today this gap is fully closed and adding devices to uniprocessors is well

William J. Dally; Steve Lacy

1999-01-01

55

Performance optimization of VLSI interconnect layout  

Microsoft Academic Search

This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design un- der the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver\\/gate delay models of various degrees of accuracy and efficiency

Jason Cong; Lei He; Cheng-kok Koh; Patrick H. Madden

1996-01-01

56

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories  

NASA Astrophysics Data System (ADS)

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

57

A practical, flip-chip, multi-layer pre-encapsulation technology for wafer-scale underfill  

Microsoft Academic Search

This paper describes the conception, development, and application of a novel materials set and methodology for fabricating assembly-ready flip chips pre-encapsulated, at the wafer level, with a low coefficient of thermal expansion (CTE) underfill. This technology is unique in that it addresses a key challenge currently facing the high density interconnect (HDI) electronics industry-how to produce cost-effectively, in a streamlined

Robert V. Burress; M. Albert Capote; Yong-Joon Lee; Howard A. Lenos; Jeffrey F. Zamora

2001-01-01

58

High-Brightness GaN-Based Light-Emitting Diodes on Si Using Wafer Bonding Technology  

Microsoft Academic Search

GaN-based light-emitting diodes (LEDs) grown on Si(111) substrates were fabricated with a vertical electrode method by using wafer bonding technology. The fabricated vertical LEDs showed a lower operating voltage and larger light output power than conventional LEDs due to enhancement in current spreading and reduction in tensile strain. The light output power of the vertical structured LEDs was 2.6 times

Seung-Jae Lee; Kang Ho Kim; Jin-Woo Ju; Tak Jeong; Cheul-Ro Lee; Jong Hyeob Baek

2011-01-01

59

Titanium Nitride Membrane Application to Extended Gate Field Effect Transistor pH Sensor Using VLSI Technology  

NASA Astrophysics Data System (ADS)

A new process for the fabrication of the extended gate field effect transistor (EGFET) together with complementary metal oxide semiconductor (CMOS) circuits on the same chip is reported. The sensing membrane of the EGFET is titanium nitride (TiN) conducting material and it is fabricated using the r.f. sputtering method. The chips are fabricated using the standard submicron 0.5 ?m double poly double metal (DPDM) N-well CMOS IC process. No extra mask is used in the post-process. An instrument amplifier circuit is described that provides an output voltage dependent on the threshold-voltage variations in the sensing membrane. According to the experimental results, the high linear sensitivity approaches 57 mV/pH@. The hysteresis voltage is 0.5 mV per cycle of buffer solutions of pH7?pH4?pH7?pH10?pH7. This structure is also insensitive to light. This EGFET is fabricated using the standard technology and no difficulty is experienced in realizing this multi species device. The EGFET and readout circuits are produced using VLSI technology, achieving reduced area and low cost. This device has the advantages of mass production.

Chin, Yuan-Lung; Chou, Jung-Chuan; Lei, Zhen-Ce; Sun, Tai-Ping; Chung, Wen-Yaw; Hsiung, Shen-Kan

2001-11-01

60

Study of thinned Si wafer warpage in 3D stacked wafers  

Microsoft Academic Search

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study,

Youngrae Kim; Sung-Keun Kang; Sarah Eunkyung Kim

2010-01-01

61

Stress analysis of stacked Si wafer in 3D WLP  

Microsoft Academic Search

In 3D wafer-stacking technology, one of the major manufacturing issues is wafer warpage because it causes process and product failures, such as delamination, cracking, mechanical stresses, and even electrical failure. In this study, the wafer warpage and local strain of thinned Si wafers in a wafer stack were investigated. A blanket Cu film was deposited on a Si wafer by

Ki-Ho Maeng; Youngrae Kim; Sung-Geun Kang; Sung-Dong Kim; Sarah Eunkyung Kim

2011-01-01

62

Yield-driven multi-project reticle design and wafer dicing  

NASA Astrophysics Data System (ADS)

The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has lead to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.

Kahng, Andrew B.; Mandoiu, Ion; Xu, Xu; Zelikovsky, Alex

2005-11-01

63

High Energy IED measurements with MEMs based Si grid technology inside a 300mm Si wafer  

NASA Astrophysics Data System (ADS)

The measurement of ion energy at the wafer surface for commercial equipment and process development without extensive modification of the reactor geometry has been an industry challenge. High energy, wide frequency range, process gases tolerant, contamination free and accurate ion energy measurements are the base requirements. In this work we will report on the complete system developed to achieve the base requirements. The system includes: a reusable silicon ion energy analyzer (IEA) wafer, signal feed through, RF confinement, and high voltage measurement and control. The IEA wafer design required carful understanding of the relationships between the plasma Debye length, the number of grids, intergrid charge exchange (spacing), capacitive coupling, materials, and dielectric flash over constraints. RF confinement with measurement transparency was addressed so as not to disturb the chamber plasma, wafer sheath and DC self-bias as well as to achieve spectral accuracy The experimental results were collected using a commercial parallel plate etcher powered by a dual frequency (VHF + LF). Modeling and Simulations also confirmed the details captured in the IED.

Funk, Merritt

2012-10-01

64

Temporary bonding for Chips In Wafer processing  

Microsoft Academic Search

Chip In Wafer is a very challenging concept because this solution allows wafer scale processes for System in Package and a very high miniaturization and performance level. This paper describes a technologies developed for Chip integration In Wafer (CIW). The approach consists in reconstituting a wafer from heterogeneous chips embedded in a resin with the active sides coplanar. This paper

J.-C. Souriau; A. Jouve; N. Sillon

2009-01-01

65

Optical interconnections for VLSI systems  

Microsoft Academic Search

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The

S.-Y. Kung; R. A. Athale; Sun-Yuan Kung

1984-01-01

66

Analysis and optimization of VLSI Clock Distribution Networks for skew variability reduction  

E-print Network

As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one...

Rajaram, Anand K.

2004-11-15

67

Interconnect Synthesis in High Speed Digital VLSI Routing  

Microsoft Academic Search

The advent of the nanotechnology has introduced new challenges and non-conventional problems to high speed digital Very Large Scale Integrated (VLSI) design. Moreover, the resultant progress of manufacturing technology is widening the gap between current Computer Aided Design (CAD) tools and VLSI technologies. This is reflected clearly in the IC design process where the Integrated Circuit (IC) flow has become

Moustafa A. Sayed; Ehab Y. Abdel Maksoud

2009-01-01

68

Customizable VLSI artificial neural network chips based on a novel technology  

SciTech Connect

The human cerebral cortex contains approximately 10{sup 11} neurons and 10{sup 14} synapses. It thus seems logical that any technology intended to mimic human capabilities should have the ability to fabricate a very large number of neurons and even larger numbers of synapses. This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems.

Fu, C. Y.; Law, B.; Chapline, G. [Lawrence Livermore National Lab., CA (United States); Swenson, D. [Naval Air Warfare Center, China Lake, CA (United States)

1993-09-14

69

Toward 300 mm wafer-scalable high-performance polycrystalline chemical vapor deposited graphene transistors.  

PubMed

The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26,000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ? 74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ? 40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available. PMID:25198884

Rahimi, Somayyeh; Tao, Li; Chowdhury, Sk Fahad; Park, Saungeun; Jouvray, Alex; Buttress, Simon; Rupesinghe, Nalin; Teo, Ken; Akinwande, Deji

2014-10-28

70

Bondability of processed glass wafers  

NASA Astrophysics Data System (ADS)

The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness will result in small real area of contact, and therefore yield voids in the bonding interface. Usually, the root mean square roughness (RMS) or the mean roughness (Ra) are used as parameters to evaluate the wafer bondability. It was found from experience that for a bondable wafer surface the mean roughness must be in the subnanometer range, preferentially less than 0.5 nm. When the surface roughness exceeds a critical value, the wafers will not bond at all. However RMS and Ra were found to be not sufficient for evaluating the wafer bondability. Hence one tried to relate wafer bonding to the spatial spectrum of the wafer surface profile and indeed some empirical relations that have been found. The first, who proposed a theory on the problem of the closing gaps between contacted wafers was Stengl. This gap-closing theory was then further developed by Tong and Gosele. The elastomechanics theory was used to study the balance between the decrease of surface energy due to the bonding and the increase of elastic energy due to the distortion of the wafer. They considered the worst case by assuming that both wafers have a waviness, with a wavelength (lambda) and a height amplitude h, resulting in a gap height of 2h in a head to head position. This theory is simple and can be used in practice, for studying the formation of the voids, or for constructing design rules for the bonding of deliberately structured wafers. But it is insufficient to know what is the real area of contact in the wafer interface after contact at room temperature because the wafer surface always possesses a random distribution of the surface topography. Therefore Gui developed a continuous model on the influence of the surface roughness to wafer bonding, that is based on a statistical surface roughness model Pandraud demonstrated experimentally that direct bonding between processed glass wafers is possible. This result cannot be explained by considering the RMS value of the surfaces only, because the wafers used show a RMS value larger than 1 nm. Based on the approach exposed in reference six, a rigorous analysis of wafer bonding of these processed glass wafers is presented. We will discuss the relation between the bonding process and different waveguide technologies used for implementing optical waveguides into one or both glass wafers, and give examples of optical devices benefiting from such a bonding process.

Pandraud, Gregory; Gui, Cheng-Qun; Pigeon, Florent; Lambeck, Paul V.; Parriaux, Olivier M.

1999-09-01

71

Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies  

NASA Astrophysics Data System (ADS)

We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of InP/Si substrates for bulk InP in the fabrication of such a four-junction solar cell could significantly reduce the substrate cost since the current prices for commercial InP substrates are much higher than those for Si substrates by two orders of magnitude. Direct heteroepitaxial growth of InP thin films on Si substrates has not produced the low dislocation-density high quality layers required for active InGaAs/InP in optoelectronic devices due to the ˜8% lattice mismatch between InP and Si. We successfully fabricated InP/Si substrates by He implantation of InP prior to bonding to a thermally oxidized Si substrate and annealing to exfoliate an InP thin film. The thickness of the exfoliated InP films was only 900 nm, which means hundreds of the InP/Si substrates could be prepared from a single InP wafer in principle. The photovoltaic current-voltage characteristics of the In0.53Ga0.47As cells fabricated on the wafer-bonded InP/Si substrates were comparable to those synthesized on commercially available epi-ready InP substrates, and had a ˜20% higher short-circuit current which we attribute to the high reflectivity of the InP/SiO2/Si bonding interface. This work provides an initial demonstration of wafer-bonded InP/Si substrates as an alternative to bulk InP substrates for solar cell applications. We have observed photocurrent enhancements up to 260% at 900 nm for a GaAs cell with a dense array of Ag nanoparticles with 150 nm diameter and 20 nm height deposited through porous alumina membranes by thermal evaporation on top of the cell, relative to reference GaAs cells with no metal nanoparticle array. This dramatic photocurrent enhancement is attributed to the effect of metal nanoparticles to scatter the incident light into photovoltaic layers with a wide range of angles to increase the optical path length in the absorber layer. GaAs solar cells with metallic structures at the bottom of the photovoltaic active layers, not only at the top, using semiconductor-metal direct bonding have been fabricated. These metallic back structures could incouple the incident

Tanake, Katsuaki

72

A high aspect-ratio silicon substrate-via technology and applications: through-wafer interconnects for power and ground and Faraday cages for SOC isolation  

Microsoft Academic Search

The reduction of ground inductance is crucial to the gain of RF and microwave circuits. To provide a low-inductance interconnect, we have developed a through-wafer via technology in silicon that incorporates a silicon nitride barrier liner and is filled with electroplated Cu. We have demonstrated vias with an aspect ratio as high as 14 and an inductance that approaches the

J. H. Wu; J. A. Del Alamo; K. A. Jenkins

2000-01-01

73

Assessment of thinned Si wafer warpage in 3D stacked wafers  

Microsoft Academic Search

3D (three-dimensional) wafer stacking technology has been developed extensively recently. Among many technical challenges in 3D stacked wafers the wafer warpage is one of the important processing issues to be resolved because the wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, WIW (within wafer) non-uniformity and electrical failure.

Youngrae Kim; Sung-Geun Kang; Eun-kyung Kim

2009-01-01

74

Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology  

Microsoft Academic Search

High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 ?m to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form

P. M. Mendes; S. Sinaga; A. Polyakov; M. Bartek; J. N. Burghartz; J. H. Correia

2004-01-01

75

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology  

NASA Astrophysics Data System (ADS)

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

76

MIT Microsystems Technology LaboratoriesMIT Microsystems Technology LaboratoriesDavid White, Duane Boning and Aaron GowerDavid White, Duane Boning and Aaron Gower Characterization of Endpoint and Wafer LevelCharacterization of Endpoint and Wafer Level  

E-print Network

30 2814 1 Pad Positions qq Using a IR camera to monitor the CMP processUsing a IR camera to monitor CMP IR image of a copper CMP polishIR image of a copper CMP polish angle Table/Pad IR Camera ViewingOverview: Wafer Scale Endpoint Uniformity Ā·Ā· Spatial Dependencies Between the Pad & WaferSpatial Dependencies

Boning, Duane S.

77

Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding  

E-print Network

Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

Spearing, S. Mark

78

Wafer level encapsulation technology for MEMS devices using an HF-permeable PECVD SIOC capping layer  

Microsoft Academic Search

In this paper, a novel technology for the encapsulation of MEMS devices using a porous capping material is presented. The capping material consists of a low temperature PECVD layer of SiOC and is shown to be permeable to HF-vapor and H2O and therefore allows for removal of a SiO2 sacrificial layer. Furthermore, it is demonstrated that a cavity defined underneath

G. J. A. M. Verheijden; G. E. J. Koops; K. L. Phan; J. T. M. van Beek

2008-01-01

79

VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.  

PubMed

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (?1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology. PMID:24628497

Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip

2014-01-01

80

Yield enhancement of VLSI/WSI array systems  

E-print Network

single wafer, tllils avoiding lugli manufacturing costs. In this research, vield enhancement of two typical VLSI/IVSI array systems, PLAs aud Pipeline 4rrays, is considered Yield enhancement of PLAs tluough reconfiguration is an important issue... in the uianufacturing process as PLAs are used extensively for logic design The reconfigu- ration of PLAs starts with a full diagnosis ( i e fault detection and location ). In the first chapter, a, new approach I' or diagnosing PLAs is proposed It offers full control...

Koo, Peter Yunemo

1989-01-01

81

VLSI Signal Processing for Wireless Communication  

Microsoft Academic Search

Wireless communication system is a heavy dense composition of signal processing techniques with semiconductor technologies. With the ever increasing system capacity and data rate, VLSI design and implementation method for wireless communications becomes more challenging, which urges researchers in signal processing to provide new architectures and efficient algorithms to meet low power and high performance requirements. This paper presents a

Xinming Huang

82

VLSI Universal Noiseless Coder  

NASA Technical Reports Server (NTRS)

Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

1989-01-01

83

Minimum silicon wafer thickness for ID wafering  

NASA Technical Reports Server (NTRS)

An analytical model, based on fracture mechanics analysis, is proposed for estimating the minimum wafer thickness as a function of the diameter requirement for solar cells. The conditions under which the model can be applied are discussed with reference to the critical flaw size, the applied force, and the width of the side support. It is shown that the equivalent cantilever force applied during ID slicing can be estimated from the wafering mechanical yield data. The width of the wafer side support was found to be a significant factor in controlling the minimum allowable wafer thickness during slicing. Wafer side support width requirements were found to increase with decreasing wafer thickness.

Chen, C. P.

1982-01-01

84

The 1992 4th NASA SERC Symposium on VLSI Design  

NASA Technical Reports Server (NTRS)

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

Whitaker, Sterling R.

1992-01-01

85

Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits  

Microsoft Academic Search

In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.

Wojciech Maly

1985-01-01

86

NASA Space Engineering Research Center for VLSI System Design  

NASA Technical Reports Server (NTRS)

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

1993-01-01

87

A coherent VLSI design environment  

NASA Astrophysics Data System (ADS)

This report covers the period from October 1, 1984 through March 31, 1985. The research discussed here is described in more detail in several published and unpublished reports cited below. Several fundamental bounds on the complexity of network architecture, parallel computation, VLSI design, and algorithms have been established and/or improved during this period. The grid-matching problem, of importance to wafer-scale integration, is close to solution, Improved algorithms for two-layer channel routing have been developed. The fat-tree interconnection network has been studied further, and a better algorithm for on-line routing of messages in this network has been developed. There is continued interest in compaction, and a provably fast algorithm for solving constraint systems has been devised. The CAD frame Schema has been solidified in several ways during this period. It is now possible to use Schema as a schematic capture and data storage system, There is better support being developed for PC-board designs. Some advanced ideas in describing waveforms qualitatively are being incorporated. A novel PROM device that is UV-enabled for writing has been designed and tested. The tradeoff between speed and fault probability in A/D converters has been viewed from a new angle.

Penfield, P., Jr.; Glasser, L. A.; Knight, T. F., Jr.; Leiserson, C. E.; Rivest, R. L.

1985-03-01

88

Stencil Printing Technology for Wafer Level Bumping at sub-100 Micron Pitch Using Pb-Free Alloys  

Microsoft Academic Search

In this paper solder paste printing is reported at sub 100mum pitch using Pb-free solder paste with IPC type-6 (15-5|im) particle size distributions. The results confirm that consistent sized paste deposits can be produced onto wafers at ultra fine pitch geometries using a stencil printing process. Furthermore, a stencil printing evaluation has determined the impact that the print parameters have

R. W. Kay; E. de Gourcuff; M. P. Y. Desmulliez; G. J. Jackson; H. A. H. Steen; C. Liu; P. P. Conway

2005-01-01

89

The quality of 200 mm diameter epitaxial Si wafers for advanced CMOS technology monitored using synchrotron X-ray topography  

Microsoft Academic Search

The control and characterisation of wafer defect and strain distributions is of crucial importance for the development of advanced Ultra Large Scale Integration (ULSI) circuits. Within the IC manufacturing sector 0.35 ?m linewidth-based advanced Complementary Metal Oxide Semiconductor (CMOS) logic has recently emerged at a high level of maturity, to be closely followed by an even more demanding 0.25 ?m

Patrick J. McNally; A. N. Danilewsky; J. W. Curley; A Reader; R. Rantamäki; T. Tuomi; M. Bolt; M. Taskinen

1999-01-01

90

Silicon Wafer Epitaxy  

NSDL National Science Digital Library

This Quicktime animation shows an optional process for creating silicon epitaxial wafers. The animations shows a trichlorosilane gas being injected which creates a monocrystaline film atop the preexisting wafer. This is the seventh animation in a series of how silicon wafers are created. The previous animation showing silicon wafer polishing can be seen here.The next and final animation in this sequence about silicon wafer laser inspection can be seen here.

91

Wafer-Level ANA Calibrations at NIST  

Microsoft Academic Search

The National Institute of Standards and Technology has begun a program supporting on-wafer scattering parameter measurements. In contrast to many previous NIST endeavors, this program seeks to transfer methodology into industrial measurement laboratories. The subject of this paper is the development of calibration techniques and algorithms, rather than physical standards, for the measurement of on-wafer scattering parameters. In particular, we

Roger Marks; Kurt Phillips

1989-01-01

92

Atmospheric downstream plasma etching of Si wafers  

Microsoft Academic Search

A dry etch technology for processing Si wafers using an atmospheric downstream plasma (ADP) source is described. Application of ADP etching for backside damage removal after grinding and wafer thinning is discussed. ADP is an inert gas thermal plasma generated by DC discharge at atmospheric pressure in the process chamber. The reactant (freon) is injected into the plasma stream outside

Oleg Siniaguine

1998-01-01

93

Exploring the VLSI Scalability of Stream Processors  

Microsoft Academic Search

Stream processors are high-performance programmable processors optimized to run media applications. Recent work has shown these processors to be more area- and energy-efficient than conventional programmable architec- tures. This paper explores the scalability of stream archi- tectures to future VLSI technologies where over a thousand floating-point units on a single chip will be feasible. Two techniques for increasing the number

Brucek Khailany; William J. Dally; Scott Rixner; Ujval J. Kapasi; John D. Owens; Brian Towles

2003-01-01

94

Electron multi-beam technology for mask and wafer writing at 0.1nm address grid  

NASA Astrophysics Data System (ADS)

An overview of electron beam tool configurations is provided. The adoption of multi-beam writing is mandatory in order to fulfill industrial needs for 11nm HP nodes and below. IMS Nanofabrication realized a 50keV electron multibeam proof-of-concept (POC) tool confirming writing principles with 0.1nm address grid and lithography performance capability. The new architecture will be introduced for mask writing at first, but has also the potential for 1xmask (master template) and direct wafer writing. The POC system achieves the predicted 5nm 1sigma blur across the 82?m x 82?m array of 512 x 512 (262,144) programmable 20nm beams. 24nm HP has been demonstrated and complex patterns have been written in scanning stripe exposure mode. The first production worthy system for the 11nm HP mask node is scheduled for 2014 (Alpha), 2015 (Beta) and 1st generation HVM mask writer tools in 2016. Implementing a multi-axis column configuration, 50x / 100x productivity enhancements are possible for direct 300mm / 450mm wafer writing.

Platzgummer, Elmar; Klein, Christof; Loeschner, Hans

2013-03-01

95

Parallel VLSI Architecture  

NASA Technical Reports Server (NTRS)

Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

1985-01-01

96

Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects  

Microsoft Academic Search

We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after

G. Anelli; M. Campbell; M. Delmastro; F. Faccio; S. Floria; A. Giraldo; E. Heijne; P. Jarron; K. Kloukinas; A. Marchioro; P. Moreira; W. Snoeys

1999-01-01

97

Scheduling semiconductor wafer fabrication  

Microsoft Academic Search

The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

LAWRENCE M. WEIN

1988-01-01

98

Silicon Wafer Polishing  

NSDL National Science Digital Library

This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

99

Role of wafer geometry in wafer chucking  

NASA Astrophysics Data System (ADS)

Wafer chucks are used in advanced lithography systems to hold and flatten wafers during exposure. To minimize defocus and overlay errors, it is important that the chuck provide sufficient pressure to completely chuck the wafer and remove flatness variations across a broad range of spatial wavelengths. Analytical and finite element models of the clamping process are presented here to understand the range of wafer geometry features that can be fully chucked with different clamping pressures. The analytical model provides a simple relationship to determine the maximum feature amplitude that can be chucked as a function of spatial wavelength and chucking pressure. Three-dimensional finite element simulations are used to examine the chucking of wafers with various geometries, including cases with simulated and measured shapes. The analytical and finite element results both demonstrate that geometry variations with short spatial wavelengths (e.g., high-frequency wafer shape features) present the greatest challenge to achieving complete chucking. The models and results presented here can be used to provide guidance on wafer geometry and chuck designs for advanced exposure tools.

Turner, Kevin T.; Ramkhalawon, Roshita; Sinha, Jaydeep K.

2013-04-01

100

Silicon Wafer Lapping  

NSDL National Science Digital Library

This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

101

Dictionary machine (for VLSI)  

SciTech Connect

The authors present the design of a dictionary machine that is suitable for VLSI implementation, and discusses how to realize this implementation efficiently. The machine supports the operations of search, insert, delete, and extractment on an arbitrary ordered set. Each of these operations takes time o(logn), where n is the number of entries present when the operation is performed. Moreover, arbitrary sequences of these instructions can be pipelined through the machine at a constant rate (i.e. independent of n and the capacity of the machine). The time o(logn) is an improvement over previous VLSI designs of dictionary machines which require time o(log n) per operation, where n is the maximum number of keys that can be stored. 10 references.

Ottmann, T.A.; Rosenberg, A.L.; Stockmeyer, L.J.

1982-09-01

102

Wafer capping of MEMS with fab-friendly metals  

NASA Astrophysics Data System (ADS)

Inertial MEMS (Micro Electro Mechanical System) sensors are normally sealed in hermetic enclosures. Some are assembled in hermetic packages but wafer level packaging has become much more important in recent years. Anodic bonding can be used to achieve wafer level seals between silicon and glass but most suppliers of inertial sensors screen print glass frit onto silicon cap wafers. After removing the organic vehicle, these patterned cap wafers are sealed to device wafer prior to wafer singulation and plastic packaging. Anodic and glass frit bonding are both cost-effective. However, they impose size, quality and performance limitations. Wafer level sealing with a metal removes some of these limitations but introduces other concerns. This paper will review the current wafer level hermetic processes followed by a description of a thermocompression metal seal technology that is compatible with IC fabrication.

Martin, Jack

2007-01-01

103

Hydrophobic silicon wafer bonding  

NASA Astrophysics Data System (ADS)

Wafers prepared by an HF dip without a subsequent water rinse were bonded at room temperature and annealed at temperatures up to 1100 °C. Based on substantial differences between bonded hydrophilic and hydrophobic Si wafer pairs in the changes of the interface energy with respect to temperature, secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM), we suggest that hydrogen bonding between Si-F and H-Si across two mating wafers is responsible for room temperature bonding of hydrophobic Si wafers. The interface energy of the bonded hydrophobic Si wafer pairs does not change appreciably with time up to 150 °C. This stability of the bonding interface makes reversible room-temperature hydrophobic wafer bonding attractive for the protection of silicon wafer surfaces.

Tong, Q.-Y.; Schmidt, E.; Gösele, U.; Reiche, M.

1994-01-01

104

ATM in B-ISDN communication systems and VLSI realization  

NASA Astrophysics Data System (ADS)

The VLSI trends and how VLSI's can be used to achieve Asynchronous Transfer Mode (ATM) switching node systems for B-ISDN were discussed. Implementing a practical ATM node system will need the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service controls need several hundred thousand logic gates and several megabytes of high-speed static RAM. ATM node system architecture was based on design concepts of a building-block-type configuration and hierarchical multiplexing. Moreover, future ATM node systems are considered on the basis of 0.2 micron VLSI development trends and hardware prerequisites.

Koinuma, Takeo; Miyaho, Noriharu

1995-04-01

105

Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics  

SciTech Connect

Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

None

2010-01-15

106

Robust Si wafer  

Microsoft Academic Search

Heavily B- and Ge-codoped Si wafers with and without swirl defects have been characterized in comparison with lightly B-doped and heavily B-doped Si wafers (with and without swirl defects) as references. It was found that only very few slip dislocations could be observed in the heavily B- and Ge-codoped (1019atoms\\/cm3) Si wafers whereas many slip dislocations were observed in both

Xinming Huang; Tsuyoshi. Sato; Masami Nakanishi; Toshinori Taishi; Keigo Hoshikawa; Satoshi Uda

2005-01-01

107

Internal thermal resistance of a multi-chip packaging design for VLSI based systems  

Microsoft Academic Search

A heat-transfer study is conducted for the steady-state internal thermal resistance of a multichip packaging technology for VLSI-based systems. This technology, which is known as advanced VLSI packaging (AVP), has chips flip-chip soldered and interconnected on a silicon substrate. AVP's thermal management approach is to dissipate chip power through the silicon substrate to a heat sink or other packaging levels.

Y. C. Lee; H. T. Ghaffari; J. M. Segelken

1989-01-01

108

Wafer Pattern Defect Detection: An Automatic Inspection Technique  

NASA Astrophysics Data System (ADS)

A system to automatically inspect wafers for pattern defects has recently been developed. With this apparatus, the patterns of two neighboring chips are converted into video signals, which are then electronically compared by sophisticated hybrid circuitry to determine any differences between them. The discrepancies, if any, are recognized as defects. The inspection results are processed with a built-in microcomputer and the defect coordinates are stored in memory. By accessing them, the wafer is moved into exact position for post-inspection confirmation and close examination of each defect by the operator through a microscope. The defective wafer pattern is also displayed on a video monitor. In addition, it is possible to draw a defect map by utilizing an X-Y plotter interfaced to the inspection system. The system is equipped with two inspection modes for maximum versatility. The video signal can be generated by either bright-field or dark-field imaging methods. The user may therefore select the mode most compatible to a specific wafer and its requirements. Typical applications of this system include: - to detect pattern defects on the finished wafer (after photoresist developing an e, etching) that may have occured during the various production processes. - to detect repeating defects resulting from inconsistencies on an arrayed reticle used in the wafer stepping process. (The importance of this feature will become increas-ingly evident as direct wafer steppers become the workhorses of the VLSI era.) - to monitor various processing factors, such as foreign particle contamination. The performance and efficiency of such an automatic wafer inspection system will undoubtedly lead to its replacing the current conventional method of manual microscopic examination by the human eye in the near future. This is supported by the inclusion of data collected by end users of this system.

Uchiyama, Yasushi; Awamura, Daikichi; Nakashima, Katsuyoshi

1983-11-01

109

Extremely long life and low-cost 193nm excimer laser chamber technology for 450mm wafer multipatterning lithography  

NASA Astrophysics Data System (ADS)

193nm ArF excimer lasers are widely used as light sources for the lithography process of semiconductor production. 193nm ArF exicmer lasers are expected to continue to be the main solution in photolithography, since advanced lithography technologies such as multiple patterning and Self-Aligned Double Patterning (SADP) are being developed. In order to apply these technologies to high-volume semiconductor manufacturing, the key is to reduce the total operating cost. To reduce the total operating cost, life extension of consumable part and reduction of power consumption are an important factor. The chamber life time and power consumption are a main factor to decide the total operating cost. Therefore, we have developed the new technology for extension of the chamber life time and low electricity consumption. In this paper, we will report the new technology to extend the life time of the laser chamber and to reduce the electricity consumption.

Tsushima, Hiroaki; Katsuumi, Hisakazu; Ikeda, Hiroyuki; Asayama, Takeshi; Kumazaki, Takahito; Kurosu, Akihiko; Ohta, Takeshi; Kakizaki, Kouji; Matsunaga, Takashi; Mizoguchi, Hakaru

2014-04-01

110

Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications  

E-print Network

Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications Fred Chen, Ajay Joshi of emerging interconnect technologies, such as carbon nanotubes (CNTs), in the context of system applications (ILD) stack-up and wire dimensions for different combinations of CNT and copper interconnects and vias

Joshi, Ajay

111

High-speed parallel CRC circuits in VLSI  

Microsoft Academic Search

The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should

Tong-Bi Pei; Charles Zukowski

1992-01-01

112

Multichip Packaging Design for VLSI-Based Systems  

Microsoft Academic Search

The introduction of many VLSI devices into system designs is placing new requirements on the packaging technologies that are used to interconnect devices and assemble systems. These requirements include the assembly of high pin out (up to 500 I\\/O's) devices, the ability to sustain synchronous system operation at frequencies up to 100 MHz, and cooling at thermal loads greater than

CHARLES J. BARTLETT; JOHN M. SEGELKEN; NICHOLAS A. TENEKETGES

1987-01-01

113

Titanic: a VLSI based content addressable parallel array processor  

SciTech Connect

A design is presented for a content addressable parallel array processor (CAPAP) which is both practical and feasible. Its practicality stems from an extensive program of research into real applications of content addressability and parallelism. The feasibility of the design stems from development under a set of conservative engineering constraints tied to limitations of VLSI technology. 1 ref.

Weems, C.; Levitan, S.; Foster, C.

1982-01-01

114

Carbon Nanotubes for VLSI: Interconnect and Transistor Applications  

Microsoft Academic Search

Carbon nanotubes (CNTs) offer unique properties such as the highest current density, ballistic transport, ultrahigh thermal conductivity, and extremely high mechanical strength. Because of these remarkable properties, they have been expected for use as wiring materials and as alternate channel materials for extending complementary metal-oxide-semiconductor (CMOS) performance in future very large scale integration (VLSI) technologies. In this paper, we report

Yuji Awano; Shintaro Sato; Mizuhisa Nihei; Tadashi Sakai; Yutaka Ohno; Takashi Mizutani

2010-01-01

115

UW VLSI chip tester  

NASA Astrophysics Data System (ADS)

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

McKenzie, Neil

1989-12-01

116

Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections  

NASA Astrophysics Data System (ADS)

Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.

Lin, Chiung-Wen; Yang, Hsueh-An; Wang, Wei Chung; Fang, Weileun

2007-06-01

117

VLSI Architectures for Computing DFT's  

NASA Technical Reports Server (NTRS)

Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

1986-01-01

118

Double metalization for VLSI  

NASA Technical Reports Server (NTRS)

Postsintering process increases yield of double-layer metal conductors to almost 100 percent. When wafers containing double-metalized chips are sintered, metal layers react with oxide film remaining in insulation layer holes, breaking it up so that it no longer impedes electric current. Cooling also mechanically disrupts oxide film.

Trotter, J. D.; Wade, T. E.

1980-01-01

119

Semiconductor wafer bonding  

NASA Astrophysics Data System (ADS)

When mirror-polished, flat, and clean wafers are brought into contact, they are locally attracted to each other and adhere or bond. This phenomenon is known as semiconductor wafer bonding. Different adhesion forces (van der Waals forces, hydrogen bonding) are the reason for the bonding effect at room temperature. The different bonding mechanisms acting in dependence on the surface conditions (hydrophilic, hydrophobic) are reviewed. Variations of the properties of bonded interfaces (structural, mechanical, electrical) during annealing are discussed. The focus is on low-temperature bonding techniques. Reasons for the formation of interface defects are presented. Applications of semiconductor wafer bonding for future developments are briefly summarized.

Reiche, M.

2006-03-01

120

Internal thermal resistance of a multi-chip packaging design for VLSI-based systems  

Microsoft Academic Search

A heat-transfer study is conducted to determine the steady-state internal thermal resistance of a multichip package for VLSI-based systems. The technology, which is known as advanced VLSI packaging (AVP), has flip-chip-soldered chips interconnected on a silicon substrate. AVPs thermal management approach is to dissipate chip power through the silicon substrate to a heat sink or other packaging levels. A three-dimensional

Y. C. Lee; H. T. Ghaffari; J. M. Segelken

1988-01-01

121

Improvement in WL-CSP reliability by wafer thinning  

Microsoft Academic Search

WL-CSP is a low profile, true chip sue package that is entirely built on a wafer using front-end and back end processing. The wafers can be batch-processed in a fab, which reduces the number of materials and packaging steps, reduces inventory, and allows for wafer level burn in and test. This technology is driven by cost, sue, and ease of

Li Wetz; Jeny White; Beth Keser

2003-01-01

122

Wafer characteristics via reflectometry  

DOEpatents

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

123

From Wafer to Package  

NSDL National Science Digital Library

This website includes an animation of finished wafer to packaged integrated Circuits. Objective: Describe the wafer to packaged device process steps. This simulation is from Module 075 of the Process & Equipment III Cluster of the MATEC Module Library (MML). You will find the animation under the heading "Process & Equipment III." To view other clusters or for more information about the MML visit http://matec.org/ps/library3/process_I.shtmlKey

124

Stable wafer-carrier system  

DOEpatents

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

125

Wafer-Level Encapsulation and Sealing of Electrostatic HARPSS Transducers  

E-print Network

Wafer-Level Encapsulation and Sealing of Electrostatic HARPSS Transducers Siavash Pourkamali* and Farrokh Ayazi School of Electrical and Computer Engineering, Georgia Institute of Technology Atlanta, GA-film wafer-level encapsulation technique for packaging and CMOS integration of MEMS sensors and actuators

Ayazi, Farrokh

126

Defect detection in unpolished Si wafers by digital shearography  

Microsoft Academic Search

Defects in silicon wafers have been of great scientific and technological interest since before the earliest days of the silicon transistor. Recently much attention has been focused on crystal originated pits on the polished surface of the wafer. These defects have been shown to contribute to gate dielectric breakdown. The present work relates to surface and\\/or subsurface defect inspection systems

Ganesha Udupa; B. K. A. Ngoi; H. C. Freddy Goh; M. N. Yusoff

2004-01-01

127

Wafer screening device and methods for wafer screening  

DOEpatents

Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

Sopori, Bhushan; Rupnowski, Przemyslaw

2014-07-15

128

Synaptic dynamics in analog VLSI.  

PubMed

Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties. PMID:17716003

Bartolozzi, Chiara; Indiveri, Giacomo

2007-10-01

129

IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. XX, NO. Y, MONTH 1999 101 The Design of an SRAMBased  

E-print Network

IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. XX, NO. Y, MONTH 1999 101 The Design of an SRAM­Based Field of Electri­ cal and Computer Engineering at the University of Toronto. Soon Seo is now with ATI Technologies

Rose, Jonathan

130

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness  

SciTech Connect

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

Fong, Theodore E.

2013-05-06

131

Recursive computer architecture for VLSI  

SciTech Connect

A general-purpose computer architecture based on the concept of recursion and suitable for VLSI computer systems built from replicated (lego-like) computing elements is presented. The recursive computer architecture is defined by presenting a program organisation, a machine organisation and an experimental machine implementation oriented to VLSI. The experimental implementation is being restricted to simple, identical microcomputers each containing a memory, a processor and a communications capability. This future generation of lego-like computer systems are termed fifth generation computers by the Japanese. 30 references.

Treleaven, P.C.; Hopkins, R.P.

1982-01-01

132

AWV: high-throughput cross-array cross-wafer variation mapping  

NASA Astrophysics Data System (ADS)

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

2008-03-01

133

High-density, large scale interconnection for improved VLSI system performance  

Microsoft Academic Search

Improved VLSI chip technology has resulted in vast improvements in the performance of electronic systems. The limitations imposed by conventional chip packaging technology are now a major impediment to further improvement at the system level. Thus we are now placing new requirements on the packaging technologies that are used to interconnect devices and assemble systems. These requirements include the assembly

1987-01-01

134

Surface activation enhanced low temperature silicon wafer bonding  

NASA Astrophysics Data System (ADS)

Direct wafer bonding technology has received great attention since 1985. It enables to realize the novel combinations of different materials for expanded functionality and provides a versatile device technology for transferring device layers to another wafer for further processing or device integration onto one wafer. Silicon direct wafer bonding has found a wide range of applications including Silicon-on-Insulator (SOI) wafers, micromechanical devices, and sensors and actuators. One of the challenges facing this technology is to achieve strong bonding at low temperatures that can survive post-wafer bonding processing. This dissertation presents the results of developing new wafer bonding processes for achieving high bonding energy at low temperatures. For thermal oxide covered silicon wafer bonding, dilute HF solution has been used to etch the wafers prior to room temperature bonding. The bonding energy has been significantly enhanced which reached silicon fracture energy after annealed at 100°C for 45 hours. For native oxide covered silicon wafers, the pre-treatment in dilute HNO3 and dilute HF mixtures has been found to be able to enhance the bonding energy at low temperatures. This is attributed to the incorporation of fluorine in native oxide during the pre-treatment. Various approaches have also been explored for hydrophobic silicon wafer bonding. Both boron doped surface layers and the amorphous surface layers have demonstrated an ability to significantly enhance the bonding energy at low temperatures, with silicon fracture energy achieved at 300--400°C for hydrophobically bonded pairs. The thermal management of heterojunction bipolar transistor (HBT) circuits fabricated by Symmetric Intrinsic HBT (SIHBT) processing was also studied in this research project using simulation method. Design criteria of selecting the surrogate substrates, interconnection dimension, and dielectric materials for the optimization of thermal management have been obtained.

Gan, Qing

135

Structured wafer for device processing  

DOEpatents

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Okandan, Murat; Nielson, Gregory N

2014-11-25

136

Structured wafer for device processing  

DOEpatents

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Okandan, Murat; Nielson, Gregory N

2014-05-20

137

Scanning holographic scatterometer for wafer surface inspection  

NASA Astrophysics Data System (ADS)

The semiconductor industry requires ever smaller semiconductor structures with faster response times and more function per unit area of each chip. In addition, the industry is changing from 200 mm to 300 mm diameter wafers with fewer defects and rapid detection at all processing stages. To meet these needs, defect data must be processed in near-real-time to expedite correction of processing problems at the earliest possible stage. Under a Small Business Innovation Research (SBIR) program, sponsored by the Air Force Manufacturing Technology Division at Wright Laboratory, Dayton, Ohio, Sentec Corporation has developed a revolutionary technology for contaminant particle detection on unpatterned semiconductor wafers. A key to the Sentec technology is detection, not of the intensity of backscattered energy from particles or defects, but of the amplitude of the electro-magneitc field of this backscattered energy. This new technology will allow the detection of particles that are significantly smaller than those which can be reliably located using current scatterometers. The technical concepts for a stand-alone particle detection tool have been created. It uses a continuous scanning mechanism to perform high-speed examinations of target wafers. This tool, also, has the capability of quantifying the microroughness or background haze of a subject wafer and presenting that information separate from the contamination particle data. During the course of this project, three patent applications were filed.

Klooster, Alex; Marks, James; Hanson, Kael; Sawatari, Takeo

2004-05-01

138

Economic analysis of 450mm wafer migration  

Microsoft Academic Search

To achieve the required continuous cost reduction driven by Moore's Law, both miniaturization through technology advances and wafer size increase have been employed in order to maintain the growth and profitability of semiconductor industry. Although some technical analyses have been done for 450 mm migration, little research has been done on economic analysis to justify the decisions and thus suggest

Chen-Fu Chien; J. K. Wang; Tzu-Ching Chang; Wen-Chin Wu

2007-01-01

139

Wafer-level sandwiched packaging for high-yield fabrication of high-performance mems inertial sensors  

Microsoft Academic Search

A wafer-level sandwiched packaging technology is developed for micromechanical sensors such as inertial sensors, which comprise movable parts, e.g. spring-mass structures. Via a thin polymer intermediate layer of benzocyclobuene (BCB), a pre-micromachined silicon cap wafer is aligned bonded with the sensor-chip wafer. Prior to the BCB bonding, the sensor-chip wafer was formed by anodic bonding a Pyrex-7740 glass wafer to

Kun Zhang; Wei Jiang; Xinxin Li

2008-01-01

140

Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs  

E-print Network

architectures/technologies for future chips is wafer-level three-dimensional (3D) integration [1,2], i approach, where fully processed wafers (with multilevel on-chip interconnects) are aligned and bonded thermal- coefficient-of-expansion (TCE) matched glass wafers, (2) mechanical bonding strength tests using

Salama, Khaled

141

Closed-loop electroosmotic microchannel cooling system for VLSI circuits  

Microsoft Academic Search

The increasing heat generation rates in VLSI circuits motivate research on compact cooling technologies with low thermal resistance. This paper develops a closed-loop two-phase microchannel cooling system using electroosmotic pumping for the working fluid. The design, fabrication, and open-loop performance of the heat exchanger and pump are summarized. The silicon heat exchanger, which attaches to the test chip (1 cm2),

Linan Jiang; James Mikkelsen; Jae-Mo Koo; David Huber; Shuhuai Yao; Lian Zhang; Peng Zhou; James G. Maveety; Ravi Prasher; Juan G. Santiago; Thomas W. Kenny; Kenneth E. Goodson

2002-01-01

142

A VLSI Modulo m Multiplier  

Microsoft Academic Search

A novel method to compute the exact digits of the modulo m product of integers is proposed, and a modulo m multiply structure is defined. Such a structure can be implemented by means of a few fast VLSI binary multipliers, and a response time of about 150-200 ns to perform modular multiplications with moduli up to 32767 can be reached.

Giuseppe Alia; Enrico Martinelli

1991-01-01

143

Etching Of Semiconductor Wafer Edges  

DOEpatents

A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

2003-12-09

144

The Fifth NASA Symposium on VLSI Design  

NASA Technical Reports Server (NTRS)

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

1993-01-01

145

30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology  

NASA Technical Reports Server (NTRS)

An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

1986-01-01

146

Proceedings of the Low-Cost Solar Array Wafering Workshop  

NASA Technical Reports Server (NTRS)

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

Morrison, A. D.

1982-01-01

147

Wafer bonding : mechanics-based models and experiments  

E-print Network

Direct wafer bonding has emerged as an important technology in the manufacture of silicon-on-insulator substrates (SOI), microelectromechanical systems (MEMS), and three-dimensional integrated circuits (3D IC's). While the ...

Turner, Kevin Thomas, 1977-

2004-01-01

148

Investigation of silicon wafering by wire EDM  

Microsoft Academic Search

The new technology of silicon wafering by wire electrodischarge machining (EDM) was investigated to determine its mechanism of current-conducting and material removal. Target materials were n-type single-crystal silicon ingots with the resistivity of 7–15 cm?. It was found that the surface potential barrier of the semiconductors had a dominating effect on EDM cutting speed. Technological experiments were performed to determine

Y. F. Luo; C. G. Chen; Z. F. Tong

1992-01-01

149

VLSI architecture for concurrent data structures  

SciTech Connect

Concurrent data structures simplify the development of concurrent programs by encapsulating commonly used mechanisms for synchronization and communication into data structures. This thesis develops a notation for describing concurrent data structures, presents examples of concurrent data structures, and describes an architecture to support concurrent data structures. Concurrent Smalltalk (CST), a derivative of Smalltalk-80 with extensions for concurrency, is developed to describe concurrent data structures. CST allows the programmer to specify objects that are distributed over the nodes of a concurrent computer. These distributed objects have many constituent objects and thus can process many messages simultaneously. They are the foundation upon which concurrent data structures are built. Considering graphs as concurrent data structures, graph algorithms are presented for the shortest-path problem, the max-flow problem, and graph partitioning. These algorithms introduce new synchronization techniques to achieve better performance than existing algorithms. A message passing, concurrent architecture is developed that exploits the characteristics of VLSI technology to support concurrent data structures.

Dally, W.J.

1986-01-01

150

Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter  

NASA Technical Reports Server (NTRS)

The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

Chen, C. P.; Leipold, M. H.

1984-01-01

151

Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding  

Microsoft Academic Search

This paper presents on a novel chip-to-wafer (C2W) three- dimensional (3D) integration technology with well-controlled template alignment and wafer-level bonding, enabling precise alignment, few thermal cycles and high throughput of 3D system fabrication. The key processes are investigated and discussed in detail, including chip edge definition, template fabrication, C2W alignment and wafer-level bonding. The C2W 3D integration technology is successfully

Qianwen Chen; Dingyou Zhang; Zheyao Wang; Litian Liu; James Jian-Qiang Lu

2011-01-01

152

1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics  

SciTech Connect

The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

Lorenz, Adam [1366 Technologies] [1366 Technologies

2013-08-30

153

?-Device fabrication and packaging below 300°C utilizing plasma-assisted wafer-to-wafer bonding  

NASA Astrophysics Data System (ADS)

Wafer-to-wafer bonding techniques, such as anodic bonding or high temperature silicon direct fusion bonding, have been in development since the late 1960's and became key technologies for MEMS manufacturing. Plasma assisted wafer bonding is an emerging method offering several advantages over traditional bonding techniques. This technology was first discovered and patented in the early 1990's and has been used in SOI production for the past five years. Now plasma activation benefits are being used to enable 3D integration and advanced MEMS device fabrication and packaging. The main advantage of plasma assisted bonding is that high strength direct bonds between substrates, like Si, glass or polymers, can be achieved already below 300°C.

Kirchberger, Herwig; Pelzer, Rainer; Farrens, Sharon

2006-01-01

154

Fully-depleted silicon-on-sapphire and its application to advanced VLSI design  

NASA Technical Reports Server (NTRS)

In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

Offord, Bruce W.

1992-01-01

155

Gallium Arsenide wafer scale integration  

NASA Astrophysics Data System (ADS)

Gallium Arsenide (GaAs) digital MESFET technology has recently begun to appear in the semiconductor marketplace. The initial commercial offerings are at the small to medium scale integration levels. The high speed of these parts would seem to be very attractive for designers of high performance signal processing equipment. Persistent yield problems, however, have prevented the appearance of large scale integrated circuits. As a result, intrapackage and interpackage signal propagation problems such as coupling, parasitics and delay are likely to negate much of the benefits of the fast MESFET logic devices for large systems constructed with such small scale building blocks. An early packaging concept, Wafer Scale Integration (WSI), which could possibly be used to address some of these limitations is reexamined.

McDonald, J. F.; Taylor, G.; Steinvorth, R.; Donlan, B.; Bergendahl, A. S.

1985-08-01

156

A second generation 50 Mbps VLSI level zero processing system prototype  

NASA Technical Reports Server (NTRS)

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

1994-01-01

157

Wafer Level Packaging by residual stress evaluation using piezoresistive stress sensors for the enhancement of reliability  

Microsoft Academic Search

Wafer Level Packaging (WLP) is the technology which it is an IC package completely fabricated at the wafer level and assembled with standard SMT. WLP technology is one of promising technology which make it possible a low-cost and a high reliability packaging. Significant reductions in device form factor and cost have been achieved, while at the same time increasing the

Seung Seoup Lee; Jong Whan Baik; Jin Soo Kiml; Hyung Jin Jeon; Sung Yil

2008-01-01

158

Wafer-scale micro-optics fabrication  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Voelkel, Reinhard

2012-07-01

159

Novel 1.3-micron high-speed directly modulated semiconductor laser device designs and the development of wafer bonding technology for compliant-substrate fabrication  

NASA Astrophysics Data System (ADS)

High speed optical sources at 1.3 mum are required to drive the fiber optic infrastructure around the world. Of the three components that make up an optical link, these sources limit the overall data transmission capacity of these networks. The importance of operating at 1.3 mum, has led device engineers to rely on InP-based devices, though inferior in many ways to devices based on GaAs. This work seeks to develop new device designs to improve the directly modulated bandwidths of 1.3 mum lasers. Elevated temperatures degrade the DC and high speed performance of semiconductor lasers. InP-based devices are especially susceptible to temperature variations. Lasers were flip chip bonded to diamond heat sinks to improve heat removal from these devices. Although dramatic improvements were seen in their DC performance, the lasers' high frequency response did not improve. Other factors such, as carrier heating, likely limited the performance of these devices. Device designs on GaAs emitting at 1.3 mum were sought as a replacement for the troublesome InP devices. Laser structures employing ordered quantum wells on GaAs (111) substrates have been proposed. Theoretical calculations indicate that 1.3 mum emission should be achievable, and 1.55 mum emission may be possible. Experimental evidence from devices based on GaAs (111) indicates that such lasers should outperform their InP-based counterparts. Lasers grown on InGaAs-like substrates, either bulk ternary or compliant substrates, are promising candidates for improving 1.3 mum device performance. In anticipation of availability of such substrates, a toolkit for designing InxGa1--xAs quantum well lasers on InyGa 1--yAs substrates has been developed. The choice of well and substrate compositions, well width and desired percentage strain combinations emitting at 1.3 mum can be made using a few simple graphs. An analytical valence band model has been employed to qualitatively test competing device designs. Twist bonded compliant substrate production requires the wafer fusion of two substrates. A wafer bonding system has been designed, built and tested to improve wafer bonding techniques for this application. This machine's scalable design is capable of improved reproducibility, uniformity and yield over comparable techniques.

Greenberg, Joseph

2000-10-01

160

Optical pressure sensor head fabrication using ultrathin silicon wafer anodic bonding  

Microsoft Academic Search

A technology for fabricating fiber optically interrogated pressure sensors is described. This technology is based on anodic bonding of ultra-thin silicon wafers to patterned, micro-machined glass wafers, providing low-cost fabrication of optical pressure sensor heads that operate with reproducible technical characteristics in various dynamic ranges. Pressure sensors using 10, 20 and 50 micron thick silicon wafers for membranes have been

Michael H. Beggans; Dentcho I. Ivanov; Steven G. Fu; Thomas G. Digges; Kenneth R. Farmer

1999-01-01

161

Accelerating litho technology development for advanced design node flash memory FEOL by next-generation wafer inspection and SEM review platforms  

NASA Astrophysics Data System (ADS)

Development of an advanced design node for NAND flash memory devices in semiconductor manufacturing requires accelerated identification and characterization of yield-limiting defect types at critical front-end of line (FEOL) process steps. This enables a shorter development cycle time and a faster production ramp to meet market demand. This paper presents a methodology for detecting defects that have a substantial yield impact on a FEOL after-develop inspection (ADI) layer using an advanced broadband optical wafer defect inspector and a scanning electron microscope (SEM) review tool. In addition, this paper presents experimental data that demonstrates defect migration from an ADI layer to an after-clean inspection (ACI) layer, and provides clear differentiation between yield-impacting critical defects and noncritical defects on the layers. The goal of these studies is to determine the feasibility of implementing an inspection point at ADI. The advantage of capturing yield-limiting defects on an ADI layer is that wafers can be reworked when an excursion occurs, an option that is not always possible for ACI layers. Our investigation is divided into two parts: (1) Inspection of an ADI layer with high sensitivity to find an accurate representation of the defect population and to gain understanding on the propagation of defects from the ADI layer to the ACI layer; and, (2) Inspection of an ACI layer to develop an understanding of unique defects generated by the ACI process step. Overall, this paper discusses the advantages of baselining defectivity at ADI process levels for accelerated development of advanced design node memory devices.

Lee, Byoung Ho; Ahn, Jeongho; Ihm, Dongchul; Chin, Soobok; Lee, Dong-Ryul; Choi, Seongchae; Lee, Junbum; Kang, Ho-Kyu; Sivaraman, Gangadharan; Yamamoto, Tetsuya; Lakhawat, Rahul; Sanapala, Ravikumar; Lee, Chang Ho; Lobo, Arun

2012-03-01

162

Development of a 2 micrometer silicon-gate-CMOS-technology for microcomputer oriented VLSI circuits with a supply voltage range between 1.5 and 5 V  

NASA Astrophysics Data System (ADS)

The processes necessary for a 2 micron CMOS-technology were developed, including projection lithography, the oxidation process, the fabrication of thin oxides, and dry etching techniques for patterning silicon nitride, polysilicon, silicon oxide, and aluminum. With the aid of process simulations and experimental results, a process flow chart was established. A test chip with a large number of single structures and circuit blocks was designed in 2 micron tubes. Different runs of this test chip are produced. The success of the developed technology is demonstrated on different logic circuit blocks.

Fischer, G.; Kiss, T.; Kummerow, K.; Link, M.; Scharzmann, U.

1984-10-01

163

Constant fan-in digital neural networks are VLSI-optimal  

SciTech Connect

The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

Beiu, V.

1995-12-31

164

Neural network control of a plasma gate etch: Early steps in wafer-to-wafer process control  

Microsoft Academic Search

A gate oxide thickness controller for a plasma etch reactor has been developed. This controller is for 0.9-?m technology. By monitoring certain processes, signatures are fed forward into a neural network trained by the backpropagation method. It is possible to predict in real time the correct over-etch time on a wafer-by-wafer basis. Computer simulations indicate that the neural network is

E. A. Rietman; S. H. Patel; E. R. Lory

1993-01-01

165

Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers  

Microsoft Academic Search

Through-silicon via (TSV) technology has been widely investigated recently for 3-D electronic packaging integration. Reducing TSV wafer warpage is one of the most challenging concerns for successfully subsequent processes. In this paper, a wafer-level warpage modeling methodology has been developed by the finite element analysis method using an equivalent material model. The developed modeling methodology has been verified by numerical

Faxing Che; Hongyu Y. Li; Xiaowu Zhang; Shan Gao; Kenghwa H. Teo

2012-01-01

166

Are Carbon Nanotubes the Future of VLSI Interconnections? Kaustav Banerjee and Navin Srivastava  

E-print Network

Are Carbon Nanotubes the Future of VLSI Interconnections? Kaustav Banerjee and Navin Srivastava, navins}@ece.ucsb.edu ABSTRACT Increasing resistivity of copper with scaling and rising demands on current technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address

167

The triangle processor and normal vector shader: a VLSI system for high performance graphics  

Microsoft Academic Search

Current affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated. Massively parallel VLSI system have the potential to bypass this bottleneck, but

Michael Deering; Stephanie Winner; Bic Schediwy; Chris Duffy; Neil Hunt

1988-01-01

168

The VLSI design of error-trellis syndrome decoding for convolutional codes  

NASA Technical Reports Server (NTRS)

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

1985-01-01

169

The VLSI design of an error-trellis syndrome decoder for certain convolutional codes  

NASA Technical Reports Server (NTRS)

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

1986-01-01

170

Importance of on-chip inductance in designing RLC VLSI interconnects  

Microsoft Academic Search

With deeper and faster VLSI technologies, on-chip inductance gained significance in the design of high-speed interconnects. This paper surveys the importance of on-chip inductance, its useful effects and the associated negative drawbacks. It also covers the existing RLC interconnect delay models and optimal repeater insertion methodologies.

Falah R. Awwad; Tawfeeq Lammoshi; Mohamed Nekili

2002-01-01

171

VLSI thermo-mechanical stress analysis by gradient direction sensor method  

Microsoft Academic Search

Silicon integrated sensors for thermo-mechanical stress measurement in VLSI (very large scale integration) has been studied extensively in recent years due to the increasing complexity of modern semiconductor devices. As chip size has increased continuously to accommodate more functions in modern integrated circuits (IC) technology, the stress induced in a chip from packaging combined with self heating becomes serious and

M. Bougataya; A. Lakhsasi; D. Massicotte

2005-01-01

172

VLSI layout for a pipelined dadda multiplier  

SciTech Connect

Parallel counters (unary-to-binary converters) are the principal component of a dadda multiplier. The authors specify a design first for a pipelined parallel counter, and then for a complete multiplier. As a result of its structural regularity, the layout is suitable for use in a VLSI implementation. They analyze the complexity of the resulting design using a VLSI model of computation, showing that it is optimal with respect to both its period and latency. In this sense the design compares favorably with other recent VLSI multiplier designs. 24 references.

Cappello, P.R.; Steiglitz, K.

1983-05-01

173

Systolic VLSI for Kalman filters  

NASA Technical Reports Server (NTRS)

A novel two-dimensional parallel computing method for real-time Kalman filtering is presented. The mathematical formulation of a Kalman filter algorithm is rearranged to be the type of Faddeev algorithm for generalizing signal processing. The data flow mapping from the Faddeev algorithm to a two-dimensional concurrent computing structure is developed. The architecture of the resulting processor cells is regular, simple, expandable, and therefore naturally suitable for VLSI chip implementation. The computing methodology and the two-dimensional systolic arrays are useful for Kalman filter applications as well as other matrix/vector based algebraic computations.

Yeh, H.-G.; Chang, J. J.

1986-01-01

174

Silicon cast wafer recrystallization for photovoltaic applications  

E-print Network

Current industry-standard methods of manufacturing silicon wafers for photovoltaic (PV) cells define the electrical properties of the wafer in a first step, and then the geometry of the wafer in a subsequent step. The ...

Hantsoo, Eerik T. (Eerik Torm)

2008-01-01

175

Wafer Fusion for Integration of Semiconductor Materials and Devices  

SciTech Connect

We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

1999-05-01

176

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied MaterialsĀ® and Nikon CorporationĀ®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

2009-03-01

177

VLED for Si wafer-level packaging  

NASA Astrophysics Data System (ADS)

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

178

Software Structuring Principles for VLSI CAD  

E-print Network

A frustrating aspect of the frequent changes to large VLSI CAD systems is that so little of the old available programs can be reused. It takes too much time and effort to find the reusable pieces and recast them for ...

Katzenelson, Jacob

1987-12-01

179

PARALLEL IMPLEMENTATION OF VLSI HED CIRCUIT SIMULATION  

E-print Network

14 PARALLEL IMPLEMENTATION OF VLSI HED CIRCUIT SIMULATION INFORMATICA 2/91 Keywords: circuit simulation, direct method, vvaveform relaxation, parallel algorithm, parallel computer architecture Srilata, India Junj Sile Marjan Spegel Jozef Stefan Institute, Ljubljana, Slovenia The importance of circuit

Silc, Jurij

180

Experimental study of restructurable VLSI techniques  

E-print Network

recent Restructurable VLSI developments. The research presented investigates some applications of a Nd:YAG laser system to restruc- turable VLSI. Integrated circuits used on the experiments are fabricated with a double polysilicon process. Good laser... formed connections are reported. Metal and upper polysilicon layers, metal and lower polysilicon layers, upper polysilicon and lower polysilicon layers can be connected by the laser beam. The I-V characteristics and temperature dependence associated...

Fanini, Otto Nilson

1982-01-01

181

Selecting Colors for Representing VLSI Layout Giordano Bruno Beretta  

E-print Network

Selecting Colors for Representing VLSI Layout Giordano Bruno Beretta #12;#12;Selecting Colors for Representing VLSI Layout Giordano Bruno Beretta EDL·88·7 December 1988 [P88·00226j © Copyright 1988 Xerox

Beretta, Giordano

182

A VLSI design concept for parallel iterative algorithms  

NASA Astrophysics Data System (ADS)

Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified ?-rotation CORDIC architecture.

Sun, C. C.; Götze, J.

2009-05-01

183

Plasma-assisted InP-to-Si low temperature wafer bonding  

Microsoft Academic Search

The applicability of wafer bonding as a tool to integrate the dissimilar material system InP-to-Si is presented and discussed with recent examples of InP-based optoelectronic devices on Si. From there, the lowering of annealing temperature in wafer bonding by plasma-assisted bonding is the essence of this review paper. Lower annealing temperatures would further launch wafer bonding as a competitive technology

Donato Pasquariello; Klas Hjort

2002-01-01

184

Wafer level warpage modeling methodology and characterization of TSV wafers  

Microsoft Academic Search

Through-silicon-via (TSV) approach has been widely investigated recently for three-dimensional (3D) electronic packaging integration. TSV wafer warpage is one of the most challenges for successfully subsequent processes. In this work, wafer level warpage modeling methodology has been developed by finite element analysis (FEA) method using equivalent material model. The developed modeling methodology has been verified by numerical results and experiment

F. X. Che; H. Y. Li; Xiaowu Zhang; S. Gao; K. H. Teo

2011-01-01

185

Wafer level test solutions for IR sensors  

NASA Astrophysics Data System (ADS)

Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

Giessmann, Sebastian; Werner, Frank-Michael

2014-05-01

186

The 1991 3rd NASA Symposium on VLSI Design  

NASA Technical Reports Server (NTRS)

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

Maki, Gary K.

1991-01-01

187

System for slicing wafers  

NASA Technical Reports Server (NTRS)

A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

1982-01-01

188

Automated Measurement Procedures of Three-Port and Four-Port Devices on Silicon Wafers  

Microsoft Academic Search

The development of telecommunication networks and wireless systems has led to a continually increasing market for RF integrated circuits. The CMOS and BiCMOS silicon technologies are particularly attractive for the fabrication of these circuits because of the good performance of their transistors coupled with the low cost of production. They allow the development of very complex RF integrated circuits (RF-VLSI)

F. Rerat; J. L. Carbonero; G. Morin; B. Cabon

1997-01-01

189

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process  

NASA Astrophysics Data System (ADS)

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on–off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10?13–10?11 µm2/Hz for n-type and 10?12–10?10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

2015-04-01

190

Development of Megasonic cleaning for silicon wafers. Final report  

SciTech Connect

The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

Mayer, A.

1980-09-01

191

Scaling wafer stresses and thermal processes to large wafers 1 Presented at the TCMCTF '97. 1  

Microsoft Academic Search

Gravitational stresses limit maximum temperatures for processing semiconductor wafers. Allowable rates of heating and cooling are also limited by the combined affects of thermal and gravitational stresses, particularly in batch processing of stacked wafers. With increasing wafer diameter these limitations become more severe, requiring such measures as improved wafer support to maintain a desired processing temperature or increased wafer spacing

Robert H Nilson; Stewart K Griffiths

1998-01-01

192

A dielectrophoretic chip packaged at wafer level  

Microsoft Academic Search

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer\\u000a bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in\\u000a the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer\\u000a level) anodically and

Ciprian Iliescu; Francis E. H. Tay; Guolin Xu; Li Ming Yu; Victor Samper

2006-01-01

193

Seamless on-wafer integration of GaN HEMTs and Si(100) MOSFETs  

Microsoft Academic Search

The integration of III-V compound semiconductors and silicon (100) CMOS technologies has been a long pursued goal. A robust low-cost heterogeneous integration technology would make the outstanding analog and mixed-signal performance of compound semiconductor electronics available on an as-needed basis to realize key functions on VLSI chips that are difficult to implement in Si technology. In this paper, we demonstrate

J. W. Chung; J. Lee; E. L. Piner; T. Palacios

2009-01-01

194

Wafer level encapsulation - a transfer molding approach to system in package generation  

Microsoft Academic Search

Flip chip and wafer level CSP technology have been widely accepted as a means for maximum miniaturization. Both package types do not generally include an explicit encapsulation layer, but only die passivation and dielectric rewiring layers respectively. To fulfill the reliability demands of harsh environment applications, the use of an additional encapsulant is recommended. Processes for wafer level encapsulation include

T. Braun; K.-F. Becker; M. Koch; V. Bader; U. Oestermann; D. Manessis; R. Aschenbrenner; H. Reichl

2002-01-01

195

Resonance ultrasonic vibrations in Cz-Si wafers as a possible diagnostic technique in ion implantation  

Microsoft Academic Search

The semiconductor industry does not have effective metrology for well implants. The ability to measure such deep level implants will become increasingly important as we progress along the technology road map. This work explores the possibility of using the acoustic whistle effect on ion implanted silicon wafers. The technique detects the elastic stress and defects in silicon wafers by measuring

Z. Y. Zhao; S. Ostapenko; R. Anundson; M. Tvinnereim; A. Belyaev; M. Anthony

2001-01-01

196

Influence of intrinsic stresses on crystallographic defects distribution in Cz-Si wafers  

Microsoft Academic Search

The influence of intrinsic stress in silicon wafers during the Czochralski crystal growth process and during technological processing of semiconductor devices on defect distribution and yield was investigated. The determination method of intrinsic defect distribution by applying subtle flatness measurements (GFLT parameter) is proposed. Results of measurements are compared with calculated stress distributions. Defect density distributions measured on wafers subjected

T Piotrowski; W Jung

2000-01-01

197

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism  

Microsoft Academic Search

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP)

Chang-Chun Lee; Hsing-Chih Liu; Kuo-Ning Chiang

2007-01-01

198

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?  

NASA Astrophysics Data System (ADS)

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Green, Martin A.

2014-03-01

199

Design Technologies for Low Power VLSI  

Microsoft Academic Search

Low power has emerged as a principal theme in today's electronics indus- try. The need for low power has caused a major paradigm shift where power dis- sipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power cir- cuits and systems. It describes the many issues facing designers

Massoud Pedram

1997-01-01

200

Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature  

Microsoft Academic Search

Micromechanical smart sensor and actuator systems of high complexity bemme commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated to contain the readout circuits. The individually-processed wafers can be assembled using wafer-to-wafer bonding and can be combined to one single functional electro-mechanical unit using

K. D. Wise

1994-01-01

201

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.  

PubMed

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

2014-08-15

202

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers  

NASA Astrophysics Data System (ADS)

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

203

Wafer characteristics via reflectometry and wafer processing apparatus and method  

DOEpatents

An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

Sopori, Bhushan L. (Denver, CO)

2007-07-03

204

450mm wafer patterning with jet and flash imprint lithography  

NASA Astrophysics Data System (ADS)

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

205

Wafer level encapsulation for system in package generation  

Microsoft Academic Search

Within this paper, encapsulation technologies as transfer molding and printing have been investigated; focusing on the feasibility of reliable wafer encapsulation and the suitability of current materials. For these processes the potential of 3D structuring during the encapsulation has been evaluated. An electroless metallization process and laser techniques for structuring the metallization layer have been investigated for reliable interconnections. Summarized

T. Braun; K.-F. Becker; M. Koch; V. Bader; D. Manessis; A. Neumann; A. Ostmann; R. Aschenbrenner; H. Reichl

2003-01-01

206

Wafer level glass frit bonding for MEMS hermetic packaging  

Microsoft Academic Search

Wafer level bonding is widely applied in the manufacture of sensors, actuators and CMOS MEMS. Bonding technology includes direct bonding, anodic bonding, eutectic bonding, adhesive bonding and glass frit bonding. Glass frit bonding has pattern-able, excellent sealing performances, high bonding strength, don't need apply any voltage during bonding process and less CTE mismatch compared to glass and silicon is more

Jin-Sheng Chang; Jing-Yuan Lin; Shu-Ching Ho; Yao-Jung Lee

2010-01-01

207

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

208

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Vosen, Steven R. (Berkeley, CA)

1999-01-01

209

Associative Pattern Recognition In Analog VLSI Circuits  

NASA Technical Reports Server (NTRS)

Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

Tawel, Raoul

1995-01-01

210

Real-time inference in a VLSI spiking neural Dane Corneil, Daniel Sonnleithner, Emre Neftci, Elisabetta Chicca, Matthew Cook,  

E-print Network

of Excellence Bielefeld University, Germany Abstract--The ongoing motor output of the brain depends on its processes these data using networks of neurons that communicate by asynchronous spikes, a technology Integration (VLSI) [5] neurons that communicate by asynchronous events (spikes). Our neuromorphic network

211

MAPPER alignment sensor evaluation on process wafers  

NASA Astrophysics Data System (ADS)

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3? std) of alignment mark readings can be achieved while being robust against various process steps.

Vergeer, N.; Lattard, L.; de Boer, G.; Couweleers, F.; Dave, D.; Pradelles, J.; Bustos, J.

2013-03-01

212

Ultrathin wafer level chip size package  

Microsoft Academic Search

The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant

Avner Badihi

2000-01-01

213

A VLSI implementation and evaluation of a Signed Bit-Sequential Binary Multiplier  

E-print Network

) is described in this thesis. The SBSMX algorithm is investigated in order to first develop a system block diagram, and eventually an NMOS circuit design capable of implementing the signed multiplication in existing VLSI technology. New modular design..., the rapidly growing field of signal processing has created a demand for serial architecture in arithmetic hardware in order to accommodate a real-time environment where digital signals are transmitted and processed in serial form. Furthermore, the trend...

McCullin, James Edward

1982-01-01

214

A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases  

NASA Technical Reports Server (NTRS)

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to Berlekamp; the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in different areas. Finally, they are implemented on silicon chips with nitride metal oxide semiconductor technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.

Hsu, I. S.; Truong, T. K.; Deutsch, L. J.; Reed, I. S.

1988-01-01

215

A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases  

NASA Astrophysics Data System (ADS)

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to Berlekamp; the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in different areas. Finally, they are implemented on silicon chips with nitride metal oxide semiconductor technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.

Hsu, I. S.; Truong, T. K.; Deutsch, L. J.; Reed, I. S.

1988-06-01

216

Modeling concepts for VLSI CAD objects  

Microsoft Academic Search

VLSI CAD applications deal with design objects that have an interface description and an implementation description. Versions of design objects have a common interface but differ in their implementations. A molecular object is a modeling construct which enables a database entity to be represented by two sets of heterogeneous records, one set describes the object's interface and the other describes

Don S. Batory; Won Kim

1985-01-01

217

The theory of signature testing for VLSI  

Microsoft Academic Search

Several methods for testing VLSI chips can be classified as signature methods. Both conventional and signature testing methods apply a number of test patterns to the inputs of the circuit. The difference is that a conventional method examines each output, while a signature method first accumulates the outputs in some data compression device, then examines the signature - the final

J. Lawrence Carter

1982-01-01

218

SSI/MSI/LSI/VLSI/ULSI.  

ERIC Educational Resources Information Center

Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

Alexander, George

1984-01-01

219

Delay and power optimization in VLSI circuits  

Microsoft Academic Search

The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macromodels are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.

Lance A. Glasser; Lennox P. J. Hoyte

1984-01-01

220

Optimal mesh algorithms for VLSI routing  

Microsoft Academic Search

Optimal mesh algorithms are developed for several VLSI routing problems, such as river routing between rectangles, routing within a rectilinear polygon, and wiring module pins to frame pads. It is assumed that the mesh consists of ?n×?n processors, where n is the input size. Each processor has a constant amount of memory. All the algorithms run in time O(?n ).

Shing-Chong Chang; J. JaJa

1988-01-01

221

Analysis and Design of Resilient VLSI Circuits  

E-print Network

are fast and accurate compared to SPICE. Therefore, these analysis approaches can be easily integrated in a VLSI design flow to analyze the radiation tolerance of such circuits, and harden them early in the design flow. From 3D device-level analysis...

Garg, Rajesh

2010-07-14

222

On Modeling Top-down VLSI Design  

Microsoft Academic Search

We present an improved data model that rejects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept that describes the convergence of a design. The design history which makes the semantics of most other version concepts, is modeled explicitly by additional object classes (entities types) but not by

Bernd Schurmann; Joachim Altmeyer; Martin Schiitze

1994-01-01

223

Silicon Wafer Processing Dr. Seth P. Bates  

E-print Network

Silicon Wafer Processing Dr. Seth P. Bates Applied Materials Summer, 2000 Objective To provide from blank silicon wafers. Goals The Transfer Plan provides a curriculum covering the process of manufacturing integrated circuits from the silicon wafer blanks, using the equipment manufactured by Applied

Colton, Jonathan S.

224

Dicing of optical wafer level packages  

Microsoft Academic Search

The optical wafer level packaging, developed by Schott Advanced Packaging, consists of a Silicon wafer, comprising the optical sensors, which is bonded to a glass wafer in the very first process step to protect the sensors. The package utilizes a via through contact through the Silicon by contacting the bond pads of the image sensor from the backside. By this

Dennis Tangaha; Florian Bieck

2006-01-01

225

Wafer scale photonic-die attachment  

Microsoft Academic Search

A diebonding system has been developed for the bonding of photonic chips, such as lasers and photo detectors, at a rate suitable for low cost manufacturing. This system is designed for wafer scale diebonding, making it compatible with wafer scale fabrication. This system combines the passive positional optical alignment of photonic chips on a silicon or glass wafer board surface

Robert Boudreau; Ping Zhou; Terry Bowen

1998-01-01

226

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

227

A radix-8 wafer scale FFT processor  

Microsoft Academic Search

Wafer Scale Integration promises radical improvements in the performance of digital signal processing systems. This paper describes the design of a radix-8 systolic (pipeline) fast Fourier transform processor for implementation with wafer scale integration. By the use of the radix-8 FFT butterfly wafer that is currently under development, continuous data rates of 160 MSPS are anticipated for FFTs of up

Earl E. Swartzlander Jr.; Vijay K. Jain; Hiroomi Hikawa

1992-01-01

228

Wafer bonding of 75 mm diameter GaP to AlGaInP-GaP light-emitting diode wafers  

Microsoft Academic Search

The AlGaInP\\/GaP wafer-bonded transparent-substrate (TS) light-emitting diodes (LEDs) have been shown to exhibit luminous efficiencies\\u000a exceeding many conventional lightning sources including 60 W incandescent sources. This paper will demonstrate the feasibility\\u000a of scaling wafer bonding technology to 75 mm diameter wafers and some of the unique challenges associated with this scaling.\\u000a The quality and uniformity of bonding were characterized via

I.-H. Tan; D. A. Vanderwater; J.-W. Huang; G. E. Hofler; F. A. Kish; E. I. Chen; T. D. Ostentowski

2000-01-01

229

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress  

NASA Astrophysics Data System (ADS)

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Brunner, Timothy A.; Menon, Vinayan C.; Wong, Cheuk Wun; Gluschenkov, Oleg; Belyansky, Michael P.; Felix, Nelson M.; Ausschnitt, Christopher P.; Vukkadala, Pradeep; Veeraraghavan, Sathish; Sinha, Jaydeep K.

2013-10-01

230

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Astrophysics Data System (ADS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-02-01

231

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Technical Reports Server (NTRS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

232

Architecture for VLSI design of Reed-Solomon encoders  

NASA Technical Reports Server (NTRS)

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

Liu, K. Y.

1981-01-01

233

Cascaded VLSI Chips Help Neural Network To Learn  

NASA Technical Reports Server (NTRS)

Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

1993-01-01

234

Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.  

PubMed

A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 ?m CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 ?W per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data. PMID:23852175

Abdelhalim, K; Smolyakov, V; Genov, R

2011-10-01

235

New fabrication method of glass packages with inclined optical windows for micromirrors on wafer level  

NASA Astrophysics Data System (ADS)

For many applications it is inevitable to protect MEMS devices against environmental impacts like humidity which can affect their performance. Moreover recent publications demonstrates that micro mirrors can achieve very large optical scan angles at moderate driving voltages even exceeding 100 degrees when hermetically sealed under vacuum. While discrete chips may be evacuated and sealed on single die level using small can packages like TO housings, it is obvious that for high volume production a much more economical solution for the realisation of transparent optical packages already on wafer level must be developed. However, since any laser beam crossing a transparent glass surface is partly reflected even when anti-reflective coatings are applied, the construction of a wafer level optical housing suitable for laser projection purpose requires more than the integration of simple plane glass cap. The use of inclined optical windows avoids the occurrence of intense reflections of the incident laser beam in the projected images. This paper describes a unique technology to fabricate glass packages with inclined optical windows for micro mirrors on 8 inch wafers. The new process uses a high temperature glass forming process based on subsequent wafer bonding. A borosilicate glass wafer is bonded together with two structured silicon wafers. By grinding both sides of the wafer stack, a pattern of isolated silicon structures is defined. This preprocessed glass wafer is bonded thereon on a third structured silicon wafer, wherein the silicon islands are inserted into the cavities. By setting a defined pressure level inside the cavities during the final wafer bonding, the silicon glass stack extruded and it is out of plane during a subsequent annealing process at temperatures above the softening point of the glass. Finally the silicon is selectively removed in a wet etching process. This technique allows the fabrication of 8 inch glass wafers with oblique optical surfaces with surface roughness <1 nm and an evenness of < 300 nm.

Stenchly, Vanessa; Quenzer, Hans-Joachim; Hofmann, Ulrich; Janes, Joachim; Jensen, Björn; Benecke, Wolfgang

2013-03-01

236

VLSI architectures for geometrical mapping problems in high-definition image processing  

NASA Technical Reports Server (NTRS)

This paper explores a VLSI architecture for geometrical mapping address computation. The geometric transformation is discussed in the context of plane projective geometry, which invokes a set of basic transformations to be implemented for the general image processing. The homogeneous and 2-dimensional cartesian coordinates are employed to represent the transformations, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme for a processor, which utilizes full-pipelining at the macro-level and parallel constant-factor-redundant arithmetic and full-pipelining at the micro-level, is assessed to produce a single VLSI chip for HDTV applications using state-of-art MOS technology.

Kim, K.; Lee, J.

1991-01-01

237

VLSI architectures for geometrical mapping problems in high-definition image processing  

NASA Astrophysics Data System (ADS)

This paper explores a VLSI architecture for geometrical mapping address computation. The geometric transformation is discussed in the context of plane projective geometry, which invokes a set of basic transformations to be implemented for the general image processing. The homogeneous and 2-dimensional cartesian coordinates are employed to represent the transformations, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme for a processor, which utilizes full-pipelining at the macro-level and parallel constant-factor-redundant arithmetic and full-pipelining at the micro-level, is assessed to produce a single VLSI chip for HDTV applications using state-of-art MOS technology.

Kim, K.; Lee, J.

238

Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.  

PubMed

VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed. PMID:17946695

Jiang, P C; Chen, H

2006-01-01

239

1IUCEE Workshop: VLSI Design, Day 4 Today's Topic: Research in Education  

E-print Network

1IUCEE Workshop: VLSI Design, Day 4 A. Mason July 2008 Ā·Today's Topic: Research in Education VLSI. resources 11:00 Trends in VLSI 11:30 12:00 VLSI Implementations of DSP Research: Bio-medical Electronics 12 engaging in research? Ā·Keep up-to-date with science/engineering advances Ā· research requires you to work

Mason, Andrew

240

Wafer bonding for three dimensional (3D) integration  

NASA Astrophysics Data System (ADS)

Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 · Gtip · t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400°C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400°C. Thermal cycling performed at a temperature 450°C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

Kwon, Yongchai

2003-10-01

241

Interconnect-limited VLSI architecture  

Microsoft Academic Search

As semiconductor technology scales, wires are becoming the dominant factor in determining system performance and power dissipation. By 2008, it is expected that chip traversal will require 16 clocks. Modern superscalar architectures that depend on global register files, global bypass structures, and global instruction issue logic are poorly matched to future semiconductor technology. This technology demands architectures that exploit locality

William J. Dally

1999-01-01

242

The influence of wafer dimensions on the contact wave velocity in silicon wafer bonding  

NASA Astrophysics Data System (ADS)

The contact wave velocity in silicon wafer bonding is experimentally found to decrease with wafer thickness and to be only weakly dependent on wafer diameter. Wafers of different thicknesses ranging from 270 to 5000 ?m, were dipped in HF:H2O before bonding to give the surfaces hydrophobic properties. A model based on energy conservation can explain the main characteristics of the experimental results. The contact wave velocity is determined by the amount of energy available as kinetic energy for the entrapped gas in the gap between the wafers. By increasing wafer thickness, the elastic energy stored in the material is increased, and the contact wave velocity is decreased.

Bengtsson, Stefan; Ljungberg, Karin; Vedde, Jan

1996-11-01

243

A Parallel VLSI Direction Finding Algorithm  

NASA Astrophysics Data System (ADS)

In this paper, we present a parallel VLSI architecture that is matched to a class of direction (frequency, pole) finding algorithms of type ESPRIT. The problem is modeled in such a way that it allows an easy to partition full parallel VLSI implementation, using unitary transformations only. The hard problem, the generalized Schur decomposition of a matrix pencil, is tackled using a modified Stewart Jacobi approach that improves convergence and simplifies parameter computations. The proposed architecture is a fixed size, 2-layer Jacobi iteration array that is matched to all sub-problems of the main problem: 2 QR-factorizations, 2 SVD's and a single GSD-problem. The arithmetic used is (pipelined) Cordic.

van der Veen, Alle-Jan; Deprettere, Ed F.

1988-02-01

244

Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis  

SciTech Connect

This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

Tobin, K.W.

2003-05-22

245

A 3-D wafer level hermetical packaging for MEMS  

Microsoft Academic Search

In this paper, a 3D wafer-level hermetical packaging solution for micro-electromechanical-system (MEMS) is presented. The MEMS wafer is sandwiched between a top glass wafer and a bottom Si substrate wafer. With the assistance of a gold intermediate layer, the bottom Si wafer is hermetically sealed to the MEMS wafer with 3D electric feed-through connecting the metal pads on MEMS wafer

Y F. Jinl; J. Wei; G. J. Qil; Z. F. Wang; P. C. Lim; C. K. Wong

2004-01-01

246

Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010  

SciTech Connect

1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

Lorenz, A.

2011-06-01

247

Intentional defect array wafers: their practical use in semiconductor control and monitoring systems  

NASA Astrophysics Data System (ADS)

In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

2003-07-01

248

Leak detection utilizing analog binaural (VLSI) techniques  

NASA Technical Reports Server (NTRS)

A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

Hartley, Frank T. (inventor)

1995-01-01

249

Leak detection utilizing analog binaural (VLSI) techniques  

NASA Astrophysics Data System (ADS)

A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

Hartley, Frank T.

1995-06-01

250

Leak detection utilizing analog binaural (VLSI) techniques  

NASA Astrophysics Data System (ADS)

A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium is presented. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

Hartley, Frank T.

1993-08-01

251

Analog VLSI implementation of cellular neural networks  

Microsoft Academic Search

The design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using analog VLSI circuit techniques is discussed. A cell model which exhibits advantages for reduced area and power consumption CNN implementations is proposed. This model is very well suited for implementation in the current domain, which is also important for avoiding the need for current-to-voltage dedicated interfaces in

J. L. Huertas; A. Rodriguez-Vasquez; S. Espejo

1992-01-01

252

VLSI Microsystem for Rapid Bioinformatic Pattern Recognition  

NASA Technical Reports Server (NTRS)

A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

Fang, Wai-Chi; Lue, Jaw-Chyng

2009-01-01

253

Distributed Object Oriented Data Structures and Algorithms for VLSI CAD  

E-print Network

Distributed Object Oriented Data Structures and Algorithms for VLSI CAD John A. Chandy , Steven 61801, USAĀ£ Sierra Vista Research, 236 N Santa Cruz Avenue, Los Gatos, CA 95030, USA Abstract. ProperCAD. This paper discusses the use of such distributed data structures in the context of a partic- ular VLSI CAD

Chandy, John A.

254

Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications  

E-print Network

, for example the transition from aluminum to copper some years back. Carbon nanotubes have recently beenPerformance Analysis of Carbon Nanotube Interconnects for VLSI Applications Navin Srivastava the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account

255

A Low-Power Analog VLSI Visual Collision Detector  

E-print Network

V supply. With the addition of wide-angle optics, the sensor is able to detect collisions around 500 in a traditional CPU for autonomous robot navigation [5]. In this work, we present a single-chip analog VLSI sensor designed and tested a single-chip analog VLSI sensor that detects imminent collisions by measuring radially

Harrison, Reid R.

256

CSCE 6933/5933 Advanced Topics in VLSI Systems  

E-print Network

Systems #12;Background Ā· Basic Organization of DRAM 6 Focus of this thesis Advanced Topics in VLSI SystemsCSCE 6933/5933 Advanced Topics in VLSI Systems Instructor: Saraju P. Mohanty, Ph. D. 1 Lecture 8 are borrowed from various books, websites, authors pages, and other sources for academic purpose only

Mohanty, Saraju P.

257

Modeling of interconnect capacitance, delay, and crosstalk in VLSI  

Microsoft Academic Search

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form

Shyh-Chyi Wong; Gwo-Yann Lee; Dye-Jyun Ma

2000-01-01

258

A VLSI layout for a pipelined Dadda multiplier  

Microsoft Academic Search

Parallel counters (unary-to-binary converters) are the principal component of a Dadda multiplier. We specify a design first for a pipelined parallel counter, and then for a complete multiplier. As a result of its structural regularity, the layout is suitable for use in a VLSI implementation. We analyze the complexity of the resulting design using a VLSI model of computation, showing

Peter R. Cappello; Kenneth Steiglitz

1983-01-01

259

Jitter transfer function model and VLSI jitter filter circuits  

Microsoft Academic Search

A closed form jitter transfer model is developed for modeling jitter-circuit interaction effects, such as jitter amplification and attenuation, in VLSI high-speed I\\/O circuits. The model is verified using circuit and behavioral simulations with good consistence. A novel jitter filtering concept and circuit is proposed to address VLSI high-speed I\\/O circuit performance issues.

Hongjiang Song; Jianan Song; A. Dey; Yan Song

2010-01-01

260

Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations  

Microsoft Academic Search

In some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically highly pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have

Erling Wold; Alvin M. Despain

1984-01-01

261

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads  

DOEpatents

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

2013-12-03

262

A universal process development methodology for complete removal of residues from 300mm wafer edge bevel  

NASA Astrophysics Data System (ADS)

Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

2006-03-01

263

Characterizing stress in ultrathin silicon wafers  

NASA Astrophysics Data System (ADS)

The aim of this letter is to calculate the mechanical grinding induced bow and stress in ultrathin silicon wafers. The reverse leakage current of a p-n junction diode fabricated on a 4in. silicon wafer was measured for wafers thinned to various thicknesses. A correlation with the residual stress was obtained through band gap narrowing effect. The analytical results were compared with experimental bow measurements using a laser profiler. The bow in 50?m thick wafer was found to be less than 2mm using the current grinding process.

Paul, Indrajit; Majeed, Bivragh; Razeeb, Kafil M.; Barton, John

2006-08-01

264

Performance Evaluations of Ceramic Wafer Seals  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

265

A method to maintain wafer alignment precision during adhesive wafer bonding  

Microsoft Academic Search

In this paper, a novel method is presented that prevents aligned wafers from shifting relative to each other during adhesive bonding. The attainable pre-bond wafer alignment accuracy on commercially available bonding equipment is typically 2–5?m. However, in adhesive wafer bonding, the intermediate adhesive material must exist in a liquid-like state to wet the wafer surfaces and thereby achieve bonding. When

Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

2003-01-01

266

Techniques for the evaluation of outgassing from polymeric wafer pods  

Microsoft Academic Search

In recent years there has been increasing interest in using wafer-level isolation environments or pods (microenvironments) to provide a more controllable, cleaner wafer environment during wafer processing. It has been shown that pods can be effective in reducing the amount of particulate contamination on wafers during manufacturing. However, there have also been studies that indicate that pods and wafer boxes

D. C. McIntyre; A. Liang; S. M. Thornberg; S. F. Bender; R. D. Lujan; R. S. Blewer; W. D. Bowers

1994-01-01

267

A novel wafer reclaim method for amorphous SiC and carbon doped oxide films  

Microsoft Academic Search

Amorphous SiC (a-SiC) films are the most promising dielectric diffusion barriers to replace silicon nitride in Cu-interconnect technology. However, reclaim of wafers with a-SiC films is a challenge issue for mass production. In this paper, a novel wafer reclaim method is proposed. It is observed that a-SiC can be oxidized to SiO2 in both dry O2 and steam ambients at

Bing-Yue Tsui; Kuo-Lung Fang

2005-01-01

268

Damascene patterned metal\\/adhesive wafer bonding for three-dimensional integration  

Microsoft Academic Search

Wafer bonding of damascene patterned metal\\/adhesive surfaces is explored for a new three-dimensional (3D) integration technology platform. By bonding a pair of damascene patterned metal\\/adhesive layers, high density micron-sized vias can be formed for interconnection of fully fabricated integrated circuit (IC) dies at the wafer-level. Such via dimensions increase the areal interconnect density by at least two orders of magnitude

J. Jay McMahon

2008-01-01

269

In-situ wafer curvature measurements during rapid thermal annealing of Si(100) wafers  

Microsoft Academic Search

During Rapid Thermal Annealing (RTA) of silicon wafers a nonuniform temperature distribution may exist across the wafer caused by a variation of the radiation flux. Due to the thermal gradient, differences in thermal expansion introduce thermal stresses in the material. In a modified RTA system the deformation originating from the thermal stress was monitored by measurement of the wafer curvature

J. Hans F. Jongste; T. G. Oosterlaken; G. C. Bart; G. C. Janssen; Sybrand Radelaar

1995-01-01

270

Stress Voiding During Wafer Processing  

SciTech Connect

Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

Yost, F.G.

1999-03-01

271

Development of a monolithic, multi-MEMS microsystem on a chip demonstrating iMEMS{trademark} VLSI technology. R and D status report number 10, January 1--March 31, 1996  

SciTech Connect

This quarter saw the first silicon from the iMEMS{reg_sign} test chip, with complete circuits and beam structures. The wafers looked fine cosmetically and the circuits functioned as designed, but the beams suffered an anomaly that the authors have never seen before. Diagnostic work is under way to sort out the root cause, and other wafers are coming out this quarter to see if it was a one-time anomaly. Work on the process-development front has slowed because of the construction of a dedicated fabrication line for the last-generation process. With the current robust market place for ADI`s business, the existing fabrication line has been operating at 100% capacity. On the device front, great progress has been made by both Berkeley and ADI in the area of gyroscopes. Measurements of close to a degree per second or better have been made for gyros of all three axes and of both single- (linear) and double- (rotary) axis devices. In addition, ADI has designed a gyro that can be packaged in air that very well might meet some of the low-precision needs. Accelerometers of several new formats have been designed and several have been implemented in silicon. First samples of the ADXL 181 designed especially for the fuzing, safe and arming application have been assembled and are in characterization by ADI and others. In addition, 2-axis, Z-axis and digital output designs have been demonstrated. A 3-axis micro-watt accelerometer has been designed and is in fabrication. A 2-axis design for tilt applications is also nearing silicon realization. This portfolio of linear accelerometers, and even angular versions of the same provide, an arsenal of capability for specialized needs as they arise in both commercial and military applications.

NONE

1996-04-17

272

Grain growth behavior in a columnar-grain-structured silicon wafer for photovoltaic application  

NASA Astrophysics Data System (ADS)

With direct growth technologies for obtaining ribbon-type silicon (Si) wafers from molten Si, the horizontal growth process is much faster than the vertical one in terms of the growth rate of the wafer. However, such a fast growth rate is likely to create grains of a relatively small size in the Si wafer, resulting in limited efficiency caused by grain boundary recombination. In this regard, controlling the grain growth behavior of the Si wafer with processing parameters such as the temperature of the substrate and its moving speed is very important in the horizontal growth process. The present investigation produced the experimental findings concerning the processing parameters for controlling the grain size. The size of the grains on the surface of the Si wafer increased to around 180 ?m at a lower substrate temperature and a slower the moving speed of the substrate due to the increasing thickness of the Si wafer. However, the growth rate of the grains was observed to have little relation to the variations in the wafer thickness resulting from the processing parameters unless the nucleation behavior had been controlled.

Lee, Ye-Neug; Lee, Jin-Seok; Jang, Bo-Yun; Kim, Joon-Soo; Ahn, Young-Soo; Yoon, Woo-Young

2014-07-01

273

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers  

NASA Astrophysics Data System (ADS)

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

Miki, N.; Spearing, S. M.

2003-11-01

274

Wafer level vacuum packaging of MEMS sensors  

Microsoft Academic Search

A process has been developed for wafer level vacuum packaging MEMS sensors, which are fabricated from etched, single crystal silicon structures, anodically bonded to metallized glass wafers. Key objectives of the process design were to minimize the number of changes to sensor fabrication, insure a high level of vacuum integrity, and flexible enough to accommodate a wide range of sensor

Thomas F. Marinis; Joseph W. Soucy; James G. Lawrence; Megan M. Owens

2005-01-01

275

Structural Characterization of Processed Silicon Wafers  

Microsoft Academic Search

Two techniques, chemical etching and X-ray diffraction, for the characterization of process-induced defects in silicon wafers are illustrated. The types of etchants used to reveal various defects are reviewed. The use of a Lang camera for the measurements Of bulk defects and mechanical stress in silicon wafers is presented. Examples are given demonstrating the use of these two techniques: to

PETER L. FEJES; H. MING LIAW; F. d'Aragona

1983-01-01

276

Low Temperature Curing of Polyimide Wafer Coatings  

Microsoft Academic Search

Polyimide films are commonly used on wafers as passivation layers, stress buffer layers, dry etch masks, structural layers, and re-distribution layers for chip scale packaging and wafer level packaging. These films are cured in convection or diffusion ovens at high enough temperatures (350-400 ?C) to assure adequate mechanical and electrical properties. These high temperatures can change the electrical properties of

277

Methane production using resin-wafer electrodeionization  

DOEpatents

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

278

Instrumentation for neutralization of wafer charging  

NASA Astrophysics Data System (ADS)

A detailed analysis of the physics of wafer charging, its effects on the resulting ion trajectories and energy distributions is presented. A general review of present wafer charging diagnostic instruments with emphasis on a new optical technique based upon the ion-induced photoresist damage mechanism is included. The use of this new technique to adjust the ion implanter's flood gun parameters so as to minimize wafer charging is illustrated. Experimental and theoretical results of the use of photon radiation (UV and X-ray) to induce photoconductivity as a mechanism of wafer neutralization during ion implantation are given. Special emphasis is placed on the use of a pulsed, high power, plasma X-ray source as a means of obtaining whole wafer neutralization.

Cheng, J. C.; Tripp, G. R.; Glaze, J. A.; Golin, J. R.

1985-01-01

279

Continuous-valued probabilistic behavior in a VLSI generative model.  

PubMed

This paper presents the VLSI implementation of the continuous restricted Boltzmann machine (CRBM), a probabilistic generative model that is able to model continuous-valued data with a simple and hardware-amenable training algorithm. The full CRBM system consists of stochastic neurons whose continuous-valued probabilistic behavior is mediated by injected noise. Integrating on-chip training circuits, the full CRBM system provides a platform for exploring computation with continuous-valued probabilistic behavior in VLSI. The VLSI CRBM's ability both to model and to regenerate continuous-valued data distributions is examined and limitations on its performance are highlighted and discussed. PMID:16722178

Chen, Hsin; Fleury, Patrice C D; Murray, Alan F

2006-05-01

280

Optimal VLSI dictionary machines without compress instructions  

SciTech Connect

The authors present several designs for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The authors' initial design objectives included: single-cycle operability of host-issued modify and query commands (no compress instructions), complete processor utilization (no wasted processors), and optimal 2 log {ital n} response times, where {ital n} is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously.

Li, H.F.; Probst, D.K. (Dept. of Computer Science, Concordia Univ., Montreal (CA))

1990-05-01

281

VLSI Reed-Solomon Encoder With Interleaver  

NASA Technical Reports Server (NTRS)

Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).

Hsu, In-Shek; Deutsch, L. J.; Truong, Trieu-Kie; Reed, I. S.

1990-01-01

282

Unifying parametrized VLSI Jacobi algorithms and architectures  

NASA Astrophysics Data System (ADS)

Implementing Jacobi algorithms in parallel VLSI processor arrays is a non-trivial task, in particular when the algorithms are parametrized with respect to size and the architectures are parametrized with respect to space-time trade-offs. The paper is concerned with an approach to implement several time-adaptive Jacobi-type algorithms on a parallel processor array, using only Cordic arithmetic and asynchronous communications, such that any degree of parallelism, ranging from single-processor up to full-size array implementation, is supported by a `universal' processing unit. This result is attributed to a gracious interplay between algorithmic and architectural engineering.

Deprettere, Ed F. A.; Moonen, Marc

1993-11-01

283

A VLSI architecture for concurrent data structures  

SciTech Connect

Contents: Concurrent smalltalk. The balanced cube. Graph algorithms. Architecture. Conclusion. Glossary. Bibliography. Note: This book, based on the author's Ph.D. dissertation, won the Clauser prize for the most original Caltech Ph.D thesis in 1986. It presents a coherent view of the art of designing and programming concurrent computers. It can serve as a handbook for those working in the field, or as supplemental reading for graduate courses on parallel algorithms or computer architecture. An important book for those interested in both computer architecture and VLSI design. (RA)

Dally, W.J.

1987-01-01

284

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers  

NASA Technical Reports Server (NTRS)

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.

Truong, T. K.; Hsu, I. S.; Chang, J. J.; Shyu, H. C.; Reed, I. S.

1986-01-01

285

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers  

NASA Technical Reports Server (NTRS)

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

1987-01-01

286

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

Kim, Dae Jong; Yoo, Hyung Won; Kim, Chul Hong; Lee, Hak Kwon; Kim, Sung Su; Bae, Koon Ho; Spielberg, Hedvi; Lee, Yun Ho; Levi, Shimon; Bustan, Yariv; Rozentsvige, Moshe

2010-03-01

287

Optoelectronic system integration on silicon: Waveguides, photodetectors, and VLSI CMOS circuits on one chip  

NASA Astrophysics Data System (ADS)

Optical waveguides, photodetectors, and VLSI CMOS circuits are integrated monolithically in different ways: In a combined integration technique the light-guiding film is deposited and covered with a SiO2 layer replacing standard PSG as the dielectric insulation of polysilicon and metallization. In a stacked method the waveguide fabrication starts after metallization and test of the CMOS circuits. Electrooptical coupling is performed by butt-, leaky wave-, or mirror-coupling of waveguides and photodetectors. To fabricate the system, SWAMI LOCOS technique is applied for monolithic integration of both integrated optical devices and microelectronic circuits. This paper discusses the integration technology and the results of static and dynamic measurements.

Hilleringmann, U.; Goser, K.

1995-05-01

288

Circuits for high-performance low-power VLSI logic  

E-print Network

The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and ...

Ma, Albert

2006-01-01

289

Challenges and Solutions in Modern VLSI (Invited Paper)  

E-print Network

Challenges and Solutions in Modern VLSI Placement (Invited Paper) Zhe-Wei Jiang1, Hsin-Chen Chen2, Tung-Chieh Chen1, and Yao-Wen Chang1,2 1Graduate Institute of Electronics Engineering, National Taiwan

Chang, Yao-Wen

290

An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization  

E-print Network

Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common method for handling multi...

Huang, Yi-Le

2012-02-14

291

Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation   

E-print Network

This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a ...

Wang, Shiwei

2014-11-27

292

Development of megasonic cleaning for silicon wafers  

NASA Technical Reports Server (NTRS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-01-01

293

Metal Enhanced Fluorescence on Silicon Wafer Substrates  

PubMed Central

We report on the fluorescence enhancement induced by silver island film (SIF) deposited on a silicon wafer. The model immunoassay was studied on silvered and unsilvered wafers. The fluorescence brightness of Rhodamine Red X increased about 300% on the SIF, while the lifetime was reduced by several fold and the photostability increased substantially. We discuss potential uses of silicon wafer substrates in multiplex assays in which the fluorescence is enhanced due to the SIF, and the multiplexing is achieved by using micro transponders. PMID:19137060

Gryczynski, I.; Matveeva, E.G.; Sarkar, P.; Bharill, S.; Borejdo, J.; Mandecki, W.; Akopova, I.; Gryczynski, Z.

2008-01-01

294

Mask extraction from optical images of VLSI circuits  

NASA Astrophysics Data System (ADS)

This paper explores line labeling algorithms for extracting the mask layers from an optical image of a VLSI chip. Next, representation schemes for object features are introduced, together with the natural constraints these features satisfy. This label set is an extension of Huffman, Clowes, and Kanade's label sets. Finally, it is shown how to interpret VLSI scenes by using a constrained labeling strategy. Performance of the labeling algorithms is demonstrated on some simple but representative simulated images of CMOS logic gates.

Jeong, Hong; Musicus, Bruce R.

295

Wafer inspection as alternative approach to mask defect qualification  

NASA Astrophysics Data System (ADS)

Defect inspection is one of the major challenges in the manufacturing process of photomasks. The absence of any printing defect on patterned mask is an ultimate requirement for the mask shop, and an increasing effort is spent in order to detect and subsequently eliminate these defects. Current DUV inspection tools use wavelengths five times or more larger than the critical defect size on advanced photomasks. This makes the inspectability of high-end mask patterns (including strong OPC and small SRAF's) and sufficient defect sensitivity a real challenge. The paper evaluates the feasibility of inspecting the printed wafer as an alternative way for the high-sensitivity defect inspection of photomasks. Defects originating in the mask can efficiently be filtered as repeated defects in the various dies on wafer. Using a programmed-defect mask of 65-nm technology, a reliable detection of the printing defects was achieved with an optimized inspection process. These defects could successfully be traced back to the photomask in a semi-automated process in order to enable a following repair step. This study shows that wafer inspection is able to provide a full defect qualification of advanced photomasks with the specific advantage of assessing the actual printability of arbitrary defects.

Holfeld, Christian; Katzwinkel, Frank; Seifert, Uwe; Mothes, Andreas; Peters, Jan Hendrik

2007-10-01

296

Development of an architectural design tool for 3-D VLSI sensors  

E-print Network

Three dimensional integration schemes for VLSI have the potential for enabling the development of new high-performance architectures for applications such as focal plane sensors. Due to the high costs involved in 3-D VLSI ...

Tyrrell, Brian (Brian Matthew)

2004-01-01

297

Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule  

SciTech Connect

The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the wafer. In addition, it was found to be suitable for growing very large crystals. The equipment used was simple and inexpensive to operate. Reasonable solar cells were fabricated on re-crystallized material.

Emanuel Sachs

2013-01-16

298

CMOS compatible wafer scale adhesive bonding for circuit transfer  

Microsoft Academic Search

Reports on a transfer technique for CMOS circuits based on a newly developed bonding technique, namely wafer scale adhesive bonding using epoxies. The circuit transfer sequence consists of three steps: bonding a CMOS processed SIMOX wafer to a Pyrex glass wafer, thinning the SIMOX wafer down to the buried oxide and exposing the contact pads. A test chip was designed

S. van der Green; Maartein Rosmeulen; Philippe Jansen; Kris Baert; Ludo Deferm

1997-01-01

299

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

300

Modelling deformation and fracture in confectionery wafers  

NASA Astrophysics Data System (ADS)

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

2015-01-01

301

Wafer Backside Anisotropic Wet Etching of Silicon  

NSDL National Science Digital Library

This animation, created by Southwest Center for Microsystems Education (SCME), illustrates how the "wafer backside anisotropic wet etching of silicon is used to form the pressure sensor chamber." Further information and resources can be found on the SCME website.

302

Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001  

SciTech Connect

The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.

Beetz, C.P.; Steinbeck, J.; Hsueh, K.L.

2001-03-31

303

Parameter Modeling for Wafer Probe Test  

Microsoft Academic Search

This paper presents the simulation of parameters for wafer probe test by finite-element modeling with consideration of probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. The goal is to minimize the stresses in the device under the bond pad and eliminate wafer failure in probe test. In the probe test modeling, a nonlinear finite-element contact

Yong Liu; Timwah Luk; Scott Irving

2009-01-01

304

Hydrophilic low-temperature direct wafer bonding  

NASA Astrophysics Data System (ADS)

The sealing mechanism of silicon bonding interfaces is reported as a function of annealing temperature. Details of the structural and chemical interface evolution are obtained for hydrophilic silicon/silicon and silicon/silicon dioxide wafer bonding, using x-ray reflectivity and infrared spectroscopy. A two-step mechanism is demonstrated: first a partial sealing of the interface driven by cross-wafer silanol bond condensation and second a water evacuation via oxide formation at the silicon oxide interface.

Ventosa, C.; Rieutord, F.; Libralesso, L.; Morales, C.; Fournel, F.; Moriceau, H.

2008-12-01

305

Parallel RF Wafer Sort Production Testing  

Microsoft Academic Search

The increasing demand for smaller, thinner and more complex portable electronic devices is driving the chip package to incorporate multi-die and wafer-level packaging. A key benefit for multi-die packaging is that dies from different manufacturers or fabrication processes can be incorporated without taking up too much space. Wafer-level packaging has the advantage of allowing very thin chip packages, demanded by

Martin Dresler; Frank Goh; Eng-Keong Tan

306

Low temperature curing of polyimide wafer coatings  

Microsoft Academic Search

Polyimide films are commonly used on wafers as passivation layers, stress buffer layers, dry etch masks, structural layers, and re-distribution layers for chip scale packaging and wafer level packaging. These films are cured in convection or diffusion ovens at high enough temperatures (350-400°C) to assure adequate mechanical and electrical properties. These high temperatures can change the electrical properties of the

R. L. Hubbard; Z. Fathi; I. Ahmad; H. Matsutani; T. Hattori

2004-01-01

307

Fault-tolerant multiprocessor and VLSI-based systems  

NASA Astrophysics Data System (ADS)

Study and development of certain fault-tolerant architectures that utilize the capabilities of new IC technology was undertaken. Specifically, the research was aimed at network architectures, distinguished by a close interconnection of a large number of computing elements. Included is a subclass of specialized network architectures known as VLSI processor arrays. Besides fault-tolerance-related research for such arrays, also proposed was exploration of a new array architecture, developed for the express purpose of executing general algorithms on these arrays. The precise research formulated-developing fault-tolerant multiprocessor network architectures-goes beyond earlier work. Here, the system interconnection structure, itself, was used as the primary design tool for achieving various and diverse objectives, including: low interconnection and layout complexities, dynamic reconfigurability, fault-tolerance through graceful degradation as well as self-diagnosability. Viability of the proposed research was demonstrated in the proposal. New communication structures were introduced, along with concepts of admissability of multiple logical configurations, and algorithmic and detour routing that provide fault-tolerance and graceful degradation.

Pradhan, Dhiraj K.

1987-03-01

308

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner  

NASA Technical Reports Server (NTRS)

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

309

Porous solid ion exchange wafer for immobilizing biomolecules  

DOEpatents

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

2007-12-11

310

Abstract--This paper describes the development of visualization aids for VLSI Computer-Aided Design  

E-print Network

--Visualization, Animation, VLSI CAD, Design Automation, Placement, Routing. I. INTRODUCTION HE ongoing revolution in VLSI used in the design of semi-custom VLSI chips ­ a popular style in which a pre- designed library is to adapt ideas from software visualization and algorithm animation [5], [6] to aid students, designers

Nestor, John A.

311

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder  

NASA Technical Reports Server (NTRS)

A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

312

VLSI processors for signal detection in SETI.  

PubMed

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features. PMID:11537749

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

313

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays  

NASA Technical Reports Server (NTRS)

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

2009-01-01

314

Passive Wireless Monitoring of Wafer Cleanliness During Rinsing of Semiconductor Wafers  

Microsoft Academic Search

Semiconductor facilities consume large amounts of water, most of which is used for rinsing of wafers during cleaning steps. To optimize water use, real-time and in situ monitoring of wafer cleanliness during rinsing is necessary. Yet no prior art is real-time and in situ. In this paper, we present a passive wireless sensing system capable of measuring the residual contamination

Xu Zhang; Jun Yan; Bert Vermeire; Farhang Shadman; Junseok Chae

2010-01-01

315

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

316

Ultra thin ICs and MEMS elements: techniques for wafer thinning, stress-free separation, assembly and interconnection  

Microsoft Academic Search

Ultra thin chips with a thickness below 30 ?m offer low system height, low topography and show enhanced mechanical flexibility.\\u000a These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly\\u000a and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of\\u000a ultra thin fully processed wafers. Secure handling

M. Feil; C. Alder; G. Klink; M. König; C. Landesberger; S. Scherbaum; G. Schwinn; H. Spöhrle

2003-01-01

317

3D structure design and reliability analysis of wafer level package with bubble-like stress buffer layer  

Microsoft Academic Search

With the present trend of multi-function and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLP) and chip scale packages (CSP) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP)

Chang-Chun Lee; Hsin-Chih Liu; Ming-Chih Yew; Kuo-Ning Chiang

2004-01-01

318

A microneedle-based glucose monitor: fabricated on a wafer-level using in-device enzyme immobilization  

Microsoft Academic Search

This paper presents a disposable minimally invasive self-calibrating continuous glucose monitor consisting of hollow out-of-plane microneedles to sample interstitial fluid from the epidermis, an integrated porous poly-Si dialysis membrane and an integrated enzyme-based flow-through glucose sensor. The proposed system can be fabricated on a wafer-level using standard MEMS technology and a novel in-device enzyme immobilization technique that allows wafer-level patterning

Stefan Zimmermann; Doerte Fienbork; Boris Stoeberb; Albert W. Flounders; Dorian Liepmann

2003-01-01

319

Design, manufacture and testing of microengineered stencils used for sub 100 micron wafer level bumping  

Microsoft Academic Search

Summary form only given. The advances of chip scale packaging technologies have induced an increase of the density of solder joints in microelectronics products. Pitch sizes are consequently due to further decrease, leading to joint structures at sub 100mum dimensions. Stencil printing for wafer bumping with fine particle solder pastes is potentially a low-cost assembly solution for fine pitch solder

N. J. Gorman; R. W. Kay; I. Roney; M. P. Y. Desmulliez

2006-01-01

320

A Multi-Mode Sensing System for Corrosion Detection Using Piezoelectric Wafer Active Sensors  

E-print Network

methods, including ultrasonic, impedance, and thickness measurement, we introduce the concept of PWAS1 A Multi-Mode Sensing System for Corrosion Detection Using Piezoelectric Wafer Active Sensors Columbia, SC 29208, pollocpj@engr.sc.edu ABSTRACT As an emerging technology for in-situ damage detection

Giurgiutiu, Victor

321

Defect free deep trench isolation for high voltage bipolar application on SOI wafer  

Microsoft Academic Search

The trench architecture and process flow for a 170 V complementary bipolar technology with trench isolation and bonded wafer substrates is described. Electrical and material (micro-Raman) characterization is used to show that the process architecture and optimized process flow results in defect free silicon device regions

W. Yindepol; R. Bashir; J. M. McGregor; K. C. Brown; I. De Wolf; J. De Santis; A. Ahmed

1998-01-01

322

Wafer-Level Flip Chip Packages Using Preapplied Anisotropic Conductive Films (ACFs)  

Microsoft Academic Search

Recently, wafer-level packaging (WLP) has become one of the promising packaging technologies due to its advantages, such as fewer processing steps, lower cost, and enhanced device performance compared to conventional single-chip packaging. Many developments on new WLP design, material, and process have been accomplished according to performance and reliability requirement of the devices to be packaged [1], [2]. For a

Ho-Young Son; Chang-Kyu Chung; Myung-Jin Yim; Jin-Sang Hwang; Kyung-Wook Paik; Gi-Jo Jung; Jun-Kyu Lee

2007-01-01

323

Influence of Silicon on Insulator Wafer Stress Properties on Placement Accuracy of Stencil Masks  

Microsoft Academic Search

The issue of placement control is one of the key challenges of stencil mask technology. A high placement accuracy can only be achieved with a precise control of mechanical stress on a global and local scale. For this reason, the stress properties of the mask blank material -typically silicon on insulator (SOI) wafers- have to be known and adjusted properly.

Frank-Michael Kamm; Albrecht Ehrmann; Herbert Schäfer; Werner Pamler; Rainer Käsmaier; Jörg Butschke; Reinhard Springer; Ernst Haugeneder; Hans Löschner

2002-01-01

324

Wafer bonding of gallium arsenide on sapphire  

NASA Astrophysics Data System (ADS)

Three-inch (100) gallium arsenide wafers were bonded to ( 1/line{1} 02) sapphire in a micro-cleanroom at room temperature under hydrophilic or hydrophobic surface conditions. Subsequent heating up to 500 °C increased the bond energy of the GaAs-on-sapphire (GOS) wafer pair close to the fracture energy of the bulk material. The bond energy was measured as a function of the temperature. Since the thermal expansion coefficients of GaAs and sapphire are close to each other, the bonded wafer pair is stable against thermal treatment and quenching in liquid nitrogen. During heating in different gas atmospheres, macroscopic interface bubbles and microscopic imperfections were formed within the bonding interface, which were analysed by transmission electron microscopy (TEM). These interface bubbles can be prevented by hydrophobic bonding in a hydrogen atmosphere.

Kopperschmidt, P.; Kästner, G.; Senz, S.; Hesse, D.; Gösele, U.

325

Wafer fab mask qualification techniques and limitations  

NASA Astrophysics Data System (ADS)

Mask inspection and qualification is a must for wafer fabs to ensure and guarantee high and stable yields. Single defect events can easily cause a million dollar loss through a defect duplicating onto the wafer. Several techniques and methods for mask qualification within a wafer fab are known but not all of them are neither used nor understood regarding their limitations. Increasing effort on existing tool platforms is necessary to detect the defects of interest which are at the limit of the tools specification - On the other hand next generation tools are very sensitive and therefore consume only a negligible amount of time for recipe optimization. Knowing the limits of each inspection tool helps to balance between effort and benefit. Masks with programmed defects of 90nm and 65nm design rule were used in order to compare the different available inspection techniques. During the course of this technical work, the authors concentrate mainly on two inspection techniques. The first one inspects the reticle itself using KLA-Tencor's SLF27 (TeraStar) and SL536 (TeraScan) tools. As the reticle gets inspected itself this is the so called "direct" mask defect inspection. The second inspection technique discussed is the "indirect" mask defect inspection which consists of printing the pattern on a blank wafer and use KLA-Tencor's bright-field wafer inspection tool (2xxx series) to inspect the wafer. Data of this work will include description of the techniques, inspection results, defect maps, sensitivity analysis, effort estimation as well as limitations for both techniques for the used design rule.

Poock, Andre; Maelzer, Stephanie; Spence, Chris; Tabery, Cyrus; Lang, Michael; Schnasse, Guido; Peikert, Milko; Bhattacharyya, Kaustuve

2006-10-01

326

Making Porous Luminescent Regions In Silicon Wafers  

NASA Technical Reports Server (NTRS)

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

327

On testing VLSI chips for the big Viterbi decoder  

NASA Astrophysics Data System (ADS)

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

Hsu, I. S.

1989-02-01

328

On testing VLSI chips for the big Viterbi decoder  

NASA Technical Reports Server (NTRS)

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

Hsu, I. S.

1989-01-01

329

Wafer focusing measurement of optical lithography system based on Hartmann-Shack wavefront testing  

NASA Astrophysics Data System (ADS)

To improve the focusing measurement precision of wafer in optical lithography instrument (OLI), a method based on Hartmann-Shack (HS) testing principle is introduced. Defocus of wafer is immediately detected by measuring the image change between plane and spherical wavefront. As defocus is measured by every sub-lens of microlens array (MLA), serials of defocus position are calculated at single shot of CCD sensor. Choose the average in this measurement the outstanding advantage of this technology is the high accuracy and efficiency. With an experiment to validate the feasibility, the accuracy of focusing measurement is indicated as 20 nm.

Zhu, Xianchang; Hu, Song; Zhao, Lixin

2015-03-01

330

On the chemo-mechanical polishing for nano-scale surface finish of brittle wafers.  

PubMed

Chemo-mechanical polishing (CMP) has been a common method to produce nano-scale surface finish of brittle wafers. This paper provides a relatively comprehensive review on the CMP of silicon, silicon carbide and sapphire including both patents and papers. The discussion includes the limitations and further research directions of the CMP technology, the material removal mechanisms, and the control and optimization of the CMP for brittle wafers. The paper concluded that the usage of mix- or coated- abrasives may improve the CMP in terms of less subsurface damage and higher material removal rate. PMID:20415661

Wang, Y G; Zhang, L C

2010-06-01

331

Across wafer CD uniformity optimization by wafer film scheme at double patterning lithography process  

NASA Astrophysics Data System (ADS)

The Double Patterning lithography (DPL) process is a well known method to overcome the k1 limit below 0.25, but the pattern final performance (OVL/CD) get more sensitive with the initial core CD uniformity, one of the main factors is across wafer CD uniformity control. Previous improvements applying scanner dose or PEB temperature multi-zone control, the others use the vacuum PEB plate design. In this study, we adopt various DPL sacrificial layers to modify wafer warpage level, it can adjust a suitable wafer warpage profile. By this method, we can achieve 30% CD uniformity improvement without the scanner dose/ PEB multi-zone heating compensation,

Lin, Hsiao-Chiang; Li, Yang-Liang; Wang, Shiuan-Chuan; Liu, Chien-Hung; Wang, Zih-Song; Hsuh, Jhung-Yuin

2014-04-01

332

On VLSI Design of Rank-Order Filtering using DCRAM Architecture  

PubMed Central

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 ?m 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7?m2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply. PMID:19865599

Lin, Meng-Chun; Dung, Lan-Rong

2009-01-01

333

A multi coding technique to reduce transition activity in VLSI circuits  

NASA Astrophysics Data System (ADS)

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

Vithyalakshmi, N.; Rajaram, M.

2014-02-01

334

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment  

NASA Technical Reports Server (NTRS)

Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

2013-01-01

335

Integratible process for fabrication of fluidic microduct networks on a single wafer  

NASA Astrophysics Data System (ADS)

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 mm, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectric materials.

Matzke, Carolyn M.; Ashby, Carol I. H.; Bridges, Monica M.; Griego, Leonardo; Wong, C. Channy

1999-08-01

336

Model based OPC for implant layer patterning considering wafer topography proximity (W3D) effects  

NASA Astrophysics Data System (ADS)

Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage of non-uniform reflective substrates without bottom anti-reflection coating (BARC). Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without BARC, e.g., implant layer, as technology node shrinks. For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full chip OPC on implant layers.

Park, Songyi; Youn, Hyungjoo; Chung, Noyoung; Maeng, Jaeyeol; Lee, Sukjoo; Ku, Jahum; Xie, Xiaobo; Lan, Song; Feng, Mu; Vellanki, Venu; Kim, Joobyoung; Baron, Stanislas; Liu, Hua-Yu; Hunsche, Stefan; Woo, Soung-Su; Park, Seung-Hoon; Yoon, Jong-Tai

2012-03-01

337

In-line failure analysis on productive wafers with dual-beam SEM/FIB systems  

NASA Astrophysics Data System (ADS)

Modern dual beam SEM/FIB tools will allow physical failure analysis on productive wafers in the cleanroom if contamination of wafer and production equipment can be controlled. In this study we show that the risks of Ga- diffusion and -desorption as well as heavy metal contamination can be overcome. The reentry of analyzed wafers into the production flow results in lower overall costs and a dramatically shortened feedback loop to production engineers, leading to reduced down times of production tools etc. Most FIB-applications (i.e. highlight etch of cross sections) can be processed with appropriate gas chemistry. Ion Beam deposition of an insulating material to refill the crater created by the sputtering process is also investigated. If either resolution is not sufficient or more complex analyses have to be applied a sample lift-out technique was developed making it obsolete to sacrifice wafers also in these cases. The fixed sample can be analyzed off-line with all PFA- methods, even plasma etching or lift-off in HF is possible. The benefits of this quantum leap for physical failure analysis are reduction of wafer costs and the possibility to reduce analysis cycle time as well as the number of learning cycles in technology development.

Weiland, Rainer; Boit, Christian; Dawes, Nick; Dziesiaty, Andreas; Demm, Ernst; Ebersberger, Bernd; Frey, Lothar; Geyer, Stefan; Hirsch, Alexander; Lehrer, Christoph; Meis, Peter; Kamolz, Matthias; Lezec, Henri; Rettenmaier, Hans; Tittes, Wolfgang; Treichler, Rolf; Zimmermann, Harald

2001-04-01

338

A radial basis function neurocomputer implemented with analog VLSI circuits  

NASA Technical Reports Server (NTRS)

An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

1992-01-01

339

NASA Space Engineering Research Center for VLSI systems design  

NASA Technical Reports Server (NTRS)

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

1991-01-01

340

Bubble-domain circuit wafer evaluation coil set  

NASA Technical Reports Server (NTRS)

Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

Chen, T. T.; Williams, J. L.

1975-01-01

341

Geometry control of recrystallized silicon wafers for solar applications  

E-print Network

The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

Ruggiero, Christopher W

2009-01-01

342

Performance optimization of digital VLSI circuits  

SciTech Connect

Designers of digital VLSI circuits have virtually no computer tools available for the optimization of circuit performance. Instead, a designer relies extensively on circuit-analysis tools, such as circuit simulation (SPICE) and/or critical-delay-path analysis. A circuit-analysis approach to digital design is very labor-intensive and seldom produces a circuit with optimum area/delay or power/delay trade off. The goal of this research is to provide a synthesis approach to the design of digital circuits by finding the sizes of transistors that optimize circuits by finding the sizes of transistors that optimize circuit performance (delay, area, power). Solutions are found that are optimum for all possible delay paths of a given circuit and not for just a single path. The approach of this research is to formulate the problem of area/delay or power/delay optimization as a nonlinear program. Conditions for optimality are then established using graph theory and Kuhn-Tucker conditions. Finally, the use of augmented-Lagrangian and projected-Lagrangian algorithms are reviewed for the solution of the nonlinear programs. Two computer programs, PLATO and COP, were developed by the author to optimize CMOS PLA's (PLATO) and general CMOS circuits (COP). These tools provably find the globally optimum transistor sizes for a given circuit. Results are presented for PLA's and small- to medium-sized cells.

Marple, D.P.

1987-01-01

343

Sub-imaging Techniques For 3D-Interconnects On Bonded Wafer Pairs  

NASA Astrophysics Data System (ADS)

The semiconductor industry's ability to follow Moore's law to continue to increase the number of components on integrated circuits is increasingly difficult. One way to improve the product performance even at decreased footprint is the use of 3D interconnects which stacks multiple chips in a single package. This new technology for connecting chips overcomes some of the limitations of 2D interconnects. For example, 3D interconnects significantly reduce interconnect delay and improve clock distribution. At the same time that research into 3D technology such as Through Silicon Vias (TSVs) is advancing quickly, the microscopy techniques used in the evaluation of TSV must also advance in capability. Void inspection after copper plating, defect detection and overlay measurements after wafer bonding are challenging. Microscopy techniques for which silicon is opaque such as scanning acoustic microscope (SAM) and confocal infrared microscope (IR) are capable of inspecting the interface between bonded wafer pairs, while high resolution X-Ray techniques are used to detect voids in TSVs. Initial work was done to determine the limitation of these techniques. Four pairs of bonded wafers were prepared at different thicknesses (100, 200, 300 and 400 ?m) to evaluate the effects of wafer thinning using acoustic and infrared microscopy techniques. SAM was able to resolve the 20 ?m alignment structure with 300 MHz transducer on 300 mm wafer pair, while IR has sub-micron resolution for all bonded wafers. This paper discusses the current status of SAM, IR microscopy and XRM in terms of their application to process metrology for 3D interconnects.

Kong, Lay Wai; Krueger, Peter; Zschech, Ehrenfried; Rudack, Andrew C.; Arkalgud, Sitaram; Diebold, Alain C.

2010-11-01

344

Investigations of Wafer Scale Etching with Xenon Difluoride  

Microsoft Academic Search

A good and uniform bulk silicon wafer etching method can be applied to the wafer thinning process in MEMS and 3D applications. In this study, the use of a Xenon Difluoride (XeF2) gas-phase etching system, operating at room temperature, has been investigated for bulk silicon wafer thinning. We investigated the Si-wafer surface morphology and profile following each XeF2 etching process

K. N. Chen; N. Hoivik; C. Y. Lin; A. Young; M. Ieong; G. Shahidi

2006-01-01

345

Apparatus for edge etching of semiconductor wafers  

NASA Technical Reports Server (NTRS)

A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

Casajus, A.

1986-01-01

346

Localized induction heating for wafer level packaging  

Microsoft Academic Search

Localized induction heating for wafer level packaging is discussed. This paper is to investigate the relationships between the geometry of solder loop and temperature distribution in induction heating. Using finite element method (FEM) and IR thermal imager, temperature distribution and variation are explored, which shows that the temperature on the solder loops is a function of the area and edge

Mingxiang Chen; Wenming Liu; Yanyan Xi; Changyong Lin; Sheng Liu

2009-01-01

347

Wafer fusion: materials issues and device results  

Microsoft Academic Search

A large number of novel devices have been recently demonstrated using wafer fusion to integrate materials with different lattice constants. In many cases, devices created using this technique have shown dramatic improvements over those which maintain a single lattice constant. We present device results and characterizations of the fused interface between several groups of materials

A. Black; A. R. Hawkins; N. M. Margalit; D. I. Babic; Y.-L. Chang; P. Abraham; J. E. Bowers; E. L. Hu

1997-01-01

348

Fast Photoluminescence Imaging of Silicon Wafers  

Microsoft Academic Search

Photoluminescence (PL) imaging is demonstrated as a fast characterization tool allowing variations of the minority carrier lifetime within large area silicon wafers to be measured with high spatial resolution and with a data acquisition time of only one second. PL imaging is contactless and can therefore be applied to silicon solar cells before and after every processing stage including fully

T. Trupke; R. A. Bardos; M. D. Abbott; F. W. Chen; J. E. Cotter; A. Lorenz

2006-01-01

349

Deformation of Si(100) wafers during rapid thermal annealing  

Microsoft Academic Search

In this paper insitu wafer curvature measurements are presented that were performed during rapid thermal annealing of silicon wafers. The wafer curvature due to thermal stress originating from a nonuniform temperature distribution was measured as a function of time for a fixed setting of the illumination source power. The presence of thermal stress was clearly demonstrated. It was found that

J. F. Jongste; T. G. M. Oosterlaken; G. C. J. Bart; G. C. A. M. Janssen; S. Radelaar

1994-01-01

350

Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)  

SciTech Connect

A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

Rupnowski, P.; Sopori, B.

2008-05-01

351

Temporary Bonding of Wafer to Carrier for 3D-Wafer Level Packaging  

Microsoft Academic Search

With great demand of high-end applications such as high-integration microelectronics, system-in-packaging (SiP), power application and flexible ICs, a device wafer needs to be thinned down and further structured, for example, fabrication of through-silicon via for the improved performance. Therefore, handling of ultrathin wafer (less than 100æm in thickness) becomes a great challenge for both front-end and back-end processes. In current

M. H. Shuangwu; D. Pang; S. Nathapong; P. Marimuthu

2008-01-01

352

Decoupling bulk- and surface-limited lifetimes in thin kerfless silicon wafers using spectrally resolved transient absorption pump-probe spectroscopy and computer simulations  

E-print Network

One of the key technological objectives to further decrease the cost of silicon (Si) PV and enable manufacturing of crystalline silicon is to improve the quality of thin, kerfless Si wafers to monocrystalline equivalent. ...

Siah, Sin Cheng

2013-01-01

353

Wafer-scale fabrication of nanoapertures using corner lithography.  

PubMed

Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated--based on a theoretical foundation including a statistical analysis--with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures. PMID:23792365

Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

2013-07-19

354

Development of GaN wafers via the ammonothermal method  

NASA Astrophysics Data System (ADS)

This paper reviews the current progress of ammonothermal growth at SixPoint Materials and discusses some of the remaining challenges to commercialize the technology. The mass production of the ammonothermal grown wafers of GaN for high power devices has substantial commercial potential but is currently limited by two problems: impurities which lead to semitransparent coloration and stress in the crystals which leads to cracking. To improve the coloration, it is important to understand and reduce the impurities in the crystal. Oxygen impurities were found to be the primary source of coloration. By reducing the oxygen impurities the absorption coefficient at 450 nm was improved to 3.9 cm-1 yielding semitransparent crystals. The second and more serious issue is a cracking that occurs when thick boules are produced. Currently we routinely produce ammonothermal growth over a millimeter in thickness without any cracking. However, as the thickness increases cracks develop. From a production viewpoint, the production of thick crystals is beneficial since it allows a single wafer to be processed into many. By improving a variety of parameters, the crack density was reduced and the maximum crack-free growth increased from 1 mm to 2.6 mm.

Letts, Edward; Hashimoto, Tadao; Hoff, Sierra; Key, Daryl; Male, Keith; Michaels, Mathew

2014-10-01

355

Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon wafers  

E-print Network

Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon microscopy, profilometer and wafer bow measurements. Plasma-activated direct bonding of DOI wafers to thermal September 2010 Keywords: Diamond-on-insulator Plasma activation Ultrananocrystalline diamond Direct bonding

Akin, Tayfun

356

Fabrication of GaAs laser diodes on Si using low temperature bonding of MBE grown GaAs wafers with Si wafers  

Microsoft Academic Search

The conventional heteroepitaxial GaAs-on-Si growth suffers from poor III-V material quality (dislocation density of ?108 cm-2 and a residual thermal stress of ?109 dyn\\/cm2) and some process incompatibilities between the CMOS and III-V technologies. For these reasons, we have developed a heterogeneous integration scheme, which has the wafer-scale characteristics of monolithic integration and at the same time is compatible with

D. Cengher; Z. Hatzopoulos; S. Gallis; G. Deligeorgis; E. Aperathitis; M. Alexe; V. Dragoi; E. D. Kyriakis-Bitzaros; G. Halkias; A. Georgakilas

2002-01-01

357

Algorithms for the scaling toward nanometer VLSI physical synthesis  

E-print Network

Along the history of Very Large Scale Integration (VLSI), we have successfully scaled down the size of transistors, scaled up the speed of integrated circuits (IC) and the number of transistors in a chip - these are just a few examples of our...

Sze, Chin Ngai

2007-04-25

358

SPIDER -- A CAD System for Modeling VLSI Metallization Patterns  

Microsoft Academic Search

A system of CAD programs, called SPIDER, for ensuring adequate current-carrying capacity in VLSI circuits has been developed. The approach is hierarchical, and it automates and simplifies many of the tasks previously performed by the circuit designer. The system converts transient current waveforms into dc electromigration equivalent values, and includes an algorithm for determining the line width adjustments necessary for

Joseph E. Hall; Dale E. Hocevar; Ping Yang; Michael J. Mcgraw

1987-01-01

359

Copy detection for intellectual property protection of VLSI designs  

Microsoft Academic Search

We give the first study of copy detection techniques for VLSI CAD applications; these techniques are complementary to previous watermarking-based IP protection methods in finding and proving improper use of design IP. After reviewing related literature (notably in the text processing domain), we propose a generic methodology for copy detection based on determining basic elements within structural representations of solutions

Andrew B. Kahng; Darko Kirovski; Stefanus Mantik; Miodrag Potkonjak; Jennifer L. Wong

1999-01-01

360

A reconfigurable and fault-tolerant VLSI multiprocessor array  

Microsoft Academic Search

Multiprocessor arrays have the property of regularity, enabling a low-cost VLSI implementation. However, multiprocessor systems with a fixed structure tend to be error prone and restricted to specialized applications, which makes them less attractive to the semiconductor industry. Consequently, reconfigurability and fault-tolerance are desirable features of a multiprocessor array. A multiprocessor array with a flexible structure can be adapted to

Israel Koren

1981-01-01

361

Macromodeling and Optimization of Digital MOS VLSI Circuits  

Microsoft Academic Search

Power consumption and signal delay are crucial to the design of high-performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based

Mark Douglas Matson; Lance A. Glasser

1986-01-01

362

Hybrid VLSI/QCA Architecture for Computing FFTs  

NASA Technical Reports Server (NTRS)

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

363

A special purpose silicon compiler for designing supercomputing VLSI systems  

NASA Technical Reports Server (NTRS)

Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

1991-01-01

364

Decentralized Fault-Tolerant Clock Pulse Generation in VLSI Chips  

E-print Network

Decentralized Fault-Tolerant Clock Pulse Generation in VLSI Chips The invention offers a solution for various problems associated with the steady increase of clock rates of chips. It offers a fault of faults; · self generation of clock pulses. Instead of globally distributing the clock produced

Szmolyan, Peter

365

Defect Tolerance in VLSI Circuits: Techniques and Yield Analysis  

E-print Network

Defect Tolerance in VLSI Circuits: Techniques and Yield Analysis ISRAEL KOREN, FELLOW, IEEE. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing

Koren, Israel

366

Voronoi diagrams for VLSI manufacturing: Robustness and Implementation  

E-print Network

. Watson Research Center E. Papadopoulou, IBM T. J. Watson Research Center DIMACS Workshop Dec. 4-6, 2002 1 for Critical Area Extraction: to be used by IBM manufacturing in '03 E. Papadopoulou, IBM T. J. Watson Research. Not available E. Papadopoulou, IBM T. J. Watson Research Center DIMACS Workshop Dec. 4-6, 2002 3 #12;VLSI Data

Papadopoulou, Evanthia

367

Systematic Construction of Finite State Automata Using VLSI Spiking Neurons  

E-print Network

Systematic Construction of Finite State Automata Using VLSI Spiking Neurons Emre Neftci1 , Jonathan-Verlag Berlin Heidelberg 2012 #12;Systematic Construction of Finite State Automata 383 a Neural Finite State neural net- works, which solves these two problems by mapping the computations of classical Finite State

368

Challenges and opportunities of emerging nanotechnology for VLSI nanoelectronics  

Microsoft Academic Search

This presentation will first summarize some of the most recent silicon innovations made for advanced CMOS transistors in the nanotechnology era for high-speed and energy-efficient VLSI digital applications. Through these Si nanotechnologies, it is expected that the CMOS scaling and improved performance trends will extend and continue well into the next decade. In addition, there has been good progress made

R. Chau

2007-01-01

369

A Low-Power Analog VLSI Visual Collision Detector  

Microsoft Academic Search

We have designed and tested a single-chip analog VLSI sensor that detects imminent collisions by measuring radially expansive optic flow. The design of the chip is based on a model proposed to explain leg-extension behavior in flies during landing approaches. A new elementary motion detector (EMD) circuit was developed to measure optic flow. This EMD circuit models the bandpass nature

Reid R. Harrison

2003-01-01

370

VLSI Architecturesfor Blind Equalization Based on Fractional-OrderStatistics  

E-print Network

architectures is suitable for a particular environment depending on the p and q parameters of FLOS-CMA being. Dagres, P. Tsakalides, and T. Stouraitis Electrical & Computer Engineering Dept., University of Patras, GR 26 500 Patras, Greece. Abstract Four types of VLSI architectures for the hardware realization

Tsakalides, Panagiotis

371

A note on 'free accumulation' in VLSI filter architectures  

Microsoft Academic Search

Completely pipelined inner product architectures are presented for FIR filtering and linear transformation. The designs use only full adders, organized to form multipliers. By cascading these multiplier structures, no additional area or time is needed to sum their products. The merits of the FFT are briefly reconsidered in the context of high throughput VLSI structures for digital signal processing.

P. Cappello; K. Steiglitz

1985-01-01

372

CSCE 6933/5933 Advanced Topics in VLSI Systems  

E-print Network

Ā­ Crystal oscillators Ā­ Ring oscillators Ā· VCO is an electronic oscillator specifically designed Locked Loop Ā· Components of a PLL Ā· High Level System Design Ā· Component - wise Design and Power the error detector block 5Advanced Topics in VLSI Systems #12;High Level System Design Ā· Behavioral

Mohanty, Saraju P.

373

A database approach for managing VLSI design data  

Microsoft Academic Search

We describe an approach to managing information about VLSI designs, founded upon database system methods. A database component provides a low-level flat-file interface to stored data. Built on top is a design data management system, supporting the hierarchical construction of a design from primitive cells, and organizing data about alternative design representations and versions. Programs to provide a tailored interface

Randy H. Katz

1982-01-01

374

CMOS VLSI Layout and Verification of a SIMD Computer  

NASA Technical Reports Server (NTRS)

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

Zheng, Jianqing

1996-01-01

375

The on-chip parallelism of VLSI circuits  

Microsoft Academic Search

Simulation is a bottleneck in VLSI circuit design. Not only are there many simulation runs throughout the design cycle, but each run can take hours or days to complete. One often suggested means of speeding up event-driven simulation is to use multiple processors to exploit the natural parallelism present in the circuit, that is to partition the circuit among multiple

M. L. Bailey

1989-01-01

376

Pipeline and parallel-pipeline FFT processors for VLSI implementations  

SciTech Connect

In some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically highly pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have constraints which differ from those of discrete implementations, requiring another look at some of the typical FFT algorithms in the light of these constraints. In this paper, several methods for computing the FFT in hardware are reviewed. Pipeline structures for the Cooley-Tukey algorithm and the Good prime factor algorithm are presented. The various small base modules required for the construction of these processors are examined with VLSI implementations in mind. For prime bases, an algorithm due to Rader is used which is easier to implement in a pipeline than the minimum multiply algorithms of Winograd. The Winograd technique of centralizing the multiplies of several relatively prime bases is used to develop a pipeline which requires less hardware than pipelines based on the algorithms above. A notation is then presented which allows parallel-pipeline versions of FFT processors to be developed for all of these algorithms. These versions are well suited for use in VLSI implementations due to the efficient use of chip I/O bandwidth between the stages of the FFT algorithms.

Wold, E.H.; Despain, A.M.

1984-05-01

377

Generating test patterns for VLSI circuits using a genetic algorithm  

Microsoft Academic Search

The authors present the development of a technique that uses genetic algorithms for the generation of test patterns that detect single stuck-at faults in combinational VLSI circuits. As the genetic algorithm evolves, an efficient set of test patterns are produced, by searching the solution space for patterns that detect the highest number of remaining faults in the fault list.

M. J. O'Dare; T. Arslan

1994-01-01

378

VLSI Design Through OpenVLSI Design Through Open--Source /Source / F T lF T lFree ToolsFree Tools  

E-print Network

Patra33 NanoSystemNanoSystem Design Laboratory (NSDL), University of North Texas, USA.Design Laboratory/Software Platform AlternativesHardware/Software Platform Alternatives Ā·Ā· VLSI Design and Simulation FlowVLSI Design Efficiency Positive Impact On Environment #12;5 COMPARED TO THE FIRST BILLION PCs INSTALLED THE NEXT 2

Mohanty, Saraju P.

379

Development and Optimization of Automated Dry-Wafer Separation  

E-print Network

Abstract—In a state-of-the-art industrial production line of photovoltaic products the handling and automation processes are of particular importance and implication. While processing a fully functional crystalline solar cell an as-cut photovoltaic wafer is subject to numerous repeated handling steps. With respect to stronger requirements in productivity and decreasing rejections due to defects the mechanical stress on the thin wafers has to be reduced to a minimum as the fragility increases by decreasing wafer thicknesses. In relation to the increasing wafer fragility, researches at the Fraunhofer Institutes IPA and CSP showed a negative correlation between multiple handling processes and the wafer integrity. Recent work therefore focused on the analysis and optimization of the dry wafer stack separation process with compressed air. The achievement of a wafer sensitive process capability and a high production throughput rate is the basic motivation in this research.

Tim Giesen; Christian Fischmann; Fabian Böttinger; Er Ehm; Er Verl

380

Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs  

NASA Astrophysics Data System (ADS)

The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

2004-08-01

381

Wafer surface pre-treatment study for micro bubble free of lithography process  

NASA Astrophysics Data System (ADS)

Photo resist micro bubble and void defect is reported as a typical and very puzzle defect type in photo lithography process, it becomes more and more significantly and severely with the IC technology drive towards 2× node. Introduced in this paper, we have studied the mechanism of photo resist micro bubble at different in-coming wafer surface condition and tested a series of pre treatment optimization method to resolve photo resist micro bubble defect on different wafer substrate, including in the standard flat and smooth wafer surface and also in special wafer surface with high density line/space micro-structure substrate as is in logic process FinFET tri-gate structure and Nor type flash memory cell area Floating Gate/ONO/Control Gate structure. As is discovered in our paper, in general flat and smooth wafer surface, the photo resist micro bubble is formed during resist RRC coating process (resist reduction coating) and will easy lead to Si concave defect after etch; while in the high density line/space micro-structure substrate as FinFET tri-gate, the photo resist void defect is always formed after lithography pattern formation and will final cause the gate line broken after the etching process or localized over dose effect at Ion IMP layers. The 2nd type of photo resist micro bubble is much more complicated and hard to be eliminated. We try to figure out the interfacial mechanism between different type of photo resist (ArF, KrF and I-line) and pre-wet solvent by systematic methods and DOE splits. And finally, we succeeded to dig out the best solution to eliminate the micro bubble defect in different wafer surface condition and implement in the photolithography process.

Yang, Xiaosong; Zhu, XiaoZheng; Cai, Spencer

2014-04-01

382

Parallel Logic Level simulation of VLSI Circuits In this paper, we study parallel logic level simulation of combinational VLSI Boolean  

E-print Network

Parallel Logic Level simulation of VLSI Circuits Abstract In this paper, we study parallel logic evaluated the impact on parallel circuit simulation of different number of partitions with different. Few staticstics have been published to exploit the parallelism and analyze performance in circuit

Cong, Jason "Jingsheng"

383

Boston University EC 578 FABRICATION TECHNOLOGY OF INTEGRATED CIRCUITS  

E-print Network

. Ion implantation. SOI wafers. 4. Oxidation, kinetics of oxidation, wet and dry oxidation, color chart. Design of the diffusion process. Ion implantation. 6. Photolithography and masks. Mask design technological steps starting with plain wafer; the wafer containing a few hundred patterned chips should

384

TOPICAL REVIEW: Wafer level packaging of MEMS  

NASA Astrophysics Data System (ADS)

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

Esashi, Masayoshi

2008-07-01

385

Devices using resin wafers and applications thereof  

DOEpatents

Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

2009-03-24

386

Optical cavity furnace for semiconductor wafer processing  

DOEpatents

An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

Sopori, Bhushan L.

2014-08-05

387

Molecular dynamics studies of silica wafer bonding  

NASA Astrophysics Data System (ADS)

Molecular dynamics simulations are performed to investigate the atomic processes initiated by the adhesion of two silica surfaces, which are covered with adsorbates of oxygen, hydrogen or water molecules. The calculations describe the mechanism of hydrophilic silicon wafer bonding in terms of empirical potentials assumed. The challenge of the macroscopically relevant computations is to understand and to predict the formation of covalent bonds as a function of initial silica structures, external forces, adsorbates, and annealing temperatures applied.

Timpel, Dirk; Schaible, Max; Scheerschmidt, Kurt

1999-03-01

388

Precipitating Chromium Impurities in Silicon Wafers  

NASA Technical Reports Server (NTRS)

Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

Salama, A. M.

1982-01-01

389

On-wafer large signal pulsed measurements  

Microsoft Academic Search

The authors present an on-wafer fully automated pulse-measurement system for automatically extracting the characteristics of the nonlinear current generators of a field-effect transistor (FET) as a function of the gate-to-source and drain-to-source voltages. Measurements performed for different DC and pulse width voltage conditions make it possible to extract accurate nonlinear FET models and analyze the trapping and temperature effects. The

J. F. Vidalou; F. Grossier; M. Camiade; J. Obregon

1989-01-01

390

Batch-dissolved wafer process for low-cost sensor applications  

NASA Astrophysics Data System (ADS)

As microsensor technology continues to grow and mature, the issues of cost and manufactureability become key issues in determining whether silicon transducer technologies are commercially viable. The dissolved wafer process is an attractive manufacturing technology for the production of low cost, high volume transducers. The process requires only 3 masking steps and the tooling for micromachining is inexpensive. Six sigma level yield is attainable and the turnaround time for a lot is 1.5-2 weeks for one work shift operation. This technology is currently being implemented in commercial production low cost inertial instruments.

Cho, Steve T.

1995-09-01

391

Stanford University Concurrent VLSI Architecture Memo 124 Elastic Buffer Networks-on-Chip  

E-print Network

Michelogiannakis , James Balfour and William J. Dally Concurrent VLSI Architecture Group Computer Systems Laboratory Stanford University, Stanford, CA 94305 Email: {mihelog,jbalfour,dally}@stanford.edu Abstract

Lee, Thomas H.

392

An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm  

NASA Astrophysics Data System (ADS)

The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

2015-02-01

393

The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)  

NASA Astrophysics Data System (ADS)

The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

Yeh, Ching-Fa; Hwangleu, Shyang

1992-05-01

394

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off  

NASA Astrophysics Data System (ADS)

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

2015-03-01

395

Dual side wafer metrology for micromachining applications  

NASA Astrophysics Data System (ADS)

Advances in micromachining (MEMS) applications such as optical components, inertial and pressure sensors, fluidic pumps and radio frequency (RF) devices are driving lithographic requirements for tighter registration, improved pattern resolution and improved process control on both sides of the substrate. Consequently, there is a similar increase in demand for advanced metrology tools capable of measuring the Dual Side Alignment (DSA) performance of the lithography systems. There are a number of requirements for an advanced DSA metrology tool. First, the system should be capable of measuring points over the entire area of the wafer rather than a narrow area near the lithography alignment targets. Secondly, the system should be capable of measuring a variety of different substrate types and thicknesses. Finally, it should be able to measure substrates containing opaque deposited films such as metals. In this paper, the operation and performance of a new DSA metrology tool is discussed. The UltraMet 100 offers DSA registration measurement at greater than 90% of a wafer's surface area, providing a true picture of a lithography tool"s alignment performance and registration yield across the wafer. The system architecture is discussed including the use of top and bottom cameras and the pattern recognition system. Experimental data is shown for tool repeatability and reproducibility over time.

Schurz, Dan; Flack, Warren W.; Anberg, Doug

2004-05-01

396

Mask-to-wafer alignment system  

DOEpatents

A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

2003-11-04

397

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging  

NASA Astrophysics Data System (ADS)

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

2014-07-01

398

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.  

PubMed

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-01

399

vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM  

ERIC Educational Resources Information Center

This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

2014-01-01

400

High density circuit technology, part 1  

NASA Technical Reports Server (NTRS)

The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

Wade, T. E.

1982-01-01

401

Wafer-level Accelerated Lifetesting of Individual Devices  

Microsoft Academic Search

The thermal activation energies of TriQuint Semiconductor's TQPED devices are evaluated with an innovative wafer-level technique for accelerated life testing. The method was used to determine the activation energy for. both the depletion-mode and enhancement-mode pHEMT devices. An on-wafer heating element around individual devices allowed stressing at various temperatures on the same wafer. Temperatures above 275degC were easily achieved without

D. J. M. Hamada; W. J. Roesch

2007-01-01

402

High Strength Si Wafers with Heavy B and Ge Codoping  

Microsoft Academic Search

Si wafers with heavy B and Ge codoping have been characterized in comparison with lightly B-doped and heavily B-doped Si wafers as references. It was found that only a very few slip dislocations could be observed in the heavily B- and Ge-codoped (1019 atoms\\/cm3) Si wafers, whereas many slip dislocations were observed in both the heavily B-doped (1019 atoms\\/cm3) and

Xinming Huang; Tsuyoshi Sato; Masami Nakanishi; Toshinori Taishi; Keigo Hoshikawa

2003-01-01

403

Study on Subsurface Damage Generated in Ground Si Wafer  

Microsoft Academic Search

In this paper, we study and evaluate the subsurface damage of the ground wafers to understand the effect of residual stress\\u000a on the wafer deflection. The experimental results show that two indexes of depth of the damaged layer and degree of the residual\\u000a stress are directly associated with the warpage of wafer. The degree of the damage decreases with an

Bahman Soltani Hosseini; Libo Zhou; Tatsuya Tsuruga; Jun Shimizu; Hiroshi Eda; Sumio Kamiya; Hisao Iwase

404

Wafer-Level Membrane-Transfer Process for Fabricating MEMS  

NASA Technical Reports Server (NTRS)

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

405

Wafer-based nanostructure manufacturing for integrated nanooptic devices  

Microsoft Academic Search

The authors have developed a nanomanufacturing platform based on wafer-level nanoreplication with mold and nanopattern transfer by nanolithography. The nanoreplication process, which is based on imprinting a single-layer spin-coated ultraviolet (UV)-curable resist, achieved good nanopatterning fidelity and on-wafer uniformity with high throughput. Some manufacturing issues of the nanoreplication process, such as the impact of wafer and mold surface particles on

Jian Jim Wang; Lei Chen; Stephen Tai; Xuegong Deng; P. F. Sciortino; Jiandong Deng; Feng Liu

2005-01-01

406

MEMS Vertical Probe Cards With Ultra Densely Arrayed Metal Probes for Wafer-Level IC Testing  

Microsoft Academic Search

We have developed a MEMS probe-card technology for wafer-level testing ICs with 1-D line-arrayed or 2-D area-arrayed dense pads layouts. With a novel metal MEMS fabrication technique, an area-arrayed tip matrix is realized with an ultradense tip pitch of 90 mum times196 mum for testing 2-D pad layout, and a 50-mum minimum pitch is also achieved in line-arrayed probe cards

Fei Wang; Rong Cheng; Xinxin Li

2009-01-01

407

Wafer level package with thermal-stress-absorbing interface structure and elongated pad  

Microsoft Academic Search

The increasing demand for high performance, cost-effective, and smallest packages has led to wafer level package (WLP). One of the biggest concerns about this technology is the interconnection reliability during thermal cycling. To improve solder joint reliability in WLP a thermal-stress-absorbing interface structure consisting of two stress-buffering polymer layers and elongated pad design was investigated in this study. To efficiently

Gu-Sung Kim; Sarah Eunkyung Kim

408

A wafer-bonded floating-element shear stress microsensor with optical position sensing by photodiodes  

Microsoft Academic Search

This paper discusses a noninvasive sensing technique for the direct measurement of low-magnitude shear stresses in laminar and turbulent air flows. The sensing scheme detects the flow-induced in-plane displacement of a microfabricated floating-element structure (500 ?m×500 ?m×7 ?m), using integrated photodiodes. The wall-mounted floating-element sensors were fabricated using a wafer-bonding technology. The sensors were calibrated in a custom-designed laminar flow

Aravind Padmanabhan; Howard Goldberg; Kenneth D. Breuer; Martin A. Schmidt

1996-01-01

409

Radiation hardness and annealing tests of a custom VLSI device  

SciTech Connect

Several NMOS custom VLSI ( Microplex'') circuits have been irradiated with a 500 rad/hr {sup 60}Co source. With power off three of four chips tested have survived doses exceeding 1 Mrad. With power on at a 25% duty cycle, all chips tested failed at doses ranging from 10 to 130 krad. Annealing at 200{degree}C was only partially successful in restoring the chips to useful operating conditions. 10 refs., 4 figs., 1 tab.

Breakstone, A.; Parker, S.; Adolphsen, C.; Litke, A.; Schwarz, A.; Turala, M.; Lueth, V. (Hawaii Univ., Honolulu, HI (USA); California Univ., Santa Cruz, CA (USA). Inst. for Particle Physics; Stanford Linear Accelerator Center, Menlo Park, CA (USA))

1986-10-01

410

Parallel Random Number Generation for VLSI Systems Using Cellular Automata  

Microsoft Academic Search

A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in parallel from various cells in the cellular automaton on each

Peter D. Hortensius; Robert D. Mcleod; Howard C. Card

1989-01-01

411

Computing perspectives: the rise of the VLSI processor  

Microsoft Academic Search

Around 1970 Intel discovered it could put 2,000 transistors—or perhaps a few more—on a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), an event which had been long heralded, but had been seemingly slow to come. At the time, it went almost unnoticed in the computer industry. This was partly

Maurice V. Wilkes

1990-01-01

412

A systematic method for configuring VLSI networks of spiking neurons.  

PubMed

An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems. PMID:21732859

Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

2011-10-01

413

Digital VLSI algorithms and architectures for support vector machines.  

PubMed

In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements. PMID:11011788

Anguita, D; Boni, A; Ridella, S

2000-06-01

414

Multiprocessor CAD system for the simulation of digital VLSI circuits  

NASA Astrophysics Data System (ADS)

A multiprocessor CAS system for the simulation of digital VLSI circuits is presented. The parallel activities of logic and fault simulators were investigated. The minimum hardware requirements were derived and a master-slave configuration with three slave computers in 32-bit architecture and programmable microprogram stores was elaborated. The logic and fault simulators for this configuration were developed. System control programs were developed and the whole simulation system was implemented and tested successfully.

Gross, A.; Jud, W.; Jaeger, U.

1983-05-01

415

A Systematic Method for Configuring VLSI Networks of Spiking Neurons  

Microsoft Academic Search

An increasing number of research groups are developing custom hybrid analog\\/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of

Emre Neftci; Elisabetta Chicca; Giacomo Indiveri; Rodney Douglas

2011-01-01

416

A new VLSI-oriented FFT algorithm and implementation  

Microsoft Academic Search

In this paper, we present a new VLSI-oriented fast Fourier transform (FFT) algorithm-radix-2\\/4\\/8, which can effectively minimize the number of complex multiplications. This algorithm can be implemented efficiently using a pipelined architecture. Based on this pipelined architecture, an 8 K FFT ASIC is designed for use in the DVB (Digital Video Broadcasting) application in 0.6 ?m-3.3 V triple-metal CMOS process

Lihong Jia; Yonghong Gao; Jouni Isoaho; Hannu Tenhunen

1998-01-01

417

VLSI compressor design with applications to digital neural networks  

Microsoft Academic Search

A key problem for implementing high-performance, high-capacity digital neural networks (DNN) is to design effective VLSI compressors to reduce the impact of carry propagation of large data matrix. In this paper, such a compressor design based on complex complementary pass-transistor logic (C\\/sup 2\\/PL) is presented. Some types of 3-2 compressors in C\\/sup 2\\/PL are implemented and a number of experiments

David Zhang; Mohamed I. Elmasry

1997-01-01

418

A VLSI single chip 8-bit finite field multiplier  

NASA Astrophysics Data System (ADS)

A Very Large Scale Integration (VLSI) architecture and layout for an 8-bit finite field multiplier is described. The algorithm used in this design was developed by Massey and Omura. A normal basis representation of finite field elements is used to reduce the multiplication complexity. It is shown that a drastic improvement was achieved in this design. This multiplier will be used intensively in the implementation of an 8-bit Reed-Solomon decoder and in many other related projects.

Deutsch, L. J.; Shao, H. M.; Hsu, I. S.; Truong, T. K.

1985-11-01

419

A VLSI single chip 8-bit finite field multiplier  

NASA Technical Reports Server (NTRS)

A Very Large Scale Integration (VLSI) architecture and layout for an 8-bit finite field multiplier is described. The algorithm used in this design was developed by Massey and Omura. A normal basis representation of finite field elements is used to reduce the multiplication complexity. It is shown that a drastic improvement was achieved in this design. This multiplier will be used intensively in the implementation of an 8-bit Reed-Solomon decoder and in many other related projects.

Deutsch, L. J.; Shao, H. M.; Hsu, I. S.; Truong, T. K.

1985-01-01

420

Low-temperature thin-film indium bonding for reliable wafer-level hermetic MEMS packaging  

NASA Astrophysics Data System (ADS)

This paper reports on low-temperature and hermetic thin-film indium bonding for wafer-level encapsulation and packaging of delicate and temperature sensitive devices. This indium-bonding technology enables bonding of surface materials commonly used in MEMS technology. The temperature is kept below 140?°C for all process steps and no surface treatment is applied before and during bonding. This bonding technology allows hermetic sealing at 140?°C with a leak rate below 4?×?10-12?mbar l s-1 at room temperature. The tensile strength of the bonds up to 25 MPa goes along with a very high yield.

Straessle, R.; Pétremand, Y.; Briand, D.; Dadras, M.; de Rooij, N. F.

2013-07-01

421

Characterization of silicon wafers by transient microwave photoconductivity measurements  

NASA Astrophysics Data System (ADS)

The possibilities and limitations of characterizing single crystalline silicon wafers with a contactless, nondestructive transient photoconductivity method, i.e. the time resolved microwave (TRMC) method has been demonstrated. The bulk lifetime and the diffusion constant of minority charge carriers in n- and p-doped silicon wafers (?: 1-200 ? cm) were determined in two different ways: by varying the wafer thickness and by changing the surface recombination velocity via different etching treatments. Using electron irradiated (14 MeV) wafers, it was shown that this method can be used for the detection of changes in the bulk lifetime.

Sanders, A.; Kunst, M.

1991-09-01

422

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

Selwyn, G.S.

1998-12-15

423

Micro-miniature gas chromatograph column disposed in silicon wafers  

DOEpatents

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, Conrad M. (Antioch, CA)

2000-01-01

424

Wafer-scale aluminum nano-plasmonics  

NASA Astrophysics Data System (ADS)

The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

2014-09-01

425

VLSI Architecture for Data-Reduced Steering Matrix Feedback in MIMO Systems  

E-print Network

hardware-optimized compression/decompression architecture. Our VLSI implementation achieves up to 50% data systems. For the most promising compression/decompression scheme, we describe a VLSI architecture-throughput steering matrix com- pression/decompression unit that requires low silicon area. Outline: The remainder

426

Biophysical Synaptic Dynamics in an Analog VLSI Network of Hodgkin-Huxley Neurons  

E-print Network

Biophysical Synaptic Dynamics in an Analog VLSI Network of Hodgkin-Huxley Neurons Theodore Yu1 in an analog VLSI silicon microchip. The four neurons implement a gen- eralized Hodgkin-Huxley model to interface with biological systems as a prosthesis. Here we present a network of Hodgkin-Huxley [2] neurons

Cauwenberghs, Gert

427

A Yield Study of VLSI Adders 1 Zhan Chen and Israel Koren  

E-print Network

A Yield Study of VLSI Adders 1 Zhan Chen and Israel Koren Department of Electrical and Computer designed and their ezpected yield has been estimated. OUT Tesults show that the yield of VLSI adders can structure. In certain situations, these approaches can improve the yield by 10% to 17%. 1. Introduction

Koren, Israel

428

Techniques for Yield Enhancement of VLSI Adders 1 Zhan Chen and Israel Koren  

E-print Network

Techniques for Yield Enhancement of VLSI Adders 1 Zhan Chen and Israel Koren Department application-specific a m y s and other regular VLSI circuits, two techniques are available for yield enhancement, namely defect-tolerance and layout modifications. In this paper, we compare these two yield

Koren, Israel

429

Course Number: EC 571 Course Name: VLSI Principles & Applications Semester: Spring 2011  

E-print Network

VLSI SC571 Fall 2010 Course Number: EC 571 Course Name: VLSI Principles & Applications Semester: Spring 2011 Number of credits: 4 Prerequisites: EC 311, EC 410 (optional) Lecture time & place: PSY B33 MW10-12 Available materials and links. See Blackboard 8 Staff Information Ā· Instructor: Name: Allyn E

Karpovsky, Mark

430

Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards. [Very Large Scale Integration (VLSI)  

SciTech Connect

This paper discusses the sensor-based driving of a car in a-priori unknown environments using human-like'' reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver's aid using the new fuzzy inferencing VLSI hardware and human-like'' reasoning schemes.

Pin, F.G.; Watanabe, Y.

1992-01-01

431

The investigation on research opportunities for the applications of the Internet of Things in semiconductor wafer fabrication  

Microsoft Academic Search

Based on the state-of-the-art technologies of the Internet of Things (IOT) and Radio Frequency Identifier (RFID) this paper introduces the concepts of IOT\\/RFID and investigates its open research opportunity and potential applications in real-time monitoring and dispatch controls for semiconductor wafer fabrication (FAB).

Yong-Zai Lu

2010-01-01

432

Ultra-Low Noise HEMT Device Models: Application of On-Wafer Cryogenic Noise Analysis and Improved Parameter Extraction Techniques  

NASA Technical Reports Server (NTRS)

Significant advances in the development of HEMT technology have resulted in high performance cryogenic low noise amplifiers whose noise temperatures are within an order of magnitude of the quantum noise limit. Key to the identification of optimum HEMT structures at cryogenic temperatures is the development of on-wafer noise and device parameter extraction techniques. Techniques and results are described.

Bautista, J. J.; Hamai, M.; Nishimoto, M.; Laskar, J.; Szydlik, P.; Lai, R.

1995-01-01

433

A novel wafer level hermetic packaging for MEMS devices using micro glass cavities fabricated by a hot forming process  

Microsoft Academic Search

Hermetic or vacuum packaging to maintain a controllable cavity pressure and low costs are required by many MEMS devices having moving parts. A novel fabrication technology using micro glass cavities for wafer level hermetic MEMS packaging including accelerometer or gyroscope will be presented. The micro cavities were fabricated by a hot-forming process using Pyrex 7740 since its coefficient of thermal

Di Zhang; Jintang Shang; Boyin Chen; Chao Xu; Junwen Liu; Hui Yu; Xinhu Luo; Jingdong Liu

2010-01-01

434

Novel SOI wafer engineering using low stress and high mobility CMOSFET with -channel for embedded RF\\/analog applications  

Microsoft Academic Search

For high performance RF\\/analog and logic device technology, novel SOI wafer engineering featuring -channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from to . Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (fmax) for NMOSFET is improved around 7%

T. Matsumoto; S. Maeda; H. Dang; T. Uchida; K. Ota; Y. Hirano; H. Sayama; T. Iwamatsu; T. Ipposhi; H. Oda; S. Maegawa; Y. Inoue; T. Nishimura

2002-01-01

435

Mechanisms for room temperature direct wafer bonding  

NASA Astrophysics Data System (ADS)

Reducing the temperature needed for high strength bonding which was and is driven by the need to reduce effects of coefficient of thermal expansion mismatch, reduce thermal budgets, and increase throughput has led to the development of plasma treatment procedures capable of bonding Si wafers below 300 °C with a bond strength equivalent to Si bulk. Despite being widely used, the physical and chemical mechanisms enabling low temperature wafer bonding have remained poorly understood. We developed an understanding of the beneficial surface modifications by plasma and a model based on short range low temperature diffusion through bonding experiments combined with results from spectroscopic ellipsometry, depth resolving Auger electron spectroscopy, and transmission electron microscopy measurements. We also present experimental results showing that even at room temperature reasonable bond strength can be achieved. We conclude that the gap closing mechanism is therefore a process which balances the lowering of the total energy by minimizing the sum of the free surface energy (maximizing the contact area between the surfaces) and strain energy in the oxide at the bond interface.

Plach, T.; Hingerl, K.; Tollabimazraehno, S.; Hesser, G.; Dragoi, V.; Wimplinger, M.

2013-03-01

436

Low-temperature hydrophobic silicon wafer bonding  

NASA Astrophysics Data System (ADS)

By introducing a nanometer-scale H trapping defective silicon layer on bonding surfaces, the bonding surface energy of bonded oxide-free, HF dipped, hydrophobic silicon wafers can reach a silicon fracture surface energy of 2500 mJ/m2 at 300 to 400 °C compared with 700 °C conventionally achieved. Adding boron atoms on bonding surfaces can reduce the surface hydrogen release temperature but would not increase the bonding energy unless a defective layer is also formed. This indicates that, in order to achieve high bonding energy, the released hydrogen must be removed from the bonding interface. Many prebonding treatments are available for low-temperature hydrophobic wafer bonding including the formation of an amorphous silicon layer by As+ implantation, by B2H6 or Ar plasma treatment, or by sputter deposition, followed by an HF dip and room temperature bonding in air. The interface amorphous layer may be recrystallized by annealing at elevated temperatures, e.g., at 450 °C for As+-implanted samples.

Tong, Q.-Y.; Gan, Q.; Hudson, G.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

2003-12-01

437

Quantification of CD-SEM wafer global charging effect on CD and CD uniformity of 193-nm lithography  

NASA Astrophysics Data System (ADS)

For 90 nm technology and below, we need to fight for every nanometer to improve the CD uniformity (CDU). New materials, especially for low-k material, bring about not only complicated integration challenges, but also new metrology difficulties such as SEM image focus failure if using low landing energy (300V) on charging wafer (e.g. -300V). The wafer global charging will also distort the CD SEM magnification and result in CD measurement error. CD SEM venders propose that the distortion be corrected by voltage contrast focus. In order to compare and quantify the measurement error correction with and without using retarding voltage focus, ArF resist non-uniform charging wafers (~ -300V) and low charging wafers (~ -7V) were prepared. Low landing energy like 300V is one of the solutions for ArF resist shrinkage. However, as the low landing energy (300V) meets the high global charging wafer (-300V), SEM cannot get sufficient secondary electron signal to construct image. Therefore, two landing voltages 500eV and 800eV were chosen for the evaluation. Three pitches 1600 nm, 460 nm and 230 nm were investigated. Two indexes are used to evaluate the wafer global charging effect on CD and CDU. One is within-wafer pitch uniformity for determining the CD SEM magnification error. The other is ArF-resist-shrinkage amplitude used to estimate the effective landing energy at charging area. The experimental results show that the pitch uniformity difference with and without using retarding focus can be larger than 2.5 nm. Similar phenomenon is also found for the line width uniformity. Resist shrinkage amplitude is significantly reduced at the highly charged area. Both results show that accurate focus procedure, i.e. retarding voltage focus employing first, is the key to reduce the CD metrology tool measurement error and improve CDU.

Ke, Chih-Ming; Hung, Hsueh-Liang; Chang, Anderson; Chen, Jeng-Horng; Gau, Tsai-Sheng; Ku, Yao-Ching; Lin, Burn J.; Otaka, Tadashi; Ueda, Kazuhiro; Kawada, Hiroki; Nomura, Hiroaki; Ren, Nelson

2004-05-01

438

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing  

NASA Technical Reports Server (NTRS)

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Aanstoos, J. V.; Snyder, W. E.

1981-01-01

439

The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line  

NASA Astrophysics Data System (ADS)

The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the standpoint of the generations of hundreds of SSIS recipes for the global member companies of ISMI, it is simply not economically viable to create all recipes based on PSL based light scattering response curves. This paper will explore the challenges/end results encountered with the PSL based SSIS recipe generation and compare those against the challenges/end results of SSIS recipes generated based strictly upon theoretical Bidirectional reflectance distribution function (BRDF) light scattering modeling. The BRDF modeling will allow for the creation of SSIS recipes without PSL deposition, which is greatly appealing for a multitude of both technical and commercial considerations. This paper will also explore the technical challenges of SSIS recipe generation based strictly upon BRDF modeling.

Lee, Jeffrey; McGarvey, Steve

2013-04-01

440

Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint  

SciTech Connect

This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

Rupnowski, P.; Sopori, B.

2008-05-01

441

Determination of bending stress of Si wafer using concentrated load  

Microsoft Academic Search

The technique of concentrated load with a simple O-ring supporter is used to measure the deflection of Si wafers. The load varies so that the ratio of the deflection to the wafer thickness changes from 0 to 1. For some samples, this ratio goes up to 1.4 at which the samples are fractured. It is observed in the experiment that

L. D. Chen; M. J. Zhang; S. Zhang

1994-01-01

442

Influence of bonding atmosphere on low-temperature wafer bonding  

Microsoft Academic Search

The influence of bonding atmosphere was investigated for the wafer bonding at 25~200°C using a surface activated bonding method. The results of the analysis of activated Si surfaces under different vacuum background and the residual gases in vacuum before and after Ar fast atom beam irradiation is reported. Based on the analysis, bonding of Si wafers in nitrogen atmosphere is

Ying-Hui Wang; Tadatomo Suga

2010-01-01

443

Wafer-Scale Microtensile Testing of Thin Films  

Microsoft Academic Search

This paper reports on the mechanical characterization of thin films using the microtensile technique performed for the first time at the wafer scale. Multiple test structures are processed and sequentially measured on the same silicon substrate, thus eliminating delicate handling of individual samples. The current layout uses 26 test structures evenly distributed over a 4-in wafer, each of them carrying

JoĆo Gaspar; Marek E. Schmidt; Jochen Held; Oliver Paul

2009-01-01

444

Improved method of dicing integrated circuit wafers into chips  

NASA Technical Reports Server (NTRS)

Method employing a pressure chamber is used for dicing semiconductor single-crystal wafers, containing integrated circuits, into small chips along pre-scribed lines. Uniform bending of the scribed wafer over the convex surface of a perforated hemisphere, breaks it cleanly into individual chips without damaging the circuits.

Litant, I.; Scapicchio, A. J.

1969-01-01

445

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Selwyn, Gary S. (Los Alamos, NM)

1998-01-01

446

Analysis of wafer stresses during millisecond thermal processing  

Microsoft Academic Search

A flash lamp has been used to uniformly anneal large wafers with diameters approaching 100 mm. The equipment applies a pulse, with duration of 3-20 ms, resulting in large transient thermal gradients in the wafer. In this paper, we present separate models of the thermal reaction of this process and its effect upon the mechanical behavior, in order to predict

M. P. Smith; K. A. Seffen; R. A. McMahon; M. Voelskow; W. Skorupa

2006-01-01

447

Analysis of wafer stresses during millisecond thermal processing  

Microsoft Academic Search

A flash lamp has been used to uniformly anneal large wafers with diameters approaching 100 mm. The equipment applies a pulse, with duration of 3–20 ms, resulting in large transient thermal gradients in the wafer. In this paper, we present separate models of the thermal reaction of this process and its effect upon the mechanical behavior, in order to predict

M. P. Smith; K. A. Seffen; R. A. McMahon; M. Voelskow; W. Skorupa

2006-01-01

448

REDUCED WAFER WARPAGE AND STRESS IN JSR DIELECTRIC FILMS  

Microsoft Academic Search

The addition of polymer dielectric films to silicon wafers is useful in producing stress reduction layers and interconnect structures for chip-scale packaging as well as 3D wafer stacks. The use of lower cure temperature materials offers several advantages including a lowered thermal budget on devices that are sensitive to electrical performance change with temperature. Unfortunately, enough stress remains from the

Robert L. Hubbard; Iftikhar Ahmad; Keith Hicks

449

Wafer-level calibration of stress sensing test chips  

Microsoft Academic Search

Piezoresistive sensors are a powerful tool for measurement of surface stress states in semiconductor die used within electronic packages. A new wafer-level method for calibrating on-chip piezoresistive stress sensors is presented, in which an entire circular silicon wafer (potentially containing hundreds of fabricated stress sensing chips) is supported on its edge as a simply supported plate and loaded using a

J. C. Suhling; R. A. Cordes; Y. L. Kang; R. C. Jaeger

1994-01-01

450

Contactless Characterization of Silicon Wafers Dieter K. Schroder  

E-print Network

strength thin film. The sensor electrode is held above the wafer by a porous ceramic air bearing, which provides for a very stable distance from the wafer as long as the load on the air bearing does not change, shown in Fig. 1. Pressurizing a bellows provides the controlled load. As air escapes through the porous

Schroder, Dieter K.

451

Laser induced stress wave thermometry applied to silicon wafer processing  

E-print Network

during rapid thermal processing (RTP) of silicon wafers. Wafers of 0.76mm thickness and 200 mm diameter are used in the study at temperatures ranging from 23 to 400°C. The waveguide modes generated are identified with the aid of the orthotropic...

Rabroker, George Andrew

2000-01-01

452

Investigations of Wafer Scale Etching with Xenon Difluoride  

NASA Astrophysics Data System (ADS)

A good and uniform bulk silicon wafer etching method can be applied to the wafer thinning process in MEMS and 3D applications. In this study, the use of a Xenon Difluoride (XeF2) gas-phase etching system, operating at room temperature, has been investigated for bulk silicon wafer thinning. We investigated the Si-wafer surface morphology and profile following each XeF2 etching process cycle. Theoretical results are used to compare with the experimental results as well. A clean wafer surface by proper surface treatments is significant to achieve a uniform surface profile and morphology for XeF2 etching. A proper design of etching cycle with nitrogen ambient during etching is necessary to achieve the fastest and uniform silicon etching rate. The silicon etching rate is reported as a function of etching pressure, nitrogen pressure, and etching duration.

Chen, K. N.; Hoivik, N.; Lin, C. Y.; Young, A.; Ieong, M.; Shahidi, G.

2006-03-01

453

Reduction of Thermal Conductivity in Wafer-Bonded Silicon  

SciTech Connect

Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

2006-11-27

454

Packaging solution for VLSI electronic photonic chips  

E-print Network

As the demand of information capacity grows, the adoption of optical technology will increase. The issue of resistance and capacitance is limiting the electronic transmission bandwidth while fiber optic delivers data at ...

Lee, Chieh-feng

2007-01-01

455

Approaching new metrics for wafer flatness: an investigation of the lithographic consequences of wafer non-flatness  

NASA Astrophysics Data System (ADS)

Flatness of the incoming silicon wafer is one major contributor to the ultimate focusing limitation of modern exposure tools. Exposure tools are designed to chuck wafers without creating non-flatness and then use focus control to follow as closely as possible the chucked wafer front surface topography. The smaller size of the exposure slit in a step-and-scan exposure tool, as compared to the previous generation full-field stepper tool, helps minimize the impact of chucked wafer non-flat topography. However, to maintain high throughput and improve critical dimension uniformity (CDU) at sub-wavelength line-widths requires continuous improvement in the incoming silicon wafer flatness. In this paper we report extensive experimental results that review existing wafer flatness metrics and propose the addition of a new metric. The new metric emulates the scanning motion of exposure by integrating the defocus that each point on the wafer experiences during exposure. We show that this method is in better spatial agreement with measured defocus in step-and-scan exposure tools. Simple metrics of moving average (MA) defocus prediction analysis will be defined and shown to correlate very well to post exposure defocus data. These experiments were enabled by the creation of special 300-nm wafers by MEMC. These special wafers include sites with a wide variation in flatness. Prior to exposure the wafers were measured with a high-resolution optical flatness metrology tool (WaferSight by ADE) to obtain industry standard thickness variation (flatness) data. Incoming wafer flatness data is used to predict wafer suitability for lithography at the desired device geometry node (e.g., 90 nm). The flatness data was processed and characterized using both standard metrics (SFQR) and the new MA analysis. The relationship between the industry standard metric (SFQR) and similar metrics applied to MA analysis will be presented. Full two-dimensional maps are used to present spatial correlations and permit simple physical insights into the flatness data sets. Measurements of chucked wafer flatness were made on the same wafers using ASML TWINSCAN in-line metrology. These measurements correlate very well to thickness-based flatness. Un-chucked wafer flatness metrics (SFQR and MA) are shown to correlate well to post exposure defocus data when an appropriate site size is used. This result is discussed in relationship to the industry-accepted practice of specifying un-chucked wafer flatness. Lithography performance tests were made to prove the relevance of the different flatness metrics. The same special wafers are used for lithography performance tests. These tests achieve excellent correlation between post-exposure full-wafer focus control results and predictions based on both SFQ (industry standard) and MA re-mapping of the flatness data. The relationship between measured critical dimension (CD) and defocus is also explored. Point-by-point analysis of CD residual versus measured defocus data nicely follows a Bossung curve. We also show that residual CD values predicted from defocus correlate well with measured values. These experiments confirm the application of industry standard wafer flatness measurements to step-and-scan lithography when appropriately using current metrics. They also present the potential for improved metrics based on the MA defocus prediction analysis to help drive continuous improvement of wafer flatness for advanced step-and-scan lithography.

Valley, John F.; Poduje, Noel; Sinha, Jaydeep; Judell, Neil; Wu, Jie; Boonman, Marc; Tempelaars, Sjef; van Dommelen, Youri; Kattouw, Hans; Hauschild, Jan; Hughes, William; Grabbe, Alexis; Stanton, Les

2004-05-01

456

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

457

1.55 ?m hybrid waveguide laser made by ion-exchange and wafer bonding  

NASA Astrophysics Data System (ADS)

Distributed Feed Back (DFB) lasers working in the third telecom window are essential for optical communications, eyesafe sensors and lab-on-chip devices. Glass integrated optics technology allows realizing such devices by using rareearth doped substrates. Despite their good output power and spectral characteristic, DFB lasers still present some reliability issues concerning the Bragg grating protection. Moreover Erbium doped glasses are not compatible with the realization of passive optical functions. In order to solve the DFB lasers reliability issues and to ensure a monolithic integration between active and passive functions, we propose an hybrid-device architecture based on ion-exchange technology and wafer bonding. The Ag+/Na+ ion-exchange in the silicate glass wafer is used to realize the passive functions and the lateral confinement of the electromagnetic field. Through a second ion exchange step, a slab waveguide is made on the Erbium-Ytterbium doped glass wafer. The Bragg grating is processed on the passive substrate and the two glasses are bonded. The potential of this structure has been demonstrated through the realization of a DFB hybrid laser with a fully encapsulated Bragg grating.

Casale, Marco; Bucci, Davide; Bastard, Lionel; Broquin, Jean-Emmanuel

2012-01-01

458

Design Study of Wafer Seals for Future Hypersonic Vehicles  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

459

Wafer-level Au-Au bonding in the 350-450 °C temperature range  

NASA Astrophysics Data System (ADS)

Metal thermocompression bonding is a hermetic wafer-level packaging technology that facilitates vertical integration and shrinks the area used for device sealing. In this paper, Au-Au bonding at 350, 400 and 450 °C has been investigated, bonding wafers with 1 µm Au on top of 200 nm TiW. Test Si laminates with device sealing frames of 100, 200, and 400 µm in width were realized. Bond strengths measured by pull tests ranged from 8 to 102 MPa and showed that the bond strength increased with higher bonding temperatures and decreased with increasing frame width. Effects of eutectic reactions, grain growth in the Au film and stress relaxation causing buckles in the TiW film were most pronounced at 450 °C and negligible at 350 °C. Bond temperature below the Au-Si eutectic temperature 363 °C is recommended.

Tofteberg, Hannah R.; Schjųlberg-Henriksen, Kari; Fasting, Eivind J.; Moen, Alexander S.; Taklo, Maaike M. V.; Poppe, Erik U.; Simensen, Christian J.

2014-08-01

460

Mixing And Matching Of Wafer Steppers And Wafer Scanners For Cost-Effective, High-Volume Device Production  

NASA Astrophysics Data System (ADS)

The mixing and matching of Step-and-Repeat Alignment systems and wafer scanners is a viable method of providing the high levels of overlay accuracy and resolution that are now required in the manufacturing of the most advanced devices such as 1 MBIT DRAMs. At the same time, significant reduction of the production costs, especially on large wafers, are realized. The utilization of scanner systems allows very high wafer throughput, in excess of 100 wafers/hour. The utilization of Step-and-Repeat Alignment systems allows the reduction of overlay errors to less than 0.3 micron (98%). The mixing of equipment has been enhanced by the introduction of Universal Mix-and-Match Prealigners on the Micralign scanner systems. These prealigners are capable of simulating the performance of any Step-and-Repeat Alignment system prealigner by the use of wafer edge mapping techniques and special prealigner simulation algorithms in software. Using these prealigners, device arrays and alignment keys are accurately positioned on the wafers. This allows the implementation of automatic alignment systems and the maintenance of high wafer throughputs on the scanner systems. New developments in metrology equipment now allow the use of automated overlay measurement systems for the mapping of overlay errors on wafers. The extraction of equipment overlay correction factors is now possible. The implementation of such systems will allow <= 0.4-micron overlay processes, such as 1 MBIT DRAMs, to be run routinely on mixed equipment.

Sewell, Harry; Gansfried, Myles

1986-08-01

461

Analytic modeling, optimization, and realization of cooling devices in silicon technology  

Microsoft Academic Search

A novel cooling device fully built in silicon technology is presented. The new concept developed in this work consists of micromachining the bottom side of the circuit wafer in order to embed heat sinking microchannels directly into the silicon material. These microchannels are then sealed, by a direct wafer bonding procedure, with another silicon wafer where microchannels and inlet-outlet nozzles

Corinne Perret; Jumana Boussey; Christian Schaeffer; Martin Coyaud

2000-01-01

462

Piezoresistive stress sensors on (110) silicon wafers  

NASA Technical Reports Server (NTRS)

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

1992-01-01

463

Direct to digital holography for semiconductor wafer defect detection and review  

NASA Astrophysics Data System (ADS)

A method for recording true holograms directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for dining defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep UV light.

Thomas, C. E., Jr.; Bahm, Tracy M.; Baylor, Larry R.; Bingham, Philip R.; Burns, Steven W.; Chidley, Matt; Dai, Long; Delahanty, Robert J.; Doti, Christopher J.; El-Khashab, Ayman; Fisher, Robert L.; Gilbert, Judd M.; Goddard, James S., Jr.; Hanson, Gregory R.; Hickson, Joel D.; Hunt, Martin A.; Hylton, Kathy W.; John, George C.; Jones, Michael L.; Macdonald, Ken R.; Mayo, Michael W.; McMackin, Ian; Patek, Dave R.; Price, John H.; Rasmussen, David A.; Schaefer, Louis J.; Scheidt, Thomas R.; Schulze, Mark A.; Schumaker, Philip D.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin, Kenneth W., Jr.; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Jones, Paul G.; Owen, Robert W.

2002-07-01

464

Direct to Digital Holography for Semiconductor Wafer Defect Detection and Review  

SciTech Connect

A method for recording true holograms (not holographic interferometry) directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional to wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for finding defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep ultra-violet light.

ThomasJr., C. E. [nLine Corporation, Austin, TX; Bahm, Tracy M. [nLine Corporation, Austin, TX; Baylor, Larry R [ORNL; Bingham, Philip R. [nLine Corporation, Austin, TX; Burns, Steven W. [nLine Corporation, Austin, TX; Chidley, Matthew D [ORNL; Dai, Xiaolong [nLine Corporation, Austin, TX; Delahanty, Robert J. [nLine Corporation, Austin, TX; Doti, Christopher J. [nLine Corporation, Austin, TX; El-Khashab, Ayman [nLine Corporation, Austin, TX; Fisher, Robert L. [nLine Corporation, Austin, TX; Gilbert, Judd M. [nLine Corporation, Austin, TX; Cui, Hongtao [ORNL; Goddard Jr, James Samuel [ORNL; Hanson, Gregory R [ORNL; Hickson, Joel D. [nLine Corporation, Austin, TX; Hunt, Martin A. [nLine Corporation, Austin, TX; Hylton, Kathy W [ORNL; John, George C. [nLine Corporation, Austin, TX; Jones, Michael L. [nLine Corporation, Austin, TX; McDonald, Kenneth R. [nLine Corporation, Austin, TX; Mayo, Michael W. [nLine Corporation, Austin, TX; McMackin, Ian [nLine Corporation, Austin, TX; Patek, David [ORNL; Price, John H. [nLine Corporation, Austin, TX; Rasmussen, David A [ORNL; Schaefer, Louis J. [nLine Corporation, Austin, TX; Scheidt, Thomas R. [nLine Corporation, Austin, TX; Schulze, Mark A. [nLine Corporation, Austin, TX; Schumaker, Philip D. [nLine Corporation, Austin, TX; Shen, Bichuan [nLine Corporation, Austin, TX; Smith, Randall G. [nLine Corporation, Austin, TX; Su, Allen N. [nLine Corporation, Austin, TX; Tobin Jr, Kenneth William [ORNL; Usry, William R. [nLine Corporation, Austin, TX; Voelkl, Edgar [nLine Corporation, Austin, TX; Weber, Karsten S. [nLine Corporation, Austin, TX; Jones, Paul G. [nLine Corporation, Austin, TX; Owen, Robert W. [nLine Corporation, Austin, TX

2002-01-01

465

Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility  

NASA Astrophysics Data System (ADS)

One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles played by the process engineering expert and the knowledge engineer are discussed. The features of the systems are shown, particularly the interactive quality of the consultations and the ease of system use.

Weatherwax Scott, Caroline; Tsareff, Christopher R.

1990-06-01

466

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch  

NASA Astrophysics Data System (ADS)

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

467

Technology mapping with crosstalk noise avoidance  

Microsoft Academic Search

In today's VLSI designs, crosstalk effects causing chips to fail or suffer from low yields have become one of the very essential design issues. In this paper, we attempt to reduce crosstalk noise in logic and physical synthesis stage, which is usually done in post-layout stage. We propose a technology mapping method that can reduce the crosstalk noise while meeting

Fang-Yu Fan; Hung-Ming Chen; I-Min Liu

2010-01-01

468

Three dimensional integration technology using copper wafer bonding  

E-print Network

With 3-D integration, the added vertical component could theoretically increase the device density per footprint ratio of a given chip by n-fold, provide a means of heterogeneous integration of devices fabricated from ...

Fan, Andy, 1976-

2006-01-01

469

High-speed VLSI fuzzy processors designed for HEPE  

NASA Astrophysics Data System (ADS)

Neural chips now are used in the trigger devices for HEPE. Three years ago we talked the problem of using also fuzzy chip microprocessors because a fuzzy system in principle can work as a neural system and is more flexible. We made them a comparison between the two approaches and the conclusions were: fuzzy chips running at a speed suitable for trigger devices were not available on the market, therefore one should have to design his own VLSI chip while, for the neural solution, one can use commercial chips or design a dedicated VLSI chip; the fuzzy solution requires an expert to develop the fuzzy system, that is the rules, while the neural solution requires a training phase; the fuzzy solution is more flexible because you known its knowledge basis and you can improve on-line the related performances by changing the rules. To day this situation is improved because there are SW tools, called Rule Generators, able to develop a fuzzy system by means of Neural Network or Genetic Algorithms. This paper starts with a comparison between Neural Networks and Fuzzy Logic with the aim to summarize the advantages of using both the HEPE trigger devices, then are described the chips already constructed or designed: a first 1 micrometers VLSI fuzzy chip with four 7 bits input and one output running at 50 Mega Fuzzy Inference per Second therefore its processing rate depends upon the fuzzy system to process; a second one, which will be sent to the foundry next march with four 7 bit inputs running at a rate of 300 ns whichever is the fuzzy system; a third one, now in design phase, with 8 - 16 inputs running at 100 - 50 MFIPS with a rule selector to further reduce the total processing speed.

Gabrielli, Alessandro; Gandolfi, Enzo; Masetti, Massimo; Russo, Marco

1996-03-01

470

A VLSI architecture for simplified arithmetic Fourier transform algorithm  

NASA Technical Reports Server (NTRS)

The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

1992-01-01

471

A VLSI design of a pipeline Reed-Solomon decoder.  

PubMed

A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new coder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a RS code. PMID:11539661

Shao, H M; Truong, T K; Deutsch, L J; Yuen, J H; Reed, I S

1985-05-01

472

A digital neuron-type processor and its VLSI design  

SciTech Connect

A set of neuron-type circuits elements based on logic gate circuits with multi-input capability is described. Three types of elements are introduced, one called the cell body with its dendritic inputs and synaptic junction, another representing the axon base and finally the axon circuit. These three elements are cascaded to form a neuron type processing element. The circuit performs input temporal and spatial summation as well as thresholding. The entire neuron circuit is simulated and a design is given using VLSI techniques.

Habib, M.K.; Akel, H. (Electrical and Computer Engineering Dept., Kuwait Univ., 13060 Safat (KW))

1989-05-01

473

Infrared study of Si surfaces and bonded Si wafers  

NASA Astrophysics Data System (ADS)

Attenuated total reflection (ATR) spectra of hydrophobic and hydrophilic Si wafers, Si wafers with thermally grown 0268-1242/14/1/009/img2 layers and bonded Si wafers were investigated. It was found that the surface of the as-prepared hydrophobic wafer is terminated by hydrogen and water molecules while the IR spectra of the hydrophilic wafer demonstrate only the presence of water molecules at the surface. ATR spectra of Si wafers covered by a thermally grown 0268-1242/14/1/009/img2 layer exhibit a number of the strong absorption bands. The analysis of ATR spectra and the single-transmission spectra allows these modes to be assigned to combinational phonon bands in 0268-1242/14/1/009/img2. The use of a double-bonded Si structure allows the influence of the outer surfaces to be excluded. The wafer bonding leads to the appearance of siloxane and hydroxyl groups at the buried interface whose absorption bands were observed in ATR spectra.

Milekhin, A.; Friedrich, M.; Hiller, K.; Wiemer, M.; Gessner, T.; Zahn, D. R. T.

1999-01-01

474

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.  

PubMed

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. PMID:24700434

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

475

Novel on chip-interconnection structures for giga-scale integration VLSI ICS  

NASA Astrophysics Data System (ADS)

Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

Nelakuditi, Usha R.; Reddy, S. N.

2013-01-01

476

New LEEPL technology  

NASA Astrophysics Data System (ADS)

A new concept of semiconductor lithography is presented. The new technology is tentatively called as New LEEPL since it is an outgrowth of LEEPL which has been developed around 2002. However the new system is completely different from LEEPL. Instead of a single membrane mask used in LEEPL, we use "mask wafer" where mask patterns are made on a wafer by NIL at corresponding positions of chip patterns of chip wafer. The mask patterns on mask wafer have parallel struts structure of 2 division complementary mask (2-DCMPS) Gold (or Si ) dots of thickness of ~50?m are made on the surface of struts and scribing region for equalizing the temperature of mask wafer and chip wafer. Without these contact dots the temperature difference of ~0.5 K will be generated by full power of 1000?A at 2KV. Both mask wafer and chip wafer are cramped together and kept united throughout the processes. The overlay errors between mask patterns and corresponding chip patterns are measured optically. The error map data are fed to 10 e-beam column array to correct the overlay placement errors. Each column does not have main scanning deflector but has tiny deflector only for beam-tilt operation to correct errors. It can deliver 100?A without space charge blur and thus the resolution of L/S pattern of 10nm range can be achieved at resist thickness of 20nm. The e-beam exposure over the mask is performed by the stage motion. Since mask wafer does not have thermal distortion, the thin membrane's distortion alone will affect the image placement accuracy. In order to obtain less than 1nm distortion of the membrane, the size of 2-DCPS must be smaller 0.7mm.

Utsumi, Takao

2014-10-01

477

A phase 3 trial of local chemotherapy with biodegradable carmustine (BCNU) wafers (Gliadel wafers) in patients with primary malignant glioma.  

PubMed Central

A previous placebo-controlled trial has shown that biodegradable 1,3-bis (2-chloroethyl)-1-nitrosourea (BCNU) wafers (Gliadel wafers) prolong survival in patients with recurrent glioblastoma multiforme. A previously completed phase 3 trial, also placebo controlled, in 32 patients with newly diagnosed malignant glioma also demonstrated a survival benefit in those patients treated with BCNU wafers. Because of the small number of patients in that trial, a larger phase 3 trial was performed to confirm these results. Two hundred forty patients were randomized to receive either BCNU or placebo wafers at the time of primary surgical resection; both groups were treated with external beam radiation postoperatively. The two groups were similar for age, sex, Karnofsky performance status (KPS), and tumor histology. Median survival in the intent-to-treat group was 13.9 months for the BCNU wafer-treated group and 11.6 months for the placebo-treated group (log-rank P -value stratified by country = 0.03), with a 29% reduction in the risk of death in the treatment group. When adjusted for factors affecting survival, the treatment effect remained positive with a risk reduction of 28% ( P = 0.03). Time to decline in KPS and in 10/11 neuroperformance measures was statistically significantly prolonged in the BCNU wafer-treated group ( P wafer-treated group vs. 0.8% in the placebo-treated group) and intracranial hypertension (9.1% in the BCNU wafer-treated group vs. 1.7% in the placebo group). This study confirms that local chemotherapy with BCNU wafers is well tolerated and offers a survival benefit to patients with newly diagnosed malignant glioma. PMID:12672279

Westphal, Manfred; Hilt, Dana C.; Bortey, Enoch; Delavault, Patrick; Olivares, Robert; Warnke, Peter C.; Whittle, Ian R.; Jääskeläinen, Juha; Ram, Zvi

2003-01-01

478

Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers  

NASA Astrophysics Data System (ADS)

By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate–source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

Goto, Tetsuya; Kuroda, Rihito; Akagawa, Naoya; Suwa, Tomoyuki; Teramoto, Akinobu; Li, Xiang; Obara, Toshiki; Kimoto, Daiki; Sugawa, Shigetoshi; Ohmi, Tadahiro; Kamata, Yutaka; Kumagai, Yuki; Shibusawa, Katsuhiko

2015-04-01

479

SCALX: A VLSI architecture for concurrent symbolic processing  

SciTech Connect

A VLSI architecture intended for concurrent symbolic processing is presented. The approach starts with developing a hardware model for on-chip knowledge acquisition and works progressively towards the architectural basis. The model concepts, while formally conceived from neural network theory, do not target physiological modeling. Instead, the goal is to help develop autonomous systems that can make intelligent decisions on a real time basis. With this model, the knowledge is first represented by conceptual digraphs that in turn are stored into a reconfigurable perceptron-like network in which each node is a Boolean McCulloch-Pitts neuron. For on-chip knowledge representation, two methods are presented which directly map digraphs onto silicon. For inference, a computational approach is developed by which knowledge deduction and search processes are resorted to matrix and/or vector operations. A few algorithms which are specifically designed to implement the high speed search operations based on index-driven and value-driven systolic arrays are presented. These algorithms are analyzed in terms of time and space requirements. It is also shown that the index-driven systolic processing architecture can effectively solve the sparse matrix computation problem. Based on the computational model and the systolic design methodology, an array processor architecture suitable for VLSI implementation is developed. A hierarchical network simulator, encoded in C under VAX-8650, is also developed. This simulator is comprised of a conceptual digraph interpreter and a functional emulator for an application specific microprocessor, named SCALX 8900.

Shiue, L.C.

1989-01-01

480

Testing interconnected VLSI circuits in the Big Viterbi Decoder  

NASA Technical Reports Server (NTRS)

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.

1991-01-01

481

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays  

NASA Astrophysics Data System (ADS)

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 ?m is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 ?m × 25 ?m that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

2013-09-01

482

Parallel VLSI architecture emulation and the organization of APSA/MPP  

NASA Technical Reports Server (NTRS)

The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.

Odonnell, John T.

1987-01-01

483

Real-time simulation of biologically realistic stochastic neurons in VLSI.  

PubMed

Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale. PMID:20570768

Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie

2010-09-01

484

Infrared spectroscopy as a probe of fundamental processes in microelectronics: silicon wafer cleaning and bonding  

NASA Astrophysics Data System (ADS)

In this paper, we review our recent infrared studies of the fundamental physical and chemical processes occurring at the interface of bonded silicon wafers, as a function of surface preparation and annealing temperature. We present a brief overview of the practical aspects of silicon-wafer bonding and the techniques used to evaluate the interface integrity, which highlight the need for fundamental studies of the microscopic interface phenomena. Importantly, we show that the interface between two silicon wafers approximates an ideal spectroscopic environment, in that there is a 28-fold enhancement in the sensitivity to the normal component of the interface absorption over any other surface optical geometry. Furthermore, the interface region is almost infinitely stable at room temperature, but can exhibit partial pressures ranging from near vacuum to several atmospheres upon annealing. We present results for two distinct types of wafer bonding: hydrophobic (hydrogen-terminated) and hydrophilic (oxide-terminated), since the origin of the initial attraction between the opposing surfaces is quite different in the two cases. Specifically, we show that ideally hydrogen-terminated Si(111) surfaces come within a few Å, under the influence of a Van der Waals attraction, as evidenced by a pronounced perturbation of the isolated Si?H stretch mode. In contrast, the initial attraction between hydrophilic surfaces is via hydrogen bonding, which is mediated by the presence of 2-4 monolayers of water that are trapped at the interface upon room-temperature joining. We demonstrate that vibrational spectroscopy provides unprecedented mechanistic insight into the thermal evolution of the molecular interface, which necessarily has a profound influence on the bonding process. Throughout the paper, emphasis is given to the need for a wide variety of additional (fundamental) studies of the surface phenomena occurring in these novel, technologically important systems.

Weldon, M. K.; Marsico, V. E.; Chabal, Y. J.; Hamann, D. R.; Christman, S. B.; Chaban, E. E.

1996-12-01

485

Residual Stress Analysis in Thin Device Wafer Using Piezoresistive Stress Sensor  

Microsoft Academic Search

In this paper, piezoresistive stress sensors have been used to analyze the residual stress in thin device wafers. For the analysis, device wafers having piezoresistive stress sensors were fabricated. The stress sensors were then calibrated to determine the piezoresistive coefficients. The analysis of residual stress in device wafers was carried out after thinning the device wafers to three different thicknesses

Aditya Kumar; Xiaowu Zhang; Qing Xin Zhang; Ming Chinq Jong; Guanbo Huang; Lee Wen Sheng Vincent; Vaidyanathan Kripesh; Charles Lee; John H. Lau; Dim Lee Kwong; Venky Sundaram; Rao R. Tummula; Georg Meyer-Berg

2011-01-01

486

High productivity multiple DUT CV test for MEMS microphone wafer with automatic correction  

Microsoft Academic Search

Productivity in MEMS wafer process is getting more and more important as mass production on 200 mm wafer is increasing. Multiple DUT parallel CV test is a high productive way for MEMS Microphone wafer test process, however, in case of the one of two electrodes is connected to the wafer substrate with some contact resistance, interference among DUTs has an

S. Inuzuka

2010-01-01

487

RF MEMS Switch with Wafer Level Package Utilizing Frit Glass Bonding  

Microsoft Academic Search

This paper reports experimental results of RF characteristics up to 20 GHz of a RF MEMS switch applied with wafer level packaging. A glass wafer is used as a package substrate on which frit glass is printed as material to seal the MEMS devices. The package wafer is bonded to a device wafer, which consists of actuators and base substrates.

M. Fujii; I. Kimura; T. Satoh; K. Imanaka

2002-01-01

488

Electrochemical method for defect delineation in silicon-on-insulator wafers  

DOEpatents

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

1991-01-01

489

Distribution of polishing times for a wafer with different patterned polishing pads during CMP and CCMP  

Microsoft Academic Search

During chemical-mechanical polishing (CMP), the polishing pad is placed under a wafer and it completely covers the wafer. Compensating CMP (CCMP) decreases the polishing pad wear and enhances end-point detection (EDP). In CCMP, a polishing pad is placed above the wafer and does not completely cover the wafer. Regardless of CMP or CCMP, there are grooved patterns on the polishing

Zone-Ching Lin; Chein-Chung Chen

2010-01-01

490

Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor  

Microsoft Academic Search

In this work, piezoresistive stress sensors have been used to evaluate the stresses in thin device wafer. For the evaluation, device wafers having piezoresistive stress sensors were fabricated. The stress sensors were then calibrated to determine the piezoresistive coefficients. The evaluation of stresses in device wafer was carried out after thinning the device wafers to three different thicknesses ranging from

Aditya Kumar; Xiaowu Zhang; Q. X. Zhang; M. C. Jong; G. B. Huang; L. Vincent; V. Kripesh; C. Lee; J. H. Lau; D. L. Kwong; V. Sundaram; R. R. Tummula; G. Meyer-Berg

2008-01-01

491

Effect of handling stress on resonance ultrasonic vibrations in thin silicon wafers  

Microsoft Academic Search

Resonance Ultrasonic Vibration (RUV) metrology offers a sensitive non-destructive real-time solution to silicon wafer crack detection. The stresses generated in the wafers by the handling device used in the RUV method may have a significant influence on the effectiveness of this method, particularly for thinner wafers. The handling stresses produced by different designs of the vacuum wafer holders and their

Hao Wu; Shreyes N. Melkote; A. Belyaev; I. Tarasov; Deven Cruson; S. Ostapenko

2010-01-01

492

Nanoscale Transistors: Advanced VLSI Devices (Introductory Lecture)  

NSDL National Science Digital Library

Contributed by Mark Lundstrom of Purdue University, this introductory lecture to nanoscale transistors is available both as a Flash video with audio and as presentation slides in PDF form (the links to these are on the right hand side of the page). The lecture introduces the course, which "examines the device physics of advanced transistors and the process, device, circuit, and systems considerations that enter into the development of new integrated circuit technologies." This is a helpful resource for nanotechnology instructors looking to introduce the concept of nanoscale transistors into their classrooms. For more from this course (lectures, assignments, etc.) click the Course Information Website link.

Lundstrom, Mark

493

9nm node wafer defect inspection using visible light  

NASA Astrophysics Data System (ADS)

Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

2014-04-01

494

Multiple internal reflection spectroscopy of bonded silicon wafers  

NASA Astrophysics Data System (ADS)

Interfaces of bonded hydrophilic and hydrophobic wafer pairs are studied by multiple internal reflection spectroscopy after annealing at 1100 °C. Si H x and SiO H stretching modes are still present in bonded hydrophilic wafers. Interfaces of bonded hydrophobic wafers, prepared by joining HF-etched surfaces without de-ionized water rinsing, are characterized by the dominance of hydrides (SiH, SiH2, SiH3). Their concentration is about 100 times higher than for bonded hydrophilic wafers. Comparison with the ATR-spectra of HF-treated surfaces show