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Sample records for vlsi technology wafers

  1. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

  2. High speed synchronizer card utilizing VLSI technology

    NASA Technical Reports Server (NTRS)

    Speciale, Nicholas; Wunderlich, Kristin

    1988-01-01

    A generic synchronizer card capable of providing standard NASA communication block telemetry frame synchronization and quality control was fabricated using VLSI technology. Four VLSI chip sets are utilized to shrink all the required functions into a single synchronizer card. The application of VLSI technology to telemetry systems resulted in an increase in performance and a decrease in cost and size.

  3. Full custom VLSI - A technology for high performance computing

    NASA Technical Reports Server (NTRS)

    Maki, Gary K.; Whitaker, Sterling R.

    1990-01-01

    Full custom VLSI is presented as a viable technology for addressing the need for the computing capabilities required for the real-time health monitoring of spacecraft systems. This technology presents solutions that cannot be realized with stored program computers or semicustom VLSI; also, it is not dependent on current IC processes. It is argued that, while design time is longer, full custom VLSI produces the fastest and densest VLSI solution and that high density normally also yields low manufacturing costs.

  4. Various Applications Of An Automated Wafer Inspection System In VLSI Manufacturing

    NASA Astrophysics Data System (ADS)

    Matsuda, Kimihiro; Takashima, Isamu; Aoki, Yasuo; Araki, Junichi

    1988-01-01

    Although the VLSI products produced in our manufacturing lines are mostly designed with 1 micron geometries, we expect the majority of products will shift to sub-micron design very soon. This article discusses results of our experiments to releaf human operators from the already difficult visual inspection tasks with a fully automated equipment. We have two groups of visual inspection tasks necessary on the VLSI manufacturing floor. One is Engineering Analysis and the other is in-line monitor, or Product Wafer Auditing. The former, Engineering Analysis, demands a variety of different measurements and inspections, such as line width, contact area, multilayer alignment precision and defect density. On the otherhand, Product Wafer Auditing, will need only one or two such functions per mo-nitoring point in the process, but will use the function more extensively, continuously, and repeatedly. In the manufacturing environment, where the ever pressing demand to increase yield is para-mount, it is crucial to reduce defect finding and analysing time. For that purpose, we need higher speed and accuracy for production wafer inspection than can be obtained with human inspectors. In this context, our experience on the KLA-2020, fully automated wafer inspection equipment has proven to be truely beneficial in the area of the following five different cases of evaluation of the KLA-2020, conducted in our plant. Case: 1. Visual inspection of the VLSI production wafer after aluminum dry-etching was studied in comparison with human operators. The result is that not only was the KLA-2020 much more thorough in detecting defects but also was much faster than any of the operators, by far. Case: 2. We applied the KLA-2020 to identify the cause of die, lost at probe test. We traced the killer defect, which was originated from the reticle. KLA-2020 is effective in reticle qualification. Case: 3. We found that the line-width instruments based upon laser scatterology cannot properly measure most of the dense 1 micron geometry of our VLSI devices. However, the KLA-2020 has provided excellent data of such Case: 4. During the course of process development, where the objective was to improve the LW uniformity within a production wafer, we found the efficiency and accuracy of the KLA-2020 were so good that the objective was met successfully in a very short time. In addition, the yield was improved remarkably. Case: 5. There have been no practical and simple methods to measure a small area in a pro-duction VLSI wafer. We will show the experimental results of measuring the area of contact holes in dropouts using the KLA-2020.

  5. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  6. Modeling of passive components in VLSI technologies

    NASA Astrophysics Data System (ADS)

    Sieiro, Javier; Lopez-Villegas, Jose M.; Cabanillas, Jose

    2005-06-01

    On-chip passives, such as inductors, transformers, are key components in the design of RF building blocks when using VLSI technologies. Most of the time of the design cycle is used in the simulation of passives, trying to obtain the maximum performance. Recently, work on modelling of passives has been directed to pursuit fast computation algorithms due to the need to handle several passives in a complete RF circuit. However, small attention has been paid in the optimization of passives. The work presented tries to fill this gap. The algorithm is based on three steps: the split of the magnetic and electric modelling problem based in a PEEC description; a model order reduction, based on plausible arguments; and the use of analytical formulae to keep scalability. Fast computation is achieved thanks to both the separation of the magnetic and electric problem, and the model order reduction. By keeping an analytical formulation, the optimization of the layout for minimum losses is driven by a physical algorithm, instead of a mathematical one. The tool has been checked with experimental data from inductors fabricated in different VLSI technologies, showing its possibilities in the design of RF building blocks.

  7. MEMS Wafer-level Packaging Technology Using LTCC Wafer

    NASA Astrophysics Data System (ADS)

    Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

    This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

  8. Potential impact of VLSI technologies on guided missile design

    NASA Astrophysics Data System (ADS)

    Maurer, H. A.; Kongelbeck, K. S.

    1985-08-01

    Some aspects of the anticipated impact of emerging VLSI technologies on tactical missiles, present and future generations are discussed. VLSI evolution represents a unique example of a very dynamic and pervasive trend in commercial and military applications. It is our opinion, however, that the characteristics of this trend are quite different in tactical missiles, not only compared to commercial electronics but even to strategic or space missiles. Considering the particular objectives and constraints as they seem common to most tactical guided missiles and smart munitions, the VLSI technologies should be almost tailored to this application. However, there are some perequisites to be considered to make the introduction of VLSIs successful. Here are some examples: careful planning to be in step with the maturity of the VLSI technology, sensible selection of targets for insertion or new designs and - quite importantly - consideration of program stability in terms of volume, rates, and changes. From a technical viewpoint alone, the current trend to light and small, 4- to 8-inch-diameter configuration whether ground or air-launched encourages an early insertion of VLSIs. Electronic packaging with unusual form factors, e.g., having a central hole for warhead effectiveness, high density and low weight, and low power dissipation, poses conflicting requirements to the missile designer. With very few exceptions, such as in magnetics or battery chemistry, the electronics sections cannot benefit from other technological breakthroughs. It is the evolution of monolithic large scale integration of circuits on Silicon and to a lesser degree on Gallium Arsenide which bears the main load to meeting these criteria of processing density at minimum power dissipation, and of providing an ever-increasing functional throughput. Those VLSI embodiments which appear to be most likely to influence missile electronics are defined. They may be divided into four categories, with some ranking indicated regarding their maturity and avaliability, as well as nonrecurring cost weight: (1) Memories (RAM and ROM); (2) Catalog special devices (ADC, DAC, (CP); (3) Semicustom (CGAs); and (4) Full custom.

  9. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    ERIC Educational Resources Information Center

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  10. GaAs VLSI technology and circuit elements for DSP

    NASA Astrophysics Data System (ADS)

    Mikkelson, James M.

    1990-10-01

    Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

  11. Deep sub-micron stud-via technology for superconductor VLSI circuits

    NASA Astrophysics Data System (ADS)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-05-01

    A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.

  12. Deep sub-micron stud-via technology of superconductor VLSI circuits

    NASA Astrophysics Data System (ADS)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-02-01

    A fabrication process has been developed for fully planarized Nb-based superconducting interlayer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of etched contact holes in the interlayer dielectric it employs etched and planarized Nb pillars (studs) as connectors between adjacent wiring layers. Detailed results are presented for one version of the process that utilizes Nb/Al/Nb trilayers for each wiring layer instead of single Nb wiring layers. Nb studs are etched in the top layer of the trilayer to provide vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A μm-2 and approaches the depairing current density of Nb films.

  13. A VLSI implementation of DCT using pass transistor technology

    NASA Technical Reports Server (NTRS)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  14. Dry Cleaning Technology of Silicon Wafer with a Line Beam for Semiconductor Fabrication by KrF Excimer Laser

    NASA Astrophysics Data System (ADS)

    Kim, Dae-Jin; Kim, Yong-Kee; Ryu, Je-Kil; Kim, Hyun-Jung

    2002-07-01

    The contaminants on a bare wafer or a patterned wafer can seriously impact the yield of manufacturing devices in semiconductor fabrication. In very large scale integrated circuit (VLSI) technology, as the device density increases, particularly for flat panel displays, the importance of cleaning also increases. The removal of particles and the Photoresist (PR) layer on a silicon wafer was investigated by a line beam of a KrF excimer laser in a cleanroom condition. This paper reports the effects of a high-energy laser beam onto the electrical, structural and morphological properties of the wafer and introduces a practical line beam laser cleaning method for particle removal and PR stripping. The removal of particles and the PR layer on a silicon wafer was performed using a KrF excimer laser in the cleanroom condition. The results of surface morphology were observed using a scanning electron microscope (SEM) and atomic force microscopy (AFM). The crystallization of the silicon wafer was observed by X-ray diffraction (XRD) studies. The electrical properties of the silicon wafer before and after laser irradiation were characterized by Hall measurements. The compositions of the PR covered wafers were determined by energy dispersive X-ray diffraction (EDX). The carrier concentration and resistivity of the bare silicon wafer were 1.4× 1015 cm-3 and 17.7 Ω{\\cdot}cm, respectively, before laser irradiation. The carrier concentration of the silicon wafers after laser irradiation was in the range of 1.1× 1015-1.6× 1015 cm-3, and the resistivity was in the range of 17.0-18.2 Ω{\\cdot}cm. The carrier concentration and resistivity of the bare silicon wafers were not changed even after high-energy laser irradiation of up to 600 mJ/cm2. After 6-pulse laser irradiation, the PR layer of 0.82 μm thickness was stripped perfectly with an energy density of 300 mJ/cm2 without the aid of any chemical or solvent. The ablation rates were 0.06 μm/pulse for 100 mJ/cm2, 0.10 μm/pulse for 200 mJ/cm2 and 0.13 μm/pulse for 300 mJ/cm2. Dry laser cleaning technology shows that particles and organic compounds, like PR, on the bare silicon wafer can be effectively removed without any damage to the silicon substrate.

  15. National solar technology roadmap: Wafer-silicon PV

    SciTech Connect

    Sopori, Bhushan

    2007-06-01

    This report applies to all bulk-silicon-based PV technologies, including those based on Czochralski, multicrystalline, float-zone wafers, and melt-grown crystals that are 100 μm or thicker, such as ribbons, sheet, or spheral silicon.

  16. Product assurance technology for custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

    1985-01-01

    The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

  17. Advanced FTIR technology for the chemical characterization of product wafers

    NASA Astrophysics Data System (ADS)

    Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

    2001-01-01

    Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

  18. VLSI neuroprocessors

    NASA Technical Reports Server (NTRS)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional techniques and enables multiple assignments, (many to many), not achievable with standard statistical approaches. Tactical movement planning (finding the best path from A to B) is accomplished with a digital two-dimensional concurrent processor array. By exploiting the natural parallel decomposition of the problem in silicon, a four order of magnitude speed-up over optimized software approaches has been demonstrated.

  19. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  20. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  1. Designing defect spins for wafer-scale quantum technologies

    SciTech Connect

    Koehl, William F.; Seo, Hosung; Galli, Giulia; Awschalom, David D.

    2015-11-27

    The past decade has seen remarkable progress in the development of the nitrogen-vacancy (NV) defect center in diamond, which is one of the leading candidates for quantum information technologies. The success of the NV center as a solid-state qubit has stimulated an active search for similar defect spins in other technologically important and mature semiconductors, such as silicon carbide. If successfully combined with the advanced microfabrication techniques available to such materials, coherent quantum control of defect spins could potentially lead to semiconductor-based, wafer-scale quantum technologies that make use of exotic quantum mechanical phenomena like entanglement. In this article, we describe the robust spin property of the NV center and the current status of NV center research for quantum information technologies. We then outline first-principles computational modeling techniques based on density functional theory to efficiently search for potential spin defects in nondiamond hosts suitable for quantum information applications. The combination of computational modeling and experimentation has proven invaluable in this area, and we describe the successful interplay between theory and experiment achieved with the divacancy spin qubit in silicon carbide.

  2. New dynamic FET logic and serial memory circuits for VLSI GaAs technology

    NASA Technical Reports Server (NTRS)

    Eldin, A. G.

    1991-01-01

    The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

  3. Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

    2015-02-01

    The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

  4. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  5. Fast integral rigorous modeling applied to wafer topography effect prediction on 2x nm bulk technologies

    NASA Astrophysics Data System (ADS)

    Michel, J.-C.; Le Denmat, J.-C.; Tishchenko, A.; Jourlin, Y.

    2014-03-01

    Reflection by wafer topography and underlying layers during optical lithography can cause unwanted overexposure in the resist [1]. In most cases, the use of bottom anti reflective coating limits this effect. However, this solution is not always suitable because of process complexity, cost and cycle time penalty, as for ionic implantation lithography process in 28nm bulk technology. As a consequence, computational lithography solutions are currently under development to simulate and correct wafer topographical effects [2], [3]. For ionic implantation source drain (SD) photolithography step, wafer topography influences resulting in implant pattern variation are various: active silicon areas, Poly patterns, Shallow Trench Isolation (STI) and topographical transitions between these areas. In 28nm bulk SD process step, the large number of wafer stack variations involved in implant pattern modulation implies a complex modeling of optical proximity effects. Furthermore, those topography effects are expected to increase with wafer stack complexity through technology node downscaling evolution. In this context, rigorous simulation can bring significant value for wafer topography modeling evolution in R and D process development environment. Unfortunately, classical rigorous simulation engines are rapidly run time and memory limited with pattern complexity for multiple under layer wafer topography simulation. A presentation of a fast rigorous Maxwell's equation solving algorithm integrated into a photolithography proximity effects simulation flow is detailed in this paper. Accuracy, run time and memory consumption of this fast rigorous modeling engine is presented through the simulation of wafer topography effects during ionic implantation SD lithography step in 28nm bulk technology. Also, run time and memory consumption comparison is shown between presented fast rigorous modeling and classical rigorous RCWA method through simulation of design of interest. Finally, integration opportunity of such fast rigorous modeling method into OPC flow is discussed in this paper.

  6. High transmittance silicon terahertz polarizer using wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Yu, Ting-Yang; Tsai, Hsin-Cheng; Wang, Shiang-Yu; Luo, Chih-Wei; Chen, Kuan-Neng

    2015-08-01

    Due to the difficulties faced in fabricating robust Terahertz (THz) optical components with low Fresnel reflection loss, the need to increase the efficiency of THz system with reduced cost is still considered as one of the most essential tasks. In this report, a new low cost THz polarizer with robust structure is proposed and demonstrated. This new THz wire grid polarizer was based on an anti-reflection (AR) layer fabricated with low temperature metal bonding and deep reactive ion etching (DRIE). After patterning Cu wire gratings and the corresponding In/Sn solder ring on the individual silicon wafers, the inner gratings were sealed by wafer-level Cu to In/Sn guard ring bonding, providing the protection against humidity oxidation and corrosion. With the low eutectic melting point of In/Sn solder, wafers could be bonded face to face below 150°C. Two anti-reflection layers on both outward surfaces were fabricated by DRIE. With the mixing of empty holes and silicon, the effective refractive index was designed to be the square root of the silicon refractive index. The central frequency of the anti-reflection layers was designed between 0.5THz to 2THz with an approximate bandwidth of 0.5THz. The samples were measured with a commercial free-standing wire grid polarizer by a THz time domain spectroscopy (THz-TDS) from 0.2THz to 2.2THz. The power transmittance is close to 100% at central frequency. Extinction ratio of the polarizer is between 20dB to 40dB depending on the frequency. The advantages of this new polarizer include high transmittance, robust structure and low cost with no precision optical alignment required.

  7. 3D micro-optical lens scanner made by multi-wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Bargiel, S.; Gorecki, C.; Barański, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frömel, J.

    2013-03-01

    We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

  8. VLSI array processor

    NASA Astrophysics Data System (ADS)

    Greenwood, E.

    1982-07-01

    The Arithmetic Processor Unit (APU) data base design check was completed. Minor design rule violations and design improvements were accomplished. The APU mask set has been fabricated and checked. Initial checking of all mask layers revealed a design rule problem in one layer. That layer was corrected, refabricated and checked out. The mask set has been delivered to the chip fabrication area. The fabrication process has been initiated. All work on the Array Processor Demonstration System (APDS) has been suspended at CHI until the additionally requested funding was received. That funding has been authorized and CHI will begin work on the APDS in July. The following activities are planned in the following quarter: 1) Complete fabrication of the first lot of VLSI APU devices. 2) Complete integration and check-out of the APDS simulator. 3) Complete integration and check-out of the APU breadboard. 4) Verify the VLSI APU wafer tests with the APU breadboard. 5) Complete check-out of the APDS using the APU breadboard.

  9. SEMICONDUCTOR TECHNOLOGY: Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

    NASA Astrophysics Data System (ADS)

    Yuhan, Cao; Le, Luo

    2009-08-01

    A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E.

  10. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  11. An overview of Pb-free, flip-chip wafer-bumping technologies

    NASA Astrophysics Data System (ADS)

    Kang, Sung K.; Gruber, Peter; Shih, Da-Yuan

    2008-06-01

    To meet the European Union Restriction of Hazardous Substances requirements and the continuing demand for lower costs, finer pitch, and high-reliability flip-chip packaging structures, considerable work is going on in the electronic industry to develop leadfree solutions for flip-chip technology. In this paper, various solder-bumping technologies developed for flip-chip applications are reviewed with an emphasis on a new wafer-bumping technology called C4NP (Controlled-Collapse-Chip-Connect New Process). Several inherent advantages of C4NP technology are discussed over other technologies. This paper will also discuss the recent development and implementation of lead-free C4 interconnections for 300 mm wafers demonstrated at IBM. In addition, some metallurgical considerations associated with C4NP technology are discussed.

  12. Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

    NASA Astrophysics Data System (ADS)

    Kitada, Hideki; Maeda, Nobuhide; Fujimoto, Koji; Mizushima, Yoriko; Nakata, Yoshihiro; Nakamura, Tomoji; Ohba, Takayuki

    2011-05-01

    Diffusion behavior of Cu in Cu through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vapor deposition (LT-PECVD) has been evaluated. Silicon oxynitride (SiON) barrier films were formed by LT-PECVD at 150 °C. Cu diffusion rate was found to increase with decreasing film density. The critical density and thickness for prevention of Cu diffusion into Si substrate have been estimated. In case of a film with density >60% of the bulk value and/or thickness >100 nm, no change of electrical resistance for stacked wafers containing TSVs was observed after 1000 cycles of thermal stress. According to above results, SiON film formed at 150 °C can be used for the TSV process without any degradation of electrical characteristics and reliability, enabling a reduction in total process temperature in the wafer-on-wafer technology.

  13. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    NASA Astrophysics Data System (ADS)

    Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

    2013-05-01

    A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

  14. Diamond MEMS: wafer scale processing, devices, and technology insertion

    NASA Astrophysics Data System (ADS)

    Carlisle, J. A.

    2009-05-01

    Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD® (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

  15. Wafer topography modeling for ionic implantation mask correction dedicated to 2x nm FDSOI technologies

    NASA Astrophysics Data System (ADS)

    Michel, Jean-Christophe; Le Denmat, Jean-Christophe; Sungauer, Elodie; Robert, Frédéric; Yesilada, Emek; Armeanu, Ana-Maria; Entradas, Jorge; Sturtevant, John L.; Do, Thuy; Granik, Yuri

    2013-04-01

    Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist [1]. This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technology node and below at the ionic implantation process. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but increases process complexity and adds cost and cycle time penalty. As a consequence, an OPC based solution is today under evaluation to cope with stack effects involved in ionic implantation patterning [2] [3]. For the source drain (SD) ionic implantation process step on 28nm Fully Depleted Silicon-on-Insulator (FDSOI) technology, active silicon areas, poly silicon patterns, Shallow Trench Isolation (STI), Silicon-on-Insulator (SOI) areas and the transitions between these different regions result in significant SD implant pattern critical dimension variations. The large number of stack variations involved in these effects implies a complex modeling to simulate pattern degradations. This paper deals with the characterization of stack effects on 28nm node using SOI substrates. The large number of measurements allows to highlight all individual and combined stack effects. A new modeling flow has been developed in order to generate wafer stack aware OPC model. The accuracy and the prediction of the model is presented in this paper.

  16. A novel technology for fabricating customizable VLSI artificial neural network chips

    SciTech Connect

    Fu, C.Y.; Law, B.; Chapline, G.; Swenson, D.

    1992-02-05

    This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems. These neural networks are programmed using precision laser cutting and deposition. The fast turnaround of laser-based customization allows us to explore different neural network architectures and to rapidly program the synaptic weights. Our customizable chip allows us to expand an artificial network laterally and vertically. This flexibility permits us to build very large neural network systems.

  17. VLSI and parallel computation

    SciTech Connect

    Suaya, R.; Birtwistle, G.

    1988-01-01

    This volume presents a cross-section of the most current research in parallel computation encompassing theoretical models, VLSI design, routing, and machine implementations. The book comprises a series of invited tutorial chapters on advanced topics in VLSI and concurrency. The chapters have been revised and updated to form a coherent volume exploring issues of fundamental importance in parallel computation, as well as significant research results in the contributor's specialties. Topics include load sharing models, PRAM models of computation, neural networks, Cochlea models, the design of algorithms for explicit concurrency, and VLSI CAD.

  18. VLSI Universal Noiseless Coder

    NASA Technical Reports Server (NTRS)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  19. VLSI-Chip Tester

    NASA Technical Reports Server (NTRS)

    Deutsch, Leslie J.; Olson, Erlend M.

    1987-01-01

    Compact test set integrated in computer-aided design system. Test set performs functional tests on very-large-scale integrated (VLSI) circuits. Makes tests from points within VLSI chip as well as at input and output pins. Used for quality control and design; in latter capacity, checks internal logic functions on chip and feed results directly to computer-aided design system for correction. Also simulates operation of chip design before chip is made. VLSI Tester contains three power supplies, control logic, and standard multibus circuit board in aluminum chassis. Chassis fits under platform of microprobe station. Multibus board links tester to interactive terminals and to host computer.

  20. Sensitivity analysis of add-on price estimate for select silicon wafering technologies

    NASA Technical Reports Server (NTRS)

    Mokashi, A. R.

    1982-01-01

    The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

  1. Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes

    NASA Astrophysics Data System (ADS)

    Peterson, Joel; Rusk, Gary; Veeraraghavan, Sathish; Huang, Kevin; Koffas, Telly; Kimani, Peter; Sinha, Jaydeep

    2015-03-01

    The semiconductor industry continues to push the limits of immersion lithography through multiple patterning techniques for printing features with critical dimension 20 nm and below. As a result overlay has become one of the critical lithography control parameters impacting device performance and has a stringent budget for yielding at smaller half pitch nodes. Overlay has several sources of errors related to scanner, lens, mask, and wafer. Lithographers have developed both linear and higher order field and wafer models to successfully compensate for the static fingerprints from different sources of error. After the static modeled portion of the fingerprint is removed, the remaining overlay error can be characterized as unstable modeled error or un-modeled error, commonly called uncorrectable residual error. This paper explores the fundamental relationship of overlay to wafer geometry through mechanisms of process-induced contributions to the wafer overlay, categorized as plastic and elastic wafer deformation. Correlation of overlay to local features such as slip lines is proven experimentally. The paper describes methodologies and geometry-induced overlay metrics for the application of wafer geometry to perform overlay feedback and feed forward applications. Feedback applications allow for process development and controlling semiconductor processes through in-line monitoring of wafers. Feed forward applications could include geometrybased corrections to the scanner for compensating non-static wafer geometry related overlay errors, and grouping wafers based on higher-order geometry.

  2. Novel wafer track-based resolution enhancement technology for 248-nm DUV lithography

    NASA Astrophysics Data System (ADS)

    Zhong, Tom X.; Gurer, Emir; Lewellen, John W.; Lee, Ed C.

    2000-06-01

    248 nm DUV lithography has become a mainstream production technology for sub-0.25 micrometer feature sizes due to its superior process technology and improved cost of ownership (COO). As the semiconductor industry moves to sub-0.18 micron critical layer feature sizes, there is an enormous economic incentive to extend 248 nm technology towards smaller geometries. Traditionally, resolution enhancement technologies such as various illumination types (off-axis, annular ring and quadrapole) and phase shifted masks are based on the optimization of the diffracted aerial image wave front and they concentrate on the exposure tools and masks. In this paper we report a new novel resolution enhancement technology based on the wafer track. We have demonstrated that this new technology, along with the scanner-based resolution enhancement techniques, can substantially improve resolution capabilities and process latitudes of the 248 nm technology. Consequently, semiconductor manufacturers will be able to extend 248 nm DUV technology for smaller feature sizes than was possible before. Our new resolution enhancement technology allowed us to increase the contrast of an acetal-based DUV resist from about 5 to 13 by carefully controlling the environment during the post exposure bake process. This technology provided a continuous contrast knob that could be controlled and set based on the application. Increased photoresist contrast in turn made it possible to pattern 0.15 micrometer isolated lines and 0.2 micrometer dense lines using a 248 nm mercury lamp-based scanner with projection optics designed for 0.35 micrometer features. A DOF of 0.8 micrometer for 0.25 micrometer dense lines was achieved using this PEB- based resolution enhancement technology whereas conventional technology could not resolve 0.25 micrometer dense lines at all. Detailed lithographic characterization identified a 30% improvement in process latitude. Furthermore, cross sectional SEM studies revealed high quality CD profiles and measured high side wall angles with resolution-enhanced patterns. The cross sectional SEM studies also suggested that the new resolution enhancement technology also reduces the iso-dense bias. Detailed Prolith simulations support these experimental results. Mechanistic understanding along with the experimental data and simulation results will be presented in this paper.

  3. Innovative design methodology for implementing heterogeneous multiprocessor architectures in VLSI

    SciTech Connect

    Tientien Li

    1983-01-01

    Considering the design cost of today's VLSI systems, advanced VLSI technology may not be cost-effective for implementing complex computer systems. In the paper, an innovative design approach which can drastically reduce the cost of implementing heterogeneous multiprocessor architectures in VLSI is presented. The author introduces high-level architectural design tools for assisting the design of multiprocessor systems with distributed memory modules and communication networks, and presents a logic/firmware synthesis scheme for automatically implementing multitasking structures and system service functions for multiprocessor architectures. Furthermore, the importance of the firmware synthesis aspect of VLSI system design is emphasized. Most logic of complex VLSI systems can be implemented very easily in firmware using the design approach introduced here. 10 references.

  4. Plate-like structure health monitoring based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers

    NASA Astrophysics Data System (ADS)

    Liu, Zenghua; Zhao, Jichen; He, Cunfu; Wu, Bin

    2008-11-01

    Piezoelectric ceramic wafers are applied for the excitation and detection of ultrasonic guided waves to determine the health state of plate-like structures. Two PZT wafers, whose diameter is 11mm and thickness is 0.4mm respectively, are bonded permanently on the surface of a 1mm thick aluminum plate. One of these wafers is actuated by sinusoidal tone burst at various frequencies ranging from 100kHz to 500kHz, the other one is used as a receiver for acquiring ultrasonic guided wave signals. According to the amplitudes and shapes of these received signals, guided wave modes and their proper frequency range by using these wafers are determined. For the improvement of the signal-to-noise ratio, the Daubechies wavelet of order 40 is used for signal denoising as the mother wavelet. Furthermore, the detection of an artificial cylindrical through-hole defect is achieved by using S0 at 300kHz. Experimental results show that it is feasible and effective to detect defects in plate-like structures based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers.

  5. Technology for integrated circuit micropackages for neural interfaces, based on gold-silicon wafer bonding

    NASA Astrophysics Data System (ADS)

    Saeidi, N.; Schuettler, M.; Demosthenous, A.; Donaldson, N.

    2013-07-01

    Progress in the development of active neural interface devices requires a very compact method for protecting integrated circuits (ICs). In this paper, a method of forming micropackages is described in detail. The active areas of the chips are sealed in gas-filled cavities of the cap wafer in a wafer-bonding process using Au-Si eutectic. We describe the simple additions to the design of the IC, the post-processing of the active wafer and the required features of the cap wafer. The bonds, which were made at pressure and temperature levels within the range of the tolerance of complementary metal-oxide-semiconductor ICs, are strong enough to meet MIL STD 883G, Method 2019.8 (shear force test). We show results that suggest a method for wafer-scale gross leak testing using FTIR. This micropackaging method requires no special fabrication process and is based on using IC compatible or conventional fabrication steps.

  6. 300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

    NASA Astrophysics Data System (ADS)

    Widiez, Julie; Sollier, Sébastien; Baron, Thierry; Martin, Mickaël; Gaudin, Gweltaz; Mazen, Frédéric; Madeira, Florence; Favier, Sylvie; Salaun, Amélie; Alcotte, Reynald; Beche, Elodie; Grampeix, Helen; Veytizou, Christelle; Moulet, Jean-Sébastien

    2016-04-01

    This paper reports the first demonstration of 300 mm In0.53Ga0.47As-on-insulator (InGaAs-OI) substrates. The use of direct wafer bonding and the Smart Cut™ technology lead to the transfer of high quality InGaAs layer on large Si wafer size (300 mm) at low effective cost, taking into account the reclaim of the III-V on Si donor substrate. The optimization of the three key building blocks of this technology is detailed. (1) The III-V epitaxial growth on 300 mm Si wafers has been optimized to decrease the defect density. (2) For the first time, hydrogen-induced thermal splitting is made inside the indium phosphide (InP) epitaxial layer and a wide implantation condition ranges is observed on the contrary to bulk InP. (3) Finally a specific direct wafer bonding with alumina oxide has been chosen to avoid outgas diffusion at the alumina oxide/III-V compound interface.

  7. SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

    NASA Astrophysics Data System (ADS)

    Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

    2010-05-01

    Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

  8. Supercomputing with VLSI

    SciTech Connect

    Manohar, S.

    1989-01-01

    Supercoprocessors (SCPs), highly parallel VLSI architectures tuned to solving a specific problem class, are shown to provide a means of cost-effective supercomputing. A methodology for building SCPs for different computation-intensive problems is described: two pragmatic constraints namely problem-size-independence and limited-bandwidth constraint are imposed on special-purposes architectures; a simple but powerful model of computation is used to derive general upper bounds on the speedup obtainable using such architectures. It is shown that bounds established by other authors for matrix multiplication and sorting, using problem-specific approaches, can be derived very simply using this model. Poisson Engine-I (PE-I), a prototype SCP, is a system for solving the Laplace equation using the finite difference approximation. PE-I uses a novel approach: asynchronous iteration methods are implemented using a fixed-size, synchronous array of simple processing elements. Architectural and algorithmic extensions to PE-I are briefly considered: the solution of a wider class of PDEs and the use of more sophisticated algorithms like the multigrid method are some of the issues addressed. The SCP methodology is applied to the problems of matrix-multiplication and sorting. For sorting, an SCP with superlinear speedup is outlined. For the matrix problem, the architecture and implementation details of SMP are described in detail. SMP, realized with about fifty chips using current technology, is capable of through-puts greater than 150 Mflops, and is also unique in being optimal with respect to the lowerbound derived using the SCP model. The use of a collection of sup SCPs is advanced as a cost-effective supercomputing alternative.

  9. Yield-driven multi-project reticle design and wafer dicing

    NASA Astrophysics Data System (ADS)

    Kahng, Andrew B.; Mandoiu, Ion; Xu, Xu; Zelikovsky, Alex

    2005-11-01

    The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has lead to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.

  10. Integrating III-V compound semiconductors with silicon using wafer bonding

    NASA Astrophysics Data System (ADS)

    Zhou, Yucai

    2000-12-01

    From Main Street to Wall Street, everyone has felt the effects caused by the Internet revolution. The Internet has created a new economy in the New Information Age and has brought significant changes in both business and personal life. This revolution has placed strong demands for higher bandwidth and higher computing speed due to high data traffic on today's information highway. In order to alleviate this problem, growing interconnection bottlenecks in digital designs have to be solved. The most feasible and practical way is to replace the conventional electrical interconnect with an optical interconnect. Since silicon does not have the optical properties necessary to accommodate these optical interconnect requirements, III-V based devices, most of which are GaAs-based or InP-based, must be intimately interconnected with the Si circuit at chip level. This monolithic integration technology enables the development of both intrachip and interchip optical connectors to take advantage of the enormous bandwidth provided by both high-performance very-large-scale integrated (VLSI) circuits and allied fiber and free-space optical technologies. However, lattice mismatch and thermal expansion mismatches between III-V materials and Si create enormous challenges for developing a feasible technology to tackle this problem. Among all the available approaches today, wafer bonding distinguishes itself as the most promising technology for integration due to its ability to overcome the constraints of both lattice constant mismatch and thermal expansion coefficient differences and even strain due to the crystal orientation. We present our development of wafer bonding technology for integrating III-V with Si in my dissertation. First, the pick-and-place multiple-wafer bonding technology was introduced. Then we systematically studied the wafer bonding of GaAs and InP with Si. Both high temperature wafer fusion and low/room temperature (LT/RT) wafer bonding have been investigated for different applications. We also systematically studied the electrical properties of bonding interfaces for high temperature wafer fusion of GaAs/Si and InP/Si. Room temperature and low temperature wafer bonding technology has been invented primarily for bonding GaAs with Si due to larger thermal expansion coefficient mismatches. Finally, we showed the feasibility and practicality of our wafer bonding technologies by fabricating high performance devices. A high performance InP-based avalanche photodetector on Si was fabricated utilizing the high temperature wafer fusion of InP and Si. And a 0.85 μm GaAs-based vertical cavity surface emitting lasers (VCSELs) were fabricated by utilizing the low temperature wafer bonding of GaAs and Si.

  11. Parallel VLSI Architecture

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

    1985-01-01

    Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

  12. Wafer bonding technology for new generation vacuum MEMS: challenges and promises

    NASA Astrophysics Data System (ADS)

    Dragoi, V.; Pabo, E.

    2015-05-01

    Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding process and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding processes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glass frit bonding and metal-based bonding. The outgassing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgassing. Additionally the selected bonding process must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each process for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for process characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addressed will be introduced with examples.

  13. The 1992 4th NASA SERC Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  14. VLSI implementation of neural networks.

    PubMed

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach. PMID:11011791

  15. NASA Space Engineering Research Center for VLSI System Design

    NASA Technical Reports Server (NTRS)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  16. VLSI in biomedical imaging systems.

    PubMed

    Sridhar, R; Jones, T

    1995-01-01

    This paper explores the nature of Very Large Scale Integration (VLSI) systems as applied to the area of medical imaging systems. A general discussion of imaging systems and the techniques employed therein will be presented. With this, the merits of VLSI solutions to the medical imaging problem are presented. Consideration is also given to programmable processors, such as off the shelf DSP processors, semi-custom, and full custom VLSI devices. Through the use of VLSI devices, many image processing algorithms can be integrated into a hardware solution. This has the advantage of increased computational capacity over solutions that would normally employ software techniques. PMID:7736415

  17. Dictionary machine (for VLSI)

    SciTech Connect

    Ottmann, T.A.; Rosenberg, A.L.; Stockmeyer, L.J.

    1982-09-01

    The authors present the design of a dictionary machine that is suitable for VLSI implementation, and discusses how to realize this implementation efficiently. The machine supports the operations of search, insert, delete, and extractment on an arbitrary ordered set. Each of these operations takes time o(logn), where n is the number of entries present when the operation is performed. Moreover, arbitrary sequences of these instructions can be pipelined through the machine at a constant rate (i.e. independent of n and the capacity of the machine). The time o(logn) is an improvement over previous VLSI designs of dictionary machines which require time o(log n) per operation, where n is the maximum number of keys that can be stored. 10 references.

  18. Verification of VLSI designs

    NASA Technical Reports Server (NTRS)

    Windley, P. J.

    1991-01-01

    In this paper we explore the specification and verification of VLSI designs. The paper focuses on abstract specification and verification of functionality using mathematical logic as opposed to low-level boolean equivalence verification such as that done using BDD's and Model Checking. Specification and verification, sometimes called formal methods, is one tool for increasing computer dependability in the face of an exponentially increasing testing effort.

  19. Very Large Scale Integration (VLSI).

    ERIC Educational Resources Information Center

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  20. UW VLSI chip tester

    NASA Astrophysics Data System (ADS)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  1. Interferometry for wafer dimensional metrology

    NASA Astrophysics Data System (ADS)

    Freischlad, Klaus; Tang, Shouhong; Grenfell, Jim

    2007-09-01

    Wafer shape and thickness variation are important parameters in the IC manufacturing process. The thickness variation, also called flatness, enters the depth-of-focus budget of microlithography, and also affects film thickness uniformity in the CMP processing. The shape mainly affects wafer handling, and may also require some depth-of-focus if the wafer shape is not perfectly flattened by chucking. In the progression of technology nodes to smaller feature sizes, and hence smaller depth-of-focus of the lithography tool, the requirement for the PV-flatness over stepper exposure sites is becoming progressively tighter, and has reached 45nm for the next technology node of 45nm half pitch. Consequently, in order to be gauge-capable the flatness metrology tool needs to provide a measurement precision of the order of 1nm. Future technology nodes will require wafers with even better flatness and metrology tools with better measurement precision. For the last several years the common capacitive tools for wafer dimensional metrology have been replaced by interferometric tools with higher sensitivity and resolution. In the interferometric tools the front and back surface figure of the wafer is measured simultaneously while the wafer is held vertically in its intrinsic shape. The thickness variation and shape are then calculated from these single-sided maps. The wafer shape, and hence each wafer surface figure, can be tens of microns, necessitating a huge dynamic range of the interferometer when considering the 1nm measurement precision. Furthermore, wafers are very flexible, and hence very prone to vibrations as well as bending. This presentation addresses these special requirements of interferometric wafer measurements, and discusses the system configuration and measurement performance of WaferSight TM, KLA-Tencor's interferometric dimensional metrology tool for 300mm wafers for current and future technology nodes.

  2. VLSI physical design analyzer: A profiling and data mining tool

    NASA Astrophysics Data System (ADS)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  3. Large array VLSI filter

    NASA Technical Reports Server (NTRS)

    Nathan, R.

    1983-01-01

    A 35 by 35 element pipelined convolutional kernel is being fabricated using VLSI chips, each containing a 5 by 1 segment of the kernel. Three levels of printed circuitry are used: the first level is used for the VLSI chips, the second level connects seven chips together on one platform, and the third level connects seven platforms with associated delay lines, all fitting on one board. Therefore, on each board there are seven rows of the kernel containing 245 multipliers and adders, and five such boards complete the kernel array. Each multiplier accepts an 8 bit picture element which is multiplied by a 16 bit weight. A truncated 22 bit product is added to a previously stored product sum and the results are shifted to the following multiplier as the next picture element is read in. The multiplier uses a modified Booth algorithm to reduce the number of shift add operations nearly in half. The filter box is presently configured as an ancillary box to a VAX 11/780, but can be connected to essentially any CPU. The I/O bandwidth is easily compatible with most CPU devices.

  4. Mixed voltage VLSI design

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  5. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Luo, Xianshu; Cao, Yulian; Song, Junfeng; Hu, Xiaonan; Cheng, Yungbing; Li, Chengming; Liu, Chongyang; Liow, Tsung-Yang; Yu, Mingbin; Wang, Hong; Wang, Qijie; Lo, Patrick Guo-Qiang

    2015-04-01

    Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS) fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W) bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP) laser, lateral-coupled distributed feedback (LC-DFB) laser with side wall grating, and mode-locked laser (MLL). From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC).

  6. Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies

    NASA Astrophysics Data System (ADS)

    Tanake, Katsuaki

    We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of InP/Si substrates for bulk InP in the fabrication of such a four-junction solar cell could significantly reduce the substrate cost since the current prices for commercial InP substrates are much higher than those for Si substrates by two orders of magnitude. Direct heteroepitaxial growth of InP thin films on Si substrates has not produced the low dislocation-density high quality layers required for active InGaAs/InP in optoelectronic devices due to the ˜8% lattice mismatch between InP and Si. We successfully fabricated InP/Si substrates by He implantation of InP prior to bonding to a thermally oxidized Si substrate and annealing to exfoliate an InP thin film. The thickness of the exfoliated InP films was only 900 nm, which means hundreds of the InP/Si substrates could be prepared from a single InP wafer in principle. The photovoltaic current-voltage characteristics of the In0.53Ga0.47As cells fabricated on the wafer-bonded InP/Si substrates were comparable to those synthesized on commercially available epi-ready InP substrates, and had a ˜20% higher short-circuit current which we attribute to the high reflectivity of the InP/SiO2/Si bonding interface. This work provides an initial demonstration of wafer-bonded InP/Si substrates as an alternative to bulk InP substrates for solar cell applications. We have observed photocurrent enhancements up to 260% at 900 nm for a GaAs cell with a dense array of Ag nanoparticles with 150 nm diameter and 20 nm height deposited through porous alumina membranes by thermal evaporation on top of the cell, relative to reference GaAs cells with no metal nanoparticle array. This dramatic photocurrent enhancement is attributed to the effect of metal nanoparticles to scatter the incident light into photovoltaic layers with a wide range of angles to increase the optical path length in the absorber layer. GaAs solar cells with metallic structures at the bottom of the photovoltaic active layers, not only at the top, using semiconductor-metal direct bonding have been fabricated. These metallic back structures could incouple the incident light into surface plasmon mode propagating at the semiconductor/metal interface to increase the optical path, as well as simply act as back reflector, and we have observed significantly increased short-circuit current relative to reference cells without these metal components. (Abstract shortened by UMI.)

  7. VLSI Architectures for Computing DFT's

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  8. VLSI MIL-STD-1750A processor development

    NASA Astrophysics Data System (ADS)

    Gaertner, M.; Winter, T.; Brauchmann, W.

    An American company is developing a VLSI program to design, fabricate, characterize, and deliver a family of General Purpose Computers optimized to execute MIL-STD-1750A Notice 1. The CPU architecture is fashioned in an extensible functional module configuration with a performance range from 0.9 MIPS to 1.5 MIPS (DAIS-type Mix). The three configurations which have emerged include baseline CPU, baseline CPU plus floating point accelerator, and 32-bit data path CPU (ISA Invisible). It is pointed out that these machines will employ multisource VLSI low power CMOS technology and will be fully qualified to meet military environmental specifications.

  9. Enabling more capability within smaller pixels: advanced wafer-level process technologies for integration of focal plane arrays with readout electronics

    NASA Astrophysics Data System (ADS)

    Temple, Dorota S.; Vick, Erik P.; Lueck, Matthew R.; Malta, Dean; Skokan, Mark R.; Masterjohn, Christopher M.; Muzilla, Mark S.

    2014-05-01

    Over the past decade, the development of infrared focal plane arrays (FPAs) has seen two trends: decreasing of the pixel size and increasing of signal-processing capability at the device level. Enabling more capability within smaller pixels can be achieved through the use of advanced wafer-level processes for the integration of FPAs with silicon (Si) readout integrated circuits (ROICs). In this paper, we review the development of these wafer-level integration technologies, highlighting approaches in which the infrared sensor is integrated with three-dimensional ROIC stacks composed of multiple layers of Si circuitry interconnected using metal-filled through-silicon vias.

  10. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  11. Synaptic dynamics in analog VLSI.

    PubMed

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties. PMID:17716003

  12. Algorithms for VLSI artwork

    SciTech Connect

    Wu, San-Yuan.

    1989-01-01

    The specific problems that the author studies in this thesis are painting and drawing of rectilinear polygons, covering rectilinear polygons by rectangles, and partitioning rectilinear polygons into rectangles. These problems have application to VLSI design, computer graphics, etc. He considers three display devices, one-dimensional and two dimensional pen plotters, and video screens, for the problem of painting and covering. An 0 (n log n) time algorithm to obtain an optimal drawing strategy on one-dimensional plotters is obtained (n is the number of the vertices of the polygons). Fore the case of a two-dimensional plotter, the strategy to optimally draw the contour of a rectilinear polygon can be found in linear time. However, for a collection of rectilinear polygons, this problem is NP-hard. For screen type displays, he formulates three strategies to paint a rectilinear polygon using a rectangle as a primitive. For two of these, he shows the problem NP-hard. Performance bounds for these strategies are also obtained. Three approximation algorithms to cover a rectilinear polygon that is neither horizontally nor vertically convex by rectangles are developed. All three guarantee covers that have at most twice as many rectangles as in an optimal cover. The complexities of those algorithms are O (n log n), O(n{sup 2}), and O(n{sup 4}), respectively. Finally, he develops two algorithms to obtain the optimal partition of simple rectilinear polygons. Their time complexities are {approximately} O (kn) and O (n log k), where k is the number of the inversions of the polygon. Both are significantly faster than the existing best algorithm on polygons whose size is large relative to k.

  13. 3D integration approaches for MEMS and CMOS sensors based on a Cu through-silicon-via technology and wafer level bonding

    NASA Astrophysics Data System (ADS)

    Hofmann, L.; Dempwolf, S.; Reuter, D.; Ecke, R.; Gottfried, K.; Schulz, S. E.; Knechtel, R.; Geßner, T.

    2015-05-01

    Technologies for the 3D integration are described within this paper with respect to devices that have to retain a specific minimum wafer thickness for handling purposes (CMOS) and integrity of mechanical elements (MEMS). This implies Through-Silicon Vias (TSVs) with large dimensions and high aspect ratios (HAR). Moreover, as a main objective, the aspired TSV technology had to be universal and scalable with the designated utilization in a MEMS/CMOS foundry. Two TSV approaches are investigated and discussed, in which the TSVs were fabricated either before or after wafer thinning. One distinctive feature is an incomplete TSV Cu-filling, which avoids long processing and complex process control, while minimizing the thermomechanical stress between Cu and Si and related adverse effects in the device. However, the incomplete filling also includes various challenges regarding process integration. A method based on pattern plating is described, in which TSVs are metalized at the same time as the redistribution layer and which eliminates the need for additional planarization and patterning steps. For MEMS, the realization of a protective hermetically sealed capping is crucial, which is addressed in this paper by glass frit wafer level bonding and is discussed for hermetic sealing of MEMS inertial sensors. The TSV based 3D integration technologies are demonstrated on CMOS like test vehicle and on a MEMS device fabricated in Air Gap Insulated Microstructure (AIM) technology.

  14. VLSI mixed signal processing system

    NASA Technical Reports Server (NTRS)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  15. On the optimization of VLSI contacts

    NASA Astrophysics Data System (ADS)

    Maddox, R. L.

    1985-03-01

    The contact-resistance characteristic of silicon devices has been a subject of research and development since the early days of silicon integrated-circuit technology. The contact-chain losses suffered by very large scale integration (VLSI), however, have made the minimization of contact resistance a critical parameter due to the large number of contacts per circuit and due to the increase of contact resistance with decreasing contact size. This paper will present a brief review of the theory of contact resistance, the literature, measurement techniques, and of the transmission-line model (TLM) for analyzing contact-resistance data. Contact-resistance data pertaining to shallow high-conductivity contacts for VLSI will be presented as a function of the junction parameters (implant dose, etc.) and of the contact area for BF2 and arsenic implants with aluminum-silicon metallization. Contact-resistance data of a sputtered molybdenum silicide contact barrier for boron and arsenic implants versus contact area will also be presented and compared to the aluminum-silicon control samples with a discussion regarding the uniformity of contacts to silicon.

  16. An efficient interpolation filter VLSI architecture for HEVC standard

    NASA Astrophysics Data System (ADS)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  17. Wafer Manufacturing and Slicing Using Wiresaw

    NASA Astrophysics Data System (ADS)

    Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

    Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer quality are presented. Summary and further reading are also provided.

  18. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  19. The Fifth NASA Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  20. The Fifth NASA Symposium on VLSI Design

    SciTech Connect

    Not Available

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design. Separate abstracts have been prepared for articles from this report.

  1. SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    NASA Astrophysics Data System (ADS)

    Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

    2010-10-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

  2. Research in VLSI systems. Heuristic programming project and VLSI theory project. A fast turn around facility for very large scale integration (VLSI)

    NASA Astrophysics Data System (ADS)

    Hennessy, J.; Matthews, R.; Newkirk, J.; Shott, J.; Ullman, J. D.; Brown, H.

    1983-11-01

    This report summarizes progress in the DARPA funded VLSI Systems Research Projects from May 1983 to November 1983, inclusive. The major areas under investigation have included: analysis and synthesis design aids, applications of VLSI, special purpose chip design, VLSI computer architectures, signal processing algorithms and architectures, reliability studies, hardware specification and verification, VLSI theory, and VLSI fabrication. The major research problems are introduced and progress is discussed; the Appendix contains a list of published research papers from these projects.

  3. SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

    NASA Astrophysics Data System (ADS)

    Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

    2010-02-01

    To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

  4. Fracture of silicon wafers

    NASA Astrophysics Data System (ADS)

    McLaughlin, J. C.; Willoughby, A. F. W.

    1987-11-01

    In spite of the increasing use of silicon in applications where mechanical stresses are deliberately applied to the material, such as in transducers, and the fatal nature of cracking in silicon devices, there is very limited characterisation and understanding of the fracture behaviour of silicon wafers at room temperature. This understanding is of increasing importance with the use of larger diameter wafers in modern technology. This paper examines the fracture strength of a wide range of silicon material both as-grown and after processing. The wafers tested were from crystals grwon by float-zone and Czochralski techniques and the effects of oxidation, ion-implantation and annealing in various environments have been studied. The technique used to measure the fracture stress involved simply supporting the wafer on an aluminium ring concentric to the load axis. The load was gradually increased until the wafer fractured. This method was chosen to avoid edge effects, and has proved to have adequate reproducibility. Typical values of the fracture stress obtained by this method, for different crystals, vary between 2 and 3.5 GPa. In the first part of the study, the role of the surface on the fracture behaviour has been investigated in detail. While the surface perfection of the tensile surface has a major effect on the fracture stress (as shown in previous studies), some of the results were found to be sensitive to the compressive surface as well. In the case where the results are sensitive to the compressive surface finish the fracture stress rose from 3.7 to 8.8 GPa as the surface finish was improved while in the cases where they were not sensitive the fracture stress remained at about 3.5-4.6 GPa. Only in the float-zone material were fracture stresses approaching 8.8 GPa observed. At this level of fracture stress, the behaviour is believed to be sensitive to surface defects less than 0.01 ?m in size. These results can be analyzed in terms of surface controlled defects under conditions where surface defects are dominant and bulk controlled defects where these defects are dominant. In this manner bulk effects can be isolated from surface ones. This gives the opportunity to study the effects of specific defects on the fracture stress and the results in this paper are discussed in terms of the role of surface and internal defects on the fracture stress.

  5. VLSI Processor For Vector Quantization

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  6. The test of VLSI circuits

    NASA Astrophysics Data System (ADS)

    Baviere, Ph.

    Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

  7. Focal-plane VLSI processing for multiresolution edge extraction

    NASA Astrophysics Data System (ADS)

    Tremblay, Marc; Poussart, Denis

    1992-10-01

    The challenge of information extraction in robot vision and automated inspection requires the development of efficient and dedicated hardware systems. A specific requirement relates to the hierarchical description of a scene, which is difficult to implement in real-time on conventional computers. Hardware solutions may exploit parallel computing capabilities in order to provide intelligent sensing of visual information. A promising strategy seeks to exploit VLSI solutions in novel architectures for optical sensing and processing. The Multi- port Array photo-Receptor system (MAR) discussed in this paper combines optical transduction with integrated focal-plane processing. The central element of the MAR system is a full custom VLSI photo-sensor array with hexagonal tessellation which provides parallel analog read-out from groups of pixels over prescribed areas. The overall capability of the sensor is enhanced by the addition of external analog computation which performs real-time spatial convolution at multiple resolutions and uses feedback control for automatic edge tracking. Current VLSI technology allows the fabrication of a CMOS sensor array with dimensions of up to 500 X 500 pixels on a 1.5 cm die using CMOS 1.2 micron technology. VLSI also provides means to integrate analog computing modules and microcontrol capabilities. A set of chips required by the system has been fabricated and a first prototype which integrates an array of 128 X 128 pixels with zero-crossing detection at seven different spatial resolutions runs at a rate of 1 M pixel/sec. Edge data at multiple resolutions are computed in real-time. Parallel edge extraction at 16 different resolutions will be available from a forthcoming unit. The sensor includes arbitrary pixel displacement and non-linear dark current compensation. This type of integrated sensor is a good candidate for advanced applications which require small weight and size.

  8. MOS VLSI reliability and yield trends

    NASA Astrophysics Data System (ADS)

    Woods, Murray H.

    1986-12-01

    Trends in yield and reliability of new technologies for MOS devices both drive and are a consequence of at least six major, highly interactive technology trends - tending toward (1) more complex device structures and materials, (2) reduced device dimensions and feature sizes, (3) larger wafer sizes, (4) factory automation, (5) higher pin count packages and larger die sizes, and (6) increasingly sophisticated CAD tools. Technology decisions now often involve trading off one reliabilty failure mechanism for another. The implications are that the dominant reliability mechanisms may change in the future, and wearout will start to impinge on reliability life.

  9. Multilevel VLSI interconnection—an optimum approach?

    NASA Astrophysics Data System (ADS)

    Srikrishnan, K. V.; Totta, P. A.

    1986-04-01

    The wirability of circuit elements is a key ingredient in the success of the very large scale integration technology. Multilevel wiring eliminates the need to use extensive areas of the silicon surface simply for wiring channels. Increasing the number of wiring planes significantly improves the possibility of achieving the goals of the VLSI, i.e. the interconnection of the maximum number of devices in the smallest possible area. Extensive modeling has shown the need to optimize the wiring pitch, number of wiring planes and electrical properties of the materials used (e.g-low resistivity for conductors and low dielectric constant for insulators). The choice of the interconnection technology is also influenced by other factors. Some of these areas: cost and reliability objectives; in house expertise and practice; new process/equipment availability and a desire to maintain process commonality. The selected strategy is sometimes an optimum approach for an individual situation which is not universally optimum. In IBM, for example, two different but successful multilevel wiring technologies are being used extensively. The first is used for bipolar circuits; it is a three-level metallization design, with sputtered SiO2 as the insulator. The second, for FET devices, has two-levels of metal and polyimide as the insulator. Both technologies use area array input/output terminal connections and lift off line definition. The process/material set of each is reviewed to emphasize the mechanics of reaching an ``optimum'' solution for the individual applications.

  10. Quality procedures for VLSI/VHSIC (Very Large Scale Integrated and Very High Speed Integrated Circuits) type devices

    NASA Astrophysics Data System (ADS)

    Cohen, S.

    1985-11-01

    Procedures for microcircuit screening and qualification to ensure the reliability and uniformity of VLSI/VHSIC devices were prepared. The use of Process Control Monitors (PCM) and Reliability Evaluation Modules (REM) were incorporated in the procedures. In addition, recommended guidelines for the evaluation of Computer-Aided-Manufacturing (CAM) facilities were generated in this study. A proposed replacement was provided for existing Method 5007 to MIL-STD-883, Wafer Acceptance Procedure which incorporates reliability screening, process quality evaluation, and electrical parameter testing of each wafer in a lot.

  11. Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

    NASA Technical Reports Server (NTRS)

    Offord, Bruce W.

    1992-01-01

    In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

  12. Reconfigurable VLSI architecture for a database processor

    SciTech Connect

    Oflazer, K.

    1983-01-01

    This work brings together the processing potential offered by regularly structured VLSI processing units and the architecture of a database processor-the relational associative processor (RAP). The main motivations are to integrate a RAP cell processor on a few VLSI chips and improve performance by employing procedures exploiting these VLSI chips and the system level reconfigurability of processing resources. The resulting VLSI database processor consists of parallel processing cells that can be reconfigured into a large processor to execute the hard operations of projection and semijoin efficiently. It is shown that such a configuration can provide 2 to 3 orders of magnitude of performance improvement over previous implementations of the RAP system in the execution of such operations. 27 refs.

  13. A memetic algorithm for VLSI floorplanning.

    PubMed

    Tang, Maolin; Yao, Xin

    2007-02-01

    Floorplanning is an important problem in very large scale integrated-circuit (VLSI) design automation as it determines the performance, size, yield, and reliability of VLSI chips. From the computational point of view, VLSI floorplanning is an NP-hard problem. In this paper, a memetic algorithm (MA) for a nonslicing and hard-module VLSI floorplanning problem is presented. This MA is a hybrid genetic algorithm that uses an effective genetic search method to explore the search space and an efficient local search method to exploit information in the search region. The exploration and exploitation are balanced by a novel bias search strategy. The MA has been implemented and tested on popular benchmark problems. Experimental results show that the MA can quickly produce optimal or nearly optimal solutions for all the tested benchmark problems. PMID:17278559

  14. A second generation 50 Mbps VLSI level zero processing system prototype

    NASA Technical Reports Server (NTRS)

    Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

    1994-01-01

    Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

  15. A coherent VLSI design environment

    NASA Astrophysics Data System (ADS)

    Penfield, P., Jr.; Glasser, L. A.; Knight, T. F., Jr.; Leiserson, C. E.; Rivest, R. L.

    1985-09-01

    The research discussed here is described in more detail in several published and unpublished reports cited. The CAD frame Schema has progressed to the point where it is useful for ample chip designs. The interface to CIF is complete, and work has begun on importing layout libraries. An interface to EDIF is being installed. Simulators can now be connected, and thought is going into organization of VLSI libraries. A plan for the distribution of Schema is now being worked out. Previous results on waveform bounding have been generalized to large classes of problems described in canonical control-theory form. Work has begun on models for interconnect taking account of line inductance. This domain is less general than RLC networks, and there is hope that some of the previously derived bounds still apply. During this period a novel device, the UV write-enabled PROM, was reported at a conference. Work continues on developing useful circuits employing this device.

  16. Constant fan-in digital neural networks are VLSI-optimal

    SciTech Connect

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  17. Development of a 2 micrometer silicon-gate-CMOS-technology for microcomputer oriented VLSI circuits with a supply voltage range between 1.5 and 5 V

    NASA Astrophysics Data System (ADS)

    Fischer, G.; Kiss, T.; Kummerow, K.; Link, M.; Scharzmann, U.

    1984-10-01

    The processes necessary for a 2 micron CMOS-technology were developed, including projection lithography, the oxidation process, the fabrication of thin oxides, and dry etching techniques for patterning silicon nitride, polysilicon, silicon oxide, and aluminum. With the aid of process simulations and experimental results, a process flow chart was established. A test chip with a large number of single structures and circuit blocks was designed in 2 micron tubes. Different runs of this test chip are produced. The success of the developed technology is demonstrated on different logic circuit blocks.

  18. The 1991 3rd NASA Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Maki, Gary K.

    1991-01-01

    Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

  19. The Microelectronics Center: A new force in cooperative VLSI signal processing research

    NASA Astrophysics Data System (ADS)

    Fair, R. B.

    1983-11-01

    The needs of the microelectronics industry in applying VLSI to modern signal processing are stated: (1) to innovate new designs at a rapid rate: (2) to maintain an edge on the numbers of new designs and innovations; (3) to reduces the amount of parallel research and development efforts required to make effective technology and design decisions and to achieve successful market dominance.

  20. The VLSI design of error-trellis syndrome decoding for convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

    1985-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  1. The VLSI design of an error-trellis syndrome decoder for certain convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

    1986-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  2. A VLSI design concept for parallel iterative algorithms

    NASA Astrophysics Data System (ADS)

    Sun, C. C.; Götze, J.

    2009-05-01

    Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  3. Interconnection capacitance models for VLSI circuits

    NASA Astrophysics Data System (ADS)

    Wong, Shyh-Chyi; Liu, Patrick S.; Ru, Jien-Wen; Lin, Shi-Tron

    1998-06-01

    A new set of capacitance models is developed for delay estimation of VLSI interconnections. The set of models is derived for five representative wiring structures, with their combinations covering arbitrary VLSI layouts. A semi-empirical approach is adopted to deal with complicated geometry nature in VLSI and to allow for closed-form capacitance formulas to be developed to provide direct observation of capacitance variation vs process parameters as well as computational efficiency for circuit simulation. The formulas are given explicitly in terms of wire width, wire thickness, dielectric thickness and inter-wire spacing. The models show good agreement with numerical solutions from RAPHAEL and measurement data of fabricated capacitance test structures. The models are further applied and validated on a ring oscillator. It is shown that the frequency of the ring oscillator obtained from HSPICE simulation with our models agrees well with the bench measurement.

  4. On Programming Languages for VLSI Array Processors

    NASA Astrophysics Data System (ADS)

    Kung, S. Y.

    1986-07-01

    A formal algorithmic notation and programming language will be critical in developing VLSI systems. Due to the difficulty of keeping, track of several simultaneously occuring events, parallel programming is significantly more complicated than sequential programming. Therefore, it is desirable to consider new notations or languages which fit better to the array processors, instead of always sticking to conventional languages. The advent of algorithm-oriented VLSI. architectures also necessitate new programming language theory to precisely describe concurrency imbedded in computational algorithms. For example, it is of great interest and importance to develop a complete set of programming techniques and software packages for wavefront/systolic type arrays. Some guidelines for algorithmic notations for such VLSI arrays will be addressed in this paper. We shall also discuss in great details several illustrative programming examples based on a wavefront language and Occam language.

  5. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  6. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  7. Extremely long life and low-cost 193nm excimer laser chamber technology for 450mm wafer multipatterning lithography

    NASA Astrophysics Data System (ADS)

    Tsushima, Hiroaki; Katsuumi, Hisakazu; Ikeda, Hiroyuki; Asayama, Takeshi; Kumazaki, Takahito; Kurosu, Akihiko; Ohta, Takeshi; Kakizaki, Kouji; Matsunaga, Takashi; Mizoguchi, Hakaru

    2014-04-01

    193nm ArF excimer lasers are widely used as light sources for the lithography process of semiconductor production. 193nm ArF exicmer lasers are expected to continue to be the main solution in photolithography, since advanced lithography technologies such as multiple patterning and Self-Aligned Double Patterning (SADP) are being developed. In order to apply these technologies to high-volume semiconductor manufacturing, the key is to reduce the total operating cost. To reduce the total operating cost, life extension of consumable part and reduction of power consumption are an important factor. The chamber life time and power consumption are a main factor to decide the total operating cost. Therefore, we have developed the new technology for extension of the chamber life time and low electricity consumption. In this paper, we will report the new technology to extend the life time of the laser chamber and to reduce the electricity consumption.

  8. Associative Pattern Recognition In Analog VLSI Circuits

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  9. MIL-STD-1553 VLSI components

    NASA Astrophysics Data System (ADS)

    Friedman, Steven N.

    The performance, physical and electrical characteristics of novel VLSI components which will support all MIL-STD-1553 terminals are described. A transceiver, protocol, and computer interface set of chips supports remote terminal unit, bus controller, and bus monitor modes of operation. A discussion of these VLSI components is given, and their special features are explored. These features include size and packaging options, radiation hardness, power, and reliability considerations. The special capabilities of these devices are highlighted, along with programming options that facilitate a broad array of applications.

  10. Thermal conduction phenomena in VLSI circuits and systems

    NASA Astrophysics Data System (ADS)

    Im, Sungjun

    Continuous scaling of very large scale integrated (VLSI) circuits poses severe thermal problems, which have major implications for performance and reliability in high-performance planar (2-D) integrated circuits (ICs) and emerging circuit architectures, such as vertically integrated (3-D) ICs. This dissertation aims to understand the thermal conduction phenomena from the fundamental material level to the system level and provides guidelines to the robust thermal design of VLSI circuits and systems. Accurate analytical thermal models for estimating the spatial temperature distributions along interconnects and vias have been presented, and verified by three-dimensional electrothermal simulations based on finite-element methods (FEM). This model, incorporating both interconnect and via self-heating effects, showed that localized hot spots and spatial temperature distributions in the interconnect structures are strongly affected by various geometric and material parameters. In addition, a rigorous scaling analysis of multilevel interconnect temperatures has been performed using 3-D electrothermal FEM simulations, combined with accurate calculations of resistivity of copper, thermal conductivity of low-k interlayer dielectrics (ILD), and various scaling factors. Comprehensive scaling analysis has showed that the interconnect temperature rise is expected to increase significantly in sub-50 nm technologies. As a potential cooling solution, conduction cooling offered by novel multilayered substrates has been investigated by measuring the thermal conductivity of a novel multilayer substrate using a harmonic Joule heating technique. Finally, the thermal analysis of both 2-D and 3-D ICs has been presented, providing chip-level thermal management strategies in high-performance VLSI circuits and systems.

  11. Analog VLSI-based modeling of the primate oculomotor system.

    PubMed

    Horiuchi, T K; Koch, C

    1999-01-01

    One way to understand a neurobiological system is by building a simulacrum that replicates its behavior in real time using similar constraints. Analog very large-scale integrated (VLSI) electronic circuit technology provides such an enabling technology. We here describe a neuromorphic system that is part of a long-term effort to understand the primate oculomotor system. It requires both fast sensory processing and fast motor control to interact with the world. A one-dimensional hardware model of the primate eye has been built that simulates the physical dynamics of the biological system. It is driven by two different analog VLSI chips, one mimicking cortical visual processing for target selection and tracking and another modeling brain stem circuits that drive the eye muscles. Our oculomotor plant demonstrates both smooth pursuit movements, driven by a retinal velocity error signal, and saccadic eye movements, controlled by retinal position error, and can reproduce several behavioral, stimulation, lesion, and adaptation experiments performed on primates. PMID:9950732

  12. A single-supply, monolithic, MIL-STD-1553 transceiver implemented in BiCMOS wafer fabrication technology

    NASA Astrophysics Data System (ADS)

    Albrecht, Thomas L.; Molinari, Lou

    An integrated circuit has been designed for use as a single supply, MIL-STD-1553 transceiver using BiCMOS technology. Use of the BiCMOS fabrication process has advantages over both Bipolar and CMOS technologies. These advantages include: reduced standby current drain, increased flexibility in mating the transceiver to various remote terminals, increased control over output amplitude and rise/fall times, easier methods for adjusting filter response and residual voltage, and reduced chip size (over a CMOS transceiver). Development of this monolithic transceiver opens the door to future advances in remote terminal design. By combining the current driving capacity of Bipolar with the digital design capability of CMOS, the next probable step in the progression of MIL-STD-1553 technology would be a fully monolithic remote terminal. This device would combine a transceiver with the encoder/decoder and protocol logic on a single semiconductor device.

  13. Bridging the gaps between mask inspection/review systems and actual wafer printability using computational metrology and inspection (CMI) technologies

    NASA Astrophysics Data System (ADS)

    Pang, Linyong; Tolani, Vikram; Satake, Masaki; Hu, Peter; Peng, Danping; Liu, Tingyang; Chen, Dongxue; Gleason, Bob; Vacca, Anthony

    2012-11-01

    Computational techniques have become increasingly important to improve resolution of optical lithography. Advanced computational lithography technologies, such as inverse lithography (ILT) and source mask optimization (SMO), are needed to print the most challenging layers, such as contact and metal, at the 20nm node and beyond. In order to deploy SMO and ILT into production, improvements and upgrades of mask manufacturing technology are required. These include writing, inspection, defect review, and repair. For example, mask plane inspection detects defect at highest resolution, but does not correlate accurately with scanner images. Aerial plane mask inspection and AIMSTM produce images close to those of a scanner, but except fot the latest AIMS-32TM, it does not have the flexibility needed to capture all the characteristics of free-form illumination. Advanced Computational Inspection and Metrology provides solutions to many of these issues.

  14. Reliability of small geometry VLSI devices for microelectronics

    NASA Astrophysics Data System (ADS)

    White, Marvin H.

    1992-02-01

    This proposal is a continuation of a project which began in August 1986. The goal of the project, in a broad sense, is to perform exploratory research into the physics of carriers in silicon inversion layers with a focus on the issues which affect the reliability of small geometry VLSI devices. This project permits us to study the physical electronics of silicon surfaces and the overlying insulators. In the proposed project we stress the application of this research to the area of Wafer Scale Integration where reliability and fault tolerance are key issues for the SDI program. The extensive signal processing and data storage required to implement high-resolution, sensor-based systems demands that consideration be given to the area of system and component reliability. At the component level the issues revolve around the reliability of the scaled MOS Transistor with nanometric feature sizes. One important area is the susceptibility of the gate insulator to (1) hot electron trapping, (2) premature dielectric breakdown, and (3) space radiation environment considerations which can limit the MTTF of the SDIO mission. A second issue at the component level is the SDI need for low-power, high-density, nonvolatile data storage with nondestructive readout (NDRO), radiation tolerance and immunity to single event upsets (SEU's).

  15. VLSI Unit for Two-Dimensional Convolutions

    NASA Technical Reports Server (NTRS)

    Liu, K. Y.

    1983-01-01

    Universal logic structure allows same VLSI chip to be used for variety of computational functions required for two dimensional convolutions. Fast polynomial transform technique is extended into tree computational structure composed of two units: fast polynomial transform (FPT) unit and Chinese remainder theorem (CRT) computational unit.

  16. SSI/MSI/LSI/VLSI/ULSI.

    ERIC Educational Resources Information Center

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  17. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  18. Forming electrical interconnections through semiconductor wafers

    NASA Astrophysics Data System (ADS)

    Anthony, T. R.

    1981-08-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  19. Scriber for silicon wafers

    NASA Technical Reports Server (NTRS)

    Yamakawa, K. A.; Fortier, E. P. (Inventor)

    1981-01-01

    A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

  20. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  1. Reciprocating Saw for Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.; Collins, E. R., Jr.

    1985-01-01

    Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

  2. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    NASA Astrophysics Data System (ADS)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  3. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  4. AWV: high-throughput cross-array cross-wafer variation mapping

    NASA Astrophysics Data System (ADS)

    Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

    2008-03-01

    Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

  5. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  6. Architecture for VLSI design of Reed-Solomon encoders

    NASA Technical Reports Server (NTRS)

    Liu, K. Y.

    1981-01-01

    The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

  7. Innovative metrology for wafer edge defectivity in immersion lithography

    NASA Astrophysics Data System (ADS)

    Pollentier, I.; Iwamoto, F.; Kocsis, M.; Somanchi, A.; Burkeen, F.; Vedula, S.

    2007-03-01

    In semiconductor manufacturing, the control of defects at the edge of the wafer is a key factor to keep the number of yielding die on a wafer as high as possible. Using dry lithography, this control is typically done by an edge bead removal (EBR) process, which is understood well. Immersion lithography however changes this situation significantly. During this exposure, the wafer edge is locally in contact with water from the immersion hood, and particles can then be transported back and forth from the wafer edge area to the scanner wafer stage. Materiel in the EBR region can also potentially be damaged by the dynamic force of the immersion hood movement. In this paper, we have investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to the inspection of the flat top part of the wafer edge, due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. This study utilized KLA-Tencor's VisEdge, a new automated edge inspection system, that provides full wafer edge imaging (top, side, bottom) using laser-based optics and multi-sensor detection, and where defects of interest can be classified with Automated Defect Classification (ADC) software. Using the VisEdge technology, the impact from the immersion lithography towards wafer edge defectivity is investigated. The work revealed several key challenges to keep the wafer edge related defectivity under control : choice of resist, optimization of EBR recipes, scanner pollution and related memory effects, wafer handling, device processing, etc... Contributing to the understanding of the mechanisms of wafer edge related immersion defects and to the optimization the die yield level, this technology is believed to be important when the immersion processes are introduced in semiconductor manufacturing.

  8. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  9. A Parallel VLSI Direction Finding Algorithm

    NASA Astrophysics Data System (ADS)

    van der Veen, Alle-Jan; Deprettere, Ed F.

    1988-02-01

    In this paper, we present a parallel VLSI architecture that is matched to a class of direction (frequency, pole) finding algorithms of type ESPRIT. The problem is modeled in such a way that it allows an easy to partition full parallel VLSI implementation, using unitary transformations only. The hard problem, the generalized Schur decomposition of a matrix pencil, is tackled using a modified Stewart Jacobi approach that improves convergence and simplifies parameter computations. The proposed architecture is a fixed size, 2-layer Jacobi iteration array that is matched to all sub-problems of the main problem: 2 QR-factorizations, 2 SVD's and a single GSD-problem. The arithmetic used is (pipelined) Cordic.

  10. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    NASA Technical Reports Server (NTRS)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  11. Systolic VLSI Reed-Solomon Decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.

    1986-01-01

    Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

  12. Leak detection utilizing analog binaural (VLSI) techniques

    NASA Technical Reports Server (NTRS)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  13. Replacing design rules in the VLSI design cycle

    NASA Astrophysics Data System (ADS)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  14. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    PubMed

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data. PMID:23852175

  15. Cascaded VLSI Chips Help Neural Network To Learn

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  16. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  17. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  18. Image Compression on a VLSI Neural-Based Vector Quantizer.

    ERIC Educational Resources Information Center

    Chen, Oscal T.-C.; And Others

    1992-01-01

    Describes a modified frequency-sensitive self-organization (FSO) algorithm for image data compression and the associated VLSI architecture. Topics discussed include vector quantization; VLSI neural processor architecture; detailed circuit implementation; and a neural network vector quantization prototype chip. Examples of images using the FSO…

  19. A VLSI structure for the deadlock avoidance problem

    SciTech Connect

    Bertolazzi, P.; Bongiovanni, G.

    1985-11-01

    In this paper the authors present two VLSI structures implementing the banker's algorithm for the deadlock avoidance problem, and we derive the area x (time)/sup 2/ lower bound for such an algorithm. The first structure is based on the VLSI mesh of trees. The second structure is a modification of the first one, and it approaches more closely the theoretical lower bound.

  20. Image Compression on a VLSI Neural-Based Vector Quantizer.

    ERIC Educational Resources Information Center

    Chen, Oscal T.-C.; And Others

    1992-01-01

    Describes a modified frequency-sensitive self-organization (FSO) algorithm for image data compression and the associated VLSI architecture. Topics discussed include vector quantization; VLSI neural processor architecture; detailed circuit implementation; and a neural network vector quantization prototype chip. Examples of images using the FSO

  1. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J.; Piwczyk, Bernhard P.

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  2. Surface activation enhanced low temperature silicon wafer bonding

    NASA Astrophysics Data System (ADS)

    Gan, Qing

    Direct wafer bonding technology has received great attention since 1985. It enables to realize the novel combinations of different materials for expanded functionality and provides a versatile device technology for transferring device layers to another wafer for further processing or device integration onto one wafer. Silicon direct wafer bonding has found a wide range of applications including Silicon-on-Insulator (SOI) wafers, micromechanical devices, and sensors and actuators. One of the challenges facing this technology is to achieve strong bonding at low temperatures that can survive post-wafer bonding processing. This dissertation presents the results of developing new wafer bonding processes for achieving high bonding energy at low temperatures. For thermal oxide covered silicon wafer bonding, dilute HF solution has been used to etch the wafers prior to room temperature bonding. The bonding energy has been significantly enhanced which reached silicon fracture energy after annealed at 100°C for 45 hours. For native oxide covered silicon wafers, the pre-treatment in dilute HNO3 and dilute HF mixtures has been found to be able to enhance the bonding energy at low temperatures. This is attributed to the incorporation of fluorine in native oxide during the pre-treatment. Various approaches have also been explored for hydrophobic silicon wafer bonding. Both boron doped surface layers and the amorphous surface layers have demonstrated an ability to significantly enhance the bonding energy at low temperatures, with silicon fracture energy achieved at 300--400°C for hydrophobically bonded pairs. The thermal management of heterojunction bipolar transistor (HBT) circuits fabricated by Symmetric Intrinsic HBT (SIHBT) processing was also studied in this research project using simulation method. Design criteria of selecting the surrogate substrates, interconnection dimension, and dielectric materials for the optimization of thermal management have been obtained.

  3. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  4. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  5. A synergistic solution to the problem of packaging and interconnecting VLSI/VHSIC chips

    NASA Astrophysics Data System (ADS)

    Gioia, J. C.

    1982-10-01

    Solutions are required for the many problems faced by the chip packaging and interconnection systems industry for effectively meeting the demanding application requirements of the rapidly emerging very-large scale integration/very-high speed integrated circuits (VLSI/VHSIC) chips. Present packaging technologies are being stretched beyond their original concepts thus requiring a new approach to the problem solution. The Military Electronics Systems Operations (MESO) has developed a new packaging approach, based on the Direct Bond Copper Process, which addressed these problems providing a completely integrated system. The problem solution starts at the chip level where en masse connections are made to the chip, chip heat is more effectively managed, low-cost chip hermetic seals accomplished, and then continues providing improved means for interconnecting many VLSI/VHSIC chips.

  6. VLSI architectures for geometrical mapping problems in high-definition image processing

    NASA Technical Reports Server (NTRS)

    Kim, K.; Lee, J.

    1991-01-01

    This paper explores a VLSI architecture for geometrical mapping address computation. The geometric transformation is discussed in the context of plane projective geometry, which invokes a set of basic transformations to be implemented for the general image processing. The homogeneous and 2-dimensional cartesian coordinates are employed to represent the transformations, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme for a processor, which utilizes full-pipelining at the macro-level and parallel constant-factor-redundant arithmetic and full-pipelining at the micro-level, is assessed to produce a single VLSI chip for HDTV applications using state-of-art MOS technology.

  7. VLSI architectures for geometrical mapping problems in high-definition image processing

    NASA Astrophysics Data System (ADS)

    Kim, K.; Lee, J.

    This paper explores a VLSI architecture for geometrical mapping address computation. The geometric transformation is discussed in the context of plane projective geometry, which invokes a set of basic transformations to be implemented for the general image processing. The homogeneous and 2-dimensional cartesian coordinates are employed to represent the transformations, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme for a processor, which utilizes full-pipelining at the macro-level and parallel constant-factor-redundant arithmetic and full-pipelining at the micro-level, is assessed to produce a single VLSI chip for HDTV applications using state-of-art MOS technology.

  8. High throughput VLSI architecture for multiresolution integer motion estimation in high definition AVS video encoder

    NASA Astrophysics Data System (ADS)

    Yin, HaiBing; Qi, Honggang; Xu, Hao; Xie, Xiaodong; Gao, Wen

    2010-07-01

    This paper proposes a hardware friendly multi-resolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and utilizing the high correlation in multi-resolution reference pixels, huge throughput and computation due to large search window are alleviated considerably. Sixteen way parallel processing element arrays with configurable multiplying technologies achieve fast search with regular data access and efficient data reuse. Also, the parallel arrays can be efficiently reused at three hierarchical levels for sequential motion vector refinement. The modified algorithm reaches a good balance between implementation complexity and search performance. Also, the logic circuit and on-chip SRAM consumption of the VLSI architecture are moderate.

  9. 30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology

    NASA Technical Reports Server (NTRS)

    Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

    1986-01-01

    An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

  10. An artificial intelligence approach to VLSI routing

    SciTech Connect

    Joobbani, R.

    1985-01-01

    An Artificial Intelligence Approach to VLSI Routing presents a system that performs routing close to what human designers do. As is carefully outlined in the book, the proposed system heavily capitalizes on the knowledge of human expertise in this area. Included in this test is background of some representative techniques for routing, and a summary of their characteristics. A detailed study is also included of the different factors that affect the routing quality and the criteria that can e used to optimize these factors.

  11. VLSI Reed-Solomon Encoder With Interleaver

    NASA Technical Reports Server (NTRS)

    Hsu, In-Shek; Deutsch, L. J.; Truong, Trieu-Kie; Reed, I. S.

    1990-01-01

    Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).

  12. High performance VLSI telemetry data systems

    NASA Technical Reports Server (NTRS)

    Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

    1990-01-01

    NASA-Goddard has over the last five years developed generic ground telemetry data system elements addressing the budget limitations-driven demand for greater modularity, flexibility, and interchangeability. These design solutions, which may be characterized as a 'functional components approach', encompasses both hardware and software components; the former involve telemetry application-specific ICs for data rate requirements of up to 300 Mbps, while the latter extend to embedded local software intelligence. Attention is given to the consequences of the functional components approach for VLSI components.

  13. Unifying parametrized VLSI Jacobi algorithms and architectures

    NASA Astrophysics Data System (ADS)

    Deprettere, Ed F. A.; Moonen, Marc

    1993-11-01

    Implementing Jacobi algorithms in parallel VLSI processor arrays is a non-trivial task, in particular when the algorithms are parametrized with respect to size and the architectures are parametrized with respect to space-time trade-offs. The paper is concerned with an approach to implement several time-adaptive Jacobi-type algorithms on a parallel processor array, using only Cordic arithmetic and asynchronous communications, such that any degree of parallelism, ranging from single-processor up to full-size array implementation, is supported by a `universal' processing unit. This result is attributed to a gracious interplay between algorithmic and architectural engineering.

  14. Optimal VLSI dictionary machines without compress instructions

    SciTech Connect

    Li, H.F.; Probst, D.K. )

    1990-05-01

    The authors present several designs for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The authors' initial design objectives included: single-cycle operability of host-issued modify and query commands (no compress instructions), complete processor utilization (no wasted processors), and optimal 2 log {ital n} response times, where {ital n} is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously.

  15. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  16. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 μm after thinning down to the nominal thickness of 75 μm and 50 μm. The measurement precision is better than 2 um.

  17. Wavelength-encoded OCDMA system using opto-VLSI processors.

    PubMed

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram. PMID:17603568

  18. VLSI Implementations of Neural Networks

    NASA Astrophysics Data System (ADS)

    Hollis, Paul William

    1992-01-01

    The purpose of this research is to explore various methods of implementing neural network architectures in hardware, with emphasis on learning networks and their associated algorithms. The approach taken utilizes hybrid (analog and digital circuitry) architectures which can benefit from the speed of parallel analog hardware, and from the ease of communication and control available with digital hardware. There are several areas of research which are highlighted in this manuscript. Three neuron models are described which have been characterized through simulation. Two of the models utilize traditional CMOS technology, while the third uses a newer BiCMOS technology. Test results are presented for hardware implementations of two of the models. The implications of the nonidealities inherent in these neuron circuits are examined, and methods of minimizing their effects are presented. It is demonstrated that the well-known backpropagation algorithm for training networks can be derived using an alternate neuron model to compensate for some of these nonidealities. The effects of precision constraints in hardware implementations are examined in the context of a hybrid architecture, and minimum precision requirements for effective learning are established for certain kinds of problems. A learning algorithm, designed to perform optimally when implemented in hardware, is introduced and verified with simulation data. This algorithm uses a perturbation method to implement gradient-descent learning, and to allow much simpler hardware than would be required by an implementation of standard backpropagation. A dynamic gain-adaption algorithm is used to maximize the effective resolution of the bounded weights which accompany any physical implementation. The use of the infinity-norm error measure facilitates the measurement of network error with simple hardware. Evidence is presented that network error information with a wide dynamic range can be coarsely encoded for weight updates without significantly affecting the quality of learning. This encoding method allows digital weight update calculations to be performed without using multipliers. Simulations of the full algorithm show that the quality and characteristics of learning are comparable between this algorithm and the standard backpropagation algorithm.

  19. Augmented reality for wafer prober

    NASA Astrophysics Data System (ADS)

    Gilgenkrantz, Pascal

    2011-03-01

    The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

  20. NASA Space Engineering Research Center Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Maki, Gary K.

    1990-01-01

    The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers.

  1. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  2. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers

    NASA Astrophysics Data System (ADS)

    Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

    2009-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

  3. Analog VLSI neural network integrated circuits

    NASA Technical Reports Server (NTRS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  4. VLSI processors for signal detection in SETI

    NASA Astrophysics Data System (ADS)

    Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

    The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artifically created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incoporate many innovative circuits and architectural features.

  5. VLSI processors for signal detection in SETI

    NASA Technical Reports Server (NTRS)

    Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

    1989-01-01

    The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

  6. Analog VLSI system for active drag reduction

    SciTech Connect

    Gupta, B.; Goodman, R.; Jiang, F.; Tai, Y.C.; Tung, S.; Ho, C.M.

    1996-10-01

    In today`s cost-conscious air transportation industry, fuel costs are a substantial economic concern. Drag reduction is an important way to reduce costs. Even a 5% reduction in drag translates into estimated savings of millions of dollars in fuel costs. Drawing inspiration from the structure of shark skin, the authors are building a system to reduce drag along a surface. Our analog VLSI system interfaces with microfabricated, constant-temperature shear stress sensors. It detects regions of high shear stress and outputs a control signal to activate a microactuator. We are in the process of verifying the actual drag reduction by controlling microactuators in wind tunnel experiments. We are encouraged that an approach similar to one that biology employs provides a very useful contribution to the problem of drag reduction. 9 refs., 21 figs.

  7. A generalized extraction system for VLSI

    NASA Astrophysics Data System (ADS)

    Dukes, Michael A.; Markham, Frank; Degroat, Joanne E.

    1990-10-01

    A Generalized Extraction System for VLSI (GES, pronounced guess) is described. GES, which is written in Prolog, performs logic extraction from transistor netlists, identification of logic errors within and between components, and generation of VHDL. The input to GES consists of a transistor netlist using format from extract in magic. Logic extraction has been performed, on transistor netlists extracted from design layouts in magic, up to the level of 32-bit adders and 32-bit registers. GES reports typical errors in the construction and interconnection of components. An error-report identifies the component and specifies its location within the magic layout, making it easy to locate the offending circuitry. GES also provides a hierarchical VHDL description of the layout-design that is verified to be free of a large class of design errors.

  8. Implementation of optical interconnections for VLSI

    NASA Technical Reports Server (NTRS)

    Wu, Wennie H.; Bergman, Larry A.; Johnston, Alan R.; Guest, Clark C.; Esener, Sadik C.

    1987-01-01

    This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: (1) the holographic optical element (HOE), (2) the laser sources, (3) the detectors and associated circuits forming an optically addressed gate, and (4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 x 20 microns has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity, and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five holograms.

  9. Finite element computation with parallel VLSI

    NASA Technical Reports Server (NTRS)

    Mcgregor, J.; Salama, M.

    1983-01-01

    This paper describes a parallel processing computer consisting of a 16-bit microcomputer as a master processor which controls and coordinates the activities of 8086/8087 VLSI chip set slave processors working in parallel. The hardware is inexpensive and can be flexibly configured and programmed to perform various functions. This makes it a useful research tool for the development of, and experimentation with parallel mathematical algorithms. Application of the hardware to computational tasks involved in the finite element analysis method is demonstrated by the generation and assembly of beam finite element stiffness matrices. A number of possible schemes for the implementation of N-elements on N- or n-processors (N is greater than n) are described, and the speedup factors of their time consumption are determined as a function of the number of available parallel processors.

  10. Hierarchical Design and Verification for VLSI

    NASA Technical Reports Server (NTRS)

    Shostak, R. E.; Elliott, W. D.; Levitt, K. N.

    1983-01-01

    The specification and verification work is described in detail, and some of the problems and issues to be resolved in their application to Very Large Scale Integration VLSI systems are examined. The hierarchical design methodologies enable a system architect or design team to decompose a complex design into a formal hierarchy of levels of abstraction. The first step inprogram verification is tree formation. The next step after tree formation is the generation from the trees of the verification conditions themselves. The approach taken here is similar in spirit to the corresponding step in program verification but requires modeling of the semantics of circuit elements rather than program statements. The last step is that of proving the verification conditions using a mechanical theorem-prover.

  11. Periodic binary sequence generators: VLSI circuits considerations

    NASA Technical Reports Server (NTRS)

    Perlman, M.

    1984-01-01

    Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

  12. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

  13. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  14. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  15. Development of a monolithic, multi-MEMS microsystem on a chip demonstrating iMEMS{trademark} VLSI technology. R and D status report number 10, January 1--March 31, 1996

    SciTech Connect

    1996-04-17

    This quarter saw the first silicon from the iMEMS{reg_sign} test chip, with complete circuits and beam structures. The wafers looked fine cosmetically and the circuits functioned as designed, but the beams suffered an anomaly that the authors have never seen before. Diagnostic work is under way to sort out the root cause, and other wafers are coming out this quarter to see if it was a one-time anomaly. Work on the process-development front has slowed because of the construction of a dedicated fabrication line for the last-generation process. With the current robust market place for ADI`s business, the existing fabrication line has been operating at 100% capacity. On the device front, great progress has been made by both Berkeley and ADI in the area of gyroscopes. Measurements of close to a degree per second or better have been made for gyros of all three axes and of both single- (linear) and double- (rotary) axis devices. In addition, ADI has designed a gyro that can be packaged in air that very well might meet some of the low-precision needs. Accelerometers of several new formats have been designed and several have been implemented in silicon. First samples of the ADXL 181 designed especially for the fuzing, safe and arming application have been assembled and are in characterization by ADI and others. In addition, 2-axis, Z-axis and digital output designs have been demonstrated. A 3-axis micro-watt accelerometer has been designed and is in fabrication. A 2-axis design for tilt applications is also nearing silicon realization. This portfolio of linear accelerometers, and even angular versions of the same provide, an arsenal of capability for specialized needs as they arise in both commercial and military applications.

  16. High throughput wafer defect monitor for integrated metrology applications in photolithography

    NASA Astrophysics Data System (ADS)

    Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

    2008-03-01

    The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

  17. A new method of VLSI conform design for MOS cells

    NASA Astrophysics Data System (ADS)

    Schmidt, K. H.; Wach, W.; Mueller-Glaser, K. D.

    An automated method for the design of specialized SSI/LSI-level MOS cells suitable for incorporation in VLSI chips is described. The method uses the symbolic-layout features of the CABBAGE computer program (Hsueh, 1979; De Man et al., 1982), but restricted by a fixed grid system to facilitate compaction procedures. The techniques used are shown to significantly speed the processes of electrical design, layout, design verification, and description for subsequent CAD/CAM application. In the example presented, a 211-transistor, parallel-load, synchronous 4-bit up/down binary counter cell was designed in 9 days, as compared to 30 days for a manually-optimized-layout version and 3 days for a larger, less efficient cell designed by a programmable logic array; the cell areas were 0.36, 0.21, and 0.79 sq mm, respectively. The primary advantage of the method is seen in the extreme ease with which the cell design can be adapted to new parameters or design rules imposed by improvements in technology.

  18. A bioinspired collision detection algorithm for VLSI implementation

    NASA Astrophysics Data System (ADS)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  19. Design and implementation of highly parallel pipelined VLSI systems

    NASA Astrophysics Data System (ADS)

    Delange, Alphonsus Anthonius Jozef

    A methodology and its realization as a prototype CAD (Computer Aided Design) system for the design and analysis of complex multiprocessor systems is presented. The design is an iterative process in which the behavioral specifications of the system components are refined into structural descriptions consisting of interconnections and lower level components etc. A model for the representation and analysis of multiprocessor systems at several levels of abstraction and an implementation of a CAD system based on this model are described. A high level design language, an object oriented development kit for tool design, a design data management system, and design and analysis tools such as a high level simulator and graphics design interface which are integrated into the prototype system and graphics interface are described. Procedures for the synthesis of semiregular processor arrays, and to compute the switching of input/output signals, memory management and control of processor array, and sequencing and segmentation of input/output data streams due to partitioning and clustering of the processor array during the subsequent synthesis steps, are described. The architecture and control of a parallel system is designed and each component mapped to a module or module generator in a symbolic layout library, compacted for design rules of VLSI (Very Large Scale Integration) technology. An example of the design of a processor that is a useful building block for highly parallel pipelined systems in the signal/image processing domains is given.

  20. A VLSI architecture for high performance CABAC encoding

    NASA Astrophysics Data System (ADS)

    Shojania, Hassan; Sudharsanan, Subramania

    2005-07-01

    One key technique for improving the coding e+/-ciency of H.264 video standard is the entropy coder, context- adaptive binary arithmetic coder (CABAC). However the complexity of the encoding process of CABAC is signicantly higher than the table driven entropy encoding schemes such as the Hu®man coding. CABAC is also bit serial and its multi-bit parallelization is extremely di+/-cult. For a high denition video encoder, multi-giga hertz RISC processors will be needed to implement the CABAC encoder. In this paper, we provide an e+/-cient, pipelined VLSI architecture for CABAC encoding along with an analysis of critical issues. The solution encodes a binary symbol every cycle. An FPGA implementation of the proposed scheme capable of 104 Mbps encoding rate and test results are presented. An ASIC synthesis and simulation for a 0.18 ¹m process technology indicates that the design is capable of encoding 190 million binary symbols per second using an area of 0.35 mm2. ¤

  1. A High Performance VLSI Computer Architecture For Computer Graphics

    NASA Astrophysics Data System (ADS)

    Chin, Chi-Yuan; Lin, Wen-Tai

    1988-10-01

    A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

  2. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    NASA Technical Reports Server (NTRS)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  3. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Hsu, I. S.; Chang, J. J.; Shyu, H. C.; Reed, I. S.

    1986-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.

  4. A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

    1986-01-01

    A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

  5. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  6. System for slicing wafers

    NASA Astrophysics Data System (ADS)

    1982-02-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  7. System for slicing wafers

    NASA Technical Reports Server (NTRS)

    1982-01-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  8. Wafer Fusion for Integration of Semiconductor Materials and Devices

    SciTech Connect

    Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

    1999-05-01

    We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

  9. Wafer Replacement Cluster Tool (Presentation);

    SciTech Connect

    Branz, H. M.

    2008-04-01

    This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

  10. On testing VLSI chips for the big Viterbi decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.

    1989-01-01

    A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

  11. Wafer level test solutions for IR sensors

    NASA Astrophysics Data System (ADS)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  12. NASA Space Engineering Research Center for VLSI systems design

    NASA Technical Reports Server (NTRS)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  13. Architecture for VLSI design of Reed-Solomon encoders

    NASA Technical Reports Server (NTRS)

    Liu, K. Y.

    1982-01-01

    A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

  14. Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

    NASA Astrophysics Data System (ADS)

    Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

    2015-04-01

    In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

  15. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  16. Role for optical signal and image processing in the VLSI era

    NASA Astrophysics Data System (ADS)

    Roberts, J. B. G.

    1986-02-01

    Likely areas for applications of optical signal processing (OSP) in the near-term, which is now dominated by VLSI technologies, are discussed. VLSI devices have the attributes of arbitrary accuracy, predictability of performance and versatility. The devices can be manufactured before extensive definition of their possible applications. Optical devices are analog and suffer inflexibility of application, variations in performance due to, e.g., temperature, and limited dynamic range. Optical devices can carry extremely high bandwidths at ultra-high speeds, significant factors in remote sensing and parallel processing applications. The range of applications for Fourier optics is limited by the capabilities of peripheral systems, e.g., the ability to adjust the FOV for SAR systems and computer memory storage. Although the range of OSP applications is limited by a lack of suitable peripherals, digital devices are approaching maximum complexity, size and processing speeds. It is speculated that the first nominal application of OSP devices will be where optical inputs are specified and where an acousto-optic analyzer are necessary. The usage of the technology will, in any case, be limited for at least a decade.

  17. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  18. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L.

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  19. A special purpose silicon compiler for designing supercomputing VLSI systems

    NASA Technical Reports Server (NTRS)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  20. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  1. Single-Chip VLSI Reed-Solomon Decoder

    NASA Technical Reports Server (NTRS)

    Shao, Howard M.; Truong, Trieu-Kie; Hsu, In-Shek; Deutsch, Leslie J.

    1988-01-01

    Efficient utilization of computing elements reduces size while preserving throughput. VLSI architecture is pipeline Reed-Solomon decoder for correction of errors and erasures. Uses transform circuit to compute syndrome polynomial. Erasure information enters decoder as binary sequence. Applied to variety of digital communications involving error-correcting RS codes.

  2. Hybrid VLSI/QCA Architecture for Computing FFTs

    NASA Technical Reports Server (NTRS)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  3. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    ERIC Educational Resources Information Center

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  4. BCB wafer bonding for microfluidics

    NASA Astrophysics Data System (ADS)

    Hwang, Taejoo; Popa, Dan; Sin, Jeongsik; Stephanou, Harry E.; Leonard, Eric M.

    2004-01-01

    In this paper we show that BCB wafer bonding, combined with deep-reactive-ion-etching (DRIE) for silicon, and HF etching for FOTURAN glass are viable methods to fabricate three-dimensional microfluidics. The BCB film is patterned by dry-etching technique with a photoresist mask and the target wafer is then bulk-micromachined together with the BCB mask. The two micromachined wafers are then bonded together under vacuum or nitrogen gas environment, at low temperature. Silicon-glass, silicon-silicon and glass-glass are all possible bonding pairs using thermocompressive bonding with BCB. It was found that hard-cured BCB bonding is more suitable for microfluidic channel fabrications than soft-cured BCB bonding, due to adhesive overflows in microfluidic channels and delamination during wet etching.

  5. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  6. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R. (Berkeley, CA)

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  7. A Sharp methodology for VLSI layout

    NASA Astrophysics Data System (ADS)

    Bapat, Shekhar

    1993-01-01

    The layout problem for VLSI circuits is recognized as a very difficult problem and has been traditionally decomposed into the several seemingly independent sub-problems of placement, global routing, and detailed routing. Although this structure achieves a reduction in programming complexity, it is also typically accompanied by a reduction in solution quality. Most current placement research recognizes that the separation is artificial, and that the placement and routing problems should be solved ideally in tandem. We propose a new interconnection model, Sharp and an associated partitioning algorithm. The Sharp interconnection model uses a partitioning shape that roughly resembles the musical sharp 'number sign' and makes extensive use of pre-computed rectilinear Steiner trees. The model is designed to generate strategic routing information along with the partitioning results. Additionally, the Sharp model also generates estimates of the routing congestion. We also propose the Sharp layout heuristic that solves the layout problem in its entirety. The Sharp layout heuristic makes extensive use of the Sharp partitioning model. The use of precomputed Steiner tree forms enables the method to model accurately net characteristics. For example, the Steiner tree forms can model both the length of the net and more importantly its route. In fact, the tree forms are also appropriate for modeling the timing delays of nets. The Sharp heuristic works to minimize both the total layout area by minimizing total net length (thus reducing the total wiring area), and the congestion imbalances in the various channels (thus reducing the unused or wasted channel area). Our heuristic uses circuit element movements amongst the different partitioning blocks and selection of alternate minimal Steiner tree forms to achieve this goal. The objective function for the algorithm can be modified readily to include other important circuit constraints like propagation delays. The layout technique first computes a very high-level approximation of the layout solution (i.e., the positions of the circuit elements and the associated net routes). The approximate solution is alternately refined, objective function. The technique creates well defined sub-problems and offers intermediary steps that can be solved in parallel, as well as a parallel mechanism to merge the sub-problem solutions.

  8. The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Shao, H. M.; Deutsch, L. J.

    1987-01-01

    The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.

  9. A multi coding technique to reduce transition activity in VLSI circuits

    NASA Astrophysics Data System (ADS)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  10. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  11. Bare wafer metrology challenges in microlithography at 45 nm node and beyond

    NASA Astrophysics Data System (ADS)

    Huang, Chunsheng

    2008-03-01

    The shrinking depth of focus (100-150 nm) of high numerical aperture immersion microlithography optics dictates a tight wafer flatness budget. Wafer flatness nanotopography (NT), and edge roll off (ERO) are critical parts of the equation in immersion microlithographic technology at the 45 nm node and beyond. Wafer features at the nanometer level could result not only in focus variation of the litho process, or thin film thickness variation in CMP process, but also in structural defects of the devices. Therefore, the metrology to measure nanometer level features and to control the quality of wafer geometry is a key to the success of IC production at the 45 nm node and beyond.

  12. WaferOptics® mass volume production and reliability

    NASA Astrophysics Data System (ADS)

    Wolterink, E.; Demeyer, K.

    2010-05-01

    The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

  13. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  14. μ-Device fabrication and packaging below 300°C utilizing plasma-assisted wafer-to-wafer bonding

    NASA Astrophysics Data System (ADS)

    Kirchberger, Herwig; Pelzer, Rainer; Farrens, Sharon

    2006-01-01

    Wafer-to-wafer bonding techniques, such as anodic bonding or high temperature silicon direct fusion bonding, have been in development since the late 1960's and became key technologies for MEMS manufacturing. Plasma assisted wafer bonding is an emerging method offering several advantages over traditional bonding techniques. This technology was first discovered and patented in the early 1990's and has been used in SOI production for the past five years. Now plasma activation benefits are being used to enable 3D integration and advanced MEMS device fabrication and packaging. The main advantage of plasma assisted bonding is that high strength direct bonds between substrates, like Si, glass or polymers, can be achieved already below 300°C.

  15. Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001

    SciTech Connect

    Beetz, C.P.; Steinbeck, J.; Hsueh, K.L.

    2001-03-31

    The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.

  16. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  17. Characterization of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  18. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  19. On-wafer magnetic resonance of magnetite nanoparticles

    NASA Astrophysics Data System (ADS)

    Little, Charles A. E.; Russek, Stephen E.; Booth, James C.; Kabos, Pavel; Usselman, Robert J.

    2015-11-01

    Magnetic resonance measurements of ferumoxytol and TEMPO were made using an on-wafer transmission line technique with a vector network analyzer, allowing for broadband measurements of small sample volumes (4 nL) and small numbers of spins (1 nmol). On-wafer resonance measurements were compared with standard single-frequency cavity-based electron paramagnetic resonance (EPR) measurements using a new power conservation approach and the results show similar line shape. On-wafer magnetic resonance measurements using integrated microfluidics and microwave technology can significantly reduce the cost and sample volumes required for EPR spectral analysis and allow for integration of EPR with existing lab-on-a-chip processing and characterization techniques for point-of-care medical diagnostic applications.

  20. VLSI architectures for the new (T,L) algorithm

    NASA Astrophysics Data System (ADS)

    Bengough, P. A.; Simmons, S. J.

    Trellis coding techniques have seen much use in error correction codes for space and satellite applications. When long sequences of data are encoded, the number of possible paths through the trellis becomes great and a trellis search algorithm must be used to determine the path that best matches the received data sequence. The (T,L) algorithm is a new reduced complexity trellis search algorithm, applicable to data sequence estimation in digital communications, that adapts to changing channel conditions. Its simplicity and inherent parallelism suits it well for very large scale integration (VLSI) implementation. A number of alternative VLSI architectures are presented which can be used to realize this algorithm. While one uses a simple nonsorting structure, two other sorting designs based on parallel insertion and weavesorting algorithms are proposed. The area-time performance of the various architectures is compared.

  1. Noise-margin limitations on gallium-arsenide VLSI

    NASA Technical Reports Server (NTRS)

    Long, Stephen I.; Sundaram, Mani

    1988-01-01

    Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

  2. Semiconductor measurement technology: Design and testing guides for the COMOS and lateral bipolar-on-SOI test library

    NASA Astrophysics Data System (ADS)

    Marshall, J. C.; Zaghloul, M. E.

    1994-03-01

    Design and testing guides have been developed for the test library from which test chip NIST8 and test wafer NIST9 were derived. They were designed for use in process monitoring and device parameter extraction to evaluate and compare CMOS (Complementary Metal-Oxide-Semiconductor) test structures, including devices and circuits, fabricated on both bulk silicon and SOI (Silicon-on-Insulator), specifically SIMOX (Separation by the IMplantation of OXygen), wafers. The test library consists of both CMOS-on-SOI and lateral bipolar-on-SOI modules. From it, 20 modules were assembled to create CMOS test chip NIST8 that was fabricated using a standard bulk CMOS foundry through the MOSIS service. SOI/SIMOX test wafer NIST9 contains approximately 1000 modules and was also assembled from modules in this test library. Fourteen processing masks are used to fabricate depletion-mode MOSFET's, lateral bipolar devices, and CMOS MOSFET's with source-to-channel ties. The SOI/SIMOX technology file used with the Magic VLSI layout editor was modified to include the layers necessary to generate these 14 processing masks. This modification is discussed, and unique test structure designs are presented.

  3. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  4. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-01-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  5. A VLSI single chip 8-bit finite field multiplier

    NASA Technical Reports Server (NTRS)

    Deutsch, L. J.; Shao, H. M.; Hsu, I. S.; Truong, T. K.

    1985-01-01

    A Very Large Scale Integration (VLSI) architecture and layout for an 8-bit finite field multiplier is described. The algorithm used in this design was developed by Massey and Omura. A normal basis representation of finite field elements is used to reduce the multiplication complexity. It is shown that a drastic improvement was achieved in this design. This multiplier will be used intensively in the implementation of an 8-bit Reed-Solomon decoder and in many other related projects.

  6. Handshake circuits: An intermediary between communicating processes and VLSI

    NASA Astrophysics Data System (ADS)

    Vanberkel, Cornelis Hermanus

    Tangram and handshake circuits are introduced. The cost and performance of the circuits is the primary concern, as they make Very Large Scale Integration (VLSI) programming different from (and also more difficult than) traditional computer programming. The theory for handshake circuits makes up the body of the thesis. The key motion is that of the handshake process. A handshake process is a mathematical object that describes a handshake communication behavior. This handshake behavior may be that of the components of a handshake circuit. A handshake circuit is a set of handshake processes that satisfy a simple compositional rule. The behavior of the handshake circuit is defined through parallel composition of its constituents components and is, again, a handshake process. In appendix A, the delay insensitivity of handshake circuits is related to the theory reported in the literature. A calculus for handshake processes is developed. This calculus allows concise descriptions of behaviors of handshake components. A precise definition of Tangram is given. For a subset of Tangram, which we call Core Tangram, a formal denotation 'H' is given in terms of handshake processes. In appendix B, a link to the well known failure semantics of CSP (Communication Sequential Processes) is established. The translation of Tangram programs into handshake circuits by means of the mathematical function 'C' is described. For Core Tangram it is proven that the behavior of the compiled handshake circuit is equivalent to that of the original program in a well defined sense. The realization of handshake circuits in VLSI is considered. Issues such as peephole optimization, handshake refinement, data encoding, decompositions into VLSI operator networks, initialization, and testing are discussed. VLSI programming and silicon compilation are discussed.

  7. A VLSI design of a pipeline Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

    1985-01-01

    A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

  8. Radiation hardness and annealing tests of a custom VLSI device

    SciTech Connect

    Breakstone, A.; Parker, S.; Adolphsen, C.; Litke, A.; Schwarz, A.; Turala, M.; Lueth, V.; California Univ., Santa Cruz, CA . Inst. for Particle Physics; Stanford Linear Accelerator Center, Menlo Park, CA )

    1986-10-01

    Several NMOS custom VLSI ( Microplex'') circuits have been irradiated with a 500 rad/hr {sup 60}Co source. With power off three of four chips tested have survived doses exceeding 1 Mrad. With power on at a 25% duty cycle, all chips tested failed at doses ranging from 10 to 130 krad. Annealing at 200{degree}C was only partially successful in restoring the chips to useful operating conditions. 10 refs., 4 figs., 1 tab.

  9. Drift chamber tracking with a VLSI neural network

    SciTech Connect

    Lindsey, C.S.; Denby, B.; Haggerty, H. ); Johns, K. . Dept. of Physics)

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers.

  10. ULYSSES - an expert-system-based VLSI design environment

    SciTech Connect

    Bushnell, M.L.

    1987-01-01

    Ulysses is a VLSI computer-aided design (CAD) environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation (DA) system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment employs artificial intelligence techniques, functions as an interactive expert system, and interprets descriptions of design tasks encoded in the scripts language. An integrated-circuit silicon compilation task is presented as an example of the ability of Ulysses to automatically execute CAD tools to solve a problem where inferencing is required to obtain a viable VLSI layout. The inferencing mechanism, in the form of a controlled production system, allows Ulysses to recover when routing channel congestion or over-constrained leaf-cell boundary conditions make it impossible for CAD tools to complete layouts. Also, Ulysses allows the designer to intervene while design activities are being carried out. Consistency-maintenance rules encoded in the scripts language enforce geometric floor-plan consistency when CAD tools fail and when the designer makes adjustments to a VLSI chip layout.

  11. Deposition uniformity inspection in IC wafer surface

    NASA Astrophysics Data System (ADS)

    Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

    2014-03-01

    This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

  12. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  13. Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards. [Very Large Scale Integration (VLSI)

    SciTech Connect

    Pin, F.G.; Watanabe, Y.

    1992-01-01

    This paper discusses the sensor-based driving of a car in a-priori unknown environments using human-like'' reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver's aid using the new fuzzy inferencing VLSI hardware and human-like'' reasoning schemes.

  14. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    NASA Astrophysics Data System (ADS)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2015-02-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  15. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    PubMed

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-01-01

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

  16. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    ERIC Educational Resources Information Center

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.

  17. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    ERIC Educational Resources Information Center

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  18. A VLSI Reed-Solomon decoder architecture for concatenate-coded space and spread spectrum communications

    NASA Technical Reports Server (NTRS)

    Liu, K. Y.

    1983-01-01

    In this paper, a VLSI Reed-Solomon (RS) decoder architecture for concatenate-coded space and spread spectrum communications, is presented. The known decoding procedures for RS codes are exploited and modified to obtain a repetitive and recursive decoding technique which is suitable for VLSI implementation and pipeline processing.

  19. New fabrication method of glass packages with inclined optical windows for micromirrors on wafer level

    NASA Astrophysics Data System (ADS)

    Stenchly, Vanessa; Quenzer, Hans-Joachim; Hofmann, Ulrich; Janes, Joachim; Jensen, Björn; Benecke, Wolfgang

    2013-03-01

    For many applications it is inevitable to protect MEMS devices against environmental impacts like humidity which can affect their performance. Moreover recent publications demonstrates that micro mirrors can achieve very large optical scan angles at moderate driving voltages even exceeding 100 degrees when hermetically sealed under vacuum. While discrete chips may be evacuated and sealed on single die level using small can packages like TO housings, it is obvious that for high volume production a much more economical solution for the realisation of transparent optical packages already on wafer level must be developed. However, since any laser beam crossing a transparent glass surface is partly reflected even when anti-reflective coatings are applied, the construction of a wafer level optical housing suitable for laser projection purpose requires more than the integration of simple plane glass cap. The use of inclined optical windows avoids the occurrence of intense reflections of the incident laser beam in the projected images. This paper describes a unique technology to fabricate glass packages with inclined optical windows for micro mirrors on 8 inch wafers. The new process uses a high temperature glass forming process based on subsequent wafer bonding. A borosilicate glass wafer is bonded together with two structured silicon wafers. By grinding both sides of the wafer stack, a pattern of isolated silicon structures is defined. This preprocessed glass wafer is bonded thereon on a third structured silicon wafer, wherein the silicon islands are inserted into the cavities. By setting a defined pressure level inside the cavities during the final wafer bonding, the silicon glass stack extruded and it is out of plane during a subsequent annealing process at temperatures above the softening point of the glass. Finally the silicon is selectively removed in a wet etching process. This technique allows the fabrication of 8 inch glass wafers with oblique optical surfaces with surface roughness <1 nm and an evenness of < 300 nm.

  20. Wafer CD variation for random units of track and polarization

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

    2012-03-01

    After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

  1. Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis

    SciTech Connect

    Tobin, K.W.

    2003-05-22

    This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

  2. Wafer-bonded surface plasmon waveguides

    NASA Astrophysics Data System (ADS)

    Berini, Pierre; Mattiussi, Greg; Lahoud, Nancy; Charbonneau, Robert

    2007-02-01

    Direct wafer bonding and thinning were explored as an approach for constructing long-range surface plasmon waveguides. The structures consist of a thin metal stripe deposited into a shallow trench etched into one of the claddings, to which another cladding of the same material is directly bonded. The approach was developed first using Pyrex wafers in order to assess feasibility and then using lithium niobate wafers. Optical and electro-optical measurements validate the approach.

  3. Particle detector with three microchannel wafers

    SciTech Connect

    Gribov, I.V.; Gubin, S.V.; Lazutin, E.V.; Persiantseva, N.M.; Shumakov, A.V.

    1985-11-01

    A particle detector consisting of three series-connected microchannel wafers is described. The detector provides a singleelectron gain of 2x10/sup 7/ without using extreme wafer operating conditions and the width of the pulse amplitude distribution is approximately 100%. The particle sources used were a tritium beta source, a Pierce electron gun with spherical electrodes, and a /sup 233/ Pu alpha source. The load characteristics of one microchannel wafer for various supply voltages were measured.

  4. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  5. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    SciTech Connect

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  6. A reclaiming process for solar cell silicon wafer surfaces.

    PubMed

    Pa, P S

    2011-01-01

    The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost. PMID:21446525

  7. An adaptive, lossless data compression algorithm and VLSI implementations

    NASA Technical Reports Server (NTRS)

    Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

    1993-01-01

    This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

  8. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    NASA Technical Reports Server (NTRS)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  9. A VLSI R = 1/2, K = 7 Viterbi decoder

    NASA Astrophysics Data System (ADS)

    Cain, J. B.; Kriete, R. A.

    Convolutional coding with Viterbi decoding has become a very important component in many communication systems. Specifically, the R = 1/2, K = 7 machine has become a de facto standard in many applications because of its high coding gain (5.0 dB at Pb = 0.00001 with PSK) relative to implementation complexity. In this paper a description is given of the design and implementation of the fastest known (10 Mb/s) single-chip design of this machine. It is implemented in CMOS VLSI. Naturally, the availability of such a chip will greatly increase the application of this technique in communication systems.

  10. MUSE - a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer-scale integration. Technical report

    SciTech Connect

    Rader, C.M.; Allen, D.L.; gLASCO , D.B.; Woodward, C.E.

    1990-05-18

    This report describes an architecture for a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which we call MUSE (Matrix Update Systolic Experiment), and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 decibel of signal-to-noise improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI (Very Large Scale Integration). The complete design of such a wafer is described.

  11. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    PubMed Central

    Devi, T. Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz. PMID:26558289

  12. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  13. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  14. Preparation and Characterization of PZT Wafers

    NASA Astrophysics Data System (ADS)

    Seal, A.; Rao, B. S. S. Chandra; Kamath, S. V.; Sen, A.; Maiti, H. S.

    2008-07-01

    Piezoelectric materials have recently attracted a lot of attention for ultrasonic structural health monitoring (shm) in aerospace, defence and civilian sectors, where they can act as both actuators and sensors. Incidentally, piezoelectric materials in the form of wafers (pwas-piezoelectric wafer active sensor, approx. 5-10 mm square and 0.2-0.3 mm thickness) are inexpensive, non intrusive and non-resonant wide band devices that can be surface-mounted on existing structures, inserted between the layers of lap joints or embedded inside composite materials. The material of choice for piezoelectric wafers is lead zirconate titanate (PZT) of composition close to morphotropic phase boundary [pb(zr0.52 ti0.48)o3]. However, an excess pbo is normally added to pzt as a densification aid and also to make up for the lead loss during high temperature sintering. Hence, it is of paramount importance to know how the shift of the lead content from the morphotropic composition affects the piezoelectric and mechanical properties of the sintered wafers, keeping in view the importance of mechanical properties of wafers in shm. In the present study, we observed that with the increase in the lead content of the sintered wafers, the dielectric and piezoelectric constants decreased. However, the elastic modulus, hardness and fracture toughness of the wafers increased with increasing lead content in the composition. Hence, the lead content in the sintered wafers should be optimized to get acceptable piezoelectric and mechanical

  15. A fast neural-network algorithm for VLSI cell placement.

    PubMed

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average. PMID:12662737

  16. New VLSI complexity results for threshold gate comparison

    SciTech Connect

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  17. Comparing structurally different views of a VLSI design

    NASA Astrophysics Data System (ADS)

    Spreitzer, Mike

    1990-06-01

    One of the major problems of Very Large Scale Integration (VLSI) is coping with the quantity and complexity of the design data. The leading solutions use divide-and-conquer techniques. Two different ways of dividing are popular: division by a structural hierarchy, and division into various levels of abstraction (a view is a description at a particular level of abstraction). The VLSI designs are so large and complex that both divisions are needed, which raises a question: should all the views of a design use the same hierarchy. The question is currently controversial. The dissertation, while not presuming to settle that question, argues in favor of allowing the view to have different hierarchies, and addresses a problem that is complicated by differences in hierarchy. That is the comparison problem, which has two parts: verify consistency between alternate views, and determine the correspondence between the design entities of those views. A new comparison method, Informed Comparison, which neither requires the views to have essentially identical hierarchies nor flattens the views is introduced. Informed Comparison requires the designers to maintain a key, which is a description of the intended relation between the hierarchies of the views.

  18. Methane production using resin-wafer electrodeionization

    SciTech Connect

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  19. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices

    NASA Astrophysics Data System (ADS)

    Kim, Dae Jong; Yoo, Hyung Won; Kim, Chul Hong; Lee, Hak Kwon; Kim, Sung Su; Bae, Koon Ho; Spielberg, Hedvi; Lee, Yun Ho; Levi, Shimon; Bustan, Yariv; Rozentsvige, Moshe

    2010-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

  20. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

  1. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    NASA Astrophysics Data System (ADS)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  2. A silicon wafer packaging solution for HB-LEDs

    NASA Astrophysics Data System (ADS)

    Murphy, Tom; Weichel, Steen; Isaacs, Steven; Kuhmann, Jochen

    2007-09-01

    In this paper we present HyLED, a silicon wafer packaging solution for high-brightness LEDs. The associated technology is batch micro-machining/metallisation processing of silicon wafers allowing significant reduction of the final device size. The presented package is multi-functional where the micro-machined cavity acts as reflector, thermal conductor and reservoir for the silicone/colour conversion substance. The base material, silicon, has excellent mechanical and thermal properties and enables direct integration of intelligence. We present customer specific solutions, open tool samples and performance data for optical and thermal parameters and reliability testing. Thermal resistance values of R<5 K/W, junction-to-board are demonstrated.

  3. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    DOE PAGESBeta

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; Castellanos, Sergio; Buonassisi, Tonio

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

  4. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    SciTech Connect

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; Castellanos, Sergio; Buonassisi, Tonio

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled to effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.

  5. Parallel VLSI architecture emulation and the organization of APSA/MPP

    NASA Technical Reports Server (NTRS)

    Odonnell, John T.

    1987-01-01

    The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.

  6. The VLSI design of a single chip Reed-Solomon encoder

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Deutsch, L. J.; Reed, I. S.

    1982-01-01

    A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

  7. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  8. Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

    NASA Technical Reports Server (NTRS)

    Aanstoos, J. V.; Snyder, W. E.

    1981-01-01

    Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

  9. VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

    NASA Technical Reports Server (NTRS)

    Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

    1984-01-01

    Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

  10. Optoelectronic interconnects for 3D wafer stacks

    NASA Astrophysics Data System (ADS)

    Ludwig, David E.; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as a means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper provides definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies are discussed.

  11. ELID supported grinding of thin sapphire wafers

    NASA Astrophysics Data System (ADS)

    Makarenko, Igor; Vogt, Christian; Rascher, Rolf; Sperber, Peter; Stirner, Thomas

    2010-10-01

    Sapphire material is, due to its crystal structure, difficult to machine in an economic way. There is a request for thin, i.e. below 0.2 mm thickness, sub surface damage free wafers to produce sensor elements. ELID -- electrolytic in process dressing -- is an innovative high end grinding technology, using small grain sizes, which enable to manufacture surfaces in a quality that is close to polished. ELID grinding requires exactly aligned machining parameters of the grinding process. To grind sapphire the material's behavior is additionally to be considered. Studies on the necessary oxide layer on the grinding wheel and influences on its build-up process will be presented. The presentation shows the results of comparing grinding experiments on different -- c-plane and r-plane -- sapphire materials. Different tool specifications are used. Infeed and grinding velocity are varied and the results on wear, removal rate and surface quality are shown. The process parameters the stiffness of the machine, the grinding forces and pressure are evaluated. The ELID grinding is compared in its results to conventional grinding steps. The material removal rate on sapphire is relatively small due to the extreme hardness of sapphire. The achieved excellent surface roughness will be discussed.

  12. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    NASA Astrophysics Data System (ADS)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  13. Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

    NASA Technical Reports Server (NTRS)

    Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

    1989-01-01

    The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

  14. VLSI-based Video Event Triggering for Image Data Compression

    NASA Technical Reports Server (NTRS)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  15. Modeling selective attention using a neuromorphic analog VLSI device.

    PubMed

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features. PMID:11112258

  16. Opto-VLSI-based reconfigurable photonic RF filter

    NASA Astrophysics Data System (ADS)

    Xiao, Feng; Shen, Mingya; Juswardy, Budi; Alameh, Kamal

    2009-08-01

    Radio frequency (RF) signal processors based on photonics have several advantages, such as broadband capability, immunity to electromagnetic interference, flexibility, and light weight in comparison to all-electronics RF filters. It still requires innovative research and development to achieve high-resolution reconfigurable photonic RF signal processors featuring high selectivity, resolution, wide tunability, and fast reconfigurability. In this paper, we propose and experimentally demonstrate the concept of a reconfigurable photonic RF filter structure integrating an Amplified Spontaneous Emission (ASE) source, an Opto-VLSI processor that generates arbitrary phase-only steering and multicasting holograms for wavelength selection and attenuation, arrayed waveguide gratings (AWGs) for waveband multiplexing and demultiplexing, high-dispersion fibres for RF delay synthesis, and a balanced photodetector for generating positive and negative processor weights. Independent control of the weights of a reconfigurable photonic RF filter is experimentally demonstrated.

  17. Efficient VLSI architecture for training radial basis function networks.

    PubMed

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  18. Event-driven neural integration and synchronicity in analog VLSI.

    PubMed

    Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

    2012-01-01

    Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics. PMID:23366007

  19. A laser plotting system for VLSI chip layouts

    NASA Technical Reports Server (NTRS)

    Deutsch, L. J.; Harding, J. A.

    1985-01-01

    One of the most time consuming facets of custom Very Large Scale Integration (VLSI) design is obtaining hardcopy plots of the mask geometries of cells and chips. The traditional method of generating these plots is to use a multicolor pen plotter. Pen plotters are inherently slow and the plotting speed increases linearly with the number of edges that must be plotted. A moderate custom chip design at the Jet Propulsion Laboratory (JPL) now consists of more than 200,000 such edges and can take as much as eight hours to plot using a pen plotter. Software is described that was written at JPL to produce similar plots using a laser printer. It is shown that, for rather small layouts, the laser printer can provide nearly instantaneous turnaround. For moderate to large chip designs, the laser printer provides a factor of five or more improvement is speed over pen plotting.

  20. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  1. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  2. Critical dimension control for prevention of wafer-to-wafer and module-to-module difference

    NASA Astrophysics Data System (ADS)

    Deguchi, Masatoshi; Tanaka, Kouichirou; Nagatani, Naohiko; Miyata, Yuichiro; Yamashita, Mitsuo; Minami, Yoshiaki; Matsuyama, Yuji

    2004-05-01

    In recent years, the worldwide semiconductor market has changed drastically, and it is expected that the digital device market will continue to expand towards general consumer electronics and away from the personal computers that have been the core of the market. To accommodate this shift, the new devices will be diversified with improved productivity, higher process yield, and higher precision. Clean Track (LITHIUS) design also has been changed drastically to maintain equal productivity with new high throughput exposure equipment. Design changes include increasing the number of processing chambers by stacking reduced size modules in order to meet high throughput and small footprint requirements. However, this design change concept raises concerns about increased wafer-to-wafer difference (WtW) and module-to-module different (MtM). These variations can result in lower process yield and have a negative effect on design rule shrinkage. The primary causes of WtW difference and MtM difference stem from minute module hardware variations, module height differences, and module parameter adjustment differences during the installation of the tool. Previous Clean Track development focused mainly on reduction of module hardware difference as an approach to reduce WtW variation. However, to further improve lot level uniformity, it is necessary to reduce module height difference factors within the system and module adjustment disparities such as plate temperature calibrations. Highly temperature sensitive ArF processes have necessitated precise manual PEB temperature adjustments. These calibrations are labor intensive and require many field hours to ensure optimal CD uniformity. Therefore, an auto temperature measurement and adjustment tool is developed to eliminate the human error due to manual adjustment and minimize adjustment time. In order to meet demands for design rules shrinkage and increased process uniformity we minimized the WtW and MtM difference by using thermal history adjustment and transfer time control. This method is also used to improve within wafer CD control technology resulting in a more stable process. In this report, we introduce improved features to reduce WtW and MtM variation and their effect on CD uniformity with 193nm (ArF) resist and 248nm (KrF) resist.

  3. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  4. Analyzes Data from Semiconductor Wafers

    Energy Science and Technology Software Center (ESTSC)

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore » of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  5. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  6. Improvement of focus accuracy on processed wafer

    NASA Astrophysics Data System (ADS)

    Higashibata, Satomi; Komine, Nobuhiro; Fukuhara, Kazuya; Koike, Takashi; Kato, Yoshimitsu; Hashimoto, Kohji

    2013-04-01

    As feature size shrinkage in semiconductor device progress, process fluctuation, especially focus strongly affects device performance. Because focus control is an ongoing challenge in optical lithography, various studies have sought for improving focus monitoring and control. Focus errors are due to wafers, exposure tools, reticles, QCs, and so on. Few studies are performed to minimize the measurement errors of auto focus (AF) sensors of exposure tool, especially when processed wafers are exposed. With current focus measurement techniques, the phase shift grating (PSG) focus monitor 1) has been already proposed and its basic principle is that the intensity of the diffraction light of the mask pattern is made asymmetric by arranging a π/2 phase shift area on a reticle. The resist pattern exposed at the defocus position is shifted on the wafer and shifted pattern can be easily measured using an overlay inspection tool. However, it is difficult to measure shifted pattern for the pattern on the processed wafer because of interruptions caused by other patterns in the underlayer. In this paper, we therefore propose "SEM-PSG" technique, where the shift of the PSG resist mark is measured by employing critical dimension-scanning electron microscope (CD-SEM) to measure the focus error on the processed wafer. First, we evaluate the accuracy of SEM-PSG technique. Second, by applying the SEM-PSG technique and feeding the results back to the exposure, we evaluate the focus accuracy on processed wafers. By applying SEM-PSG feedback, the focus accuracy on the processed wafer was improved from 40 to 29 nm in 3σ.

  7. Testability of VLSI (Very Large Scale Integration) leakage faults in CMOS (Complementary Metal Oxide Semiconductor)

    NASA Astrophysics Data System (ADS)

    Malaiya, Y. K.; Su, S. Y. H.

    1983-09-01

    With the advent of VLSI (Very Large Scale Integration), the importance of CMOS (Complementary Metal Oxide Semiconductor) technology has increased. CMOS offers some very significant advantages over NMOS, and has emerged very competitive. Therefore, testability of CMOS devices is of considerable importance. CMOS devices exhibit some failure modes which are not adequately represented by the classical stuck-at fault model. A new fault model is introduced here to represent such faults. Leakage faults are specifically examined in this report, such faults increase the static supply current (which is ordinarily quite low) substantially. A leakage testing experiment consists of applying different vectors to the circuit, and in each case measuring the static supply current. This experimentally obtained data is then analyzed to obtain fault-related information. Leakage testing offers extra testability without any additional pins. It can detect some faults which cannot be detected by the conventional testing. Test generation for several basic CMOS structures is considered. Correspondence between leakage testing and conventional testing is studied. Two methods for analyzing experimental data are presented. Available experimental data was analyzed to obtain statistical information.

  8. Knowledge-based synthesis of custom VLSI router software. [Very Large Scale Integration

    SciTech Connect

    Setliff, D.E.

    1989-01-01

    This thesis describes a synthesis architecture for automatic generation of technology-sensitive VLSI physical design tools from high-level specifications. Physical design refers to the process of reducing a structural description of a piece of hardwater down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The author argues that the appropriate place for technology-dependent information is not in the run-time environment of such tools, but in a generator for these tools. They describe a synthesis architecture and its prototype implementation - called ELF - that integrates knowledge of the application domain with knowledge of generic programming mechanics. ELF strives to meet the demands of the target technology by automatically generating an implementation of the tool to match the application requirements. The ELF synthesis architecture has three key features. First, a very high level language, lacking data structure implementation specifications, is used to describe algorithm design styles. Second, application domain knowledge and generic program synthesis knowledge are used to guide search among candidate design styles for all necessary component algorithms, and to deduce compatible data structure implementations for these components. Third, code generation is used to transform the resulting abstract descriptions of selected algorithms and data structures into final, executable code. Code generation is an incremental, stepwise refinement process, and also relies on application domain knowledge, as well as generic program synthesis knowledge. A wide variety of fully-functional routers has been synthesized by ELF, and verified on both synthetic and industrial routing benchmarks. ELF demonstrates a synthesis architecture that efficiently generates router software using router domain-specific and generic program synthesis knowledge as a synthesis guide.

  9. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    SciTech Connect

    Emanuel Sachs Tonio Buonassisi

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the wafer. In addition, it was found to be suitable for growing very large crystals. The equipment used was simple and inexpensive to operate. Reasonable solar cells were fabricated on re-crystallized material.

  10. VLSI processor with a configurable processing element array for balanced feature extraction in high-resolution images

    NASA Astrophysics Data System (ADS)

    Zhu, Hongbo; Shibata, Tadashi

    2014-01-01

    A VLSI processor employing a configurable processing element array (PEA) is developed for a newly proposed balanced feature extraction algorithm. In the algorithm, the input image is divided into square regions and the number of features is determined by noise effect analysis in each region. Regions of different sizes are used according to the resolutions and contents of input images. Therefore, inside the PEA, processing elements are hierarchically grouped for feature extraction in regions of different sizes. A proof-of-concept chip is fabricated using a 0.18 µm CMOS technology with a 32 × 32 PEA. From measurement results, a speed of 7.5 kfps is achieved for feature extraction in 128 × 128 pixel regions when operating the chip at 45 MHz, and a speed of 55 fps is also achieved for feature extraction in 1920 × 1080 pixel images.

  11. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  12. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    PubMed

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365 faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365 real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems. PMID:25538613

  13. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease

    PubMed Central

    Niu, Chuanxin M.; Nandyala, Sirish K.; Sanger, Terence D.

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin–Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems. PMID:25538613

  14. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

  15. Advanced technologies for Mission Control Centers

    NASA Technical Reports Server (NTRS)

    Dalton, John T.; Hughes, Peter M.

    1991-01-01

    Advance technologies for Mission Control Centers are presented in the form of the viewgraphs. The following subject areas are covered: technology needs; current technology efforts at GSFC (human-machine interface development, object oriented software development, expert systems, knowledge-based software engineering environments, and high performance VLSI telemetry systems); and test beds.

  16. Using wafer stacks as neutron monochromators

    NASA Astrophysics Data System (ADS)

    Vogt, T.; Passell, L.; Cheung, S.; Axe, J. D.

    1994-01-01

    A process to introduce a spatially homogeneous but anisotropic mosaic structure into thin, single-crystal wafers, which are then stacked and used as neutron monochromators, is described. The advantages compared to conventional techniques are good reproduceability, low cost and reduced risk of process failure. A focusing Ge(115) monochromator made from 24 wafer stacks was built for the high-resolution neutron powder diffractometer at the High Flux Beam Reactor at Brookhaven National Laboratory. Besides building "classical" monochromators for elastic neutron scattering experiments, individual wafers with a given peak reflectivity can be tilted with respect to each other to increase the reflected wavelength band Δλ/λ. Such "fanned" arrays present a competitive alternative to monochromators using highly-oriented pyrolitic graphite (HOPG).

  17. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  18. Wafer-level micro-optics: trends in manufacturing, testing, and packaging

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Weible, Kenneth J.; Eisner, Martin

    2011-10-01

    Micro-optics is an indispensable key enabling technology (KET) for many applications today. The important role of micro-optical components is based on three different motivations: miniaturization, high functionality and packaging aspects. It is obvious that miniaturized systems require micro-optics for light focusing, light shaping and imaging. More important for industrial applications is the high functionality of micro-optics that allows combining these different functions in one element. In DUV Lithography Steppers and Scanners an extremely precise beam shaping of the Excimer laser profile is required. High-precision diffractive optical elements are well suited for this task. For Wafer-Level Cameras (WLC) and fiber optical systems the packaging aspects are more important. Wafer-Level Micro-Optics technology allows manufacturing and packaging some thousands of sub-components in parallel. We report on the state of the art in wafer-based manufacturing, testing and packaging.

  19. Metallic nanowires by full wafer stencil lithography.

    PubMed

    Vazquez-Mena, O; Villanueva, G; Savu, V; Sidler, K; van den Boogaart, M A F; Brugger, J

    2008-11-01

    Aluminum and gold nanowires were fabricated using 100 mm stencil wafers containing nanoslits fabricated with a focused ion beam. The stencils were aligned and the nanowires deposited on a substrate with predefined electrical pads. The morphology and resistivity of the wires were studied. Nanowires down to 70 nm wide and 5 mum long have been achieved showing a resistivity of 10 microOmegacm for Al and 5 microOmegacm for Au and maximum current density of approximately 10(8) A/cm(2). This proves the capability of stencil lithography for the fabrication of metallic nanowires on a full wafer scale. PMID:18817451

  20. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  1. VLSI design of a programmable DCT engine for digital cameras

    NASA Astrophysics Data System (ADS)

    Zhao, Debin; Tai, M. L.; Ho, W. K.; Chan, Yiu K.

    1999-03-01

    In still image compression, the JPEG lossy still image compression standard for continuous tone image is often used. JPEG compression efficiency is achieved by decorrelating an image using Discrete Cosine Transform (DCT). Resulting quantized DCT coefficients are then entropy coded for higher compression efficiency. In the quest for higher compression efficiency, wavelet is an attractive alternative at the cost of higher computational complexity. It is proposed in here that DCT followed by Embedded Zerotree Coding (EZC) of DCT coefficients can be competitive to wavelet compression scheme. The basis of competitiveness is base don achievable visual quality at medium bit rate relevant to digital camera applications. As the computational complexity of proposed compression scheme using DCT followed by EZC is still dominated by DCT operations, it is also proposed in here that a very efficient DCT algorithm should be used that has a good computational complexity as well as good inherent parallelism. Finally, a VLSI design is proposed in here that harnesses the inherent parallelism in the efficient DCT algorithm for digital camera applications.

  2. VLSI array processor R&D status report

    NASA Astrophysics Data System (ADS)

    Greenwood, E.

    1982-01-01

    Detail design of the Arithmetic Processor Unit (APU) chip has been completed. All cell types (100) have been run through the design rule check (DRC) programs, corrected and verified. DRC runs on the entire chip have been run and all corrections have been made. Fifteen out of eighteen of the chip DRC corrections have been verified. The metal, polysilicon and information data layers of the APU layout is shown. The attached drawings, titled 'VLSI Array Processor Arithmetic Processor Unit Chip Plan' is a detail drawing of the APU Chip Plan. The functional level simulator of the APU has been built and verified using a set of APU diagnostic code. A gate level logic simulation of the APU has been built. The APU breadboard modules have been fabricated and check out has been initiated. The Array Processor Demonstration System (APDS) modules are in the wire-wrap process. The APDS and APU microcode assembler have been built and checked out. The linker and loader for the APDS have also been built.

  3. A VLSI decomposition of the deBruijn graph

    NASA Technical Reports Server (NTRS)

    Collins, O.; Dolinar, S.; Mceliece, R.; Pollara, F.

    1990-01-01

    A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

  4. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    PubMed

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system. PMID:17385639

  5. Thermal Behavior of Large-Diameter Silicon Wafers during High-Temperature Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Yokoyama, Ichiro; Kang, Kitaek; Takahashi, Nobuaki

    2002-07-01

    Thermal behavior of 200-mm- and 300-mm-diameter Si (100) wafers during high-temperature rapid thermal processing (RTP) in a single wafer furnace (SWF) is investigated as a function of temperature, pressure, process time, wafer handling method and speed. Significant elastic wafer shape deformation was observed during wafer temperature ramp-up. Slip generation was frequently observed in wafers processed above 1050°C. Size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in reducing defect generation during RTP at the given process conditions. Highly reproducible, slip-free RTP results were achieved in 200-mm- and 300-mm-diameter Si (100) wafers processed at 1100°C by optimizing the wafer handling method and speed.

  6. Effective Memetic Algorithms for VLSI design = Genetic Algorithms + local search + multi-level clustering.

    PubMed

    Areibi, Shawki; Yang, Zhen

    2004-01-01

    Combining global and local search is a strategy used by many successful hybrid optimization approaches. Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. This paper provides a forum for identifying and exploring the key issues that affect the design and application of Memetic Algorithms. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit layout in the form of circuit partitioning and placement. Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35% for the VLSI circuit partitioning problem and 54% for the VLSI standard cell placement problem. PMID:15355604

  7. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    NASA Technical Reports Server (NTRS)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  8. Performance optimisation of reconfigurable optical add-drop multiplexers employing Opto-VLSI processors

    NASA Astrophysics Data System (ADS)

    Shen, Mingya; Xiao, Feng; Alameh, Kamal

    2009-08-01

    In this paper, we propose and experimentally demonstrate the principle of a novel reconfigurable optical add-drop multiplexer (ROADM) structure employing an Opto-VLSI processor. The ROADM structure integrates two arrayed waveguide gratings for wavelength division multiplexing and demultiplexing, a 4-f imaging system comprising a fiber array, an imaging lens array and a reflective Opto-VLSI processor. The Opto-VLSI processor is driven by phase holograms to switch the various wavelength channels between the fiber ports to achieve "through" or "drop" operations. Phase hologram optimization is investigated, for maximising the number of wavelength channels while keeping adequate insertion loss and crosstalk levels. Experimental results are shown, which demonstrate the principle of the ROADM with crosstalk of less than -30dB and insertion loss of less than 6dB for the drop and through operation modes.

  9. Methanol Steam Reformer on a Silicon Wafer

    SciTech Connect

    Park, H; Malen, J; Piggott, T; Morse, J; Sopchak, D; Greif, R; Grigoropoulos, C; Havstad, M; Upadhye, R

    2004-04-15

    A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Comparison of computed and measured conversion efficiencies are shown to be favorable. Concepts for insulating the reactor while maintaining small overall size and starting operation from ambient temperature are analyzed.

  10. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  11. A procedural method for the efficient implementation of full-custom VLSI designs

    NASA Technical Reports Server (NTRS)

    Belk, P.; Hickey, N.

    1987-01-01

    An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system.

  12. A parallel VLSI architecture for a digital filter using a number theoretic transform

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1983-01-01

    The advantages of a very large scalee integration (VLSI) architecture for implementing a digital filter using fermat number transforms (FNT) are the following: It requires no multiplication. Only additions and bit rotations are needed. It alleviates the usual dynamic range limitation for long sequence FNT's. It utilizes the FNT and inverse FNT circuits 100% of the time. The lengths of the input data and filter sequences can be arbitraty and different. It is regular, simple, and expandable, and as a consequence suitable for VLSI implementation.

  13. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

    NASA Technical Reports Server (NTRS)

    Shao, Howard M.; Reed, Irving S.

    1988-01-01

    A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

  14. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Deutsch, L. J.; Reed, I. S.

    1987-01-01

    A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

  15. A fast lightstripe rangefinding system with smart VLSI sensor

    NASA Technical Reports Server (NTRS)

    Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

    1989-01-01

    The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

  16. Thin-Film Devices Fabricated With Benzocyclobutene Adhesive Wafer Bonding

    NASA Astrophysics Data System (ADS)

    Christiaens, Ilse; Roelkens, Günther; de Mesel, Kurt; van Thourhout, Dries; Baets, Roel

    2005-02-01

    In this paper, we present and elaborate on die to wafer bonding technology with benzocyclobutene (BCB). This technology allows to fabricate a variety of reliable waferbonded components in a fairly simple way using only standard cleanroom equipment. We demonstrate the fabrication of passive devices such as microring resonators, as well as active components such as lasers and LEDs. We show good performance of these devices by presenting measurements of their characteristics. Furthermore, these devices were subjected to damp-heat testing, demonstrating the good quality of the BCB-bonding procedure. Finally,due to the low thermal conductivity of BCB, thermal management needs some attention. We present an analysis of the thermal problem and suggest a possible solution.

  17. High density circuit technology, part 3

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations.

  18. First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

    NASA Technical Reports Server (NTRS)

    Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

    2008-01-01

    Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

  19. Wafer sub-layer impact in OPC/ORC models for advanced node implant layers

    NASA Astrophysics Data System (ADS)

    Le-Denmat, Jean-Christophe; Michel, Jean-Christophe; Sungauer, Elodie; Yesilada, Emek; Robert, Frederic; Lan, Song; Feng, Mu; Wang, Lei; Depre, Laurent; Kapasi, Sanjay

    2014-03-01

    From 28 nm technology node and below optical proximity correction (OPC) needs to take into account light scattering effects from prior layers when bottom anti-reflective coating (BARC) is not used, which is typical for ionic implantation layers. These effects are complex, especially when multiple sub layers have to be considered: for instance active and poly structures need to be accounted for. A new model form has been developed to address this wafer topography during model calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification (using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction and verification. This paper discusses an exploration of this new model results using extended wafer measurements (including SEM). Current results show good accuracy on various representative structures.

  20. Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer

    SciTech Connect

    Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

    1999-09-07

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

  1. Low cost camera modules using integration of wafer-scale optics and wafer-level packaging of image sensors

    NASA Astrophysics Data System (ADS)

    Han, Hongtao; Main, Keith

    2009-11-01

    Using wafer scale optics, wafer scale integration, and wafer level packaging of image sensor, we developed small form factor (3.3mmx3.3mmx2.5mm), low manufacturing cost, Pb-free solder reflow compatible digital camera modules which are suitable for many applications including mobile electronic devices, automotives, security, and medical applications.

  2. Progress on 300-mm wafer lithography equipment and processes

    NASA Astrophysics Data System (ADS)

    Mautz, Karl E.; Maltabes, John G.

    2001-09-01

    SEMICONDUCTOR300 was the first pilot-production facility for 300mm wafers in the world. The company, a joint venture between Motorola, Inc. and Infineon Technologies started in early 1998 to test and compare process, metrology and probe equipment, develop robust processes, and manufacture products using a 300mm wafer tool set. The lithography tools included I-line steppers, an I-line scanner, a DUV stepper, and DUV scanners. All of these exposure tools were running in-line with various photoresist coat and develop tracks. The lithography tools were used to build both 64M and 256M DRAM devices and aggressive test vehicles. The process capability of the initial 0.25 micrometers reference process was done and compared to the 200mm data set of the sister factory. Automation issues for lithography tools were addressed and the cost metrics were calculated. SC300 demonstrated that a manufacturable 300mm lithography tool set and process for various ground rule devices was possible with the required performance in image transfer, CD control, and overlay. Further testing on 0.18micrometers and 0.15micrometers ground rule features indicated a sufficient process window for potential manufacturing. Additionally, it was demonstrated that non-concentric subfield stepping was feasible.

  3. A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

    NASA Technical Reports Server (NTRS)

    Fang, W.

    1994-01-01

    For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

  4. A comparison of heavy ion sources used in cosmic ray simulation studies of VLSI circuits

    NASA Astrophysics Data System (ADS)

    Stephen, J. H.; Sanderson, T. K.; Mapper, D.; Farren, J.; Harboe-Sorensen, R.; Adams, L.

    1984-12-01

    A comparison has been made between the heavy ions from the ALICE cyclotron and Californium-252. The results of SEU cross-section measurements support the use of the CASE system (Californium-252 Assessment of Single-event Effects) to simulate cosmic ray effects in VLSI circuits.

  5. A VLSI implementation of a correlator/digital-filter based on distributed arithmetic

    NASA Technical Reports Server (NTRS)

    Zohar, Shalhav

    1989-01-01

    The design of a VLSI chip which applies the ideas of distributed arithmetic to a nonrecursive digital filter is described. The main features of this design are very high precision and a high degree of flexibility, which allows one chip to implement a large number of quite different digital filters and correlators.

  6. VLSI chip-set for data compression using the Rice algorithm

    NASA Technical Reports Server (NTRS)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  7. MIL-STD-1553 VLSI components supports a variety of multiplex applications

    NASA Astrophysics Data System (ADS)

    Friedman, Steven N.

    The performance as well as the physical and electrical characteristics of a series of new VLSI components are described. These devices are capable of supporting MIL-STD-1553 and a variety of computer/microprocessor based subsystems. VSLI features such as size, packaging options, radiation hardness, and power and reliability considerations are discussed.

  8. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.; St. Martin, Edward; Arora, Michelle; de la Garza, Linda

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  9. Innovative optical alignment technique for CMP wafers

    NASA Astrophysics Data System (ADS)

    Sugaya, Ayako; Kanaya, Yuho; Nakajima, Shinichi; Nagayama, Tadashi; Shiraishi, Naomasa

    2002-07-01

    Detecting position of the wafers such as after CMP process is critical theme of current and forthcoming IC manufacturing. The alignment system must be with high accuracy for any process. To satisfy such requirements, we have studied and analyzed factors that have made alignment difficult. From the result of the studies, we have developed new optical alignment techniques which improve the accuracy of FIA (alignment sensor of Nikon's NSR series) and examined them. The approaches are optimizing the focus position, developing an advanced algorithm for position detection, and selecting a suitable mark design. For experiment, we have developed the special wafers that make it possible to evaluate the influence of CMP processes. The experimental results show that the overlay errors decrease dramatically with the new alignment techniques. FIA with these new techniques will be much accurate and suitable alignment sensor for CMP and other processes of future generation ULSI production.

  10. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  11. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  12. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  13. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

  14. Wafer weak point detection based on aerial images or WLCD

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Philipp, Peter; Litt, Lloyd C.; Ackmann, Paul; Crell, Christian; Chen, Norman

    2015-10-01

    Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

  15. High density circuit technology, part 1

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

  16. Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

    NASA Astrophysics Data System (ADS)

    Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

    2004-08-01

    The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

  17. Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process

    NASA Astrophysics Data System (ADS)

    Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

    2013-09-01

    Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements™) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

  18. Wafer surface pre-treatment study for micro bubble free of lithography process

    NASA Astrophysics Data System (ADS)

    Yang, Xiaosong; Zhu, XiaoZheng; Cai, Spencer

    2014-04-01

    Photo resist micro bubble and void defect is reported as a typical and very puzzle defect type in photo lithography process, it becomes more and more significantly and severely with the IC technology drive towards 2 node. Introduced in this paper, we have studied the mechanism of photo resist micro bubble at different in-coming wafer surface condition and tested a series of pre treatment optimization method to resolve photo resist micro bubble defect on different wafer substrate, including in the standard flat and smooth wafer surface and also in special wafer surface with high density line/space micro-structure substrate as is in logic process FinFET tri-gate structure and Nor type flash memory cell area Floating Gate/ONO/Control Gate structure. As is discovered in our paper, in general flat and smooth wafer surface, the photo resist micro bubble is formed during resist RRC coating process (resist reduction coating) and will easy lead to Si concave defect after etch; while in the high density line/space micro-structure substrate as FinFET tri-gate, the photo resist void defect is always formed after lithography pattern formation and will final cause the gate line broken after the etching process or localized over dose effect at Ion IMP layers. The 2nd type of photo resist micro bubble is much more complicated and hard to be eliminated. We try to figure out the interfacial mechanism between different type of photo resist (ArF, KrF and I-line) and pre-wet solvent by systematic methods and DOE splits. And finally, we succeeded to dig out the best solution to eliminate the micro bubble defect in different wafer surface condition and implement in the photolithography process.

  19. Nanotribology of nanooxide materials in ionic liquids on silicon wafers

    NASA Astrophysics Data System (ADS)

    Hamidunsani, Ahmad Termizi; Radiman, Shahidan; Hassan, Masjuki Haji; Rahman, Irman Abdul

    2015-09-01

    Nanotribological properties have a significant impact on daily life. Ionic liquids (ILs) are becoming new favourable lubricants currently in researches. Addition of nanooxide materials in lubricants provide improvements to new technology. In this study, we determine nanotribological properties of BMIM+BF4- IL addition of different amount of ZnO nanomaterial on single crystals silicon wafer (Si110). The viscosity changes of IL samples against temperature increase were determined by rheological method. Nanotribological properties were determined by changes in friction coefficient and wear rate on silicon substrate surfaces using a reciprocating friction and wear monitor in 1 hour duration time. Aluminium cylinders acted as pins used to rub Si (110) substrate sample surfaces. Thus, on range between 0 mg to 3.5 mg of ZnO nanooxide material dispersed in 10ml BMIM+BF4- showed a good friction coefficient, wear and surface roughness reduction.

  20. Electrooptic shutter devices utilizing PLZT ceramic wafers

    SciTech Connect

    Thornton, A.L.

    1981-01-01

    Optical transparency was achieved in lead zirconate-titanate ferroelectric ceramics by substituting moderate amounts of the element lanthanum (8 to 12%) for lead. These compositions exhibit the quadratic (Kerr) electrooptic effect. The excellent optical qualities of these materials (designated PLZT) has permitted the practical utilization of their electrooptic properties in a number of devices. All of these devices utilize the classic Kerr cell arrangement. A PLZT wafer with optical axis oriented at 45/sup 0/ with respect to the axes of polarization is sandwiched between crossed polarizers. Application of an electric field via an interdigital array of electrodes on opposing wafer surfaces forces the PLZT material into a tetragonal state with the resulting induced birefringence proportional to the square of the applied electric field. Hence, the electrooptic wafer provides a retardation of light so that a component is passed by the second crossed polarizer to achieve an ON or open state. Maximum transmission is achieved when the retardation is half-wave. Shutter devices developed by Sandia and those in continuing development are described with respect to operational characteristics and physical configuration. The devices range in size from very small apertures of 50 ..mu..m x 2 mm with center-to-center repeat dimensions of 125 ..mu..m - to very large - apertures of 15.2 cm in single pieces and mosaics with apertures of 15.2 cm x 20.3 cm. Major efforts have centered on shutter development for the protection of aircrew from eye-damaging weapon effects. Other devices are also described which: provide eye protection for welders, protect vidicon tubes, function as page composers for holographic memories serve as large aperture photographic shutters, provide stereoscopic three-dimensional TV displays, and serve as data links in a fiber-optic transmission path.

  1. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  2. Photoluminescence method of testing double heterostructure wafers

    SciTech Connect

    Besomi, P.R.; Wilt, D.P.

    1984-04-10

    Under photoluminescence (PL) excitation, the lateral spreading of photo-excited carriers can suppress the photoluminescence signal from double heterostructure (DH) wafers containing a p-n junction. In any DH with a p-n junction in the active layer, PL is suppressed if the power of the excitation source does not exceed a threshold value. This effect can be advantageously used for a nondestructive optical determination of the top cladding layer sheet conductance as well as p-n junction misplacement, important parameters for injection lasers and LEDs.

  3. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  4. Slip-Free Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-06-01

    Defect generation phenomena in Si wafers during atmospheric pressure rapid thermal processing (RTP) in a single wafer furnace (SWF) are investigated as a function of temperature, process time, wafer handling method and speed. The size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in controlling defect generation during RTP under given process conditions. Highly reproducible slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100°C for 60 s (up to 5 times) by optimizing the wafer handling method and speed.

  5. Resonance ultrasonic vibrations for crack detection in photovoltaic silicon wafers

    NASA Astrophysics Data System (ADS)

    Dallas, W.; Polupan, O.; Ostapenko, S.

    2007-03-01

    The resonance ultrasonic vibrations (RUV) technique is adapted for non-destructive crack detection in full-size silicon wafers for solar cells. The RUV methodology relies on deviation of the frequency response curve of a wafer, ultrasonically stimulated via vacuum coupled piezoelectric transducer, with a periphery crack versus regular non-cracked wafers as detected by a periphery mounted acoustic probe. Crack detection is illustrated on a set of cast wafers. We performed vibration mode identification on square-shaped production-grade Si wafers and confirmed by finite element analyses. The modelling was accomplished for the different modes of the resonance vibrations of a wafer with a periphery crack to assess the sensitivity of the RUV method relative to crack length and crack location.

  6. TiW particle control for VLSI manufacturing

    NASA Astrophysics Data System (ADS)

    Gn, Fang H.; Yeap, Chuin B.; Li, He M.; Liu, E. Z.; Chew, Heng L.

    1995-09-01

    TiW has been used extensively as the barrier metal in submicron metallization. However, TiW has also drawn much attention as the source of defect generation contributing to functional yield loss. Usually, the defects are in the form of flakes which can be detected by either using light scattering metrology tools or naked eye in severe situations. In this paper various manufacturing techniques will be presented which reduce defect during the TiW sputtering process. Both arc-sprayed process kit (chamber shield and clamping ring) and TiW paste at fixed intervals have been proven to be effective in reducing TiW particles. Implementation of these two techniques is relatively simple and has been used very successfully in Chartered's 6 inch wafer fab. Another study shows that by reducing the process kit thermal cycling through continuously having the bake-out lamp turned on is effective for particle control. Effect of the grain size of TiW sputter target and the application of Particle Gettering (PG) foil will also be discussed in detail as other means of particle reduction.

  7. In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system

    NASA Astrophysics Data System (ADS)

    Yang, Yi-Bin; Liu, Ming-Gang; Chen, Wei-Jie; Han, Xiao-Biao; Chen, Jie; Lin, Xiu-Qi; Lin, Jia-Li; Luo, Hui; Liao, Qiang; Zang, Wen-Jie; Chen, Yin-Song; Qiu, Yun-Ling; Wu, Zhi-Sheng; Liu, Yang; Zhang, Bai-Jun

    2015-09-01

    In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2″ Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), the International Science and Technology Collaboration Program of Guangdong Province, China (Grant No. 2013B051000041), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), the National High Technology Research and Development Program of China (Grant No. 2014AA032606), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics, China (Grant No. IOSKL2014KF17).

  8. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  9. Desirable wafer edge flatness for CD control in photolithography

    NASA Astrophysics Data System (ADS)

    Fujisawa, Tadahito; Inoue, Soichi; Hagiwara, Tsuneyuki; Kennichi, Kodama; Kobayashi, Makoto; Okumura, Katsuya

    2003-06-01

    Desirable wafer edge flatness was investigated to obtain optimum free-standing wafer edge shape for photolithography. In order to obtain the criteria of free-standing edge shape, we clarified the desirable post-chuck flatness at edge sites in advance. We investigated a desirable free-standing wafer edge, taking into consideration both the wafer and wafer holder shape. Firstly, to obtain a desirable post-chuck wafer edge shape, the vicinity of wafer edge after chucking was modeled, and SFQR was simulated. Secondly, a shape in the vicinity of free-standing edge shape was modeled, and the edge flatness after chucking was simulated. And finally, the simulated flatness was compared with the desirable post-chucked wafer edge shape, and we could obtain desirable free-standing wafer edge shape. Individual measurement of the free-standing back-side and front-side surfaces as well as the thickness of the edge position was found to be necessary for accurate estimation of the post-chuck edge shape.

  10. Dominant factors of the laser gettering of silicon wafers

    SciTech Connect

    Bokhan, Yu. I. E-mail: yuibokhan@gmail.com; Kamenkov, V. S.; Tolochko, N. K.

    2015-02-15

    The laser gettering of silicon wafers is experimentally investigated. The typical gettering parameters are considered. The surfaces of laser-treated silicon wafers are investigated by microscopy. When studying the effect of laser radiation on silicon wafers during gettering, a group of factors determining the conditions of interaction between the laser beam and silicon-wafer surface and affecting the final result of treatment are selected. The main factors determining the gettering efficiency are revealed. Limitations on the desired value of the getter-layer capacity on surfaces with insufficiently high cleanness (for example, ground or matte) are established.

  11. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  12. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  13. Laser soft marking on silicon wafer

    NASA Astrophysics Data System (ADS)

    Khoong, L. E.; Lam, Y. C.; Zheng, H. Y.; Chen, X.

    2010-03-01

    A laser soft marking technique is developed for laser markings on a silicon wafer. Due to negligible surface modification, the laser soft wafer markings are invisible by naked eyes under room condition and are undetectable using sophisticated instruments. However, these laser markings are found to be visible to naked eyes through a differential condensation of water droplets on the laser-marked and unmarked silicon surfaces. To understand this phenomenon, a model is established to study the condensation of water droplets on laser-marked and unmarked silicon surfaces. Experimental observations and simulation results indicate that the laser soft marking could have modified the silicon surface with a thin polycrystalline silicon layer which has a much lower conductivity than the crystalline silicon. In addition, this thin layer exhibits a thermal conductivity which is approximately two orders of magnitude lower than that of its equivalent bulk material. As a result, heat transfer on the laser-marked silicon surface is much lower than the crystalline silicon and thus makes these laser soft markings easily visible visually under condensation.

  14. Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

    NASA Astrophysics Data System (ADS)

    Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

    2011-09-01

    Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

  15. VLSI architectures for computing multiplications and inverses in GF(2m)

    NASA Technical Reports Server (NTRS)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  16. WARP: Weight Associative Rule Processor. A dedicated VLSI fuzzy logic megacell

    NASA Technical Reports Server (NTRS)

    Pagni, A.; Poluzzi, R.; Rizzotto, G. G.

    1992-01-01

    During the last five years Fuzzy Logic has gained enormous popularity in the academic and industrial worlds. The success of this new methodology has led the microelectronics industry to create a new class of machines, called Fuzzy Machines, to overcome the limitations of traditional computing systems when utilized as Fuzzy Systems. This paper gives an overview of the methods by which Fuzzy Logic data structures are represented in the machines (each with its own advantages and inefficiencies). Next, the paper introduces WARP (Weight Associative Rule Processor) which is a dedicated VLSI megacell allowing the realization of a fuzzy controller suitable for a wide range of applications. WARP represents an innovative approach to VLSI Fuzzy controllers by utilizing different types of data structures for characterizing the membership functions during the various stages of the Fuzzy processing. WARP dedicated architecture has been designed in order to achieve high performance by exploiting the computational advantages offered by the different data representations.

  17. Learning and optimization with cascaded VLSI neural network building-block chips

    NASA Technical Reports Server (NTRS)

    Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

    1992-01-01

    To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

  18. A new VLSI architecture for a single-chip-type Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.

    1989-01-01

    A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.

  19. A cost-effective methodology for the design of massively-parallel VLSI functional units

    NASA Technical Reports Server (NTRS)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  20. Direct To Digital Holography For High Aspect Ratio Inspection of Semiconductor Wafers

    NASA Astrophysics Data System (ADS)

    Thomas, C. E. (Tommy); Hunt, Martin A.; Bahm, Tracy M.; Baylor, Larry R.; Bingham, Philip R.; Chidley, Matthew D.; Dai, Xiaolong; Delahanty, Robert J.; El-Khashab, Ayman; Gilbert, Judd M.; Goddard, James S.; Hanson, Gregory R.; Hickson, Joel D.; Hylton, Kathy W.; John, George C.; Jones, Michael L.; Mayo, Michael W.; Marek, Christopher; Price, John H.; Rasmussen, David A.; Schaefer, Louis J.; Schulze, Mark A.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin, Kenneth W.; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Owen, Robert W.

    2003-09-01

    Direct to Digital Holography (DDH) has been developed as a semiconductor wafer inspection tool and in particular as a tool for seeing defects in high aspect ratio (HAR) structures on semiconductor wafers and also for seeing partial-height defects. While the tool works very well for general wafer inspection, it has unusual capabilities for high aspect ratio inspection (HARI) and for detecting thin residual film defects (partial height defects). Inspection of HAR structures is rated as one of the highest unmet priorities of the member companies of International SEMATECH, and finding residual thin film defects (in some cases called "stringers") is also a very difficult challenge. The capabilities that make DDH unusually sensitive include: 1) the capture of the whole waveboth the classical amplitude captured by traditional optical systems, and the phase of the wave, with phase potentially measured to 1/1000'th of a wavelength or 2 to 3 Angstroms for a deep ultra-violet (DUV) laser; 2) heterodyne detectionthis allows it to capture very low signal levels; and 3) a head-on geometry using a collimated laser beam that allows best penetration of HAR structures. The basic features and methods of this patented technology are presented, along with simple calculations of signal strength and expected noise levels for various circumstances. Full-wave numerical calculations of electromagnetic field penetration into HAR contacts and experimental results from various wafer types and structures are also presented.

  1. Magnetometory of AlGaN/GaN heterostructure wafers

    NASA Astrophysics Data System (ADS)

    Tsubaki, K.; Maeda, N.; Saitoh, T.; Kobayashi, N.

    2005-06-01

    AlGaN/GaN heterostructure wafers are becoming a key technology for next generation cellar-phone telecommunication system because of their potential for high-performance microwave applications. Therefore, the electronic properties of a 2DEG in AlGaN/GaN heterostructures have recently been discussed. In this paper, we performed the extraordinary Hall effect measurement and the SQUID magnetometory of AlGaN/GaN heterostructure wafer at low temperature. The AlGaN/GaN heterostructures were grown by low-pressure metal-organic chemical vapour phase epitaxy on (0001) SiC substrate using AlN buffers. The electron mobility and electron concentration at 4.2 K are 9,540cm2/V s and 6.6 × 1012cm-2, respectively. In the extraordinary Hall effect measurement of AlGaN/GaN heterostructures, the hysteresis of Hall resistance appeared below 4.5 K and disappeared above 4.5 K. On the other hand, the hysteresis of magnetometric data obtained by SQUID magnetometory appears near zero magnetic field when the temperature is lower than 4.5 K. At the temperature larger than 4.5 K, the hysteresis of magnetometric data disappears. And the slopes of magnetometric data with respect to magnetic field become lower as obeying Currie-Weiss law and the Curie temperature TC is 4.5 K. Agreement of TC measured by the extraordinary Hall effect and the SQUID magnetometory implies the ferromagnetism at the AlGaN/GaN heterojunction. However, the conformation of the ferromagnetism of AlGaN/GaN heterostructure is still difficult and the detailed physical mechanism is still unclear.

  2. Parallel VLSI architecture for a digital filter of arbitrary length using fermat number transforms

    SciTech Connect

    Truong, T.K.; Reed, I.S.; Yeh, C.S.; Shao, H.M.

    1982-01-01

    In this paper a parallel and pipeline architecture is developed to compute the linear convolution of two sequences of arbitrary lengths using the fermat number transform (FNT). Such a new architecture is developed to realize the overlap-save method using one FNT and several inverse FNTS of 128 points. The generalized overlap-save method alleviates the usual dynamic range limitation in FNTS of long transform lengths. Its architecture is regular, simple, expandable, and naturally suitable for VLSI implementation. 6 references.

  3. A VLSI design for universal noiseless coding. [for spacecraft imaging equipment

    NASA Technical Reports Server (NTRS)

    Lee, Jun-Ji; Fang, Wai-Chi; Rice, Robert F.

    1988-01-01

    The practical, noiseless and efficient data-compression technique presented involves a conceptual VLSI design which is capable of meeting real-time processing rates and meets low-power, low-weight, and small-volume requirements. This form of data compression is applicable to image data compression aboard future low-budget spaceflight missions, for such instruments as visual-IR mapping spectrometers and high-resolution imaging spectrometers.

  4. A Systolic VLSI Design of a Pipeline Reed-solomon Decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

    1984-01-01

    A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

  5. A VLSI single chip (255,223) Reed-Solomon encoder with interleaver

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Deutsch, L. J.; Truong, T. K.; Reed, I. S.

    1987-01-01

    A single-chip implementation of a Reed-Solomon encoder with interleaving capability is described. The code used was adapted by the CCSDS (Consulative Committee on Space Data Systems). It forms the outer code of the NASA standard concatenated coding system which includes a convolutional inner code of rate 1/2 and constraint length 7. The architecture, leading to this single VLSI chip design, makes use of a bit-serial finite field multiplication algorithm due to E.R. Berlekamp.

  6. Application of a VLSI vector quantization processor to real-time speech coding

    NASA Technical Reports Server (NTRS)

    Davidson, G.; Gersho, A.

    1986-01-01

    Attention is given to a working vector quantization processor for speech coding that is based on a first-generation VLSI chip which efficiently performs the pattern-matching operation needed for the codebook search process (CPS). Using this chip, the CPS architecture has been successfully incorporated into a compact, single-board Vector PCM implementation operating at 7-18 kbits/sec. A real time Adaptive Vector Predictive Coder system using the CPS has also been implemented.

  7. Product assurance technology efforts: Technical accomplishments

    NASA Technical Reports Server (NTRS)

    1985-01-01

    Product assurance technology topics addressed include: wafer acceptance procedures, test chips, test structures, test chip methodology, fault models, and the Combined Release and Radiation Effects Satellite test chip.

  8. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity

    PubMed Central

    Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices. PMID:21031027

  9. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.

    PubMed

    Bill, Johannes; Schuch, Klaus; Brderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices. PMID:21031027

  10. Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

    NASA Astrophysics Data System (ADS)

    Altmeyer, Ronald C.

    2002-09-01

    This thesis documents the research, circuit design, and simulation testing of a VLSI (Very Large Scale Integration) ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1). Specifically, the circuit will convert the In-Phase and Quadrature terms into their corresponding phase angle. The design specifications were to implement the design in CMOS (Complementary Metal Oxide Semiconductors) technology with a minimum transistor count and ability to operate at a clock frequency of 700 MHz. Research on the arctangent function was performed to determine mathematical calculation methods and the CORDIC method was chosen to achieve the stated design specifications. MATLAB simulations were used to calculate and verify accuracy and to implement Quine-McClusky logic minimization. T-SPICE netlists were generated and simulations were run to determine transistor and circuit electrical operation and timing. Finally, overall circuit logic functionality of all possible input combinations was completed using a VHDL (VHSIC(Very High Speed Integrated Circuit) Hardware Description Language) simulation program.

  11. Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint

    SciTech Connect

    Rupnowski, P.; Sopori, B.

    2008-05-01

    This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

  12. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  13. Low-temperature vacuum hermetic wafer-level package for uncooled microbolometer FPAs

    NASA Astrophysics Data System (ADS)

    Garcia-Blanco, S.; Topart, P.; Desroches, Y.; Caron, J. S.; Williamson, F.; Alain, C.; Jerominek, H.

    2008-02-01

    Micro-Electro-Mechanical Systems (MEMS) packaging constitutes most of the cost of such devices. For the integration of MEMS with microelectronics systems to be widespread, a drastic reduction of the overall price is required. Wafer-level-packaging allows a fundamental reduction of the packaging cost by combining wafer-level microfabrication techniques with wafer-to-wafer bonding. To achieve the vacuum atmosphere required for the operation of many MEMS devices, bonding techniques such as anodic bonding, eutectic bonding, fusion bonding and gold to gold thermocompression bonding have been utilized, which require relatively high temperatures (>300°C) being in some cases incompatible with MEMS and microelectronics devices. Furthermore, to maintain vacuum integrity over long periods of time, getters requiring high activation temperatures are usually employed. INO has developed a hybrid wafer-level micropackaging technology based on low temperature fluxless solder joints in which the micropackaged MEMS device is not exposed to a temperature over 150°C. The micropackages have been designed for 160×120 microbolometer FPAs. Ceramic spacers are patterned by standard microfabrication techniques followed by laser micromachining. AR-coated floatzone silicon IR windows are patterned with a solderable layer. Both, microbolometer dies and windows are soldered to the ceramic tray by a combination of solder paste stencil printing, reflow and fluxless flip-chip bonding. A low temperature getter is also introduced to control outgassing of moisture and CO II during the lifetime of the package. Vacuum sealing is carried out by locally heating the vacuum port after bake out of the micropackages. In this paper, the vacuum integrity of micropackaged FPA dies will be reported. Base pressures as low as 5 mTorr and equivalent flow rates at room temperature of 4×10 -14 Torr.l/s without getter incorporation have been demonstrated using integrated micro-pressure gauges. A study of the influence of different packaging parameters on the lifetime of micropackages will be presented.

  14. Backside EBR process performance with various wafer properties

    NASA Astrophysics Data System (ADS)

    Goto, Tomohiro; Shigemori, Kazuhito; Vangheluwe, Rik; Erich, Daub; Sanada, Masakazu

    2009-03-01

    In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled film edge position and good uniformity around the wafer circumference is needed. We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse system has a good controllability of film edge position and good uniformity around the wafer circumference. The results indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to provide a suitable film stacking architecture for immersion lithography mass production process.

  15. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  16. Step and flash imprint process integration techniques for photonic crystal patterning: template replication through wafer patterning irrespective of tone

    NASA Astrophysics Data System (ADS)

    Miller, Mike; Brooks, Cindy; Lentz, David; Doyle, Gary; Resnick, Doug; LaBrake, Dwayne

    2008-02-01

    Photonic crystal structures in for example light emitting diodes (LED) have been demonstrated to improve performance by preferential mode coupling near the surface of the diode.1 Such demonstrations were limited by using direct write e-beam lithography due to long write times, a single tone and only small areas patterned for study. S-FIL technology provides a means to pattern entire wafers in a single imprint step using templates replicated by step and repeat (S&R) imprint2. Large area template replication by S-FIL/R has been described using S&R templates 3. Photonic crystal based LED manufacturers prefer holes in substrates requiring pillar tone templates for S-FIL patterning. Pillar tone templates are not easily derived from the preferred e-beam tone for sub-200 nm template fabrication. Therefore step and repeat and/or whole wafer template replication by the combination of S-FIL and/or S-FIL/R can be used to produce the desired working template tone. These processes further enable the desired tone and wafer die layout for fully patterning wafers to their edge with no missing die or edge fields. The advantages of using S-FIL processes for template and wafer patterning are clear in that there is no tone preference required by the original e-beam generated pattern, which allows the preferred positive tone to be used for e-beam patterning of templates. The present work will describe template replication processes for the fabrication of either pillar or hole tone templates and subsequent wafer pattern processes, through oxide hard mask, producing both pillar and hole tone patterns. In summary process flows exist so that any e-beam written template tone can be used to produce either tone in replicated templates and/or patterned wafers.

  17. Research News: Are VLSI Microcircuits Too Hard to Design?

    ERIC Educational Resources Information Center

    Robinson, Arthur L.

    1980-01-01

    This research news article on microelectronics discusses the scientific challenge the integrated circuit industry will have in the next decade, for designing the complicated microcircuits made possible by advancing miniaturization technology. (HM)

  18. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  19. Study of temperature distributions in wafer exposure process

    NASA Astrophysics Data System (ADS)

    Lin, Zone-Ching; Wu, Wen-Jang

    During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

  20. Development of optical automatic positioning and wafer defect detection system

    NASA Astrophysics Data System (ADS)

    Tien, Chuen-Lin; Lai, Qun-Huang; Lin, Chern-Sheng

    2016-02-01

    The data of a wafer with defects can provide engineers with very important information and clues to improve the yield rate and quality in manufacturing. This paper presents a microscope automatic positioning and wafer detection system with human-machine interface based on image processing and fuzzy inference algorithms. In the proposed system, a XY table is used to move the position of each die on 6 inch or 8 inch wafers. Then, a high-resolution CCD and one set of two-axis optical linear encoder are used to accurately measure the position on the wafer. Finally, the developed human-machine interface is used to display the current position of an actual wafer in order to complete automatic positioning, and a wafer map database can be created. In the process of defect detection, CCD is used for image processing, and during preprocessing, it is required to filter noise, acquire the defect characteristics, define the defective template, and then take the characteristic points of the defective template as the reference input for fuzzy inference. A high-accuracy optical automatic positioning and wafer defect detection system is thus constructed. This study focused on automatic detection of spots, scratches, and bruises, and attempted to reduce the time to detect defective die and improve the accuracy of determining the defects of semiconductor devices.

  1. Direct Simulation Monte Carlo (DSMC) of rarefied gas flow during etching of large diameter (300-mm) wafers

    SciTech Connect

    Economou, D.J.; Bartel, T.J.

    1996-02-01

    As microelectronic devices are scaled down to enhance functionality and speed, wafer size increases to accommodate the larger dice and improve throughput. For example, the wafer diameter is projected to increase from the current 200 to 300 mm by the year 2001. Uniform deposition and etching of thin films over these large diameter wafers is of major concern to the microelectronics industry. Also, flat panel display and solar conversion technologies require uniform processing over large area substrates. Computer simulation can provide valuable insight concerning the physicochemical processes occurring in the reactor and can be used as a guide to new reactor designs that deliver uniform etching or deposition. Strong density gradients of a gas species can be sustained even at very low pressures when the reaction probability of that species is high. Under these conditions, inlet gas arrangements are very important to reaction uniformity.

  2. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    PubMed

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. PMID:24732237

  3. Applications of atomic force microscopy for silicon wafer characterization

    SciTech Connect

    Suhren, M.; Graef, D.; Schmolke, R.; Piontek, H.; Wagner, P.

    1996-12-01

    AFM (Atomic Force Microscopy) is a highly sensitive tool for the analysis of the microroughness of Si wafers and for the investigation of crystal defects. AFM images of atomic steps were used for verification of the vertical AFM calibration on slightly misoriented Si(111) wafers after chemical etching and epitaxial deposition. The roughness analysis of etched, polished and epitaxial Si(100) wafers shows a reduction of the surface roughness by chemomechanical polishing by more than two orders of magnitude compared to an etched surface. The morphology of crystal originated particles on Si(100) appears as smooth surface depression after polishing and sharply defined pit after SCI treatment.

  4. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime τbulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various τbulk conditions. The modeling results show that for the IBC solar cell with high τbulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low τbulk (for instance, < 500 μs) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  5. Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility

    NASA Astrophysics Data System (ADS)

    Weatherwax Scott, Caroline; Tsareff, Christopher R.

    1990-06-01

    One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles played by the process engineering expert and the knowledge engineer are discussed. The features of the systems are shown, particularly the interactive quality of the consultations and the ease of system use.

  6. Direct to Digital Holography for Semiconductor Wafer Defect Detection and Review

    SciTech Connect

    ThomasJr., C. E.; Bahm, Tracy M.; Baylor, Larry R; Bingham, Philip R.; Burns, Steven W.; Chidley, Matthew D; Dai, Xiaolong; Delahanty, Robert J.; Doti, Christopher J.; El-Khashab, Ayman; Fisher, Robert L.; Gilbert, Judd M.; Cui, Hongtao; Goddard Jr, James Samuel; Hanson, Gregory R; Hickson, Joel D.; Hunt, Martin A.; Hylton, Kathy W; John, George C.; Jones, Michael L.; McDonald, Kenneth R.; Mayo, Michael W.; McMackin, Ian; Patek, David; Price, John H.; Rasmussen, David A; Schaefer, Louis J.; Scheidt, Thomas R.; Schulze, Mark A.; Schumaker, Philip D.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin Jr, Kenneth William; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Jones, Paul G.; Owen, Robert W.

    2002-01-01

    A method for recording true holograms (not holographic interferometry) directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional to wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for finding defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep ultra-violet light.

  7. Fast wafer-level detection and control of interconnect reliability

    NASA Astrophysics Data System (ADS)

    Foley, Sean; Molyneaux, James; Mathewson, Alan

    2000-08-01

    Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterize particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure results. The Isothermal test method combine with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.

  8. Fault tolerant VLSI (Very Large-Scale Integration) design using error correcting codes

    NASA Astrophysics Data System (ADS)

    Hartmann, C. R.; Lala, P. K.; Ali, A. M.; Ganguly, S.; Visweswaran, G. S.

    1989-02-01

    Very Large-Scale Integration (VLSI) provides the opportunity to design fault tolerant, self-checking circuits with on-chip, concurrent error correction. This study determines the applicability of a variety of error-detecting, error-correcting codes (EDAC) in high speed digital data processors and buses. In considering both microcircuit faults and bus faults, some of the codes examined are: Berger, repetition, parity, residue, and Modified Reflected Binary codes. The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.

  9. A VLSI architecture for performing finite field arithmetic with reduced table look-up

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.; Reed, I. S.

    1986-01-01

    A new table look-up method for finding the log and antilog of finite field elements has been developed by N. Glover. In his method, the log and antilog of a field element is found by the use of several smaller tables. The method is based on a use of the Chinese Remainder Theorem. The technique often results in a significant reduction in the memory requirements of the problem. A VLSI architecture is developed for a special case of this new algorithm to perform finite field arithmetic including multiplication, division, and the finding of an inverse element in the finite field.

  10. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    SciTech Connect

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  11. Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

    1985-01-01

    The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  12. Efficient VLSI parallel algorithm for Delaunay triangulation on orthogonal tree network in two and three dimensions

    SciTech Connect

    Saena, S.; Bhatt, P.C.P.; Prasad, V.C. )

    1990-03-01

    In this paper, a parallel algorithm for two- and three-dimensional Delaunay triangulation on an orthogonal tree network is described. The worst case time complexity of this algorithm is O(log {sup 2} N) in two dimensions and O(m {sup 1/2} log N) in three dimensions with N input points and m as the number of tetrahedra in tiangulation. The AT {sup 2} VLSI complexity on Thompson's logarithmic delay model is O(N {sup 2} log {sup 6} N) in two dimensions and O(m {sup 2} N log {sup 4} N) in three dimensions.

  13. Efficient data transmission from silicon wafer strip detectors

    SciTech Connect

    Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

    1991-12-31

    An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

  14. 9nm node wafer defect inspection using visible light

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

    2014-04-01

    Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

  15. Stress rate and proof-testing of silicon wafers

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1985-01-01

    Fracture mechanics test methods were applied to evaluate the proof-test characteristics of single-crystal silicon wafers. The results indicate that the strength distribution of silicon wafers is truncated by proof-testing. No subcritical crack growth occurred during proof-loading, as inferred from the lack of a stress-rate effect on strength. Mechanical proof-testing appears to be an effective method for eliminating weak samples before cell processing.

  16. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  17. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  18. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  19. Epitaxial silicon carbide on a 6″ silicon wafer

    NASA Astrophysics Data System (ADS)

    Kukushkin, S. A.; Lukyanov, A. V.; Osipov, A. V.; Feoktistov, N. A.

    2014-01-01

    The results of the growth of silicon-carbide films on silicon wafers with a large diameter of 150 mm (6″) by using a new method of solid-phase epitaxy are presented. A SiC film growing on Si wafers was studied by means of spectral ellipsometry, SEM, X-ray diffraction, and Raman scattering. As follows from the studies, SiC layers are epitaxial over the entire surface of a 150-mm wafer. The wafers have no mechanical stresses, are smooth, and do not have bends. The half-width of the X-ray rocking curve (FWHMω- θ) of the wafers varies in the range from 0.7° to 0.8° across the thickness layer of 80-100 nm. The wafers are suitable as templates for the growth of SiC, AlN, GaN, ZnO, and other wide-gap semiconductors on its surface using standard CVD, HVPE, and MBE methods.

  20. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  1. An introduction GaAs microprocessor architecture for VLSI

    SciTech Connect

    Milutinovic, V.; Fura, D.; Helbig, W.

    1986-03-01

    Gallium arsenide, or GaAs, technology has recently shown rapid increases in maturity. In particular, the advances made in digital chip complexity have been enormous. This progress is especially evident in two types of chips: static rams and gate arrays. In 1983, static rams containing 1K bits were announced. One year later both a 4K-bit and a 16K-bit version were presented. Gate arrays have advanced from a 1000-gate design presented in 1984 to a 2000-gate design announced in 1985. With this enormous progress underway, it is now appropriate to consider the use of this new technology in the implementation of high-performance processors. GaAs technology generates high levels of enthusiasm primarily because of two advantages it enjoys over silicon: higher speed and greater resistance to adverse environmental conditions. GaAs gates switch faster than silicon transistor-transistor logic, or TTL, gates by nearly an order of magnitude. These switching speeds are even faster than those attained by the fastest silicon emitter-coupled logic, or ECL, but at power levels an order of magnitude lower. For this reason, GaAs is seen to have applications in computer design within several computationally intensive areas. In fact, it has been reported that the Cray-3 will contain GaAs parts. GaAs also enjoys greater resistance to radiation and temperature variations than does silicon. GaAs successfully operates in radiation levels of 10 to 100 million rads. Its operating temperature range extends from -200 to 200/sup 0/C. Consequently, GaAs has created great excitement in the military and aerospace markets.

  2. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  3. Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

    NASA Astrophysics Data System (ADS)

    Goto, Tetsuya; Kuroda, Rihito; Akagawa, Naoya; Suwa, Tomoyuki; Teramoto, Akinobu; Li, Xiang; Obara, Toshiki; Kimoto, Daiki; Sugawa, Shigetoshi; Ohmi, Tadahiro; Kamata, Yutaka; Kumagai, Yuki; Shibusawa, Katsuhiko

    2015-04-01

    By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate-source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

  4. Imprinted laminate wafer-level packaging for SAW ID-tags and SAW delay line sensors.

    PubMed

    Kuypers, Jan H; Tanaka, Shuji; Esashi, Masayoshi

    2011-02-01

    We have developed a wafer-level packaging solution for surface acoustic wave devices using imprinted dry film resist (DFR). The packaging process involves the preparation of an imprinted dry film resist that is aligned and laminated to the device wafer and requires one additional lithography step to define the package outline. Two commercial dry film solutions, SU-8 and TMMF, have been evaluated. Compared with traditional ceramic packages, no detectable RF parasitics are introduced by this packaging process. At the same time, the miniature package dimensions allow for wafer-level probing. The packaging process has the great advantage that the cavity formation does not require any sacrificial layer and no liquids, and therefore prevents contamination or stiction of the packaged device. This non-hermetic packaging process is ideal for passive antenna modules using polymer technology for low-cost SAW identification (ID)-tags or lidding in low-temperature cofired ceramic (LTCC) antenna substrates for high-performance wireless sensors. This technique is also applicable to SAW filters and duplexers for module integration in cellular phones using flip-chip mounting and hermetic overcoating. PMID:21342826

  5. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    PubMed

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging. PMID:22966554

  6. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    NASA Astrophysics Data System (ADS)

    Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu (Andy)

    2003-12-01

    The technique of orthogonal frequency division multiplexing (OFDM) is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the fast Fourier transform (FFT) and inverse FFT (IFFT) operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly processing element (PE) based on the coordinate rotation digital computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC[InlineEquation not available: see fulltext.]m 1P4M CMOS technology. The simulations results show that the chip can perform ([InlineEquation not available: see fulltext.]-[InlineEquation not available: see fulltext.])-point FFT/IFFT operations up to[InlineEquation not available: see fulltext.] operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL ([InlineEquation not available: see fulltext.]), DAB, and[InlineEquation not available: see fulltext.]-mode DVB.

  7. Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects

    NASA Astrophysics Data System (ADS)

    Sharma, Himani; Krabbe, Joshua D.; Farsinezhad, Samira; van Popta, Andy C.; Wakefield, Nick G.; Fitzpatrick, Glen A.; Shankar, Karthik

    2015-04-01

    Electrical through-wafer interconnect technologies such as vertical through-silicon vias (TSVs) are essential in order to maximize performance, optimize usage of wafer real estate, and enable three-dimensional packaging in leading edge electronic and microelectromechanical systems (MEMS) products. Although copper TSVs have the advantage of low resistance, highly doped polysilicon TSVs offer designers a much larger range of processing options due to the compatibility of polysilicon with high temperatures and also with the full range of traditional CMOS processes. Large stresses are associated with both Cu and polysilicon TSVs, and their accurate measurement is critical for determining the keep-out zone (KOZ) of transistors and for optimizing downstream processes to maintain high yield. This report presents the fabrication and stress characterization of 400-μm deep, 20-Ω resistance, high aspect ratio (25:1) polysilicon TSVs fabricated by deep reactive ion etching (DRIE) followed by low-pressure chemical vapor deposition (LPCVD) of polysilicon with in-situ boron doping. Micro-Raman imaging of the wafer surface showed a maximum stress of 1.2 GPa occurring at the TSV edge and a KOZ of ˜9 to 11 μm. For polysilicon TSVs, the stress distribution in the TSVs far from the wafer surface(s) was not previously well-understood due to measurement limitations. Raman spectroscopy was able to overcome this limitation; a TSV cross section was examined and stresses as a function of both depth and width of the TSVs were collected and are analyzed herein. An 1100°C postanneal was found to reduce average stresses by 40%.

  8. Finite-field arithmetic operations in VLSI-algorithms, realizations, and applications

    SciTech Connect

    Shyu, H.C.

    1986-01-01

    Congruences and residue arithmetic are the basis for the arithmetic operations on a finite ring. A new symbol (am)/sub L/ is defined to determine whether an integer a is a quadratic residue, modulo m, where m is a positive odd integer. A new theorem is proved which establishes the relationship between this new symbol and the corresponding Legendre symbol for the prime factors of m. The diminished-1 representation performs the arithmetic operations over the finite ring, modulo a Fermat number. The diminished-1 representation and arithmetic operations are valid also over the finite ring, modulo 2/sup n/ + 1. A new pipeline architecture for a prime factor DFT is developed. Also, a new shuffling algorithm is developed to solve the problem of rearranging the data sequence when a one- to two-dimensional index mapping is applied. The general case of this shuffling algorithm is established in theorems. Finally, the VLSI architecture for the pipeline prime factor DFT that makes use of this new shuffling algorithm is presented. VLSI designs for a integer multiplier modulo 2/sup 4/ + 1 = 17, a complex multiplier modulo 17, etc., which use the algorithms developed in this dissertation are shown

  9. New VLSI smart sensor for collision avoidance inspired by insect vision

    NASA Astrophysics Data System (ADS)

    Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran

    1995-01-01

    An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

  10. Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits

    SciTech Connect

    Savaria, Y.; Rumin, N.C.; Hayes, J.F.; Agarwal, V.

    1986-05-01

    As the semiconductor industry continues to scale down the feature sizes in VLSI digital circuits, soft errors will eventually limit the reliability of these circuits. An important source of these errors will be the products of radioactive decay. It is proposed to combat these transient errors by a new technique called soft-error filtering (SEF). This is based on filtering the input to every latch in the VLSI circuit, thereby preventing these transients, generated by alpha particle hits in the combinational section, from being latched in the corresponding registers. Several approaches to the problem of designing filtering latches are compared. This comparison demonstrates the superiority of a double-filter realization. The design for a CMOS implementation of the double-filter latch is presented. Not only is the design simple and efficient, but it can be expected to be tolerant to process variations. A comparison of SEF with conventional techniques for dealing with soft errors shows the former to be generally much more attractive, from the point of view of both area and time overhead.

  11. Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards

    SciTech Connect

    Pin, F.G.; Watanabe, Y.

    1992-09-01

    This paper discusses the sensor-based driving of a car in a-priori unknown environments using ``human-like`` reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver`s aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver`s aid using the new fuzzy inferencing VLSI hardware and ``human-like`` reasoning schemes.

  12. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    NASA Technical Reports Server (NTRS)

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  13. New design methodologies and circuits needed for parallel VLSI supercomputers

    SciTech Connect

    Lee, R.B.; Wiemann, A.L.

    1982-01-01

    The degree of parallelism dictated by the high performance requirements of special-purpose supercomputers motivates a departure from the design methodology of inherently sequential Von Neumann computers. A new methodology is proposed which integrates the functions of processing, memory, control, and timing into primitive, autonomous operators. These operators act on the principle of the production and consumption of data, both on the conceptual level and on the hardware level. An extra empty state is introduced for self-synchronisation. Systems are constructed by interconnecting the operators according to the logical data and control dependencies imposed by the particular application. It is recommended that new semiconductor circuits be designed to implement these operators. The need to develop new circuits and technologies as dictacted by computer design requirements is indicated. 12 references.

  14. Evolution of the MOS transistor - From conception to VLSI

    NASA Astrophysics Data System (ADS)

    Sah, Chih-Tang

    1988-10-01

    Historical developments of the MOSFET during the last 60 years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triode structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon MOSFET in 1960. A survey is then made of the milestones of the past 30 years leading to the latest submicron silicon logic CMOS and BICMOS (bipolar-junction transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor DRAM cell. The status of the submicron lithographic technologies is summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs FETs are reviewed.

  15. Design and Implementation of VLSI Architecture for Generation of Ternary Pulse Compression Sequence Based on Characteristic Parameters

    NASA Astrophysics Data System (ADS)

    Rao, M. Srinivasa; Reddy, N. Madhusudhana

    2010-11-01

    This paper describes the VLSI implementation for identification of characteristic parameters of the given ternary pulse compression sequence and also generates the ternary pulse compression sequence for transmission purpose if the characteristic parameter satisfies certain required value. In this paper an efficient VLSI architecture is proposed to calculate the characteristic parameters of the given ternary pulse compression sequence simultaneously or separately. The hardware architectures reported in the literature till now have the capability of identification of only one characteristic parameter of the ternary pulse compression sequence. In this paper an effort is made for proposing an efficient VLSI architecture for identification of the characteristic parameters i.e. merit factor and discrimination of the ternary pulse compression sequence either simultaneously or separately. If the identified characteristic parameter satisfies certain required value then the proposed architecture in this paper automatically generates the ternary pulse compression sequence for transmission purpose. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogramability.

  16. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    PubMed Central

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  17. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    NASA Astrophysics Data System (ADS)

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, Sanghyeon; Choi, Won Jun

    2016-02-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  18. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications.

    PubMed

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called "Si photonics"). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  19. "Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

    NASA Astrophysics Data System (ADS)

    Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

    2013-04-01

    During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

  20. Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

    NASA Technical Reports Server (NTRS)

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

    1986-01-01

    The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

  1. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  2. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  3. 100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices

    SciTech Connect

    OLIVER,ANDREW D.; MATZKE,CAROLYN M.

    2000-04-06

    A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

  4. Development of a Wafer Positioning System for the Sandia Extreme Ultraviolet Lithography Tool

    NASA Technical Reports Server (NTRS)

    Wronosky, John B.; Smith, Tony G.; Darnold, Joel R.

    1996-01-01

    A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

  5. Effective learning and feedback to designers through design and wafer inspection integration

    NASA Astrophysics Data System (ADS)

    Huang, Crockett; Liu, Hermes; Tzou, S. F.; Park, Allen; Young, Chris; Chang, Ellis

    2008-03-01

    As design rules continue to shrink beyond the lithography wavelength, pattern printability becomes a significant challenge in fabrication for 45nm and beyond. Model-based OPC and DRC checkers have been deployed using metrology data such as CD to fine-tune the model, and to predict and identify potential structures that may fail in a manufacturing environment. For advanced technology nodes with tighter process windows, it is increasingly important to validate the models with empirical data from both product and FEM wafers instead of relying solely on traditional metrology and simulations. Furthermore, feeding the information back to designers can significantly reduce the development efforts.

  6. Damascene patterned metal/adhesive wafer bonding for three-dimensional integration

    NASA Astrophysics Data System (ADS)

    McMahon, J. Jay

    Wafer bonding of damascene patterned metal/adhesive surfaces is explored for a new three-dimensional (3D) integration technology platform. By bonding a pair of damascene patterned metal/adhesive layers, high density micron-sized vias can be formed for interconnection of fully fabricated integrated circuit (IC) dies at the wafer-level. Such via dimensions increase the areal interconnect density by at least two orders of magnitude over current package and die-stacking approaches to 3D integration. The adhesive field-dielectric produces a high critical adhesion energy bond and has the potential to produce void-free bonded interfaces. This new technology platform has been demonstrated by fabricating and characterizing inter-wafer via-chains on 200 mm diameter Si wafers. Copper and partially cured divinylsiloxane bis-benzocyclobutene (BCB) are selected as the metal and adhesive, respectively, and unit processes for this demonstration are described. Typical alignment tolerance is ˜2 mum, and baseline bonding conditions include vacuum of 5x10-4 mbar, bonding force of 10 kN, and two step bonding temperature of 250°C for 60 min followed by 350°C for 60 min. Integration issues associated with the damascene patterning and the wafer bonding processes are discussed, particularly the resulting topography of damascene patterned Cu/BCB. Cross-sectional investigation of bonded and annealed inter-wafer interconnections provides insight into the Cu-Cu and BCB-BCB bonding interfaces. Inter-wafer specific contact resistance is measured to be on the order of 10-7 O-cm 2 for these via-chains. Several material characterization techniques have been explored to evaluate partially cured BCB as an adhesive field-dielectric. To investigate the critical adhesion energy, Gc, four-point bending is utilized to compare surfaces bonded after chemical-mechanical planarization (CMP) and various post-CMP treatments. The Gc of bonded 50% partially cured BCB is measured to be in the range of 32--44 J/m2. The elastic modulus of the BCB is investigated by monitoring film stress behavior for temperatures just below that needed for crosslinking (i.e. the temperature where BCB-BCB bonding begins). The film-stress temperature dependence is then used as an indicator for phase transitions in the BCB that affect elastic modulus. Surface analysis techniques are used to explore the surface chemistry of the BCB and measure its surface energy over the temperature range required for bonding. The surface energy of partially cured BCB at both 50 and 90% crosslinking is measured to decrease by ˜30% when the temperature is raised from 35°C to 230°C. The surface analysis and mechanical properties studies provide insight into the capability of BCB to close gaps when in contact during bonding, a necessary condition for forming void-free bonding interfaces. One important aspect for implementing wafer-level 3D integration is the ability of a technology platform to accommodate topography on fully fabricated wafers. The aforementioned metal/adhesive 3D platform has strict requirements in this regard if void-free surfaces are to be attained. A bonding protocol that eliminates the copper and tantalum interconnect structure is utilized to investigate the deformation capability of partially cured BCB during bonding. The results indicate that the defect density of such BCB-BCB bonds depends on material parameters such as the degree of crosslinking and surface energy, the pitch of the features, and the depth of the topography to be accommodated. For 70--90% crosslinked BCB, accommodation was observed for lines ˜120 nm deep and ˜100 mum in pitch. Furthermore, 70--90% crosslinked BCB lines with pitch ˜1 mum and depth ˜12 nm were accommodated during bonding. When the BCB crosslinking is reduced to 50%, additional accommodation is observed. In such cases, lines with pitch ˜100 mum and depth ˜500 nm, and those with pitch ˜1 mum and depth ˜50 nm were accommodated. Additional work has shown that accommodation of some topography is possible even with zero down-force during bonding. The accommodation of topography has been evaluated by extending previously published models that focused on Si-Si bonding to this new 3D integration technology platform. Accommodation prediction through use of this first-order model is found to agree with experimentally observed results when the BCB is crosslinked to a degree of 70--90%, with increased accommodation observed in the experiments that use 50% crosslinked BCB. This disagreement is attributed to the elastic modulus of the 50% BCB decreasing when passing through its glass transition temperature. The feasibility of a new 3D integration technology platform has been demonstrated with critical unit processes characterized. Key results include the demonstration of inter-wafer via-chains, material characterization for partially cured BCB for this new bonding application, and quantification of topography accommodation.

  7. Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

    NASA Astrophysics Data System (ADS)

    den Boef, Arie J.

    2016-06-01

    This paper presents three optical wafer metrology sensors that are used in lithography for robustly measuring the shape and position of wafers and device patterns on these wafers. The first two sensors are a level sensor and an alignment sensor that measure, respectively, a wafer height map and a wafer position before a new pattern is printed on the wafer. The third sensor is an optical scatterometer that measures critical dimension-variations and overlay after the resist has been exposed and developed. These sensors have different optical concepts but they share the same challenge that sub-nm precision is required at high throughput on a large variety of processed wafers and in the presence of unknown wafer processing variations. It is the purpose of this paper to explain these challenges in more detail and give an overview of the various solutions that have been introduced over the years to come to process-robust optical wafer metrology.

  8. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  9. Nano-particle laser removal from silicon wafers

    NASA Astrophysics Data System (ADS)

    Lee, J. M.; Cho, S. H.; Kim, T. H.; Park, Jin-Goo; Busnaina, Ahmed A.

    2003-11-01

    A laser shock cleaning (LSC) technique as a new dry cleaning methodology has been applied to remove micro and nano-scale inorganic particulate contaminants. Shock wave is generated in the air just above the wafer surface by focusing intensive laser beam. The velocity of shock wave can be controlled to 10,000 m/sec. The sub-micron sized silica and alumina particles are attempted to remove from bare silicon wafer surfaces. More than 95% of removal efficiency of the both particles are carried out by the laser-induced airborne shock waves. In the final, a removal of nano-scale slurry particles from real patterned wafers are successfully demonstrated by LSC after chemical-mechanical polishing (CMP) process.

  10. White-light interferometric microscopy for wafer defect inspection

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Christopher; Bryniarski, Casey; Dallmann, Marjorie F.; Popescu, Gabriel; Goddard, Lynford L.

    2015-03-01

    White-light imaging systems are free of laser-speckle. Thus, they offer high sensitivity for optical defect metrology, especially when used with interferometry based quantitative phase imaging. This can be a potential solution for wafer inspection beyond the 9 nm node. Recently, we built a white-light epi-illumination diffraction phase microscopy (epi-wDPM) for wafer defect inspection. The system is also equipped with an XYZ scanning stage and real-time processing. Preliminary results have demonstrated detection of 15 nm by 90 nm in a 9 nm node densely patterned wafer with bright-field imaging. Currently, we are implementing phase imaging with epi-wDPM for additional sensitivity.

  11. Wafer-scale synthesis and transfer of graphene films.

    PubMed

    Lee, Youngbin; Bae, Sukang; Jang, Houk; Jang, Sukjae; Zhu, Shou-En; Sim, Sung Hyun; Song, Young Il; Hong, Byung Hee; Ahn, Jong-Hyun

    2010-02-10

    We developed means to produce wafer scale, high-quality graphene films as large as 3 in. wafer size on Ni and Cu films under ambient pressure and transfer them onto arbitrary substrates through instantaneous etching of metal layers. We also demonstrated the applications of the large-area graphene films for the batch fabrication of field-effect transistor (FET) arrays and stretchable strain gauges showing extraordinary performances. Transistors showed the hole and electron mobilities of the device of 1100 +/- 70 and 550 +/- 50 cm(2)/(V s) at drain bias of -0.75 V, respectively. The piezo-resistance gauge factor of strain sensor was approximately 6.1. These methods represent a significant step toward the realization of graphene devices in wafer scale as well as application in optoelectronics, flexible and stretchable electronics. PMID:20044841

  12. New laser marking technology using ultrafast lasers

    NASA Astrophysics Data System (ADS)

    Gu, Bo

    2005-04-01

    Laser marking of silicon wafers has been an industrial standard for many years. One of the emerging challenges for wafer marking is the recent introduction of very thin wafers. In this paper, we present a completely new laser marking technology using ultra-fast lasers in an attempt to address these challenges. Permanent and high contrast shallow marks (less than 1 micron) on silicon wafers are achieved with no bump or kerf height. The visibility of these marks is independent of the viewing angle, which is very unique and desirable. Mark font sizes much less than 0.3 mm have been demonstrated, which shows potential for micro and nano marking.

  13. Digital model planning and computerized fabrication of orthognathic surgery wafers.

    PubMed

    Cousley, Richard R J; Turner, Mark J A

    2014-03-01

    Conventional orthognathic wafers are made by a process involving manual movement of stone dental models and acrylic laboratory fabrication. In addition, a facebow record and semi-adjustable articulator system are required for maxillary osteotomy cases. This paper introduces a novel process of producing both intermediate and final orthognathic surgical wafers using a combination of computerized digital model simulation and three-dimensional print fabrication, without the need for either a facebow record or the additional ionizing radiation exposure associated with cone beam computerized tomography. PMID:24235100

  14. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  15. Piezoelectric photoacoustic evaluation of Si wafers with buried structures.

    PubMed

    Shen, Y C; Zhang, S Y

    1992-01-01

    The piezoelectric photoacoustic evaluation of Si wafers with buried structures is studied experimentally and theoretically. In the experiment, the authors have detected and imaged the Sb-doped regions in a Si wafer covered by an epitaxial Si layer with about 10-mum thickness. In order to explain the experimental results, the one-dimensional multilayered model with discontinuous thermal impedance between the neighboring layers is used, and the expressions for the thermal and acoustic fields in the sample and PZT transducer are also presented. Moreover, numerical calculations in accordance with the practical experimental conditions have been carried out. PMID:18263140

  16. Computational Modeling in Plasma Processing for 300 mm Wafers

    NASA Technical Reports Server (NTRS)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  17. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    SciTech Connect

    Pin, F.G.; Pattay, R.S. ); Watanabe, H.; Symon, J. . Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  18. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    SciTech Connect

    Pin, F.G.; Pattay, R.S. ); Watanabe, Hiroyuki; Symon, J. . Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  19. Opto-VLSI-based broadband true-time delay generation for phased array beamforming

    NASA Astrophysics Data System (ADS)

    Juswardy, Budi; Xiao, Feng; Alameh, Kamal

    2009-08-01

    Electronically controlled phased-array antennas can adaptively scan radiated beams in three-dimensional space without mechanically moving parts. While most of the research on phased-array antennas has been focusing on broadband beam steering less attention has been devoted to null steering. Broadband null steering requires a beamformer that can generate variable and frequency independent true time-delays (TTD). In this paper we propose and demonstrate the concept of an Opto-VLSI-based tunable true-time delay generation unit for adaptive null steering in phased array antennas, where arbitrary single or multiple true-time delays can simultaneously be synthesized. Simulated azimuth gain patterns for a 4- element antenna arrays is presented, and experimental results are shown, which demonstrate the principle of the proposed true-time delay unit.

  20. VLSI systems design for digital signal processing. Volume 1 - Signal processing and signal processors

    NASA Astrophysics Data System (ADS)

    Bowen, B. A.; Brown, W. R.

    This book is concerned with the design of digital signal processing systems which utilize VLSI (Very Large Scale Integration) components. The presented material is intended for use by electrical engineers at the senior undergraduate or introductory graduate level. It is the purpose of this volume to present an overview of the important elements of background theory, processing techniques, and hardware evolution. Digital signals are considered along with linear systems and digital filters, taking into account the transform analysis of deterministic signals, a statistical signal model, time domain representations of discrete-time linear systems, and digital filter design techniques and implementation issues. Attention is given to aspects of detection and estimation, digital signal processing algorithms and techniques, issues which must be resolved in a processor design methodology, the fundamental concepts of high performance processing in terms of two early super computers, and the extension of these concepts to more recent processors.

  1. A Model of Stimulus-Specific Adaptation in Neuromorphic Analog VLSI.

    PubMed

    Mill, R; Sheik, S; Indiveri, G; Denham, S L

    2011-10-01

    Stimulus-specific adaptation (SSA) is a phenomenon observed in neural systems which occurs when the spike count elicited in a single neuron decreases with repetitions of the same stimulus, and recovers when a different stimulus is presented. SSA therefore effectively highlights rare events in stimulus sequences, and suppresses responses to repetitive ones. In this paper we present a model of SSA based on synaptic depression and describe its implementation in neuromorphic analog very-large-scale integration (VLSI). The hardware system is evaluated using biologically realistic spike trains with parameters chosen to reflect those of the stimuli used in physiological experiments. We examine the effect of input parameters and stimulus history upon SSA and show that the trends apparent in the results obtained in silico compare favorably with those observed in biological neurons. PMID:23852174

  2. Increase of the packaging density of Very Large Scale Integration (VLSI) circuits using automatic alignment

    NASA Astrophysics Data System (ADS)

    Fehling, H.

    1985-03-01

    Experiments in a production line were conducted to investigate the possible reduction of safety distances in VLSI circuits when an automatic alignment system is used. The test setup is described. With the very accurate alignment system of the Philips silicon repeater, the safety distance between a contact hole and a polysilicon-gate in a modified microcomputer circuit is reduced 0.7 micron without any yield loss. Design rules based on these experiments, and on lithography investigations were applied to redesign a 4 k static read-only memory. The area of a single memory cell in this redesign is 825 59 microns, compared to 1800 sq microns in the original version, and the final chip area is reduced to 8 sq mm compared to 13 sq mm.

  3. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    PubMed

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces. PMID:24613794

  4. An area-efficient VLSI architecture for AVS intra frame encoder

    NASA Astrophysics Data System (ADS)

    Zhang, Ke; Yu, Lu

    2007-01-01

    In this paper, we propose a VLSI architecture for AVS intra frame encoder. Reconstruction loop hinders the parallelism exploration and becomes the critical path in an intra frame encoder. A First Selection Then Prediction (FSTP) method is proposed to break the loop and enable the parallel process of intra mode selection and reconstruction on neighboring blocks. In addition, area-efficient modules were developed. Configurable intra predictor can support all the intra prediction modes. A CA-2D-VLC engine with an area-efficient Exp-Golomb encoder was developed to meet the encoding speed demand with comparably low hardware cost. Synthesized with 0.18 m CMOS standard-cell library, the overall hardware cost of the proposed intra frame encoder is 89k logic gates at the clock frequency constraint of 125MHz. Proposed encoder can satisfy real time encoding of 720x576 4:2:0 25fps video at the working frequency of 54MHz.

  5. An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

    SciTech Connect

    Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

    1995-12-01

    A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC`s. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used.

  6. A comparison of VLSI architectures for time and transform domain decoding of Reed-Solomon codes

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.; Deutsch, L. J.; Satorius, E. H.; Reed, I. S.

    1988-01-01

    It is well known that the Euclidean algorithm or its equivalent, continued fractions, can be used to find the error locator polynomial needed to decode a Reed-Solomon (RS) code. It is shown that this algorithm can be used for both time and transform domain decoding by replacing its initial conditions with the Forney syndromes and the erasure locator polynomial. By this means both the errata locator polynomial and the errate evaluator polynomial can be obtained with the Euclidean algorithm. With these ideas, both time and transform domain Reed-Solomon decoders for correcting errors and erasures are simplified and compared. As a consequence, the architectures of Reed-Solomon decoders for correcting both errors and erasures can be made more modular, regular, simple, and naturally suitable for VLSI implementation.

  7. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    NASA Technical Reports Server (NTRS)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  8. A system for the functional testing and simulation of custom and semicustom VLSI chips

    NASA Technical Reports Server (NTRS)

    Olson, E. M.; Deutsch, L. J.

    1986-01-01

    A system for the functional testing and simulation of custom and semicustom very large scale integrated (VLSI) chips that are designed using the integrated UNIX-based computer-aided design (CAD) system is described. The testing and simulation system consists of two parts. One of these is a special purpose hardware device that is capable of controlling the digital imputs and outputs on a custom chip. This device, the Digital Microcircuit Functionality Tester (DMFT) system, can be operated by itself or in conjunction with the VAX host computer on the CAD system. The DMFT is integrated into a microprobe station so that these signals can be injected or read from nodes inside the chip, as well as at the pins. The second part of the system is a software package that is installed on the VAX. This software package, logic, includes a full-screen editor for developing chip test sequences and drivers for both the DMFT and the esim logic simulator.

  9. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, Theodoer F.

    1995-01-01

    Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

  10. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  11. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    NASA Technical Reports Server (NTRS)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  12. High-throughput polarization imaging for defocus and dose inspection for production wafers

    NASA Astrophysics Data System (ADS)

    Sun, Gang; Onoichenco, Eugene; Fu, Yonghuang; Liu, Yongqiang; Amell, Ricardo; McCandless, Casey; Reddy, Rajasekar; Kumar, Gidesh; Guest, Max

    2007-03-01

    Advances in lithography create a unique challenge for process window control with defects inspection tools. As the technology moves towards smaller line widths and more complicated structures, the sensitivity requirements for some process defects become higher, such as defocus and dose defects at 50nm or lower technology nodes. Currently automated macro inspection tools are used to detect a wide range of macro defects in the litho area, such as coating defects, particles, scratches, as well as the process defects. Most tools, however, cannot satisfy the new sensitivity requirements for the process defects while maintaining their current inspection capability for other defects. Rudolph Technologies approaches this challenge by integrating a unique polarization-imaging configuration, which enhances detection of defocus and dose defects without sacrificing the existing capability to detect other types of macro defects. The improved inspection system has demonstrated high sensitivity for defocus and dose defects on production wafers at multiple process nodes at high throughput.

  13. Wafer and reticle positioning system for the Extreme Ultraviolet Lithography Engineering Test Stand

    SciTech Connect

    WRONOSKY,JOHN B.; SMITH,TONY G.; CRAIG,MARCUS J.; STURGIS,BEVERLY R.; DARNOLD,JOEL R.; WERLING,DAVID K.; KINCY,MARK A.; TICHENOR,DANIEL A.; WILLIAMS,MARK E.; BISCHOFF,PAUL

    2000-01-27

    This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EUVL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100nm. EUVL research and development includes development of capabilities for demonstrating key EUV technologies. The ETS is under development at the EUV Virtual National Laboratory, to demonstrate EUV full-field imaging and provide data that supports production-tool development. The stages and their associated metrology operated in a vacuum environment and must meet stringent outgassing specifications. A tight tolerance is placed on the stage tracking performance to minimize image distortion and provide high position repeatability. The wafer must track the reticle with less than {+-}3nm of position error and jitter must not exceed 10nm rms. To meet these performance requirements, magnetically levitated positioning stages utilizing a system of sophisticated control electronics will be used. System modeling and experimentation have contributed to the development of the positioning system and results indicate that desired ETS performance is achievable.

  14. Scatterometry on pelliclized masks: an option for wafer fabs

    NASA Astrophysics Data System (ADS)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  15. Interaction of an argon plasma jet with a silicon wafer

    NASA Astrophysics Data System (ADS)

    Engelhardt, Max; Pothiraja, Ramasamy; Kartaschew, Konstantin; Bibinov, Nikita; Havenith, Martina; Awakowicz, Peter

    2016-04-01

    A filamentary discharge is ignited in an argon plasma jet under atmospheric pressure conditions. The gas discharge is characterized with voltage-current measurements, optical emission spectroscopy and an ICCD-camera with a high temporal resolution down to 10 ns. In the effluent of the plasma jet, filaments come into contact with the surface of a silicon wafer and modify it, namely etching traces are produced and microcrystals are deposited. These traces are studied with optical and electron microscopes. The material of the deposited microcrystals and the surface modifications of the silicon wafer are analyzed with Raman microspectroscopy. Amorphous silicon is found within the etching traces. The largest part of the deposited microcrystals are composed of nitratine (NaNO3) and some of them are calcite (CaCO3). Analyzing the possible reasons for the silicon wafer modifications we come to the conclusion that plasmoids, which are produced near the substrate surface by interaction with ionization waves, are a plausible explanation for the observed surface modifications of the silicon wafer.

  16. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  17. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  18. Multi-wafer slicing with a fixed abrasive

    NASA Technical Reports Server (NTRS)

    Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

    1988-01-01

    A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

  19. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

  20. Virtual fab flow for wafer topography aware OPC

    NASA Astrophysics Data System (ADS)

    Stock, Hans-Jürgen; Bomholt, Lars; Krüger, Dietmar; Shiely, James; Song, Hua; Voznesenskiy, Nikolay

    2010-04-01

    Small feature sizes down to the current 45 nm node and precision requirements of patterning in 193 nm lithography as well as layers where the wafer stack does not allow any BARC require - not only correction of optical proximity (OPC) effects originating from mask topography and imaging system, but also correction of wafer topography proximity (WTPC) effects as well. In spite of wafer planarization process steps, wafer topography (proximity) effects induced by different optical properties of the patterned materials start playing a significant role, and correction techniques need to be applied in order to minimize the impact. In this paper, we study a methodology to create fast models intended for effective use in OPC and WTPC procedures. In order to be short we use the terms "OPCWTPC modeling" and "OPCWTPC models" through the paper although it would be more correctly to take the terms "mask synthesis modeling" and "mask synthesis models". A comprehensive data set is required to build a reliable OPC model. We present a "virtual fab" concept using extensive test pattern sets with both 1D and 2D structures to capture optical proximity effects as well as wafer topography effects. A rigorous lithography simulator taking into account exposure tool source maps, topographic mask effects as well as wafer topography is used to generate virtual measurement data, which are used for model calibration as well as for model validation. For model building, we use a two step approach: in a first step, an OPC model is built using test patterns on a planar, homogenous substrate; in a second step a WTPC model is calibrated, using results from simulated test patterns on shallow trench isolation (STI) layer. This approach allows building models from experimental data, including hybrid approaches where only experimental data from planar substrates is available and a corresponding OPC model for the planar case can be retrofitted with capabilities for correcting wafer topography effects. We analyze the relevant effects and requirements for model building and validation as well as the performance of fast WTPC models.

  1. Novel broadband reconfigurable optical add-drop multiplexer employing custom fiber arrays and Opto-VLSI processors.

    PubMed

    Xiao, Feng; Juswardy, Budi; Alameh, Kamal; Lee, Yong Tak

    2008-08-01

    A reconfigurable optical add/drop multiplexer (ROADM) structure based on using a custom-made fiber array and an Opto-VLSI processor is proposed and demonstrated. The fiber array consists of N pairs of angled fibers corresponding to N channels, each of which can independently perform add, drop, and thru functions through a reconfigurable Opto-VLSI beam steerer. Experimental results show that the ROADM structure can attain an average add, drop/thru insertion loss of 5.5 dB and a uniformity of 0.3 dB over a wide bandwidth from 1524 nm to 1576 nm, and a drop/thru crosstalk level as small as -40 dB. PMID:18679439

  2. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  3. Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

    NASA Astrophysics Data System (ADS)

    Calaway, M. J.; Rodriguez, M. C.; Allton, J. H.; Stansbery, E. K.

    2009-03-01

    The cleaning efficiency of the Genesis Ultra-pure Water Megasonic Wafer Spin Cleaner will be presented. Results show the effectiveness of the new cleaner removing particle contamination from Genesis silicon wafers implanted with solar wind.

  4. Electrical characterization of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Kang, Sunggun

    Silicon-on-Insulator (SOI) metal oxide semiconductor field effect transistors (MOSFET) have become a common subject in the semiconductor community due to enhanced performance such as simple processing, excellent scalability, sharp subthreshold characteristics, minimum short-channel effects, and reduced hot electron degradation. Since these films are used for devices, it is necessary to know the SOI film quality with simple and nondestructive methods. In this study, surface photovoltage (SPV) measurements, pseudo-MOSFET characterization, and capacitance-voltage (C-V) are used. Literature review and simulations show that material properties of SOI wafers can have significant effects on the device and circuit performance such as floating body effects, switching speed, leakage current, and noise characteristics. SPV results show the surface charges of SOI wafers to increase with frequency in the low frequency region, with several interface components acting in opposing directions. Iron contaminated wafers show increased surface charges due to a high density of interface states. The efficacy of surface passivation is clearly shown by measuring the effective generation lifetime as a function of time after applying the liquid to the pseudo-MOSFET surface. A more controlled method is the additional top gate controlling either the upper or lower silicon film surface, separately. C-V measurements for some SOI wafers show a leaky buried oxide (BOX) and high density of interface states. SOI wafers can exhibit quite different breakdown voltage before and after removing the Si layer, indicating that the gate current flows through weaker current paths in the BOX beyond the gate area. Transmission electron microscopy (TEM) images display smooth interfaces and a clean BOX, regardless of the breakdown voltage.

  5. Wafer bonding process for building MEMS devices

    NASA Astrophysics Data System (ADS)

    Pabo, Eric F.; Meiler, Josef; Matthias, Thorsten

    2014-06-01

    The technology for the measurement of colour rendering and colour quality is not new, but many parameters related to this issue are currently changing. A number of standard methods were developed and are used by different specialty areas of the lighting industry. CIE 13.3 has been the accepted standard implemented by many users and used for many years. Light-emitting Diode (LED) technology moves at a rapid pace and, as this lighting source finds wider acceptance, it appears that traditional colour-rendering measurement methods produce inconsistent results. Practical application of various types of LEDs yielded results that challenged conventional thinking regarding colour measurement of light sources. Recent studies have shown that the anatomy and physiology of the human eye is more complex than formerly accepted. Therefore, the development of updated measurement methodology also forces a fresh look at functioning and colour perception of the human eye, especially with regard to LEDs. This paper includes a short description of the history and need for the measurement of colour rendering. Some of the traditional measurement methods are presented and inadequacies are discussed. The latest discoveries regarding the functioning of the human eye and the perception of colour, especially when LEDs are used as light sources, are discussed. The unique properties of LEDs when used in practical applications such as luminaires are highlighted.

  6. In-situ detection method for wafer movement and micro-arc discharge around a wafer in plasma etching process using electrostatic chuck wafer stage with built-in acoustic emission sensor

    NASA Astrophysics Data System (ADS)

    Kasashima, Yuji; Tabaru, Tatsuo; Yasaka, Mitsuo; Kobayashi, Yoshikazu; Akiyama, Morito; Nabeoka, Natsuko; Motomura, Taisei; Sakamoto, Shingo; Uesugi, Fumihiko

    2014-01-01

    We report an electrostatic chuck (ESC) wafer stage with a built-in acoustic emission (AE) sensor for detecting anomalies occurring around a wafer during plasma etching. The built-in AE sensor detects acoustic waves caused by wafer movement and micro-arc discharge with high sensitivity, and identifies these anomalies based on the frequency characteristics of the waves. The results demonstrate the effectiveness of using an ESC wafer stage with a built-in AE sensor for in-situ anomaly detection, which can improve the production yield and overall equipment efficiency in large scale integrated circuit (LSI) manufacturing.

  7. Characteristics and issues of haze management in a wafer fabrication environment

    NASA Astrophysics Data System (ADS)

    Woo, Sung Ha; Hwang, Dae Ho; Jeong, Goo Min; Lee, Young Mo; Kim, Sang Pyo; Yim, Dong Gyu

    2014-10-01

    The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been promoted in the semiconductor industry which has been shown to suppress or minimize the propensity for haze formation, but none of these technologies can stop every instance of haze. Fortunately, a novel technology which uses a dry (no chemical effluents) removal system, laser-based, through pellicle process has been reported recently. The technology presented here avoids many of the shortcomings of the wet clean process mentioned previously. The dry clean process extends the life of the photomask; maintains more consistent CD's, phase, and transmission; avoids adjustment to the exposure dose to account for photomask changes, reduces the number of required inspections and otherwise improves the efficiency and predictability of the lithography cell. We report on the performance of photomask based on a design developed to study the impact of metrology variations on dry clean process. In a first step we focus on basic characteristics: CD variation, phase, Cr/MoSi transmission, pellicle transmission, registration variations. In a second step, we evaluate haze removal and prevention performance and wafer photo margin. Haze removal is studied on the masks for several haze types and various exposure conditions. The results of this study show that some of metrology variation are likely to be a problem at high technology node, and haze removal performance is determined whether the component of haze is remained or not after treatment.

  8. Flat-Plate Solar Array Project: Final report: Volume 3, Silicon sheet: Wafers and Ribbons

    SciTech Connect

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison A.

    1986-10-01

    The primary objective of the Silicon Sheet Task of the FSA Project was the development of one or more low-cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high-purity crystalline silicon of size and thickness for fabrication into solar cells. The Task effort began with state-of-the-art sheet technologies and then solicited and supported any new silicon sheet alternatives that had the potential to achieve the Project goals. A total of 48 contracts were awarded that covered work in the areas of ingot growth and casting, wafering, ribbon growth, other sheet technologies, and programs of supportive research. Periodic reviews of each sheet technology were held, assessing the technical progress and the long-range potential. Technologies that failed to achieve their promise, or seemed to have lower probabilities for success in comparison with others, were dropped. A series of workshops was initiated to assess the state of the art, to provide insights into problems remaining to be addressed, and to support technology transfer. The Task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding other characteristics associated with high-quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the Task cost goals were not achieved.

  9. Integrated optical MEMS using through-wafer vias and bump-bonding.

    SciTech Connect

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  10. Mask manufacturing mix-and-match in front-end wafer processing

    NASA Astrophysics Data System (ADS)

    Frangen, Andreas; Jakob, Roland; Kubis, Michael

    2004-12-01

    Different mask manufacturing methods can lead to specific signatures (fingerprints) in registration and CD distribution across the mask blanks. A mix-and-match strategy can thereby cause systematic contributions to the total overlay and CD error on the wafer. As a result, mixing masks between different mask vendors or different mask writing tools is often regarded as detrimental to wafer yields. Especially overlay and CD sensitive structuring layers, like gate and capacitor layer, it is often preferred to use only one mask vendor and mask making process to cancel out systematic errors. However in reality, due to delivery constraints or other logistics boundary conditions, it would sometimes be preferable to be able to mix-and-match for different masks. That could be the case if one manufacturing site is not able to supply a specific type or spec class. On top of that, it might even be required that different copies of one layer are supplied by different vendors. That could be caused by commercial reasons or by switching the mask vendor. In this paper we investigate systematically the influence of mix-and-match masks on frontend wafer yields. Three main issues can be identified as potential pitfalls: registration fingerprints, CD characteristics (linearity, line-end-shortening, proximity), and metrology matching. Main contributors for differences are the writer technology (tool-type, correction settings), developer and etch process, as well as different calibration and metrology methods. The CD characteristic can be compensated by generating appropriate OPC models, and the metrology- and correction methods can be matched. Consequently, we would like to focus on the registration fingerprint of different writer tools from different maskshops as the one systematic contribution which cannot be eliminated. We will investigate the impact of registration fingerprints by analyzing the electrical performance of memory chips.

  11. An efficient VLSI implementation of on-line recursive ICA processor for real-time multi-channel EEG signal separation.

    PubMed

    Shih, Wei-Yeh; Liao, Jui-Chieh; Huang, Kuan-Ju; Fang, Wai-Chi; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2013-01-01

    This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90 nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1 s frame is 0.9763. PMID:24111307

  12. Rinsing of wafers after wet processing: Simulation and experiments

    NASA Astrophysics Data System (ADS)

    Chiang, Chieh-Chun

    In semiconductor manufacturing, a large amount (50 billion gallons for US semiconductor fabrication plants in 2006) of ultrapure water (UPW) is used to rinse wafers after wet chemical processing to remove ionic contaminants on surfaces. Of great concern are the contaminants left in narrow (tens of nm), high-aspect-ratio (5:1 to 20:1) features (trenches, vias, and contact holes). The International Technology Roadmap for Semiconductors (ITRS) stipulates that ionic contaminant levels be reduced to below ˜ 10 10 atoms/cm2. Understanding the bottlenecks in the rinsing process would enable conservation of rinse water usage. A comprehensive process model has been developed on the COMSOL platform to predict the dynamics of rinsing of narrow structures on patterned SiO 2 substrates initially cleaned with NH4OH. The model considers the effect of various mass-transport mechanisms, including convection and diffusion/dispersion, which occur simultaneously with various surface phenomena, such as adsorption and desorption of impurities. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, have been addressed. Modeling results show that the efficacy of rinsing is strongly influenced by the rate of desorption of adsorbed contaminants, mass transfer of contaminants from the mouth of the feature to the bulk liquid, and the trench aspect ratio. Detection of the end point of rinsing is another way to conserve water used for rinsing after wet processing. The applicability of electrochemical impedance spectroscopy (EIS) to monitor rinsing of Si processed in HF with and without copper contaminant was explored. In the first study, the effect of the nature of surface state (flat band, depletion, or accumulation) of silicon on rinsing rate was investigated. The experimental results show that the state of silicon could affect rinsing kinetics through modulation of ion adsorption. In the second study, silicon was intentionally contaminated by spiking HF with copper ions, cleaned in dilute HCl and then rinsed, and the entire process was followed by continuous impedance measurements. The measured impedance values at different stages have been correlated to the nature of the silicon surface, as characterized by scanning electron microscope (SEM) and inductively coupled plasma mass spectrometry (ICP-MS) methods.

  13. Enhanced capture rate for haze defects in production wafer inspection

    NASA Astrophysics Data System (ADS)

    Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

    2010-03-01

    Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

  14. A Flip-Chip AlGaInP LED with GaN/Sapphire Transparent Substrate Fabricated by Direct Wafer Bonding

    NASA Astrophysics Data System (ADS)

    Liang, Ting; Guo, Xia; Guan, Bao-Lu; Guo, Jing; Gu, Xiao-Ling; Lin, Qiao-Ming; Shen, Guang-Di

    2007-04-01

    A red-light AlGaInP light emitting diode (LED) is fabricated by using direct wafer bonding technology. Taking N-GaN wafer as the transparent substrate, the red-light LED is flip-chiped onto a structured silicon submount. Electronic luminance (EL) test reveals that the luminance flux is 130% higher than that of the conventional LED made from the same LED wafer. Current-voltage (I-V) measurement indicates that the bonding processes do not impact the electrical property of AlGaInP LED in the small voltage region (V<1.5 V). In the large voltage region (V>1.5 V), the I-V characteristic exhibits space-charge-limited currents characteristic due to the p-GaAs/n-GaN bonding interface.

  15. Thin Body III-V-Semiconductor-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors on Si Fabricated Using Direct Wafer Bonding

    NASA Astrophysics Data System (ADS)

    Yokoyama, Masafumi; Yasuda, Tetsuji; Takagi, Hideki; Yamada, Hisashi; Fukuhara, Noboru; Hata, Masahiko; Sugiyama, Masakazu; Nakano, Yoshiaki; Takenaka, Mitsuru; Takagi, Shinichi

    2009-12-01

    We have demonstrated thin body III-V-semiconductor-on-insulator (III-V-OI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) on a Si wafer fabricated using a novel direct wafer bonding (DWB) process. A 100-nm-thick InGaAs channel was successfully transferred by the low damage and low temperature DWB process using low energy electron cyclotron resonance (ECR) plasma. The transferred InGaAs-OI nMOSFET on the Si wafer exhibited a high electron channel mobility of 1200 cm2.V-1.s-1, indicating that the present DWB process allows us to form thin III-V-OI channels without serious plasma and bonding damage. This technology is expected to open up the possibility of integrating the ultrathin body III-V-OI MOSFETs on Si platform.

  16. Wafer-level Au-Au bonding in the 350-450 °C temperature range

    NASA Astrophysics Data System (ADS)

    Tofteberg, Hannah R.; Schjølberg-Henriksen, Kari; Fasting, Eivind J.; Moen, Alexander S.; Taklo, Maaike M. V.; Poppe, Erik U.; Simensen, Christian J.

    2014-08-01

    Metal thermocompression bonding is a hermetic wafer-level packaging technology that facilitates vertical integration and shrinks the area used for device sealing. In this paper, Au-Au bonding at 350, 400 and 450 °C has been investigated, bonding wafers with 1 µm Au on top of 200 nm TiW. Test Si laminates with device sealing frames of 100, 200, and 400 µm in width were realized. Bond strengths measured by pull tests ranged from 8 to 102 MPa and showed that the bond strength increased with higher bonding temperatures and decreased with increasing frame width. Effects of eutectic reactions, grain growth in the Au film and stress relaxation causing buckles in the TiW film were most pronounced at 450 °C and negligible at 350 °C. Bond temperature below the Au-Si eutectic temperature 363 °C is recommended.

  17. Formation and combustion characteristics of elephantgrass and energycane wafers

    NASA Astrophysics Data System (ADS)

    Mofleh, Mohamad I.

    Elephantgrass (Pennisetum purpureum Schum.) and energycane (Saccharum Spp.) are two cane type grasses. These are tall-growing perennial bunchgrasses that produce long hardened stems and grow in the tropics and subtropics. Traditionally, they have been used for forage and, in some regions, have been randomly burned on fields or disposed of uselessly. However, these plants have high dry matter yield and, thus, are excellent candidates as energy crops. Elephantgrass and energycane have been used for direct combustion in their loose form in large-scale applications. Several problems, many of which were attributed to their low bulk density, were encountered with using the materials. Consequently, this project was initiated to investigate the formation and combustion characteristics of the two materials in the form of small compact units called wafers. A hydraulic press that applied axial stresses on the material in four different dies was used. A load cell and a displacement transducer were utilized to measure the stresses and material detection. Wafer quality was evaluated using a tumbler built according to the American Society of Agricultural Engineers standards. In addition, a small stove was built to test wafer combustion. Thermocouples were used to measure temperatures during combustion. All the data gathered was transferred to a computer using a data acquisition system. It was found that the stress-deformation and stress-density relationships of elephantgrass and energycane were of exponential nature. Compaction energy required, which was calculated from the area under the force-deformation curves, ranged from 0.1 to 0.3% of their energy content. It was also found that wafer quality (durability) was mainly a function of wafer size and its final (relaxed) density in addition to material stem-to-leaf ratio and its crude protein content. Wafers possessed poor ignition quality but once ignited, they burned satisfactorily. The results indicated that sufficient and uniform combustion air distribution and a stove lining were critical factors in burning these materials. Further, the findings revealed that it may not be recommended to use elephantgrass or energycane in large-scale applications due to their high slagging index. Nonetheless, using them in small-scale applications may be possible. Elephantgrass was generally a better candidate for such an application.

  18. Height inspection of wafer bumps without explicit 3D reconstruction

    NASA Astrophysics Data System (ADS)

    Dong, Mei; Chung, Ronald; Zhao, Yang; Lam, Edmund Y.

    2006-02-01

    The shrunk dimension of electronic devices leads to more stringent requirement on process control and quality assurance of their fabrication. For instance, direct die-to-die bonding requires placement of solder bumps not on PCB but on the wafer itself. Such wafer solder bumps, which are much miniaturized from the counterparts on PCB, still need to have their heights meet the specification, or else the electrical connection could be compromised, or the dies be crushed, or even the manufacturing equipments be damaged. Yet the tiny size, typically tens of microns in diameter, and the textureless and mirror nature of the bumps pose great challenge to the 3D inspection process. This paper addresses how a large number of such wafer bumps could have their heights massively checked against the specification. We assume ball bumps in this work. We propose a novel inspection measure about the collection of bump heights that possesses these advantages: (1) it is sensitive to global and local disturbances to the bump heights, thus serving the bump height inspection purpose; (2) it is invariant to how individual bumps are locally displaced against one another on the substrate surface, thus enduring 2D displacement error in soldering the bumps onto the wafer substrate; and (3) it is largely invariant to how the wafer itself is globally positioned relative to the imaging system, thus having tolerance to repeatability error in wafer placement. This measure makes use of the mirror nature of the bumps, which used to cause difficulty in traditional inspection methods, to capture images of two planes. One contains the bump peaks and the other corresponds to the substrate. With the homography matrices of these two planes and fundamental matrix of the camera, we synthesize a matrix called Biplanar Disparity Matrix. This matrix can summarize the bumps' heights in a fast and direct way without going through explicit 3D reconstruction. We also present a design of the imaging and illumination setup that allows the measure to be revealed in two images, and how the inspection measure could be estimated from the image data so acquired. Both synthetic and real data experimental results are shown to illustrate the effectiveness of the proposed system.

  19. Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

    NASA Astrophysics Data System (ADS)

    Altan, Hakan

    All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

  20. Studies of the Effects of Side Walls on VLSI Semiconductor Devices.

    NASA Astrophysics Data System (ADS)

    Guo, Xin Sheng

    1990-08-01

    Properties and effects of side walls in very large scale integrated (VLSI) devices are explored and studied. Many side wall related properties, such as damage on side walls caused by reactive ion etching (RIE) and ion implantation, impurity diffusion in from side walls, segregation of atoms to side walls, and side wall heat absorption, are investigated and found to be significant. Properties of the side walls are compared to those of a horizontal surface. The wake potential of a fast charged particle is derived for an atomic system using a first-order quantum -mechanical perturbation theory. The atomic Coulomb excitation cross sections of the target atoms by this wake potential are then derived and found to be large. Numerical results for a model system of condensed atomic hydrogen show that the wake potential is important and should be included in calculating the atomic Coulomb excitation cross sections in condensed matter. The wake potential along the path of a fast charged particle is also calculated for the case of hydrogen 1s 2s and 2p transitions without a cutoff parameter. A computer program has been written to simulate the RBS spectrum from stripes that are similar to VLSI device components. The simulation fits experimental data well and can be used to determine diffusion in horizontal directions. It also provides an accurate way of measuring angle of the stripe side walls. The charged particle stopping power change due to the transition to the superconducting state is estimated and measured. The change of stopping power depends on the energy gap of the superconductor, and may be measurable for low energy charged particles. The relative stopping power difference of a 1 MeV proton between the superconducting and normal states of polycrystalline YBa_2 Cu_3O_7 at 77K was measured to be 0.06 +/- 0.14%. The hydrogen concentration in CVD P glass, CVD TEOS oxide, phosphorus doped TEOS oxide, plasma enhanced CVD oxide, low pressure CVD nitride and plasma enhanced nitride are studied. Hydrogen redistribution during furnace and rapid thermal annealing (RTA), room temperature diffusion, and hydrogen diffusion from nitride layer into oxide layer are also studied.

  1. MEMS probes for on-wafer RF microwave characterization of future microelectronics: design, fabrication and characterization

    NASA Astrophysics Data System (ADS)

    Marzouk, Jaouad; Arscott, Steve; El Fellahi, Abdelhatif; Haddadi, Kamel; Lasri, Tuami; Boyaval, Christophe; Dambrine, Gilles

    2015-07-01

    This article presents microelectromechanical system (MEMS) ground-signal-ground (GSG) probes based on silicon-on-insulator (SOI) technology for on-wafer microwave characterization of radio-frequency (RF) microelectronics. The probe is designed using optimized coplanar waveguide structures with the aim of ensuring a low-contact resistance between the probe and the pads of the device under test (DUT). The probes are batch fabricated using SOI substrates and employ a simple silicon micromachining process. The probes have a pitch of 4.5 µm with miniaturized dimensions for a DUT pad area with a similar size. Electrical (dc) measurements show that the fabricated probe has a low-contact resistance (~0.02 Ω) on gold pads. Excellent extracted RF performances of the probe are observed up to 30 GHz, showing an insertion loss better than 2.2 dB and return loss better than 20 dB over the frequency range. An ageing study shows the probes are capable of forming this dc contact for over 6000 contact cycles. The preliminary result of the repeatability of on-wafer one-port measurements with the miniaturized probe shows a consistent RF performance maintained through several contacts. The data indicates that the proposed MEMS probe is suitable for the high-frequency characterization of integrated nanoscale devices having reduced pad dimensions.

  2. Wafer level fabrication of single cell dispenser chips with integrated electrodes for particle detection

    NASA Astrophysics Data System (ADS)

    Schoendube, Jonas; Yusof, Azmi; Kalkandjiev, Kiril; Zengerle, Roland; Koltay, Peter

    2015-02-01

    This work presents the microfabrication and experimental evaluation of a dispenser chip, designed for isolation and printing of single cells by combining impedance sensing and drop-on-demand dispensing. The dispenser chip features 50  ×  55 µm (width × height) microchannels, a droplet generator and microelectrodes for impedance measurements. The chip is fabricated by sandwiching a dry film photopolymer (TMMF) between a silicon and a Pyrex wafer. TMMF has been used to define microfluidic channels, to serve as low temperature (75 °C) bonding adhesive and as etch mask during 300 µm deep HF etching of the Pyrex wafer. Due to the novel fabrication technology involving the dry film resist, it became possible to fabricate facing electrodes at the top and bottom of the channel and to apply electrical impedance sensing for particle detection with improved performance. The presented microchip is capable of dispensing liquid and detecting microparticles via impedance measurement. Single polystyrene particles of 10 µm size could be detected with a mean signal amplitude of 0.39  ±  0.13 V (n=439 ) at particle velocities of up to 9.6 mm s-1 inside the chip.

  3. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  4. Chemical method for producing smooth surfaces on silicon wafers

    DOEpatents

    Yu, Conrad

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  5. Metal adsorbent for alkaline etching aqua solutions of Si wafer

    NASA Astrophysics Data System (ADS)

    Tamada, Masao; Ueki, Yuji; Seko, Noriaki; Takeda, Toshihide; Kawano, Shin-ichi

    2012-08-01

    High performance adsorbent is expected to be synthesized for the removal of Ni and Cu ions from strong alkaline solution used in the surface etching process of Si wafer. Fibrous adsorbent was synthesized by radiation-induce emulsion graft polymerization onto polyethylene nonwoven fabric and subsequent amination. The reaction condition was optimized using 30 L reaction vessel and nonwoven fabric, 0.3 m width and 18 m long. The resulting fibrous adsorbent was evaluated by 48 wt% NaOH and KOH contaminated with Ni and Cu ions, respectively. The concentration levels of Ni and Cu ions was reduced to less than 1 μg/kg (ppb) at the flow rate of 10 h-1 in space velocity. The life of adsorbent was 30 times higher than that of the commercialized resin. This novel adsorbent was commercialized as METOLATE® since the ability of adsorption is remarkably higher than that of commercial resin used practically in Si wafer processing.

  6. Nanoindentation tests on diamond-machined silicon wafers

    NASA Astrophysics Data System (ADS)

    Yan, Jiwang; Takahashi, Hirokazu; Tamaki, Jun'ichi; Gai, Xiaohui; Harada, Hirofumi; Patten, John

    2005-05-01

    Nanoindentation tests were performed on ultraprecision diamond-turned silicon wafers and the results were compared with those of pristine silicon wafers. Remarkable differences were found between the two kinds of test results in terms of load-displacement characteristics and indent topologies. The machining-induced amorphous layer was found to have significantly higher microplasticity and lower hardness than pristine silicon. When machining silicon in the ductile mode, we are in essence always machining amorphous silicon left behind by the preceding tool pass; thus, it is the amorphous phase that dominates the machining performance. This work indicated the feasibility of detecting the presence and the mechanical properties of the machining-induced amorphous layers by nanoindentation.

  7. Single Wafer Furnace and Its Thermal Processing Applications

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kuribayashi, Hiromitsu; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-07-01

    A resistively heated, vacuum and atmospheric pressure compatible, single wafer furnace (SWF) system is proposed to improve operational flexibility of conventional furnaces and productivity of single wafer rapid thermal processing (RTP) systems. The design concept and hardware configuration of the SWF system are described. The temperature measurement/control techniques and thermal characteristics of the SWF system are described. Typical process results in TiSi formation, implant anneal and thin oxide formation using the SWF system are reported. Due to the vertically stacked, dual chamber configuration and steady state temperature control, very flexible operation with a high throughput at a minimal power consumption (<3.5 kW per process chamber at 1150°C) was realized. Many thermal processes used in furnaces and RTP systems can easily be converted to SWF processes without decreasing cost performance and/or deteriorating process results by using the SWF system.

  8. A gas chromatographic air analyzer fabricated on a silicon wafer

    NASA Technical Reports Server (NTRS)

    Terry, S. C.; Jerman, J. H.; Angell, J. B.

    1979-01-01

    A miniature gas analysis system has been built based on the principles of gas chromatography (GC). The major components are fabricated in silicon using photolithography and chemical etching techniques, which allows size reductions of nearly three orders of magnitude compared to conventional laboratory instruments. The chromatography system consists of a sample injection valve and a 1.5-m-long separating capillary column, which are fabricated on a substrate silicon wafer. The output thermal conductivity detector is separately batch fabricated and integrably mounted on the substrate wafer. The theory of gas chromatography has been used to optimize the performance of the sensor so that separations of gaseous hydrocarbon mixtures are performed in less than 10 s. The system is expected to find application in the areas of portable ambient air quality monitors, implanted biological experiments, and planetary probes.

  9. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    SciTech Connect

    Montoya, Angela C.; Maji, Arup K.

    2010-02-22

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  10. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  11. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  12. Towards reduced impact of EUV mask defectivity on wafer

    NASA Astrophysics Data System (ADS)

    Jonckheere, R.; Van den Heuvel, D.; Pacco, A.; Pollentier, I.; Baudemprez, B.; Jehoul, C.; Hermans, J.; Hendrickx, E.

    2014-07-01

    The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles "hopping" between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present "black-border" solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

  13. Ultrahigh-vacuum field emitter array wafer tester

    SciTech Connect

    Gray, H.F.; Ardis, L.; Campisi, G.J.

    1987-02-01

    The device reported here allows the researcher the opportunity of gaining primitive yield information, threshold voltages, emission stability, and other information, e.g., gas effects, on field emitter arrays (FEA) which are microminiature ''vacuum tubes'' fabricated by microelectronic processing methods on silicon wafers, without scribing, dicing, and mounting each device on individual vacuum-compatible headers. This device also speeds up the entire data-acquisition process by requiring only one ultrahigh-vacuum pumpdown and one set of vacuum feedthroughs.

  14. Ultrahigh-vacuum field emitter array wafer tester

    NASA Astrophysics Data System (ADS)

    Gray, H. F.; Ardis, L.; Campisi, G. J.

    1987-02-01

    The device reported here allows the researcher the opportunity of gaining primitive yield information, threshold voltages, emission stability, and other information, e.g., gas effects, on field emitter arrays (FEA) which are microminiature ``vacuum tubes'' fabricated by microelectronic processing methods on silicon wafers, without scribing, dicing, and mounting each device on individual vacuum-compatible headers. This device also speeds up the entire data-acquisition process by requiring only one ultrahigh-vacuum pumpdown and one set of vacuum feedthroughs.

  15. 100-GHz transistors from wafer-scale epitaxial graphene.

    PubMed

    Lin, Y-M; Dimitrakopoulos, C; Jenkins, K A; Farmer, D B; Chiu, H-Y; Grill, A; Avouris, Ph

    2010-02-01

    The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon transistors of the same gate length. PMID:20133565

  16. A photo-sensor on thin polysilicon membrane embedded in wafer level package LED

    NASA Astrophysics Data System (ADS)

    Kim, Jin Kwan; Lee, Hee Chul

    2012-06-01

    A wafer level packaging LED with photo-sensor which is fabricated on thin poly-silicon membrane located on the corner of silicon cavity is presented in this paper. The wafer substrate was fabricated with (100) orientation silicon wafer and a cavity was etched on the top of the wafer with wet chemical anisotropic etching process for mounting a LED chip. A thin polysilicon membrane was fabricated on the corner of the cavity and a MSM (Metal Semiconductor Metal) type photo-sensor was fabricated on the thin polysilicon membrane. The photo-sensor fabrication and LED packaging were completed on wafer level. The embedded photo-sensor in a wafer level packaging LED is designed to measure light intensity of a LED. The membrane structure photo-sensor can sense the light of the mounted LED directly, so it can measure accurate light intensity of the wafer level packing LED.

  17. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  18. Wafer-scale aluminum plasmonics for fluorescence based biodetection

    NASA Astrophysics Data System (ADS)

    Farhang, Arash; George, Matthew C.; Williamson, Brent; Black, Mike; Wangensteen, Ted; Fraser, James; Petrova, Rumyana; Prestgard, Kent

    2015-08-01

    Moxtek has leveraged existing capabilities in wafer-scale patterning of sub-wavelength wire grid polarizers into the fabrication of 1D and 2D periodic aluminum plasmonic structures. This work will discuss progress in 200 mm diameter wafer-scale fabrication, with detailed emphasis within the realm of microarray based fluorescence detection. Aluminum nanohole arrays in a hexagonal lattice are first numerically investigated. The nanohole array geometry and periodicity are specifically tuned to coincide both with the excitation of the fluorophore Cy3, and to provide a high field enhancement within the nanoholes where labeled biomolecules are captured. This is accomplished through numerical modelling, nanofabrication, SEM imaging, and optical characterization. A 200mm diameter wafer, patterned with the optically optimized nanohole array, is cut into standard 1x3 inch microscope slide pieces and then subsequently printed with various antigens at 9 different concentrations. A sandwich bioassay is then carried out, using the corresponding conjugate antibodies in order to demonstrate specificity. The nanohole array exhibit a 3-4 times total fluorescence enhancement of Cy3, when compared to a leading commercial microarray glass slide.

  19. Wafer-scale fabrication of penetrating neural microelectrode arrays.

    PubMed

    Bhandari, Rajmohan; Negi, Sandeep; Solzbacher, Florian

    2010-10-01

    The success achieved with implantable neural interfaces has motivated the development of novel architectures of electrode arrays and the improvement of device performance. The Utah electrode array (UEA) is one example of such a device. The unique architecture of the UEA enables single-unit recording with high spatial and temporal resolution. Although the UEA has been commercialized and been used extensively in neuroscience and clinical research, the current processes used to fabricate UEA's impose limitations in the tolerances of the electrode array geometry. Further, existing fabrication costs have led to the need to develop less costly but higher precision batch fabrication processes. This paper presents a wafer-scale fabrication method for the UEA that enables both lower costs and faster production. More importantly, the wafer-scale fabrication significantly improves the quality and tolerances of the electrode array and allow better controllability in the electrode geometry. A comparison between the geometrical and electrical characteristics of the wafer-scale and conventional array-scale processed UEA's is presented. PMID:20480240

  20. Wafer-scale nanowell array patterning based electrochemical impedimetric immunosensor.

    PubMed

    Lee, JuKyung; Cho, SiHyeong; Lee, JungHwan; Ryu, HeonYul; Park, JinGoo; Lim, SunHee; Oh, ByungDo; Lee, ChangWoo; Huang, Wilber; Busnaina, Ahmed; Lee, HeaYeon

    2013-12-01

    We have reported that nanowell array (NWA) can enhance electrochemical detection of molecular binding events by controlling the binding sites of the captured molecules. Using NWA biosensor based amperometric analysis, we have detected biological macromolecules such as DNA, protein or aptamers at low concentrations. In this research, we developed an impedimetric immunosensor based on wafer-scale NWA for electrochemical detection of stress-induced-phosphoprotein-1 (STIP-1). In order to develop NWA sensor through the cost-effective combination of high-throughput nanopattern, the NWA electrode was fabricated on Si wafer by krypton-fluoride (KrF) stepper semiconductor process. Finally, 12,500,000 ea nanowell with a 500 nm diameter was fabricated on 4 mm × 2 mm substrate. Next, by using these electrodes, we measured impedance to quantify antigen binding to the immunoaffinity layer. The limit of detection (LOD) of the NWA was improved about 100-fold compared to milli-sized electrodes (4 mm × 2 mm) without an NWA. These results suggest that wafer-scale NWA immunosensor will be useful for biosensing applications because their interface response is appropriate for detecting molecular binding events. PMID:24013070