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Sample records for vlsi technology wafers

  1. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

  2. Evaluation of VLSI technology

    NASA Astrophysics Data System (ADS)

    Surace, G.; Prior, B. J.; Beasley, K.; Taylor, D. G.; Pengelly, R. S.

    1984-04-01

    Silicon and GaAs VLSI parameters are tabulated. The capability of Europe, America, and Japan in VLSI technology are compared and trends are outlined. Integrated circuit (IC) custom design methodologies; gate arrays, standard cell, and full custom are highlighted and foreseen development costs with each design route are shown. Use of VLSI technology in satellite subsystems is considered. A time division multiple access system is discussed. The front end GaAs regenerative repeater and the baseband processor systems are considered with chip counts and power dissipation estimates given for each subsystem. Further systems include a multicarrier demodulator and a transmitter and soft decision receiver structures for correlative phase modulation techniques. The performance of functional blocks such as ROMs, and multipliers is studied. Work necessary to carry the subsystems to implementation in IC form, and development routes for each IC are identified.

  3. High speed synchronizer card utilizing VLSI technology

    NASA Technical Reports Server (NTRS)

    Speciale, Nicholas; Wunderlich, Kristin

    1988-01-01

    A generic synchronizer card capable of providing standard NASA communication block telemetry frame synchronization and quality control was fabricated using VLSI technology. Four VLSI chip sets are utilized to shrink all the required functions into a single synchronizer card. The application of VLSI technology to telemetry systems resulted in an increase in performance and a decrease in cost and size.

  4. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  5. Advancements in bipolar VLSI circuits and technologies

    NASA Astrophysics Data System (ADS)

    Wiedmann, S. K.

    1984-06-01

    This paper gives an overview on bipolar circuit/device techniques for VLSI logic and memories. Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic (TTL) and emitter-coupled logic (ECL) are still mainly applied, but also new circuit technologies such as integrated injection logic or merged transistor logic (I2L/MTL) and Schottky transistor logic (STL) or integrated Schottky logic (ISL) have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected by technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 micron dimensions or below. Some experimental data and projections indicate the strong potentials of bipolar VLSI.

  6. A TECHNOLOGY FOR MONOLITHIC INTEGRATION OF COMMERCIAL MESFET VLSI ELECTRONICS

    E-print Network

    Shenoy, Krishna V.

    WB2.5 A TECHNOLOGY FOR MONOLITHIC INTEGRATION OF COMMERCIAL MESFET VLSI ELECTRONICS R.J. Aggarwal heterostructures and commercial VLSI GaAs circuits. We have designed a monolithic resonant-tunneling diode- (RTD-line graph of the diode chain storage element. veloped at MIT [3, 41. This technology enables the monolithic

  7. Wafer Slicing and Wire Saw Manufacturing Technology I. Kao (PI)

    E-print Network

    Kao, Imin

    Wafer Slicing and Wire Saw Manufacturing Technology I. Kao (PI) and V. Prasad, J. Li, M. Bhagavat to cut very thin wafers from large diameter crystalline ingots of semiconductor materials, has emerged as a leading technology for wafer production in semiconductor and photovoltaic industry. Nevertheless, the wire

  8. National solar technology roadmap: Wafer-silicon PV

    SciTech Connect

    Sopori, Bhushan

    2007-06-01

    This report applies to all bulk-silicon-based PV technologies, including those based on Czochralski, multicrystalline, float-zone wafers, and melt-grown crystals that are 100 ?m or thicker, such as ribbons, sheet, or spheral silicon.

  9. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    ERIC Educational Resources Information Center

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  10. ADVANCED PLASMA-ETCHING PROCESSES FOR DIELECTRIC MATERIALS IN VLSI TECHNOLOGY

    E-print Network

    Pearton, Stephen J.

    ADVANCED PLASMA-ETCHING PROCESSES FOR DIELECTRIC MATERIALS IN VLSI TECHNOLOGY By JUAN JUAN WANG ....................................................................................... 22 2.4 Further Disscussion for Plasma Etching)........................................... 1 1.2 Challenges of Etching Processes for Dielectric Materials

  11. Comparison of the radiation hardness of various VLSI technologies for defense applications

    SciTech Connect

    Gibbon, C.F.

    1985-01-01

    In this review the radiation hardness of various potential very large scale (VLSI) IC technologies is evaluated. IC scaling produces several countervailing trends. Reducing vertical dimensions tends to increase total dose hardness, while reducing lateral feature sizes may increase susceptibility to transient radiation effects. It is concluded that during the next decade at least, silicon complimentary MOS (CMOS), perhaps on an insulating substrate (SOI) will be the technology of choice for VLSI in defense systems.

  12. GaAs VLSI technology and circuit elements for DSP

    NASA Astrophysics Data System (ADS)

    Mikkelson, James M.

    1990-10-01

    Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

  13. Post exposure bake unit equipped with wafer-shape compensation technology

    NASA Astrophysics Data System (ADS)

    Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

    2007-03-01

    In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

  14. Deep sub-micron stud-via technology for superconductor VLSI circuits

    NASA Astrophysics Data System (ADS)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-05-01

    A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/?m2 and approaches the depairing current density of Nb films.

  15. Deep sub-micron stud-via technology of superconductor VLSI circuits

    NASA Astrophysics Data System (ADS)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-02-01

    A fabrication process has been developed for fully planarized Nb-based superconducting interlayer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of etched contact holes in the interlayer dielectric it employs etched and planarized Nb pillars (studs) as connectors between adjacent wiring layers. Detailed results are presented for one version of the process that utilizes Nb/Al/Nb trilayers for each wiring layer instead of single Nb wiring layers. Nb studs are etched in the top layer of the trilayer to provide vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A ?m-2 and approaches the depairing current density of Nb films.

  16. A LOW COST WAFER-LEVEL MEMS PACKAGING TECHNOLOGY Pejman Monajemi, Paul J. Joseph*

    E-print Network

    Ayazi, Farrokh

    A LOW COST WAFER-LEVEL MEMS PACKAGING TECHNOLOGY Pejman Monajemi, Paul J. Joseph* , Paul A. Kohl-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied

  17. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  18. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  19. Wafer-Level Packaging Technology for RF Applications Based on a Rigid Low-Loss Spacer

    E-print Network

    Technische Universiteit Delft

    Wafer-Level Packaging Technology for RF Applications Based on a Rigid Low-Loss Spacer Substrate Alexander Polyakov #12;#12;Wafer-Level Packaging Technology for RF Applications Based on a Rigid Low Dr. N.J.A. van Veen, Koninklijke Philips Electronics N.V. Prof. Dr.-Ing. H. Sandmaier, Universität

  20. Assessing Merged DRAM/Logic Technology Submitted to Integration, the VLSI Journal

    E-print Network

    Ayers, Joseph

    Assessing Merged DRAM/Logic Technology Submitted to Integration, the VLSI Journal Yong-Bin Kim the impact of DRAM process on the logic circuit performance of Memory/Logic Merged Integrated Circuit simulations have been performed to study the logic circuit performance degradation when the merged chip

  1. 1144 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 10, OCTOBER 2007 Wafer-Level Modular Testing of Core-Based SoCs

    E-print Network

    Chakrabarty, Krishnendu

    2007 Wafer-Level Modular Testing of Core-Based SoCs Sudarshan Bahukudumbi, Student Member, IEEECs. To reduce packaging cost and the test cost for pack- aged chips, wafer-level testing (wafer sort) is used constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can

  2. A VLSI implementation of DCT using pass transistor technology

    NASA Technical Reports Server (NTRS)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  3. Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

    2015-02-01

    The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

  4. 3D micro-optical lens scanner made by multi-wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Bargiel, S.; Gorecki, C.; Bara?ski, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frömel, J.

    2013-03-01

    We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

  5. High transmittance silicon terahertz polarizer using wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Yu, Ting-Yang; Tsai, Hsin-Cheng; Wang, Shiang-Yu; Luo, Chih-Wei; Chen, Kuan-Neng

    2015-08-01

    Due to the difficulties faced in fabricating robust Terahertz (THz) optical components with low Fresnel reflection loss, the need to increase the efficiency of THz system with reduced cost is still considered as one of the most essential tasks. In this report, a new low cost THz polarizer with robust structure is proposed and demonstrated. This new THz wire grid polarizer was based on an anti-reflection (AR) layer fabricated with low temperature metal bonding and deep reactive ion etching (DRIE). After patterning Cu wire gratings and the corresponding In/Sn solder ring on the individual silicon wafers, the inner gratings were sealed by wafer-level Cu to In/Sn guard ring bonding, providing the protection against humidity oxidation and corrosion. With the low eutectic melting point of In/Sn solder, wafers could be bonded face to face below 150°C. Two anti-reflection layers on both outward surfaces were fabricated by DRIE. With the mixing of empty holes and silicon, the effective refractive index was designed to be the square root of the silicon refractive index. The central frequency of the anti-reflection layers was designed between 0.5THz to 2THz with an approximate bandwidth of 0.5THz. The samples were measured with a commercial free-standing wire grid polarizer by a THz time domain spectroscopy (THz-TDS) from 0.2THz to 2.2THz. The power transmittance is close to 100% at central frequency. Extinction ratio of the polarizer is between 20dB to 40dB depending on the frequency. The advantages of this new polarizer include high transmittance, robust structure and low cost with no precision optical alignment required.

  6. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300?mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700?cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  7. Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Shi, Fang Frank

    Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

  8. Product assurance technology for custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

    1985-01-01

    The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

  9. High data rate Reed-Solomon encoding and decoding using VLSI technology

    NASA Technical Reports Server (NTRS)

    Miller, Warner; Morakis, James

    1987-01-01

    Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

  10. A Novel VLSI Technology to Manufacture High-Density Thermoelectric Cooling Devices

    E-print Network

    H. Chen; L. Hsu; X. Wei

    2008-01-07

    This paper describes a novel integrated circuit technology to manufacture high-density thermoelectric devices on a semiconductor wafer. With no moving parts, a thermoelectric cooler operates quietly, allows cooling below ambient temperature, and may be used for temperature control or heating if the direction of current flow is reversed. By using a monolithic process to increase the number of thermoelectric couples, the proposed solid-state cooling technology can be combined with traditional air cooling, liquid cooling, and phase-change cooling to yield greater heat flux and provide better cooling capability.

  11. NASA VLSI 2007 Mohanty, Vadlamudi and

    E-print Network

    Mohanty, Saraju P.

    NASA VLSI 2007 Mohanty, Vadlamudi and Kougianos 1 A Universal Voltage Level Converter for Multi University of North Texas dhruva@unt.edu #12;NASA VLSI 2007 Mohanty, Vadlamudi and Kougianos 2 Agenda Custom layout design at 90nm technology Conclusion and future works #12;NASA VLSI 2007 Mohanty, Vadlamudi

  12. Engineering strained silicon on insulator wafers with the Smart Cut TM technology

    NASA Astrophysics Data System (ADS)

    Ghyselen, B.; Hartmann, J.-M.; Ernst, T.; Aulnette, C.; Osternaud, B.; Bogumilowicz, Y.; Abbadie, A.; Besson, P.; Rayssac, O.; Tiberj, A.; Daval, N.; Cayrefourq, I.; Fournel, F.; Moriceau, H.; Di Nardo, C.; Andrieu, F.; Paillard, V.; Cabié, M.; Vincent, L.; Snoeck, E.; Cristiano, F.; Rocher, A.; Ponchet, A.; Claverie, A.; Boucaud, P.; Semeria, M.-N.; Bensahel, D.; Kernevez, N.; Mazure, C.

    2004-08-01

    Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI wafers and/or bulk-like strained Si layers. This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the Smart Cut TM technology can be used to obtain good quality tensile-strained silicon on insulator wafers. Such a technique uses preferentially hydrogen implantation to peel-off the very top part of an epitaxial stack and transfer it onto another silicon substrate. The formation of an insulator, prior to the bonding onto a new silicon substrate enables the formation of a "semiconductor on insulator" structure. Two approaches based on the Smart Cut technique are considered in this paper. The first one relies on the formation by layer transfer of a relaxed SiGe on insulator ("SGOI") substrate on which a tensile-strained Si layer is then grown. The second one is based on the transfer of a SiGe relaxed buffer/Si cap stack. A SiGe-free tensile-silicon on insulator (sSOI) substrate is then obtained after the selective etching of the top SiGe layer. The epitaxial layers studied in this article are of two kinds: (i) the thick, nearly fully relaxed SiGe layers (with or without tensile-strained Si layers on top depending on the final structure targeted: SGOI or sSOI) used as the donor wafers in layer transfer operations, and (ii) the thin, relaxed SiGe layers and the thin, tensile-strained Si epitaxial films grown on SGOI substrates. In-depth physical characterizations of these epitaxial layers are used to evaluate the quality of the transferred layers in terms of thickness uniformity, Ge content, strain control, dislocation densities etc… Detailed experiments are also used to demonstrate that these final substrates are compatible with future CMOS applications. The sSOI approach is particularly challenging in this respect as the strain needs to be maintained during many technological operations such as layer transfer, selective removal of the SiGe, high temperature thermal treatments etc. First results showing how the strain is changing during such operations are presented.

  13. Technological platform for vertical multi-wafer integration of miniature imaging instruments

    NASA Astrophysics Data System (ADS)

    Bargiel, S.; Baranski, M.; Passilly, N.; Gorecki, C.; Wiemer, M.; Frömel, J.; Wünsch, D.; Wang, W.-.

    2015-02-01

    We describe a technological platform developed for miniaturization of optical imaging instruments, such as laser scanning confocal microscopes or Optical Coherence Tomography devices. The platform employs multi-wafer vertical integration approach, combined with integrated glass-based micro-optics and heterogeneous bonding and interconnecting technologies. In this paper we focus on the unconventional fabrication methods of monolithic micro-optical structures and components in borosilicate glass (e.g. micro beamsplitters, refractive microlenses) for optical beam shaping and routing. In addition, we present hybrid laser-assisted integration of glass ball microlenses on the silicon MEMS actuators for transmissive beam scanning as well as methods of electrical signals distribution through thick glass substrates, based on HF etched via holes.

  14. Thin-film encapsulation technology for above-IC MEMS wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Zhang, Qing; Cicek, Paul-Vahé; Nabki, Frederic; El-Gamal, Mourad

    2013-12-01

    This work presents a low-cost and low-temperature wafer-level packaging solution for microelectromechanical systems (MEMS) devices. Heat-sensitive polymer poly(propylene carbonate) is used as the sacrificial material to release the capping layer in a clean and fast manner. Free-standing caps made of amorphous silicon carbide films and as large as 450 µm in diameter are successfully fabricated. To demonstrate the validity of this technology, surface-micromachined Pirani vacuum gauges are fabricated as an example of MEMS devices and encapsulated. Capped Pirani gauges respond to pressure between 1 mTorr and 1 atm. The Pirani gauges are sealed with Parylene C films that exhibit near-hermetic properties and the initial sealing pressure for 300 µm diameter cavities is characterized to be in the range of tens of torr.

  15. Sensitivity analysis of add-on price estimate for select silicon wafering technologies

    NASA Technical Reports Server (NTRS)

    Mokashi, A. R.

    1982-01-01

    The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

  16. Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes

    NASA Astrophysics Data System (ADS)

    Peterson, Joel; Rusk, Gary; Veeraraghavan, Sathish; Huang, Kevin; Koffas, Telly; Kimani, Peter; Sinha, Jaydeep

    2015-03-01

    The semiconductor industry continues to push the limits of immersion lithography through multiple patterning techniques for printing features with critical dimension 20 nm and below. As a result overlay has become one of the critical lithography control parameters impacting device performance and has a stringent budget for yielding at smaller half pitch nodes. Overlay has several sources of errors related to scanner, lens, mask, and wafer. Lithographers have developed both linear and higher order field and wafer models to successfully compensate for the static fingerprints from different sources of error. After the static modeled portion of the fingerprint is removed, the remaining overlay error can be characterized as unstable modeled error or un-modeled error, commonly called uncorrectable residual error. This paper explores the fundamental relationship of overlay to wafer geometry through mechanisms of process-induced contributions to the wafer overlay, categorized as plastic and elastic wafer deformation. Correlation of overlay to local features such as slip lines is proven experimentally. The paper describes methodologies and geometry-induced overlay metrics for the application of wafer geometry to perform overlay feedback and feed forward applications. Feedback applications allow for process development and controlling semiconductor processes through in-line monitoring of wafers. Feed forward applications could include geometrybased corrections to the scanner for compensating non-static wafer geometry related overlay errors, and grouping wafers based on higher-order geometry.

  17. Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing

    NASA Astrophysics Data System (ADS)

    Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

    2005-09-01

    The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore the capability of the tool for characterizing multiple geometric parameters associated with the manufacturing process that are important to the yield and performance of advanced bottle DRAM devices.

  18. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  19. Security Challenges During VLSI Test David Hely

    E-print Network

    Cortes, Corinna

    leak information about the chip design. In an attacker's hands, the controllability provided by testSecurity Challenges During VLSI Test David H´ely LCIS Grenoble Institute of Technology Valence@poly.edu Abstract--VLSI testing is a practical requirement, but unless proper care is taken, features that enhance

  20. VLSI array processor

    NASA Astrophysics Data System (ADS)

    Greenwood, E.

    1982-07-01

    The Arithmetic Processor Unit (APU) data base design check was completed. Minor design rule violations and design improvements were accomplished. The APU mask set has been fabricated and checked. Initial checking of all mask layers revealed a design rule problem in one layer. That layer was corrected, refabricated and checked out. The mask set has been delivered to the chip fabrication area. The fabrication process has been initiated. All work on the Array Processor Demonstration System (APDS) has been suspended at CHI until the additionally requested funding was received. That funding has been authorized and CHI will begin work on the APDS in July. The following activities are planned in the following quarter: 1) Complete fabrication of the first lot of VLSI APU devices. 2) Complete integration and check-out of the APDS simulator. 3) Complete integration and check-out of the APU breadboard. 4) Verify the VLSI APU wafer tests with the APU breadboard. 5) Complete check-out of the APDS using the APU breadboard.

  1. Wafer bonding technology for new generation vacuum MEMS: challenges and promises

    NASA Astrophysics Data System (ADS)

    Dragoi, V.; Pabo, E.

    2015-05-01

    Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding process and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding processes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glass frit bonding and metal-based bonding. The outgassing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgassing. Additionally the selected bonding process must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each process for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for process characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addressed will be introduced with examples.

  2. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Luo, Xianshu; Cao, Yulian; Song, Junfeng; Hu, Xiaonan; Cheng, Yungbing; Li, Chengming; Liu, Chongyang; Liow, Tsung-Yang; Yu, Mingbin; Wang, Hong; Wang, Qijie; Lo, Patrick Guo-Qiang

    2015-04-01

    Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS) fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W) bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP) laser, lateral-coupled distributed feedback (LC-DFB) laser with side wall grating, and mode-locked laser (MLL). From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC).

  3. APPLIED PHYSICS REVIEWSFOCUSED REVIEW Adhesive wafer bonding

    E-print Network

    Lü, James Jian-Qiang

    APPLIED PHYSICS REVIEWS­FOCUSED REVIEW Adhesive wafer bonding F. Niklausa Microsystem Technology 9 February 2006 Wafer bonding with intermediate polymer adhesives is an important fabrication-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive

  4. Study on the use of VLSI ASIC technology for generic power system computer relay architectures 

    E-print Network

    Faulkner, Kenneth Ray

    1994-01-01

    This thesis discusses the feasibility of improving power system computer relay devices using Very Large Scale Integration technology. It outlines the functionality that is required of this equipment A high-level design that attempts to use dedicated...

  5. Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding

    E-print Network

    Spearing, S. Mark

    Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

  6. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  7. Wafer to wafer overlay control algorithm implementation based on statistics

    NASA Astrophysics Data System (ADS)

    Lee, Byeong Soo; Kang, Young Seog; Kong, Jeong Heung; Hwang, Hyun Woo; Song, Myeong Gyu

    2015-03-01

    For mass production of DRAM device, a stable and effective overlay control becomes more and more important as DRAM design rule shrinks. Existent technologies were already applied to overcome this situation. Nevertheless, we are still suffered from tight overlay margin and forced to move from lot-based to wafer-based overlay control. However, the wafer-based control method requires a huge amount of measurement resource. In this paper, we present the insight for the wafer-based overlay correction with optimal measurement resource which is suitable for mass production. The experiment which is the wafer-based overlay correction by several statistical analyses carried out for 2X nm node DRAM. Among them, linear regression is a strong candidate for wafer-based overlay control, which improved up to 0.8 nm of maximum overlay.

  8. VLSI research

    NASA Astrophysics Data System (ADS)

    Brodersen, R. W.

    1984-04-01

    A scaled version of the RISC II chip has been fabricated and tested and these new chips have a cycle time that would outperform a VAX 11/780 by about a factor of two on compiled integer C programs. The architectural work on a RISC chip designed for a Smalltalk implementation has been completed. This chip, called SOAR (Smalltalk On a RISC), should run program s4-15 times faster than the Xerox 1100 (Dolphin), a TTL minicomputer, and about as fast as the Xerox 1132 (Dorado), a $100,000 ECL minicomputer. The 1983 VLSI tools tape has been converted for use under the latest UNIX release (4.2). The Magic (formerly called Caddy) layout system will be a unified set of highly automated tools that cover all aspects of the layout process, including stretching, compaction, tiling and routing. A multiple window package and design rule checker for this system have just been completed and compaction and stretching are partially implemented. New slope-based timing models for the Crystal timing analyzer are now fully implemented and in regular use. In an accuracy test using a dozen critical paths from the RISC II processor and cache chips it was found that Crystal's estimates were within 5-10% of SPICE's estimates, while being a factor of 10,000 times faster.

  9. 3D integration approaches for MEMS and CMOS sensors based on a Cu through-silicon-via technology and wafer level bonding

    NASA Astrophysics Data System (ADS)

    Hofmann, L.; Dempwolf, S.; Reuter, D.; Ecke, R.; Gottfried, K.; Schulz, S. E.; Knechtel, R.; Geßner, T.

    2015-05-01

    Technologies for the 3D integration are described within this paper with respect to devices that have to retain a specific minimum wafer thickness for handling purposes (CMOS) and integrity of mechanical elements (MEMS). This implies Through-Silicon Vias (TSVs) with large dimensions and high aspect ratios (HAR). Moreover, as a main objective, the aspired TSV technology had to be universal and scalable with the designated utilization in a MEMS/CMOS foundry. Two TSV approaches are investigated and discussed, in which the TSVs were fabricated either before or after wafer thinning. One distinctive feature is an incomplete TSV Cu-filling, which avoids long processing and complex process control, while minimizing the thermomechanical stress between Cu and Si and related adverse effects in the device. However, the incomplete filling also includes various challenges regarding process integration. A method based on pattern plating is described, in which TSVs are metalized at the same time as the redistribution layer and which eliminates the need for additional planarization and patterning steps. For MEMS, the realization of a protective hermetically sealed capping is crucial, which is addressed in this paper by glass frit wafer level bonding and is discussed for hermetic sealing of MEMS inertial sensors. The TSV based 3D integration technologies are demonstrated on CMOS like test vehicle and on a MEMS device fabricated in Air Gap Insulated Microstructure (AIM) technology.

  10. Innovative design methodology for implementing heterogeneous multiprocessor architectures in VLSI

    SciTech Connect

    Tientien Li

    1983-01-01

    Considering the design cost of today's VLSI systems, advanced VLSI technology may not be cost-effective for implementing complex computer systems. In the paper, an innovative design approach which can drastically reduce the cost of implementing heterogeneous multiprocessor architectures in VLSI is presented. The author introduces high-level architectural design tools for assisting the design of multiprocessor systems with distributed memory modules and communication networks, and presents a logic/firmware synthesis scheme for automatically implementing multitasking structures and system service functions for multiprocessor architectures. Furthermore, the importance of the firmware synthesis aspect of VLSI system design is emphasized. Most logic of complex VLSI systems can be implemented very easily in firmware using the design approach introduced here. 10 references.

  11. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  12. Performance and power optimization in VLSI physical design 

    E-print Network

    Jiang, Zhanyuan

    2009-05-15

    As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic ...

  13. Design for manufacturing (DFM) in submicron VLSI design 

    E-print Network

    Cao, Ke

    2009-05-15

    As VLSI technology scales to 65nm and below, traditional communication between design and manufacturing becomes more and more inadequate. Gone are the days when designers simply pass the design GDSII ?le to the foundry and ...

  14. Performance and power optimization in VLSI physical design 

    E-print Network

    Jiang, Zhanyuan

    2008-10-10

    As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic ...

  15. Algorithmic techniques for nanometer VLSI design and manufacturing closure 

    E-print Network

    Hu, Shiyan

    2008-10-10

    As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip and power density. Imperfections due to process, ...

  16. VLSI Interconnect Optimization Considering Non-uniform Metal Stacks 

    E-print Network

    Tsai, Jung-Tai

    2013-08-01

    With the advances in process technology, comes the domination of interconnect in the overall propagation delay in modern VLSI designs. Hence, interconnect synthesis techniques, such as buffer insertion, wire sizing and layer assignment play critical...

  17. Computation in Neuromorphic Analog VLSI Giacomo Indiveri

    E-print Network

    containing electronic analog circuits that mimic neuro- biological architectures present in the nervous "neuromorphic" has also been used to describe mixed analog/digital VLSI systems that implement computational mean consumption of less than 10 watts. By comparison today's silicon digital technology can dissipate

  18. VLSI Universal Noiseless Coder

    NASA Technical Reports Server (NTRS)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  19. IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY, VOL. 9, NO. 2, MARCH 2001 381 Multivariable Feedback Relevant System Identification of a Wafer Stepper

    E-print Network

    Van den Hof, Paul

    Feedback Relevant System Identification of a Wafer Stepper System Raymond A. de Callafon and Paul M. J. Van of a positioning mechanism present in a wafer stepper. The positioning mechanism in a wafer stepper is used in chip manufacturing processes for accurate posi- tioning of the silicon wafer on which the chips are to be produced

  20. The 1992 4th NASA SERC Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  1. NASA Space Engineering Research Center for VLSI System Design

    NASA Technical Reports Server (NTRS)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  2. VLSI physical design analyzer: A profiling and data mining tool

    NASA Astrophysics Data System (ADS)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  3. Wafer capping of MEMS with fab-friendly metals

    NASA Astrophysics Data System (ADS)

    Martin, Jack

    2007-01-01

    Inertial MEMS (Micro Electro Mechanical System) sensors are normally sealed in hermetic enclosures. Some are assembled in hermetic packages but wafer level packaging has become much more important in recent years. Anodic bonding can be used to achieve wafer level seals between silicon and glass but most suppliers of inertial sensors screen print glass frit onto silicon cap wafers. After removing the organic vehicle, these patterned cap wafers are sealed to device wafer prior to wafer singulation and plastic packaging. Anodic and glass frit bonding are both cost-effective. However, they impose size, quality and performance limitations. Wafer level sealing with a metal removes some of these limitations but introduces other concerns. This paper will review the current wafer level hermetic processes followed by a description of a thermocompression metal seal technology that is compatible with IC fabrication.

  4. MultiProject Reticle Floorplanning and Wafer Dicing # Andrew B. Kahng, Ion M

    E-print Network

    Kahng, Andrew B.

    Multi­Project Reticle Floorplanning and Wafer Dicing # Andrew B. Kahng, Ion M â?? andoiu + , Qinke@engr.uconn.edu, alexz@cs.gsu.edu ABSTRACT Multi­project Wafers (MPW) are an efficient way to share the rising costs­project reticle floorplanning and wafer dicing problems under the prevalent side­ to­side wafer dicing technology

  5. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  6. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  7. Wafer bonding for optoelectronic devices

    NASA Astrophysics Data System (ADS)

    Wu, Yew-Chung Sermon

    A periodic GaAs wafer-bonded structure has been proposed for quasi-phase-matched (QPM) second harmonic generation (SHG). The basic bonding technology involves elevated temperatures and pressures, which can lead to unacceptable optical losses and poor device performance. Three sources of optical losses were first found in this study: (1) decomposition at the exposed surface, (2) interfacial defects between the bonded wafers, and (3) bulk defects within the wafers. Bulk and surface defects were studied by measuring the optical transmission through single GaAs. It was found that an increase in bonding temperature and/or time led to an increase in the bulk and surface defects. An increase in the free hole concentration (thermal conversion) is though to be the major cause of the optical losses by a free carrier absorption mechanism. Since it was difficult to eliminate free-carrier and interfacial defect losses once they have formed because of diffusion kinetic limitations, processing conditions that minimized their formation were sought. In contrast, defects on the external surfaces caused by arsenic depletion resulting from incongruent evaporation were easily eliminated by repolishing. Interfacial defects were studied by introducing artificial voids into the interface region by bonding topographically-patterned GaAs wafers to unpatterned wafers. We found that the filling of these artificial voids depended strongly on the magnitude of the height of the surface irregularities on the wafer interfaces, as well as on temperature and time. Typically, when bonding temperature and time were increased, the interfacial defect density decreased. After bonding, two kinds of features corresponding to the newly bonded areas were observed by IR microscopy. These two features, having diamond and dendrite geometries, were shown to depend on both surface energy anisotropy and growth rate anisotropy. An investigation of the relationship between bonding conditions (temperature, time and pressure) and optical losses (resulting from bulk, interfacial and surface defects), has led to the development of an optimized process for preparing periodic GaAs structures useful in quasi-phase-matched second harmonic generation applications. With this bonding process, low optical loss (~0.1-0.3%/interface) wafer-bonded (110) structures (containing up to 40 layers) for practical device applications were first fabricated in this study.

  8. Dictionary machine (for VLSI)

    SciTech Connect

    Ottmann, T.A.; Rosenberg, A.L.; Stockmeyer, L.J.

    1982-09-01

    The authors present the design of a dictionary machine that is suitable for VLSI implementation, and discusses how to realize this implementation efficiently. The machine supports the operations of search, insert, delete, and extractment on an arbitrary ordered set. Each of these operations takes time o(logn), where n is the number of entries present when the operation is performed. Moreover, arbitrary sequences of these instructions can be pipelined through the machine at a constant rate (i.e. independent of n and the capacity of the machine). The time o(logn) is an improvement over previous VLSI designs of dictionary machines which require time o(log n) per operation, where n is the maximum number of keys that can be stored. 10 references.

  9. Extremely long life and low-cost 193nm excimer laser chamber technology for 450mm wafer multipatterning lithography

    NASA Astrophysics Data System (ADS)

    Tsushima, Hiroaki; Katsuumi, Hisakazu; Ikeda, Hiroyuki; Asayama, Takeshi; Kumazaki, Takahito; Kurosu, Akihiko; Ohta, Takeshi; Kakizaki, Kouji; Matsunaga, Takashi; Mizoguchi, Hakaru

    2014-04-01

    193nm ArF excimer lasers are widely used as light sources for the lithography process of semiconductor production. 193nm ArF exicmer lasers are expected to continue to be the main solution in photolithography, since advanced lithography technologies such as multiple patterning and Self-Aligned Double Patterning (SADP) are being developed. In order to apply these technologies to high-volume semiconductor manufacturing, the key is to reduce the total operating cost. To reduce the total operating cost, life extension of consumable part and reduction of power consumption are an important factor. The chamber life time and power consumption are a main factor to decide the total operating cost. Therefore, we have developed the new technology for extension of the chamber life time and low electricity consumption. In this paper, we will report the new technology to extend the life time of the laser chamber and to reduce the electricity consumption.

  10. Titanic: a VLSI based content addressable parallel array processor

    SciTech Connect

    Weems, C.; Levitan, S.; Foster, C.

    1982-01-01

    A design is presented for a content addressable parallel array processor (CAPAP) which is both practical and feasible. Its practicality stems from an extensive program of research into real applications of content addressability and parallelism. The feasibility of the design stems from development under a set of conservative engineering constraints tied to limitations of VLSI technology. 1 ref.

  11. Wafer characteristics via reflectometry

    SciTech Connect

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  12. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  13. Electrical characterization of annular Through Silicon Vias for a Reconfigurable Wafer-sized Circuit Board

    E-print Network

    Hamoui, Anas

    Electrical characterization of annular Through Silicon Vias for a Reconfigurable Wafer characterization of annular TSV technology for full wafer applications. A possible utilization of this technology is the WaferBoardTM , a reconfigurable circuit board for rapid system prototyping. Electrical resistance

  14. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  15. Holographic optical interconnects for VLSI

    NASA Technical Reports Server (NTRS)

    Bergman, L. A.; Wu, W. H.; Johnston, A. R.; Nixon, R.; Esener, Sadik C.

    1986-01-01

    This paper introduces new applications and design trade-offs anticipated for free-space optical interconnections of VLSI chips. New implementation s of VLSI functions are described that use the capability of making optical inputs at any point on a chip and take advantage of greater flexibility in on-chip signal routing. These include n-port addressable memories, CPU clock phase distribution, hardware multipliers, and dynamic memory refresh, as well as enhanced testability. Fault tolerance and production yields may be improved by reprogramming the optical imaging system to circumvent defective elements. These attributes, as well as those related to performance alone, will affect the design methodology of future VLSI ICs. This paper focuses on identifying the design issues, their possible solutions, and their impact on VLSI design techniques and, finally, presents some preliminary measurements on various system components.

  16. VLSI Architectures for Computing DFT's

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  17. Neural Networks Of VLSI Components

    NASA Technical Reports Server (NTRS)

    Eberhardt, Silvio P.

    1991-01-01

    Concept for design of electronic neural network calls for assembly of very-large-scale integrated (VLSI) circuits of few standard types. Each VLSI chip, which contains both analog and digital circuitry, used in modular or "building-block" fashion by interconnecting it in any of variety of ways with other chips. Feedforward neural network in typical situation operates under control of host computer and receives inputs from, and sends outputs to, other equipment.

  18. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  19. Compressive Computation in Analog VLSI Motion Sensors

    E-print Network

    Deutschmann, Rainer

    Compressive Computation in Analog VLSI Motion Sensors Rainer A. Deutschmann1 and Oliver G. Wenisch2 analog VLSI mo- tion sensors developed in the past. We show how their pixel-parallel architecture can is best suited to perform the algorithm even at high noise levels. 1 Analog VLSI Motion Sensors Inthe past

  20. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  1. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  2. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  3. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  4. Test-Pattern Ordering for Wafer-Level Test-During-Burn-In

    E-print Network

    Chakrabarty, Krishnendu

    Test-Pattern Ordering for Wafer-Level Test-During-Burn-In Sudarshan Bahukudumbi and Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University, Durham, NC 27708 Abstract--Wafer [1]. Wafer level burn-in (WLBI) has recently emerged as an enabling technology to lower the cost

  5. Modeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen H. Garofalinia)

    E-print Network

    Garofalini, Stephen H.

    Modeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen for publication 31 December 2000 The role of moisture in hydrophilic wafer bonding was modeled using molecular Institute of Physics. DOI: 10.1063/1.1351538 I. INTRODUCTION Wafer bonding technology takes advantage

  6. Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors

    E-print Network

    Zhou, Chongwu

    Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications compatibility. Here in this paper, we report our progress on wafer-scale processing of separated nanotube thin-film transistors (SN-TFTs) for display applications, including key technology components such as wafer

  7. Non-Wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-bit

    E-print Network

    International Association for Cryptologic Research (IACR)

    Non-Wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-bit Willi to be about 2 to 3.5 times slower than TWIRL (a wafer-scale design). Due to the more moderate technological. ­ TWIRL [ST03,LTS+ 03] seems to be the currently best-explored design. Unfortunately, it is a wafer

  8. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  9. Quality procedures for VLSI/VHSIC (Very Large Scale Integrated and Very High Speed Integrated Circuits) type devices

    NASA Astrophysics Data System (ADS)

    Cohen, S.

    1985-11-01

    Procedures for microcircuit screening and qualification to ensure the reliability and uniformity of VLSI/VHSIC devices were prepared. The use of Process Control Monitors (PCM) and Reliability Evaluation Modules (REM) were incorporated in the procedures. In addition, recommended guidelines for the evaluation of Computer-Aided-Manufacturing (CAM) facilities were generated in this study. A proposed replacement was provided for existing Method 5007 to MIL-STD-883, Wafer Acceptance Procedure which incorporates reliability screening, process quality evaluation, and electrical parameter testing of each wafer in a lot.

  10. Wafer bonding : mechanics-based models and experiments

    E-print Network

    Turner, Kevin Thomas, 1977-

    2004-01-01

    Direct wafer bonding has emerged as an important technology in the manufacture of silicon-on-insulator substrates (SOI), microelectromechanical systems (MEMS), and three-dimensional integrated circuits (3D IC's). While the ...

  11. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  12. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

  13. 30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology

    NASA Technical Reports Server (NTRS)

    Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

    1986-01-01

    An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

  14. The Fifth NASA Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  15. Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization by Exploring Wafer-to-Wafer Correlation

    E-print Network

    Li, Xin

    Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization by Exploring Wafer-to-Wafer In this paper, we propose a new technique, referred to as Multi- Wafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Towards this goal, a novel Bayesian

  16. Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng, Ion Mandoiu, Qinke Wang, Xu Xu, and Alex Z. Zelikovsky

    E-print Network

    Zelikovsky, Alexander

    Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng, Ion Mandoiu, Qinke Wang, Xu@cs.gsu.edu ABSTRACT Multi-project Wafers (MPW) are an efficient way to share the rising costs of mask tooling between and wafer dicing problems under the prevalent side- to-side wafer dicing technology. Our contributions

  17. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  18. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  19. Wafer Post-Processing for a Reconfigurable Wafer-Scale Circuit Moufid Radji1

    E-print Network

    Hamoui, Anas

    Wafer Post-Processing for a Reconfigurable Wafer-Scale Circuit Board Moufid Radji1 , Ahmed Outaouais (3) Département d'Informatique, Université du Quebec à Montréal Abstract The WaferBoardTM rapid, performance and reliability constraints. At the core of WaferBoardTM is the WaferICTM , a wafer

  20. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  1. Silicon cast wafer recrystallization for photovoltaic applications

    E-print Network

    Hantsoo, Eerik T. (Eerik Torm)

    2008-01-01

    Current industry-standard methods of manufacturing silicon wafers for photovoltaic (PV) cells define the electrical properties of the wafer in a first step, and then the geometry of the wafer in a subsequent step. The ...

  2. VLSI Multivariate Phase Synchronization Epileptic Seizure Detector

    E-print Network

    Genov, Roman

    VLSI Multivariate Phase Synchronization Epileptic Seizure Detector Karim Abdelhalim, Vadim-- A low-power VLSI seizure detector is presented. It combines a 256-channel analog neural recording chip with in vitro epilepsy models, a low-cost technique to implement on-chip gold microelectrodes was utilized

  3. Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs

    E-print Network

    Chakrabarty, Krishnendu

    Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs Sudarshan Bahukudumbi.kacprowicz@intel.com Abstract--Wafer-level test during burn-in (WLTBI) has re- cently emerged as a promising technique to reduce result in high cost [1], [5]. Wafer level burn-in (WLBI) has recently emerged as an enabling technology

  4. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers

    NASA Astrophysics Data System (ADS)

    Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

    2009-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

  5. Wafer Fusion for Integration of Semiconductor Materials and Devices

    SciTech Connect

    Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

    1999-05-01

    We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

  6. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  7. Designing of Low-Power VLSI Circuits using Non-Clocked Logic Style

    NASA Astrophysics Data System (ADS)

    Sharma, Vishal; Srivastava, Jitendra Kaushal

    2012-08-01

    Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the vlsi circuits with the performance upto the acceptable level. The dominant term in a well designed vlsi circuit is the switching power and low-power design thus becomes the task of minimizing this switching power. So, to design a low-power vlsi circuit, it is preferable to use Nonclocked logic styles as they have less switching power. In this work various Non-clocked logic styles are compared by performing transistor level simulations for half adder circuit using TSMC 0.18 µm Technology and Eldo simulator of Mentor graphics.

  8. System for slicing wafers

    NASA Technical Reports Server (NTRS)

    1982-01-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  9. System for slicing wafers

    NASA Astrophysics Data System (ADS)

    1982-02-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  10. Wafer-Level Thermocompression Bonds

    E-print Network

    Tsau, Christine H.

    Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding without the application of an electric field or complicated pre-bond cleaning procedure. The presence of a ductile ...

  11. Spinner For Etching Of Semiconductor Wafers

    NASA Technical Reports Server (NTRS)

    Lombardi, Frank

    1989-01-01

    Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

  12. Wafer handling and placement tool

    DOEpatents

    Witherspoon, Linda L. (22 Cottonwood La., Los Lunas, NM 87031)

    1988-01-05

    A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

  13. The VLSI design of an error-trellis syndrome decoder for certain convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

    1986-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  14. The VLSI design of error-trellis syndrome decoding for convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

    1985-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  15. Warpage Measurement of Thin Wafers by Reflectometry

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

  16. VLSI Processor For Vector Quantization

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  17. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  18. [2] T.A. Chu, Synthesis of SelfTimed VLSI Circuits from Graphtheoretic Specifications, PhD thesis, Massachusetts Institute of Technology, 1987.

    E-print Network

    D thesis, Massachusetts Institute of Technology, 1987. [3] I. David, R. Ginosar, and M. Yoeli, ''Self. Acknowledgment This research was supported by an ONR Grant no. N00014­89­J­3036 and a Seed Grant from the Center

  19. Application of network coding for VLSI routing 

    E-print Network

    Nemade, Nikhil Pandit

    2009-05-15

    This thesis studies the applications of the network coding technique for intercon- nect optimization and improving the routability of Very-large-scale integration (VLSI) designs. The goal of the routing process is to connect the required sets...

  20. Reconfigurable VLSI architecture for a database processor

    SciTech Connect

    Oflazer, K.

    1983-01-01

    This work brings together the processing potential offered by regularly structured VLSI processing units and the architecture of a database processor-the relational associative processor (RAP). The main motivations are to integrate a RAP cell processor on a few VLSI chips and improve performance by employing procedures exploiting these VLSI chips and the system level reconfigurability of processing resources. The resulting VLSI database processor consists of parallel processing cells that can be reconfigured into a large processor to execute the hard operations of projection and semijoin efficiently. It is shown that such a configuration can provide 2 to 3 orders of magnitude of performance improvement over previous implementations of the RAP system in the execution of such operations. 27 refs.

  1. Software Structuring Principles for VLSI CAD

    E-print Network

    Katzenelson, Jacob

    1987-12-01

    A frustrating aspect of the frequent changes to large VLSI CAD systems is that so little of the old available programs can be reused. It takes too much time and effort to find the reusable pieces and recast them for ...

  2. Development of a 2 micrometer silicon-gate-CMOS-technology for microcomputer oriented VLSI circuits with a supply voltage range between 1.5 and 5 V

    NASA Astrophysics Data System (ADS)

    Fischer, G.; Kiss, T.; Kummerow, K.; Link, M.; Scharzmann, U.

    1984-10-01

    The processes necessary for a 2 micron CMOS-technology were developed, including projection lithography, the oxidation process, the fabrication of thin oxides, and dry etching techniques for patterning silicon nitride, polysilicon, silicon oxide, and aluminum. With the aid of process simulations and experimental results, a process flow chart was established. A test chip with a large number of single structures and circuit blocks was designed in 2 micron tubes. Different runs of this test chip are produced. The success of the developed technology is demonstrated on different logic circuit blocks.

  3. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L. (Denver, CO)

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  4. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  5. The 1991 3rd NASA Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Maki, Gary K.

    1991-01-01

    Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

  6. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  7. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R. (Berkeley, CA)

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  8. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  9. High-accuracy inspection of defects and profile of wafers by phase measuring deflectometry

    NASA Astrophysics Data System (ADS)

    Yue, Huimin; Wu, Yuxiang; Zhao, Biyu; Ou, Zhonghua; Liu, Yong

    2014-09-01

    The demands of the less-defective and high-flatness wafers are urgent in many wafer based technologies ranging from micro-electronics to the current photovoltaic industry. As the wafer becomes thinner and larger to cope with the advances in those industries, there is an increasing possibility of the emerging of crack and warp on the wafer surface. High-accuracy inspection of defects and profile are thus necessary to ensure the reliability of device. Phase measuring deflectometry(PMD) is a fast, cost-effective and high accuracy measurement technology which has been developed in recent years. As a slope measurement technology, PMD possesses a high sensitivity. Very small slope variation will lead to a large variation of the phase. PMD is very possible to have a good performance in the wafer inspection. In this paper, the requirements of the wafer inspection in the industries are discussed, and compatibility of PMD and those requirements is analyzed. In the experimental work, PMD gets the slope information of the wafer surface directly. The curvature or height information can be acquired simply by the derivation or integral of the slope. PMD is proved to make a superior result in high-precision defect detecting and shape measurement of wafer by the analysis of experiment results.

  10. Reliability of small geometry VLSI devices for microelectronics

    NASA Astrophysics Data System (ADS)

    White, Marvin H.

    1992-02-01

    This proposal is a continuation of a project which began in August 1986. The goal of the project, in a broad sense, is to perform exploratory research into the physics of carriers in silicon inversion layers with a focus on the issues which affect the reliability of small geometry VLSI devices. This project permits us to study the physical electronics of silicon surfaces and the overlying insulators. In the proposed project we stress the application of this research to the area of Wafer Scale Integration where reliability and fault tolerance are key issues for the SDI program. The extensive signal processing and data storage required to implement high-resolution, sensor-based systems demands that consideration be given to the area of system and component reliability. At the component level the issues revolve around the reliability of the scaled MOS Transistor with nanometric feature sizes. One important area is the susceptibility of the gate insulator to (1) hot electron trapping, (2) premature dielectric breakdown, and (3) space radiation environment considerations which can limit the MTTF of the SDIO mission. A second issue at the component level is the SDI need for low-power, high-density, nonvolatile data storage with nondestructive readout (NDRO), radiation tolerance and immunity to single event upsets (SEU's).

  11. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  12. Interferometric and confocal techniques for testing of silicon wafers

    NASA Astrophysics Data System (ADS)

    Galas, J.; Litwin, D.; Sitarek, S.; Surma, B.; Piatkowski, B.; Miros, A.

    2006-04-01

    The paper provides new insights into Silicon wafer measurements in context of technological problems of developing a sophisticated measurement technique, which harnesses helium atom beam as a probe. Nano-resolution imaging techniques such as scanning tunnelling microscopy (STM) and atomic force microscopy (AFM) are well-know in surface science. A scanning helium atom microscope, where a focused beam of low energy, neutral helium atoms is used as an imaging probe is a new concept creating non-destructive and non-invasive surface investigation tool in science and industry. This paper is focused on measurements of flatness and thickness of the wafer, which is used as a deflecting mirror of the helium beam. Two -optics based- measurement techniques are presented: scanning confocal system and the Fizeau interferometer. The latter is applied as a quick reference device placed close to the production line whereas the former offers high accuracy flatness and thickness maps of the wafers.

  13. Wafer scale packaging for a MEMS video scanner

    NASA Astrophysics Data System (ADS)

    Helsel, Mark P.; Barger, Jon; Wine, David W.; Osborn, Thor D.

    2001-04-01

    Miniaturized scanners have proven their usefulness in a host of applications including video display, bar code reading, image capture, laser printing and optical switching. In order for these applications to reach fruition, however, the MEMS scanner component must be packaged in a manner that is compatible with the volume manufacturing capabilities of the technology. This paper describes a process that was developed to package an SVGA resolution (800 X 600) biaxial video scanner. The scanner is designed for a head mounted display product, targeted to the medical and industrial markets. The scanner is driven magnetically on one axis and capacitively on the other axis. The first level wafer scale package described here incorporates the capacitive drive electrodes into the mounting substrate. The substrate wafer and the device wafer are then bonded using a glass frit sealing technique. Finally, the scanner and substrate are hermetically sealed into a metal can at reduced pressure.

  14. On-wafer magnetic resonance of magnetite nanoparticles

    NASA Astrophysics Data System (ADS)

    Little, Charles A. E.; Russek, Stephen E.; Booth, James C.; Kabos, Pavel; Usselman, Robert J.

    2015-11-01

    Magnetic resonance measurements of ferumoxytol and TEMPO were made using an on-wafer transmission line technique with a vector network analyzer, allowing for broadband measurements of small sample volumes (4 nL) and small numbers of spins (1 nmol). On-wafer resonance measurements were compared with standard single-frequency cavity-based electron paramagnetic resonance (EPR) measurements using a new power conservation approach and the results show similar line shape. On-wafer magnetic resonance measurements using integrated microfluidics and microwave technology can significantly reduce the cost and sample volumes required for EPR spectral analysis and allow for integration of EPR with existing lab-on-a-chip processing and characterization techniques for point-of-care medical diagnostic applications.

  15. NREL Core Program; Session: Wafer Silicon (Presentation)

    SciTech Connect

    Wang, Q.

    2008-04-01

    This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

  16. Silicon Wafer Processing Dr. Seth P. Bates

    E-print Network

    Colton, Jonathan S.

    Silicon Wafer Processing Dr. Seth P. Bates Applied Materials Summer, 2000 Objective To provide from blank silicon wafers. Goals The Transfer Plan provides a curriculum covering the process of manufacturing integrated circuits from the silicon wafer blanks, using the equipment manufactured by Applied

  17. ARCHITECTURE FOR AN aVLSI STEREO VISION SYSTEM Ralf M. Philipp1

    E-print Network

    Lewis, M. Anthony

    -computation architecture designed for, but not limited to, a single-chip current mode analog VLSI (aVLSI) implementation for a single-chip aVLSI implementation include accurately aligned mirrors [4] and a biprism [5]. This problem

  18. Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

    E-print Network

    Keast, Craig L.

    RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens ...

  19. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  20. Associative Pattern Recognition In Analog VLSI Circuits

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  1. VLSI complexity of parallel Fourier transform algorithms

    SciTech Connect

    Baradaran Seyed, T.

    1989-01-01

    Scope and method of study. The purpose of this study is to present a set of new parallel algorithms for discrete Fourier transform and compare the VLSI time and area complexity of the associated designs with the existing designs. The proposed parallel algorithms may be implemented easily in pipeline and mesh-connected parallel processing systems. Findings and conclusions. Several parallel algorithms have been proposed and associated cell layout for VLSI implementation have been presented. Comparative analysis shows that two of the designs presented by this study have better area-time performance than the existing designs in their architectural category.

  2. High performance LWIR microbolometer with Si/SiGe quantum well thermistor and wafer level packaging

    NASA Astrophysics Data System (ADS)

    Roer, Audun; Lapadatu, Adriana; Bring, Martin; Wolla, Erik; Hohler, Erling; Kittilsland, Gjermund

    2011-11-01

    An uncooled microbolometer with peak responsivity in the long wave infrared region of the electromagnetic radiation is developed at Sensonor Technologies. It is a 384 x 288 focal plane array with a pixel pitch of 25?m, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The high sensitivity (TCR) and low 1/f noise are the main performance characteristics of the product. The frame rate is maximum 60Hz and the output interface is digital (LVDS). The quantum well thermistor material is transferred to the read-out integrated circuit (ROIC) by direct wafer bonding. The ROIC wafer containing the released pixels is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. The resulting wafer stack is mounted in a standard ceramic package. In this paper the architecture of the pixels and the ROIC, the wafer packaging and the electro-optical measurement results are presented.

  3. Ultrathin silicon wafer bonding: Physics and applications

    NASA Astrophysics Data System (ADS)

    Beggans, Michael Howard

    Ultrathin silicon wafer bonding is an emerging process that simplifies device fabrication, reduces manufacturing costs, increases yield, and allows the realization of novel devices. Ultrathin silicon wafers are between 3 and 200 microns thick with all the same properties of the thicker silicon wafers (greater than 300 microns) normally used by the semiconductor electronics industry. Wafer bonding is one technique by which multiple layers are formed. In this thesis, the history and practice of wafer bonding is described and applied to the manufacture of microelectomechanical systems (MEMS) devices with layer thickness on the scale of microns. Handling and processing problems specific to ultrathin silicon wafers and their bonding are addressed and solved. A model that predicts the conformal nature of these flexible silicon wafers and its impact on bonding is developed in terms of a relatively new description of surface quality, the Power Spectral Density (PSD). A process for reducing surface roughness of silicon is elucidated and a model of this process is described. A method of detecting particle contamination in chemical baths and other processes using wafer bonding is detailed. A final section highlights some recent work that has used ultrathin silicon wafer bonding to fabricate MEMS devices that have reduced existing design complexity and made possible novel, and otherwise difficult to produce, sensors. A new fabrication process that can reduce the required time for "proof-of-principle" devices using ultrathin silicon wafers is also described.

  4. Parallel Simulation for VLSI Power Grid 

    E-print Network

    Zhang, Le

    2015-07-23

    Due to the increasing complexity of VLSI circuits, power grid simulation has become more and more time-consuming. Hence, there is a need for fast and accurate power grid simulator. In order to perform power grid simulation in a timely manner...

  5. SSI/MSI/LSI/VLSI/ULSI.

    ERIC Educational Resources Information Center

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  6. VLSI Analogs of Neuronal Visual Processing

    E-print Network

    for understanding and expressing the function of real neural systems. The working chip elevates the circuitVLSI Analogs of Neuronal Visual Processing: A Synthesis of Form and Function Thesis by Misha. This visual system is composed of three subsystems. A silicon retina, fabri- cated on a single chip, trar

  7. Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis

    SciTech Connect

    Tobin, K.W.

    2003-05-22

    This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

  8. Accurate surface profilometry of ultrathin wafers

    NASA Astrophysics Data System (ADS)

    Weeks, A. E.; Litwin, D.; Galas, J.; Surma, B.; Piatkowski, B.; MacLaren, D. A.; Allison, W.

    2007-09-01

    Geometric characterization of 50 mm diameter, 50 µm thick single-crystal Si(1 1 1) wafers has been performed using complementary methods: industry-standard capacitance measurements of warp and total thickness variation (TTV), and a technique we term scanned chromatic confocal profilometry (SCCP). We compare the measurements made by the two techniques and demonstrate the limitations of capacitance measurements when applied to ultrathin wafers. The two-dimensional SCCP measurements are shown to enhance the description of wafer thickness variations beyond that generated by the standard test method. We discuss a Fourier transform-based analysis and show it to be useful in wafer quality assessment. Adding a summary of spatial frequencies in a wafer's thickness map to the conventional measures of warp and TTV provides a more complete summary of the salient features of a wafer's geometry.

  9. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOEpatents

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  10. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  11. Wafer Resection of the Distal Ulna.

    PubMed

    Griska, Adam; Feldon, Paul

    2015-11-01

    The wafer procedure is an effective treatment for ulnar impaction syndrome, which decompresses the ulnocarpal junction through a limited open or arthroscopic approach. In comparison with other common decompressive procedures, the wafer procedure does not require bone healing or internal fixation and also provides excellent exposure of the proximal surface of the triangular fibrocartilage complex. Results of the wafer procedure have been good and few complications have been reported. PMID:26518323

  12. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2010-03-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  13. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2009-12-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  14. Full wafer metrology for chemically graded thin films

    NASA Astrophysics Data System (ADS)

    Jobin, Marc; Jotterand, Stéphane; Pellodi, Cédric; dos Santos, Sergio; Sandu, Cosmin Silviu; Wagner, Estelle; Benvenuti, Giacomo

    2012-04-01

    Combinatorial CBVD (Chemical Beam Vapor Deposition) is a thin film deposition technology which has the ability to produce multi-element thin films with large controlled composition spread gradients. If functional characterizations can be carried out systematically and rapidly on such graded films over full wafers, they enable to identify precisely the best film composition for a given application, and CBVD then easily allows for the deposition of the optimized film homogeneously on large wafers. In this article, we demonstrate the efficiency of such a process development based on the optimization of new Transparent Conductive Oxide thin films (TCO) of few % Nb doped TiO2. We have developed a full wafer metrology instrument which maps the optical thickness and the sheet resistance with a lateral resolution below 400um. We discuss the performance of various algorithms to extract the optical thickness from the white light reflectance measurement in the case of very small thickness. The sheet resistance is measured with an array of four AFM-like conductive cantilevers, allowing accurate sheet resistance (R) measurement where the standard tungsten four probes destroy porous thin oxide films. Application of these measurements to several Nb doped TiO2 films deposited on 4" wafer by CBVD is presented.

  15. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  16. Designing DWDM multiplexers on SiON wafers

    NASA Astrophysics Data System (ADS)

    Dragnea, Laurentiu

    2010-11-01

    I propose an integrated multiplexer/demultiplexer that use a concave blazed diffraction grating on SiON wafer. The paper presents a technology that overcome existing issues regarding implementation of such a microoptic device. Two types of similar integrated systems were developed but both of them have not minimized chromatic, astigmatism and spherical aberrations. Both systems use gold coating for vertical walls of diffraction grating that has reflection index lower than aluminum for wavelength used. Technology proposed in this paper minimizes the chromatic, astigmatism and spherical aberrations. Also is used aluminum for coating of vertical walls of diffraction grating. SiON wafer is etched with Argon plasma through photoresist mask with thickness of 0,8 ?m for grating configuration allowing reusing of the photoresist in next stage of coating. This makes possible that coating through liftoff to be aligned to vertical walls of concave diffraction grating, eliminating positioning errors due to coating mask.

  17. VLSI readout for imaging with polycrystalline mercuric iodide detectors

    NASA Astrophysics Data System (ADS)

    Turchetta, Renato; Dulinski, Wojtek; Husson, D.; Klein, N.; Riester, J. L.; Schieber, Michael M.; Zuck, A.; Braiman, M.; Melekhov, L.; Nissenbaum, J.; Sanguinetti, S.

    1998-11-01

    Recently polycrystalline mercuric iodide have become available, for room temperature radiation detectors over large areas at low cost. Though the quality of this material is still under improvement, ceramic detectors have been already been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors used are of different kinds: microstrips and pixels; of different sizes, up to about 1 square inch; and of different thickness, up to 600 microns. The properties of this first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed.

  18. VLSI implementation of moment invariants for automated inspection

    SciTech Connect

    Armstrong, G.A.; Simpson, M.L. ); Bouldin, D.W. )

    1990-01-01

    This paper describes the design of a VLSI ASIC for use in automated inspection. The inspection scheme uses Hu and Maitra's algorithms for moment invariants. A prototype design was generated that resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain. The prototype ASIC is currently being fabricated in 2.0-{mu}m CMOS technology and has been simulated at 20 MHz. The final ASICs will be used in parallel at the board level to achieve the 230 MOPs necessary to perform the moment invariant algorithms in real time on 512 {times} 512 pixel images with 256 grey scales. 10 refs., 2 figs.

  19. Cascaded VLSI Chips Help Neural Network To Learn

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  20. Process 2.1 Handle Wafer Bonding For Etch Processing

    E-print Network

    Healy, Kevin Edward

    Process 2.1 Handle Wafer Bonding For Etch Processing 1.0 Process Summary 1.1 Certain processes in the Nanolab require handle or breakthrough wafers to handle exotic substrates or through wafer processing. Reversible bonding attaches chips and wafers to these handle wafers with a secure bond that can handle robust

  1. VLSI architectures for geometrical mapping problems in high-definition image processing

    NASA Technical Reports Server (NTRS)

    Kim, K.; Lee, J.

    1991-01-01

    This paper explores a VLSI architecture for geometrical mapping address computation. The geometric transformation is discussed in the context of plane projective geometry, which invokes a set of basic transformations to be implemented for the general image processing. The homogeneous and 2-dimensional cartesian coordinates are employed to represent the transformations, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme for a processor, which utilizes full-pipelining at the macro-level and parallel constant-factor-redundant arithmetic and full-pipelining at the micro-level, is assessed to produce a single VLSI chip for HDTV applications using state-of-art MOS technology.

  2. CDU improvement with wafer warpage control oven for high-volume manufacturing

    NASA Astrophysics Data System (ADS)

    Tomita, T.; Weichert, H.; Hornig, S.; Trepte, S.; Shite, H.; Uemura, R.; Kitano, J.

    2009-03-01

    Immersion lithography has been developed for 45nm technology node generation during the last several years. Currently, IC manufacturers are moving to high volume production using immersion lithography. Due to the demand of IC manufactures, as the critical dimension (CD) target size is shrinking, there are more stringent requirements for CD control. Post Exposure Bake (PEB) process, which is the polymer de-protection process after exposure, is one of the important processes to control the CD in the 193nm immersion lithography cluster. Because of the importance of the PEB process for CD uniformity, accurate temperature control is a high priority. Tokyo Electron LTD (TEL) has been studying the temperature control of PEB plates. From our investigation, total thermal history during the PEB process is a key point for controlling intra wafer and inter wafer CD [1]. Further, production wafers are usually warped, which leads to a nonuniform thermal energy distribution during the PEB process. So, it is necessary to correct wafer warpage during the baking process in order to achieve accurate CD control on production wafers. TEL has developed a new PEB plate for 45nm technology node mass production, which is able to correct wafer warpage. The new PEB plate succeeded in controlling the wafer temperature on production wafers using its warpage control function. In this work, we evaluated CD process capability using the wafer warpage control PEB plate, which is mounted on a CLEAN TRACKTM LITHIUS ProTM-i (TEL) linked with the latest immersion exposure tool. The evaluation was performed together with an IC manufacturer on their 45nm production substrates in order to determine the true performance in production.

  3. Stress measurement of thin wafer using reflection grating method

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand K.

    2010-08-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this research, the system is calibrated with reference to stress measurement equipment from KLA-Tencor. Some initial results based on a joint project with Infineon Technologies are re-examined. The stress distribution of the wafers are derived with the aid of Stoney's equation. Finally, the results from our proposed system are compared and contrasted with data obtained from KLA-Tencor equipment.

  4. On Optimizing Test Cost for Wafer-to-Wafer 3D-Stacked ICs Mottaqiallah Taouil Said Hamdioui

    E-print Network

    On Optimizing Test Cost for Wafer-to-Wafer 3D-Stacked ICs Mottaqiallah Taouil Said Hamdioui to manufacture such 3D-SICs. Wafer-to-Wafer (W2W) stacking seems the most favorable approach when high manufacturing throughput, thinned wafers and small die handling is required. However, efficient and optimal test

  5. On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs Mottaqiallah Taouil1

    E-print Network

    On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs Mottaqiallah Taouil1 Said, and lower power consumption compared to planar ICs. Fabricating these 3D-SICs using Wafer-to- Wafer (W2W) stacking has several advantages including: high throughput, thin wafer and small die handling, and high TSV

  6. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

  7. Methane production using resin-wafer electrodeionization

    SciTech Connect

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  8. VLSI 'smart' I/O module development

    NASA Astrophysics Data System (ADS)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  9. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    SciTech Connect

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; Castellanos, Sergio; Buonassisi, Tonio

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled to effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.

  10. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    DOE PAGESBeta

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; Castellanos, Sergio; Buonassisi, Tonio

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore »effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

  11. PARALLEL LOGIC SIMULATION OF MILLION-GATE VLSI CIRCUITS

    E-print Network

    Varela, Carlos

    PARALLEL LOGIC SIMULATION OF MILLION-GATE VLSI CIRCUITS By Lijuan Zhu A Thesis Submitted. Introduction and background . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 VLSI Circuit simulation . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 FPGA/ASIC Design Flow . . . . . . . . . . . . . . . . . . . . 1 1.1.2 Four groups of circuit

  12. SEQUENTIAL/PARALLEL HEURISTIC ALGORITHMS FOR VLSI STANDARD CELL PLACEMENT

    E-print Network

    Areibi, Shawki M

    #12;SEQUENTIAL/PARALLEL HEURISTIC ALGORITHMS FOR VLSI STANDARD CELL PLACEMENT A Thesis Presented/PARALLEL HEURISTIC ALGORITHMS FOR VLSI STANDARD CELL PLACEMENT Guangfa Lu University of Guelph, 2004 Advisor: Dr cell designs. A number of heuristic optimization techniques for placement are studied and implemented

  13. Parallel optimization algorithms and their implementation in VLSI design

    NASA Technical Reports Server (NTRS)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  14. Modeling Networks with VLSI (linear) Integrate-and-Fire Neurons

    E-print Network

    Columbia University

    Modeling Networks with VLSI (linear) Integrate-and-Fire Neurons Maurizio Mattia and Stefano Fusi in modeling the dynamics of large scale networks of spiking neurons. A simple version of IF neuron integrates VLSI neuron with a linear integrator 1]. We show that a network of such elements can maintain both

  15. Image Compression on a VLSI Neural-Based Vector Quantizer.

    ERIC Educational Resources Information Center

    Chen, Oscal T.-C.; And Others

    1992-01-01

    Describes a modified frequency-sensitive self-organization (FSO) algorithm for image data compression and the associated VLSI architecture. Topics discussed include vector quantization; VLSI neural processor architecture; detailed circuit implementation; and a neural network vector quantization prototype chip. Examples of images using the FSO…

  16. Distributed Object Oriented Data Structures and Algorithms for VLSI CAD

    E-print Network

    Chandy, John A.

    Distributed Object Oriented Data Structures and Algorithms for VLSI CAD John A. Chandy , Steven 61801, USA£ Sierra Vista Research, 236 N Santa Cruz Avenue, Los Gatos, CA 95030, USA Abstract. ProperCAD. This paper discusses the use of such distributed data structures in the context of a partic- ular VLSI CAD

  17. AREA/CONGESTION-DRIVEN PLACEMENT FOR VLSI CIRCUIT LAYOUT

    E-print Network

    Areibi, Shawki M

    #12;AREA/CONGESTION-DRIVEN PLACEMENT FOR VLSI CIRCUIT LAYOUT A Thesis Presented to The Faculty/CONGESTION-DRIVEN PLACEMENT FOR VLSI CIRCUIT LAYOUT Zhen Yang University of Guelph, 2003 Advisor: Professor Shawki Areibi . . . . . . . . . . . . . . . . . . 16 2.3 Layout Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 Gate Array

  18. Broadband Impedance Matching for Inductive Interconnect in VLSI Packages

    E-print Network

    LaMeres, Brock J.

    Broadband Impedance Matching for Inductive Interconnect in VLSI Packages Brock LaMeres Sunil P&M University, College Station TX 77843. Abstract-- Noise induced by impedance discontinuities from VLSI pack that the interconnect of the package be treated as transmission lines. As a result, impedance discon- tinuities

  19. Leak detection utilizing analog binaural (VLSI) techniques

    NASA Technical Reports Server (NTRS)

    Hartley, Frank T. (inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  20. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    NASA Technical Reports Server (NTRS)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  1. Systolic VLSI Reed-Solomon Decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.

    1986-01-01

    Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

  2. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices

    NASA Astrophysics Data System (ADS)

    Kim, Dae Jong; Yoo, Hyung Won; Kim, Chul Hong; Lee, Hak Kwon; Kim, Sung Su; Bae, Koon Ho; Spielberg, Hedvi; Lee, Yun Ho; Levi, Shimon; Bustan, Yariv; Rozentsvige, Moshe

    2010-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

  3. Low Cost Power and Supply Noise Estimation and Control in Scan Testing of VLSI Circuits 

    E-print Network

    Jiang, Zhongwei

    2012-02-14

    Transactions on Very Large Scale Integration (VLSI) Systems. 2 for a 100oC rise in 65 nm technology. If we can predict the temperature at a given test pattern, we can adjust the capture clock timing to avoid overkill. Prior work [1... the circuit behavior during each phase of the testing. We can compute the temperature at each test pattern and adjust the capture clock timing to avoid overkill. Industry data shows that the signal delay rises by 35-55% for a 100oC rise, in 65nm technology...

  4. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  5. Multiproject wafers: not just for million-dollar mask sets

    NASA Astrophysics Data System (ADS)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task dictates careful consideration of the alternative methods.

  6. EE802 --(3L) Advanced VLSI Circuit Design A general introduction to VLSI design, analysis and simulation and some advanced topics including

    E-print Network

    Saskatchewan, University of

    . Chen) Required text(s): CMOS VLSI Design (Weste and Harris) Marking: Assignments: 10% LaboratoryEE802 -- (3L) Advanced VLSI Circuit Design A general introduction to VLSI design, analysis CMOS cell design, logical effort, circuit simulation and system design. Instructor: Engineering (L

  7. Silicon wafers for scanning helium microscopy

    NASA Astrophysics Data System (ADS)

    Litwin, D.; Galas, J.; Sitarek, S.

    2008-01-01

    The Scanning Helium Microscopy is a new technique currently under development. The paper is an overview of measurements of the geometrical characteristics of Silicon wafer concentrating on accuracy and closely related matters. In the microscope the helium atom beam is used as a probe. The overall microscope resolution depends on a deflecting element, which shapes the beam and focuses it onto a sample's surface. The most promising focusing component appears to be an ultra thin silicon wafer that is deformed under a precise electric field. Flatness and thickness uniformity of the wafer must be measured in order to select the best plate to be used in the microscope. A scanning measurement system consists of two coaxially positioned confocal heads. The paper discusses measures taken to overcome the system sensitivity to temperature variation and concludes with utilizing symmetry descriptors for final selection of wafers.

  8. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  9. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  10. Use of scanning capacitance microscopy for controlling wafer processing

    E-print Network

    Brune, Harald

    Use of scanning capacitance microscopy for controlling wafer processing O. Jeandupeux a , V tip is used for imaging the wafer topography in conven- tional contact mode. The tip also serves elec- trode is the backside of the wafer. SCM has been used to determine the 2D dopant profile of wafer

  11. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  12. C. T.-C. Nguyen, "Integrated micromechanical radio front-ends (invited plenary)," Proceedings of Tech. Program, 2008 IEEE Int. Symp. On VLSI Technolo-gy, Systems, and Applications (VLSI-TSA'08), Hsinchu, Taiwan, April 21-23, 2008, pp. 3-4.

    E-print Network

    Nguyen, Clark T.-C.

    /off switchable filter banks; and a process tech- nology that integrates nickel MEMS together with foundry CMOS Hall, Berkeley, California 94705, U.S.A. Abstract--An overview of MEMS technologies capable MEMS technology that yield on-chip resonators with Q's over 10,000 at GHz frequencies and excellent

  13. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    SciTech Connect

    Emanuel Sachs Tonio Buonassisi

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the wafer. In addition, it was found to be suitable for growing very large crystals. The equipment used was simple and inexpensive to operate. Reasonable solar cells were fabricated on re-crystallized material.

  14. A comparative analysis of Si wafer surface structure based on AFM and scattered light measurement techniques

    NASA Astrophysics Data System (ADS)

    Litwin, D.; Surma, B.; Piatkowski, B.; Miros, A.; Galas, J.

    2005-09-01

    A scanning helium atom microscope, is a very promising tool in surface science. In this technique a focused beam of low energy, neutral helium atoms is used as an imaging probe. The method is suitable to be applied to surface investigation in science and industry. The He-beam is created by supersonic expansion from a high pressure reservoir through a nozzle. It is focused onto the sample by a mirror created from an electrostatically deformed single silicon wafer. The shape of the mirror is obtained by an electrode system controlled by a computer. The focusing mirror consists of a chemically-prepared silicon wafer placed between two aluminium discs and suspended above an electrode structure. The surface quality of the mirror is the most crucial because it limits resolution of the helium microscope. Therefore it is planned to make various improvements to the mirror at both the macroscopic and atomic levels. The centre of gravity of the paper is in measurements of the surface quality of the wafer using scattered light based technique and AFM, so that the technological process of the wafers could be modified to obtain improved surface. The roughness was studied for the (111) oriented mechanically-chemically polished surfaces of silicon wafers with different miscut. The wafers with miscut of 0°, +/- 0.25o and +/- 0.5o toward (11bar2) direction were used for experiments. The miscut was determined with the accuracy of +/-1'.

  15. Measurements of the geometrical characteristics of the silicon wafer for helium microscope focusing mirror

    NASA Astrophysics Data System (ADS)

    Litwin, D.; Galas, J.; Kozlowski, T.; Sitarek, S.

    2005-09-01

    Nano-resolution imaging techniques such as scanning tunnelling microscopy (STM) and atomic force microscopy(AFM) are well-know in surface science. However, a scanning helium atom microscope, where a focused beam of low energy, neutral helium atoms is used as an imaging probe is a very new concept creating non-destructive and noninvasive surface investigation tool in science and industry. The He-beam is created by supersonic expansion from a high pressure reservoir through a nozzle. It is focused onto the sample by a mirror created from an electrostatically deformed single silicon wafer. The shape of the mirror is enforced by an electrode system controlled by a computer. The focusing mirror consists of a chemically-prepared silicon wafer placed between two aluminium discs and suspended above an electrode structure. The deflection of the mirror is controlled by an electric field between the wafer and the electrodes. The accuracy of the shape of the mirror is the most critical since it determines the resolution of the helium microscope. The required modeling of the mirror shape depends on initial quality of the wafer. Therefore it is planned to make various improvements to the mirror at both the macroscopic and atomic levels. This paper is focused on measurements of flatness and thickness of the wafer with high accuracy using specialized optics based techniques, so that the technological process of the wafers could be modified to obtain high quality material.

  16. Effects of wafer thermostability and wafer-holding materials on optical loss in GaAs annealing

    E-print Network

    Fejer, Martin M.

    Effects of wafer thermostability and wafer-holding materials on optical loss in GaAs annealing Y. S for publication 13 February 1998 A periodic structure of bonded GaAs wafers has been proposed for quasi lead to unacceptably high optical losses. When commercial semi-insulating GaAs wafers were bonded

  17. Porous solid ion exchange wafer for immobilizing biomolecules

    SciTech Connect

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  18. Optimal VLSI dictionary machines without compress instructions

    SciTech Connect

    Li, H.F.; Probst, D.K. )

    1990-05-01

    The authors present several designs for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The authors' initial design objectives included: single-cycle operability of host-issued modify and query commands (no compress instructions), complete processor utilization (no wasted processors), and optimal 2 log {ital n} response times, where {ital n} is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously.

  19. Development of a monolithic, multi-MEMS microsystem on a chip demonstrating iMEMS{trademark} VLSI technology. R and D status report number 10, January 1--March 31, 1996

    SciTech Connect

    1996-04-17

    This quarter saw the first silicon from the iMEMS{reg_sign} test chip, with complete circuits and beam structures. The wafers looked fine cosmetically and the circuits functioned as designed, but the beams suffered an anomaly that the authors have never seen before. Diagnostic work is under way to sort out the root cause, and other wafers are coming out this quarter to see if it was a one-time anomaly. Work on the process-development front has slowed because of the construction of a dedicated fabrication line for the last-generation process. With the current robust market place for ADI`s business, the existing fabrication line has been operating at 100% capacity. On the device front, great progress has been made by both Berkeley and ADI in the area of gyroscopes. Measurements of close to a degree per second or better have been made for gyros of all three axes and of both single- (linear) and double- (rotary) axis devices. In addition, ADI has designed a gyro that can be packaged in air that very well might meet some of the low-precision needs. Accelerometers of several new formats have been designed and several have been implemented in silicon. First samples of the ADXL 181 designed especially for the fuzing, safe and arming application have been assembled and are in characterization by ADI and others. In addition, 2-axis, Z-axis and digital output designs have been demonstrated. A 3-axis micro-watt accelerometer has been designed and is in fabrication. A 2-axis design for tilt applications is also nearing silicon realization. This portfolio of linear accelerometers, and even angular versions of the same provide, an arsenal of capability for specialized needs as they arise in both commercial and military applications.

  20. Analyzes Data from Semiconductor Wafers

    Energy Science and Technology Software Center (ESTSC)

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore »of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  1. Dicing of Thin Si Wafers with a Picosecond Laser Ablation Process

    NASA Astrophysics Data System (ADS)

    Fornaroli, C.; Holtkamp, J.; Gillner, A.

    These days most common way to produce electrical components like LEDs, solar cells or transistors is a batch process. Therefore a lot of identical components are processed parallel on one big wafer and eventually each chip has to be singulated. Currently two dicing technologies have established themselves, which can be devided in mechanical blade sawing and laser based processes with nanosecond lasers. In contrast to these technologies, laser dicing with picosecond lasers offers fundamental advantages like smaller kerf width and marginal heat effected zones. In this paper the cutting process of Si wafers with ps lasers is investigated with regard to optimized process parameters like pulse energy, polarization and overlap.

  2. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    NASA Technical Reports Server (NTRS)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  3. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

  4. Computing 3-D Motion in Custom Analog and Digital VLSI

    E-print Network

    Dron, Lisa

    1994-11-28

    This thesis examines a complete design framework for a real-time, autonomous system with specialized VLSI hardware for computing 3-D camera motion. In the proposed architecture, the first step is to determine point ...

  5. A Formal, Hierarchical Design and Validation Methodology for VLSI 

    E-print Network

    Davie, Bruce S.

    1988-01-01

    The high cost of fabricating VLSI circuits requires that they be validated, that is, shown to function correctly, before manufacture. The cost of design errors can be kept to a minimum if such validation occurs as early ...

  6. Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation 

    E-print Network

    Wang, Shiwei

    2014-11-27

    This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a ...

  7. Design automation tools for testable VLSI circuits

    NASA Astrophysics Data System (ADS)

    Adhem, Saman M. I.

    A very large scale integration (VLSI) circuit is assumed to contain a number of modules such as random logic circuits and read-only memories. By modifying the subcircuits locally, via selecting a design for testability (DFT) scheme, and monitoring the whole test globally the VLSI circuit is made testable. Following this framework, two problems are recognized: selection of the proper DFT technique to optimize the testability aspects of the macro cell, and modification of the macro cell to conform with the chosen DFT scheme. A generalized selection methodology has been developed to solve the selection problem employing an optimization technique and a satisfaction procedure to arrive at a solution that meets the user constraints. A knowledge based system that implements the selection mechanism has been developed to choose a built-in self-test (BIST) technique for random logic circuits. Modifying a circuit to comply with a given DFT scheme has also been studied for two DFT techniques and a number of tools have been developed. A new scan design methodology has been introduced which has simple design rules and employs two area efficient memory elements as internal storage. A comprehensive design tool has been developed to check circuits for design rule violations, check and correct scan design rule violations, and synthesize the scan path.

  8. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  9. Wafer current measurement for process monitoring

    NASA Astrophysics Data System (ADS)

    Shur, Dmitry; Kadyshevitch, Alexander; Zelenko, Jeremy; Mata, Carlos; Verdugo, Victor; Guittet, Pierre-Yves; Starr, Brian; Duncan, Craig; Ventola, Stefano; Klinger, Jan

    2005-05-01

    Wafer Current Measurement (WCM) is an emerging technique for in-line process monitoring. A joint development project (JDP) has been conducted by Infineon Technologies and Applied Ma-terials (Process Diagnostics and Control Group). The main goal of this project was development of applications for the WCM technique in production environment and specifically for state of the art DRAM Infineon process. A new generation of SEM review tool with integrated FIB (Ap-plied SEMVision G2 FIB Defect Analysis system) was used for this work. A challenging layer approached in this work was the DTMO (Deep Trench Mask Open) which serves as a hard mask for subsequent deep trench (DT) capacitor formation in a silicon substrate. The aspect ratio of the openings in the DTMO layer can be as high as 20:1. As a result of the aggressive aspect ra-tio and sub-100 nm CDs the only available techniques for evaluating DTMO etch integrity (pos-sible under-etch and/or bottom CD variation) are destructive analysis methods. As a result of the extensive JDP, crucial yield limiting problems such as dielectric or/and stop layer under-etch as well as bottom CD violation have been revealed by the WCM in-line rather than by cross-sectioning in failure analysis laboratory or other destructive means. Besides, on the basis of bottom CD sensitivity of the WCM technique, etch chamber qualification (including matching and adjustment) feasibility was conducted. The motivation behind this is that chamber qualification is essential to shorten cycle time. In production environment the WCM technique is targeted for two basic applications: process monitoring including excursion control and early etch process drift warning and in-line etch chamber qualification. WCM "pilot" has been performed in production after DTMO for four novel DRAM products with CD down to 70 nm.

  10. Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001

    SciTech Connect

    Beetz, C.P.; Steinbeck, J.; Hsueh, K.L.

    2001-03-31

    The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.

  11. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  12. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  13. CSCE 6933/5933 Advanced Topics in VLSI Systems

    E-print Network

    Mohanty, Saraju P.

    · Relatively fast but not as fast as SRAMs · Densely Packed ­ 4 times denser than SRAM · Memory Hierarchy 3 CPU plant to plant Lot Process From lot to lot in a plant Wafer Process From wafer to wafer in a lot 12

  14. NASA VLSI 2007 Mohanty & Kougianos 1 Impact of Gate Leakage on Mixed Signal

    E-print Network

    Mohanty, Saraju P.

    NASA VLSI 2007 Mohanty & Kougianos 1 Impact of Gate Leakage on Mixed Signal Design and Simulation dhruva@unt.edu #12;NASA VLSI 2007 Mohanty & Kougianos 2 Outline of the Talk Introduction Related works Remedy Conclusions #12;NASA VLSI 2007 Mohanty & Kougianos 3 Introduction Characterization of mixed signal

  15. A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

    1986-01-01

    A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

  16. An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs

    E-print Network

    Thornton, Mitchell

    An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs with a Proposal demands on these placement and routing algorithms than on VLSI or PCB layouts. However, many of the existing techniques and algorithms for VLSI and PCB placement and routing are well­suited for use in MCMs

  17. Analog VLSI Model of Locust DCMD Neuron Response for Computation of Object Approach

    E-print Network

    Analog VLSI Model of Locust DCMD Neuron Response for Computation of Object Approach Giacomo, we present an analog VLSI (aVLSI) architecture that implements a functional model of the locust or predators by using motion cues present in their visual field. It is believed that the locust neural

  18. Seasoning of Plasma Reactors: Feedback Control Strategies to Counter Wafer-to-Wafer Drifts

    NASA Astrophysics Data System (ADS)

    Agarwal, Ankur; Kushner, Mark J.

    2007-10-01

    Seasoning of plasma etching reactors is the deposition of materials on wafers and surfaces of the chamber resulting in process or wafer-to-wafer drift in etch rates or uniformity. Feedback control with in situ diagnostics is being investigated to combat this drift. The Virtual Plasma Equipment Model, an implementation of sensors, actuators and control algorithms in the HPEM, was used to investigate real-time and wafer-to-wafer control strategies. The model system is Ar/Cl2 etching of Si in an inductively coupled plasma reactor. The passivation of surfaces in contact with the plasma, including the deposition of etch products, change reactive sticking coefficients and produce etch blocks which in turn affect etch rate. Sputtering of dielectrics may introduce additional etch-block capable species. A PID controller was used to vary the bias voltage in response to an etch rate monitor to enable control of etch rate. We found that control is problematic at high bias voltages where the flux of etch products from the wafer is sufficiently large that plasma properties are affected and redeposition increases etch blocks on the wafer. Multiple sensors-and-actuators may be necessary when sputtering of dielectrics produce additional etch-block species.

  19. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  20. A bioinspired collision detection algorithm for VLSI implementation

    NASA Astrophysics Data System (ADS)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  1. Implementation of optical interconnections for VLSI

    NASA Technical Reports Server (NTRS)

    Wu, Wennie H.; Bergman, Larry A.; Johnston, Alan R.; Guest, Clark C.; Esener, Sadik C.

    1987-01-01

    This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: (1) the holographic optical element (HOE), (2) the laser sources, (3) the detectors and associated circuits forming an optically addressed gate, and (4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 x 20 microns has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity, and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five holograms.

  2. Analog VLSI neural network integrated circuits

    NASA Technical Reports Server (NTRS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  3. Periodic binary sequence generators: VLSI circuits considerations

    NASA Technical Reports Server (NTRS)

    Perlman, M.

    1984-01-01

    Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

  4. Analog VLSI system for active drag reduction

    SciTech Connect

    Gupta, B.; Goodman, R.; Jiang, F.; Tai, Y.C.; Tung, S.; Ho, C.M.

    1996-10-01

    In today`s cost-conscious air transportation industry, fuel costs are a substantial economic concern. Drag reduction is an important way to reduce costs. Even a 5% reduction in drag translates into estimated savings of millions of dollars in fuel costs. Drawing inspiration from the structure of shark skin, the authors are building a system to reduce drag along a surface. Our analog VLSI system interfaces with microfabricated, constant-temperature shear stress sensors. It detects regions of high shear stress and outputs a control signal to activate a microactuator. We are in the process of verifying the actual drag reduction by controlling microactuators in wind tunnel experiments. We are encouraged that an approach similar to one that biology employs provides a very useful contribution to the problem of drag reduction. 9 refs., 21 figs.

  5. Digital coincidence detection: A scanning VLSI implementation

    SciTech Connect

    Mertens, J.D.; Bhend, W.L.

    1993-12-01

    The authors have implemented a modular digital coincidence detection circuit in VLSI, which drastically reduces the size, and increases the performance of the coincidence detection logic required in a PET scanner. Important acquisition features contained within this integrated solution include: (1) prompt and delayed processing channels for each event-pair, with programmable coincidence time windows; (2) event time difference mode, which allows for a fast and accurate system timing calibration algorithm; (3) programmable axial event acceptance, which provides acquisition flexibility from conventional 2D through fully-3D sinogram sets and (4) programmable transaxial field of view, which provides an ``electronic`` collimator to ignore event-pairs outside of the desired field of view. The modularity of the design allows it to be used on various system geometries.

  6. VLSI Design of a Turbo Decoder

    NASA Technical Reports Server (NTRS)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  7. Geometry control of recrystallized silicon wafers for solar applications

    E-print Network

    Ruggiero, Christopher W

    2009-01-01

    The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

  8. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  9. Apparatus for edge etching of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Casajus, A.

    1986-01-01

    A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

  10. Characterization of Charging Control of a Single Wafer High Current Spot Beam Implanter

    SciTech Connect

    Schmeide, Matthias; Bukethal, Christoph

    2008-11-03

    This paper focuses on the characterization of charging control of an Axcelis Optima HD single wafer high current spot beam implanter using MOS capacitors with attached antennas of different size and shape. Resist patterns are implemented on Infineon Technologies own charging control wafers to investigate the influence of photo resist on charging damage. Compared to batch high current implanters the design of the beamline and the beam shape are comparable to single wafer high current spot beam implanters, however due to the different scanning architecture the dose rate of the single wafer high current spot beam implanters is significantly higher compared to the batch tools. Therefore, the risk of charging damage will be higher. The charging damage was studied as a function of the energy, the beam current and the most important plasma flood gun parameters. The results have shown that for very high antenna ratios the charging damage for single wafer implanters, even spot or ribbon beam implanters, is higher than for high current batch implanters.

  11. Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer

    SciTech Connect

    Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

    1999-09-07

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

  12. Study of Ag-In solder as low temperature wafer bonding intermediate layer

    NASA Astrophysics Data System (ADS)

    Made, Riko I.; Gan, Chee Lip; Lee, Chengkuo; Yan, Li Ling; Yu, Aibin; Yoon, Seung Wook; Lau, John H.

    2008-02-01

    Indium-silver as solder materials for low temperature bonding had been introduced earlier. In theory the final bonding interface composition is determined by the overall materials composition. Wafer bonding based multiple intermediate layers facilitates precise control of the formed alloy composition and the joint thickness. Thus the bonding temperature and post-bonding re-melting temperature could be easily designed by controlling the multilayer materials. In this paper, a more fundamental study of In-Ag solder materials is carried out in chip-to-chip level by using flip-chip based thermocompression bonding. Bonding at 180°C for various time duration under various bonding pressure is studied. Approaches of forming Ag IIIn with re-melting temperature higher than 400°C at the bonding interface are proposed and discussed. Knowledge learned in this process technology can support us to develop sophisticated wafer level packaging process based wafer bonding for applications of MEMS and IC packages.

  13. First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

    NASA Technical Reports Server (NTRS)

    Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

    2008-01-01

    Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

  14. Hermetic wafer bonding based on rapid thermal processing , Liwei Lin

    E-print Network

    Lin, Liwei

    Hermetic wafer bonding based on rapid thermal processing Mu Chiao* , Liwei Lin Berkeley Sensor 94720-1740, USA Abstract Hermetic wafer bonding based on rapid thermal processing (RTP) has been for wafer-level MEMS fabrication and packaging. # 2001 Elsevier Science B.V. All rights reserved. Keywords

  15. Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models

    E-print Network

    Makris, Yiorgos

    Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models Nathan Kupp, Ke) are collected to monitor the health-of-line and to make wafer scrap decisions preceding final test. These measurements are typically sampled spatially across the surface of the wafer from between-die scribe line sites

  16. Enhanced Design Flow and Optimizations for Multi-Project Wafers

    E-print Network

    Zelikovsky, Alexander

    1 Enhanced Design Flow and Optimizations for Multi-Project Wafers Andrew B. Kahng Ion I. Mandoiu Xu and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW of mask tooling among up to tens of designs. However, MPW reticle floorplanning and wafer dicing introduce

  17. Automatic Clustering of Wafer Spatial Signatures Wangyang Zhang

    E-print Network

    Li, Xin

    1 Automatic Clustering of Wafer Spatial Signatures Wangyang Zhang 1 , Xin Li 1 , Sharad Saxena 2 of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically capture wafer spatial signatures by a small number

  18. Defect detection in patterned wafers using multichannel Scanning Electron Microscope

    E-print Network

    Cohen, Israel

    Defect detection in patterned wafers using multichannel Scanning Electron Microscope Maria Zontak using Scanning Electron Microscope (SEM) images. A wafer is irradiated with a focused beam of electrons s t r a c t Recent computational methods of wafer defect detection often inspect Scanning Electron

  19. Progress on 300-mm wafer lithography equipment and processes

    NASA Astrophysics Data System (ADS)

    Mautz, Karl E.; Maltabes, John G.

    2001-09-01

    SEMICONDUCTOR300 was the first pilot-production facility for 300mm wafers in the world. The company, a joint venture between Motorola, Inc. and Infineon Technologies started in early 1998 to test and compare process, metrology and probe equipment, develop robust processes, and manufacture products using a 300mm wafer tool set. The lithography tools included I-line steppers, an I-line scanner, a DUV stepper, and DUV scanners. All of these exposure tools were running in-line with various photoresist coat and develop tracks. The lithography tools were used to build both 64M and 256M DRAM devices and aggressive test vehicles. The process capability of the initial 0.25 micrometers reference process was done and compared to the 200mm data set of the sister factory. Automation issues for lithography tools were addressed and the cost metrics were calculated. SC300 demonstrated that a manufacturable 300mm lithography tool set and process for various ground rule devices was possible with the required performance in image transfer, CD control, and overlay. Further testing on 0.18micrometers and 0.15micrometers ground rule features indicated a sufficient process window for potential manufacturing. Additionally, it was demonstrated that non-concentric subfield stepping was feasible.

  20. Towards Wafer-Scale Monocrystalline Graphene Growth and Characterization.

    PubMed

    Nguyen, Van Luan; Lee, Young Hee

    2015-08-01

    Since its discovery in 2004, graphene has boosted numerous fundamental sciences and technological applications due to its massless Dirac particle-like linear band dispersion, that causes unprecedented physical properties. Among the various methods for synthesizing graphene, chemical vapor deposition is the most suitable approach for scalable production on a wafer scale, which is a critical step for practical applications. Graphene grain boundaries (GGBs), consisting of nonhexagonal carbon rings and therefore modulating the properties of graphene films, are inevitably formed via the merging of adjacent graphene domains with different orientations. Large-area monocrystalline graphene synthesis without forming GGBs has been challenging, let alone observing such boundaries. Here, an up-to-date review is presented of how to grow wafer-scale monocrystalline graphene without GGBs. One approach is to make single domain sizes as large as possible by reducing or passivating the number of nucleation sites. Another approach is to align graphene domains in identical orientations, and then merge them atomically. The recently developed methods for observing graphene orientation and GGBs both at the atomic and macro-scales are also presented. Finally, perspectives for future research in graphene growth are discussed. PMID:25903119

  1. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime ?bulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various ?bulk conditions. The modeling results show that for the IBC solar cell with high ?bulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low ?bulk (for instance, < 500 ?s) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  2. Sensors and Achcators A, 43 (1994) 22X29 223 Low-temperature silicon wafer-to-wafer bonding using gold at

    E-print Network

    Grigoriev, Alexei

    1994-01-01

    Sensors and Achcators A, 43 (1994) 22X29 223 Low-temperature silicon wafer-to-wafer bonding using and actuator systems of high complexity bemme commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated

  3. Elimination of wafer edge die yield loss for accelerometers

    NASA Astrophysics Data System (ADS)

    Zhang, Zhenjun; Eskes, Kim A.

    2000-08-01

    Residual stresses from deposition of several micron thick polysilicon film on accelerometer wafers caused wafer to warp towards edge of wafer. The average peak to valley difference for wafer flat across wafer is 16 +/- 1 micrometers . The photo layer following the thick polysilicon deposition process is a CD critical layer with 1 micrometers spacing to be resolved. With standard stepper configuration, wafer non- flatness from residual stresses reduced overall depth of focus and made the 1 (mu) spacing in edge dies not resolved, resulting in stiction and yield loss for edge dies. To minimize the effect of wafer non-flatness on across wafer CD control and edge die CD definition at photo, three different focus algorithms as well as two different wafer chuck styles were evaluated on 1X steppers. Results showed that both oblong wafer chuck and two step focus option significantly improved CD definition and resolution of the 1 micrometers spacing in edge dies. Two step focus combined with oblong chuck offered the best CD control edge dies. Edge die yield loss was eliminated for accelerometer wafers ran with oblong chuck and two step focus. Oblong chuck, and two step focus combination have been released to full production at Poly2 layer of accelerometers.

  4. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  5. Economic impact of single-wafer multiprocessors

    NASA Astrophysics Data System (ADS)

    Wood, Samuel C.; Saraswat, Krishna C.; Harrison, J. M.

    1991-04-01

    Single wafer multiprocessors generally in the form of cluster tools are gaining increasing importance in commercial semiconductor product manufacture. This paper describes potential cost-related and timerelated advantages that could come from the multipmcessors. Next hypothetical conventional and clusterbased fabs are simulated. The simulations results are discussed in terms of their evidence for the cost and time advantages of the fabs. One general conclusion is that cluster tools can be used to achieve very short throughput times at a premium cost per wafer. Finally based on the potential advantages and the simulation results three areas of non-process issues are discussed which will determine the extent of the multiprocessors'' economic utility. These areas are cost time and fab management related. 1

  6. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  7. The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Shao, H. M.; Deutsch, L. J.

    1987-01-01

    The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.

  8. A multi coding technique to reduce transition activity in VLSI circuits

    NASA Astrophysics Data System (ADS)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  9. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  10. NASA Space Engineering Research Center for VLSI systems design

    NASA Technical Reports Server (NTRS)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  11. Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process

    NASA Astrophysics Data System (ADS)

    Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

    2013-09-01

    Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements™) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

  12. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  13. Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size

    NASA Astrophysics Data System (ADS)

    Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

    2013-06-01

    For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

  14. Performance optimization of digital VLSI circuits

    SciTech Connect

    Marple, D.P.

    1987-01-01

    Designers of digital VLSI circuits have virtually no computer tools available for the optimization of circuit performance. Instead, a designer relies extensively on circuit-analysis tools, such as circuit simulation (SPICE) and/or critical-delay-path analysis. A circuit-analysis approach to digital design is very labor-intensive and seldom produces a circuit with optimum area/delay or power/delay trade off. The goal of this research is to provide a synthesis approach to the design of digital circuits by finding the sizes of transistors that optimize circuits by finding the sizes of transistors that optimize circuit performance (delay, area, power). Solutions are found that are optimum for all possible delay paths of a given circuit and not for just a single path. The approach of this research is to formulate the problem of area/delay or power/delay optimization as a nonlinear program. Conditions for optimality are then established using graph theory and Kuhn-Tucker conditions. Finally, the use of augmented-Lagrangian and projected-Lagrangian algorithms are reviewed for the solution of the nonlinear programs. Two computer programs, PLATO and COP, were developed by the author to optimize CMOS PLA's (PLATO) and general CMOS circuits (COP). These tools provably find the globally optimum transistor sizes for a given circuit. Results are presented for PLA's and small- to medium-sized cells.

  15. A simple VLSI architecture for neurocomputing

    SciTech Connect

    Pacheco, M.; Bavan, S.; Lee, M.; Treleaven, P.

    1988-09-01

    Recent advances in ''neural'' computation models will only demonstrate their true value with the introduction of parallel computer architectures designed to optimise the computation of these neural networks. General-purpose neurocomputers is one approach which provides a framework for executing neural networks in much the same way that traditional computers address the problems of ''number crunching'', for which they are best suited. This framework must include a means of programming (i.e. operating system and programming languages) and the hardware must exploit the properties of VLSI, for parallelism and communication. At University College London, the authors have designed and are currently implementing in CMOS, a primitive processing element for building a parallel MIMD Neurocomputer, configured from arrays of these elements connected to a host computer (Figure 1). The goal of the Neurocomputer is to support a range of Connectionist algorithms spanning both neural networks and semantic networks. The primitive processing element is a self-contained microprocessor composed of three basic units: a 16 instruction set processor, a communication unit and a small local memory. Each processing element has a neuron name, used for message routing. The communication unit provides two bi-directional parallel links (implemented by four unidirectional) and a simple protocol to support a logical bus for routing message packets.

  16. In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system

    NASA Astrophysics Data System (ADS)

    Yang, Yi-Bin; Liu, Ming-Gang; Chen, Wei-Jie; Han, Xiao-Biao; Chen, Jie; Lin, Xiu-Qi; Lin, Jia-Li; Luo, Hui; Liao, Qiang; Zang, Wen-Jie; Chen, Yin-Song; Qiu, Yun-Ling; Wu, Zhi-Sheng; Liu, Yang; Zhang, Bai-Jun

    2015-09-01

    In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2? Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), the International Science and Technology Collaboration Program of Guangdong Province, China (Grant No. 2013B051000041), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), the National High Technology Research and Development Program of China (Grant No. 2014AA032606), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics, China (Grant No. IOSKL2014KF17).

  17. Nanotribology of nanooxide materials in ionic liquids on silicon wafers

    NASA Astrophysics Data System (ADS)

    Hamidunsani, Ahmad Termizi; Radiman, Shahidan; Hassan, Masjuki Haji; Rahman, Irman Abdul

    2015-09-01

    Nanotribological properties have a significant impact on daily life. Ionic liquids (ILs) are becoming new favourable lubricants currently in researches. Addition of nanooxide materials in lubricants provide improvements to new technology. In this study, we determine nanotribological properties of BMIM+BF4- IL addition of different amount of ZnO nanomaterial on single crystals silicon wafer (Si110). The viscosity changes of IL samples against temperature increase were determined by rheological method. Nanotribological properties were determined by changes in friction coefficient and wear rate on silicon substrate surfaces using a reciprocating friction and wear monitor in 1 hour duration time. Aluminium cylinders acted as pins used to rub Si (110) substrate sample surfaces. Thus, on range between 0 mg to 3.5 mg of ZnO nanooxide material dispersed in 10ml BMIM+BF4- showed a good friction coefficient, wear and surface roughness reduction.

  18. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  19. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    ERIC Educational Resources Information Center

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  20. VLSI ARCHITECTURE AND DESIGN FOR HIGH PERFORMANCE ADAPTIVE VIDEO SCALING

    E-print Network

    Liu, K. J. Ray

    for developing a good scaling algorithm is to enable display of lower resolution images on higher resolu- tionVLSI ARCHITECTURE AND DESIGN FOR HIGH PERFORMANCE ADAPTIVE VIDEO SCALING Arun Raghupathy * Pohsiang involved is extremely high. When the available bandwidth is limited, the im- age size is restricted. A high

  1. Analog VLSI Neuromorphic Network with Programmable Membrane Channel Kinetics

    E-print Network

    Cauwenberghs, Gert

    Analog VLSI Neuromorphic Network with Programmable Membrane Channel Kinetics Theodore Yu1-dependence of the channel kinetics. All 12 chemical synapses interconnecting the neurons also have individually pro of the channel kinetics. All configurable parameters in the implemented model have a biophysical origin, thus

  2. Hybrid VLSI/QCA Architecture for Computing FFTs

    NASA Technical Reports Server (NTRS)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  3. Gallium Arsenide Integrated Circuits 1988 ANZAAS Congress, VLSI Section

    E-print Network

    Gallium Arsenide Integrated Circuits 1988 ANZAAS Congress, VLSI Section Anthony E. Parker. As a result, GaAs integrated circuits are found increasingly in very high performance systems in communications, computers and instrumentation. High performance digital integrated circuits will be especially

  4. Why VLSI Implementations of Associative VLCNs Require Mult iplexingt

    E-print Network

    Hammerstrom, Dan

    process- ing on von Neumann computers. Pattern recognition, constraint satisfaction, and data completion, but powerful, emula- tion engines is VLSI CMOS. Microprocessor and memory competition has pushed the development of faster and denser CMOS processes and has provided a well understood, powerful, yet relatively

  5. "Seeing" in the Dark: Neuromorphic VLSI Modeling of Bat Echolocation

    E-print Network

    Horiuchi, Timothy K.

    "Seeing" in the Dark: Neuromorphic VLSI Modeling of Bat Echolocation IEEE SIGNAL PROCESSING around us. The bats of the suborder Micro- chiroptera have made echo detection their primary sensory engineering, and aero- nautics since the discovery in the 1790s that bats could fly in clut- tered rooms even

  6. Power Optimization in VLSI Layout: A Massoud Pedram

    E-print Network

    Pedram, Massoud

    voltage, · the standby current which is the DC current drawn continuously from Vdd to ground, · the short-circuit and circuit structures [19] in which this condi- tion holds. The short-circuit power consumption. The maximum short #12;Power Optimization in VLSI Layout: A Survey 3 circuit current flows when

  7. MODELING THE NONLINEAR ACTIVE COCHLEA: MATHEMATICS AND ANALOG VLSI

    E-print Network

    Boahen, Kwabena

    MODELING THE NONLINEAR ACTIVE COCHLEA: MATHEMATICS AND ANALOG VLSI Bo Wen A DISSERTATION Christopher Chen, Graduate Group Chair #12;COPYRIGHT Bo Wen 2006 #12;Acknowledgements This dissertation would the faith" are what I will always bear in mind in my future research. I would like to express my deep

  8. EFFICIENT VLSI IMPLEMENTATION OF BIT PLANE CODER OF JPEG2000

    E-print Network

    Kambhampati, Subbarao

    EFFICIENT VLSI IMPLEMENTATION OF BIT PLANE CODER OF JPEG2000 Kishore Andra* , Tinku Acharya, Arizona, 85226, USA ABSTRACT To overcome many drawbacks in the current JPEG standard for still image compression, a new standard, JPEG2000, is under development by the International Standard Organization

  9. Algorithms for the scaling toward nanometer VLSI physical synthesis 

    E-print Network

    Sze, Chin Ngai

    2007-04-25

    Along the history of Very Large Scale Integration (VLSI), we have successfully scaled down the size of transistors, scaled up the speed of integrated circuits (IC) and the number of transistors in a chip - these are just a few examples of our...

  10. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  11. Autonomous vehicle guidance using analog VLSI neuromorphic sensors

    E-print Network

    Autonomous vehicle guidance using analog VLSI neuromorphic sensors Giacomo Indiveri and Paul step towards the design of a fully autonomous vehicle that will safely navigate using only inputs from of compact low-power autonomous systems. We describe such a system, consisting of a mobile robot equipped

  12. Advanced technologies for Mission Control Centers

    NASA Technical Reports Server (NTRS)

    Dalton, John T.; Hughes, Peter M.

    1991-01-01

    Advance technologies for Mission Control Centers are presented in the form of the viewgraphs. The following subject areas are covered: technology needs; current technology efforts at GSFC (human-machine interface development, object oriented software development, expert systems, knowledge-based software engineering environments, and high performance VLSI telemetry systems); and test beds.

  13. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  14. Wafer warpage characterization measurement with modified fringe reflection method

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2015-05-01

    We have demonstrated a modified fringe reflection method to compensate the warpage measurement errors caused by the height difference between optical reference mirror and wafer sample surface. We have used a linearity analysis approach to obtain the parabolic height errors for a 4-inch sapphire wafer warpage measurement, which is around 1.48 ?m of 100 ?m height difference. The experimental results shows the warp discrepancy of 6-inch sapphire wafer is less than 1 ?m compared with the reference Tropel instrument.

  15. Development of Fixture Element for Vacuum Transportation of Silicon Wafer Using Electro-Rheological Gel

    NASA Astrophysics Data System (ADS)

    Tanaka, Masayuki; Kakinuma, Yasuhiro; Aoyama, Tojiro; Anzai, Hidenobu; Kawaguchi, Takafumi

    Semiconductor process technology increasingly requires high accuracy and efficiency. In the case of processing thin fragile substrate such as silicon wafer, it has to be fixed with low strain. In addition, its fixture device can be used under vacuum condition because some processes are carried out in vacuum. It is required to develop a new fixture device for vacuum transportation of silicon wafer. ERG is the functional material whose friction characteristic varies according to the intensity of applied electric field. The surface friction of ERG can be changed quickly and reversibly applying the electric field. In other words, it becomes easy to fix and release a substrate by control of electric field. In this study, ERG is applied to a fixture element of silicon wafer available for vacuum process. The ERG fixture element was trial-manufactured and its performance under vacuum condition was evaluated experimentally. The result shows that the ERG effect emerges in vacuum and ERG can fix silicon wafer sufficiently. Moreover, numerical analysis of electric filed was carried out to obtain the optimal pattern of the one-sided electrodes used for the ERG fixture element. It is clear that the optimal width of electrodes exists according to the gap of electrodes and the thickness of ERG.

  16. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  17. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M. (Antioch, CA)

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  18. Statistical equipment modeling for VLSI manufacturing

    NASA Astrophysics Data System (ADS)

    1989-10-01

    The systematic methodology presented here aims at building and calibrating equipment-specific process models. These models describe the nominal equipment response and also the inherent process variations. D-Optimal experiment design, combined with statistical modeling, is employed for the characterization and representation of the equipment and its associated processes. The methodology has been successfully applied for modeling a furnace used for low pressure chemical vapor deposition (LPCVD) of undoped polysilicon. A 2-stage D-Optimal design with 24 experiments was used to refine and calibrate physically-derived LPCVD models for the specific furnace. Statistical models have been built for two equipment responses, namely the polysilicon deposition rate and the built-in wafer stress. These models agree well with the experiment data, and account correctly for the observed variations.

  19. Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm

    E-print Network

    Wladyslaw Szczesniak

    2008-01-07

    This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.

  20. Wafer Signature Analysis of IDDQ Test Data Sagar S. Sabade D. M. H. Walker

    E-print Network

    Walker, Duncan M. "Hank"

    Wafer Signature Analysis of IDDQ Test Data Sagar S. Sabade D. M. H. Walker Department of Computer. The concept of wafer signature is proposed. A wafer signature is obtained by sorting all IDDQ readings on a wafer for a vector. A break or jump in the wafer signature is considered to indicate defective chips

  1. Magnetometory of AlGaN/GaN heterostructure wafers

    NASA Astrophysics Data System (ADS)

    Tsubaki, K.; Maeda, N.; Saitoh, T.; Kobayashi, N.

    2005-06-01

    AlGaN/GaN heterostructure wafers are becoming a key technology for next generation cellar-phone telecommunication system because of their potential for high-performance microwave applications. Therefore, the electronic properties of a 2DEG in AlGaN/GaN heterostructures have recently been discussed. In this paper, we performed the extraordinary Hall effect measurement and the SQUID magnetometory of AlGaN/GaN heterostructure wafer at low temperature. The AlGaN/GaN heterostructures were grown by low-pressure metal-organic chemical vapour phase epitaxy on (0001) SiC substrate using AlN buffers. The electron mobility and electron concentration at 4.2 K are 9,540cm2/V s and 6.6 × 1012cm-2, respectively. In the extraordinary Hall effect measurement of AlGaN/GaN heterostructures, the hysteresis of Hall resistance appeared below 4.5 K and disappeared above 4.5 K. On the other hand, the hysteresis of magnetometric data obtained by SQUID magnetometory appears near zero magnetic field when the temperature is lower than 4.5 K. At the temperature larger than 4.5 K, the hysteresis of magnetometric data disappears. And the slopes of magnetometric data with respect to magnetic field become lower as obeying Currie-Weiss law and the Curie temperature TC is 4.5 K. Agreement of TC measured by the extraordinary Hall effect and the SQUID magnetometory implies the ferromagnetism at the AlGaN/GaN heterojunction. However, the conformation of the ferromagnetism of AlGaN/GaN heterostructure is still difficult and the detailed physical mechanism is still unclear.

  2. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    NASA Astrophysics Data System (ADS)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2015-02-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  3. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    PubMed

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-01-01

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

  4. Low-temperature vacuum hermetic wafer-level package for uncooled microbolometer FPAs

    NASA Astrophysics Data System (ADS)

    Garcia-Blanco, S.; Topart, P.; Desroches, Y.; Caron, J. S.; Williamson, F.; Alain, C.; Jerominek, H.

    2008-02-01

    Micro-Electro-Mechanical Systems (MEMS) packaging constitutes most of the cost of such devices. For the integration of MEMS with microelectronics systems to be widespread, a drastic reduction of the overall price is required. Wafer-level-packaging allows a fundamental reduction of the packaging cost by combining wafer-level microfabrication techniques with wafer-to-wafer bonding. To achieve the vacuum atmosphere required for the operation of many MEMS devices, bonding techniques such as anodic bonding, eutectic bonding, fusion bonding and gold to gold thermocompression bonding have been utilized, which require relatively high temperatures (>300°C) being in some cases incompatible with MEMS and microelectronics devices. Furthermore, to maintain vacuum integrity over long periods of time, getters requiring high activation temperatures are usually employed. INO has developed a hybrid wafer-level micropackaging technology based on low temperature fluxless solder joints in which the micropackaged MEMS device is not exposed to a temperature over 150°C. The micropackages have been designed for 160×120 microbolometer FPAs. Ceramic spacers are patterned by standard microfabrication techniques followed by laser micromachining. AR-coated floatzone silicon IR windows are patterned with a solderable layer. Both, microbolometer dies and windows are soldered to the ceramic tray by a combination of solder paste stencil printing, reflow and fluxless flip-chip bonding. A low temperature getter is also introduced to control outgassing of moisture and CO II during the lifetime of the package. Vacuum sealing is carried out by locally heating the vacuum port after bake out of the micropackages. In this paper, the vacuum integrity of micropackaged FPA dies will be reported. Base pressures as low as 5 mTorr and equivalent flow rates at room temperature of 4×10 -14 Torr.l/s without getter incorporation have been demonstrated using integrated micro-pressure gauges. A study of the influence of different packaging parameters on the lifetime of micropackages will be presented.

  5. High-performance long wave infrared bolometer fabricated by wafer bonding

    NASA Astrophysics Data System (ADS)

    Lapadatu, Adriana; Kittilsland, Gjermund; Elfving, Anders; Hohler, Erling; Kvisterøy, Terje; Bakke, Thor; Ericsson, Per

    2010-04-01

    A novel microbolometer with peak responsivity in the longwave infrared region of the electromagnetic radiation is under development at Sensonor Technologies. It is a focal plane array of pixels with a 25?m pitch, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The novelty of the proposed 3D process integration comes from the choice of several of the materials and key processes involved, which allow a high fill factor and provide improved transmission/absorption properties. Together with the high TCR and low 1/f noise provided by the thermistor material, they will lead to bolometer performances beyond those of existing devices. The thermistor material is transferred from the handle wafer to the read-out integrated circuit (ROIC) by wafer bonding. The low thermal conductance legs that connect the thermistor to the ROIC are fabricated prior to the transfer bonding and are situated under the pixel. Depending on the type of the transfer bonding used, the plugs connecting the legs to the thermistor are made before or after this bonding, resulting in two different configurations of the final structure. Using a low temperature oxide bonding and subsequent plugs formation result in through-pixel plugs. Pre-bonding plugs formation followed by thermo-compression bonding result in under-pixel plugs. The pixels are subsequently released by anhydrous vapor HF of the sacrificial oxide layer. The ROIC wafer containing the released FPAs is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. Antireflection coatings and a thin layer getter are deposited on the cap wafer prior to bonding, ensuring high performance of the bolometer.

  6. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    ERIC Educational Resources Information Center

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  7. Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers

    E-print Network

    Lü, James Jian-Qiang

    Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal. Monolithic wafer-level 3D integration offers the potential for a high density of micron-sized through-die vias necessary for highest performance of integrated systems. In addition, such wafer

  8. A 50mm Copper/Polymer Substrate HBT IC Technology for >100GHz MMICs

    E-print Network

    Rodwell, Mark J. W.

    A 50mm Copper/Polymer Substrate HBT IC Technology for >100GHz MMICs James Guthrie, D. Mensa, T of Entire 2" HBT MMIC Wafer #12;Cu Surrogate Substrate Cross sectional SEM of test wafer #12;Discrete HBT

  9. Particulate contamination removal from wafers using plasmas and mechanical agitation

    SciTech Connect

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  10. A Sharp methodology for VLSI layout

    NASA Astrophysics Data System (ADS)

    Bapat, Shekhar

    1993-01-01

    The layout problem for VLSI circuits is recognized as a very difficult problem and has been traditionally decomposed into the several seemingly independent sub-problems of placement, global routing, and detailed routing. Although this structure achieves a reduction in programming complexity, it is also typically accompanied by a reduction in solution quality. Most current placement research recognizes that the separation is artificial, and that the placement and routing problems should be solved ideally in tandem. We propose a new interconnection model, Sharp and an associated partitioning algorithm. The Sharp interconnection model uses a partitioning shape that roughly resembles the musical sharp 'number sign' and makes extensive use of pre-computed rectilinear Steiner trees. The model is designed to generate strategic routing information along with the partitioning results. Additionally, the Sharp model also generates estimates of the routing congestion. We also propose the Sharp layout heuristic that solves the layout problem in its entirety. The Sharp layout heuristic makes extensive use of the Sharp partitioning model. The use of precomputed Steiner tree forms enables the method to model accurately net characteristics. For example, the Steiner tree forms can model both the length of the net and more importantly its route. In fact, the tree forms are also appropriate for modeling the timing delays of nets. The Sharp heuristic works to minimize both the total layout area by minimizing total net length (thus reducing the total wiring area), and the congestion imbalances in the various channels (thus reducing the unused or wasted channel area). Our heuristic uses circuit element movements amongst the different partitioning blocks and selection of alternate minimal Steiner tree forms to achieve this goal. The objective function for the algorithm can be modified readily to include other important circuit constraints like propagation delays. The layout technique first computes a very high-level approximation of the layout solution (i.e., the positions of the circuit elements and the associated net routes). The approximate solution is alternately refined, objective function. The technique creates well defined sub-problems and offers intermediary steps that can be solved in parallel, as well as a parallel mechanism to merge the sub-problem solutions.

  11. Wafer-Scale Fabrication of Plasmonic Crystals from Patterned Silicon Templates Prepared by Nanosphere Lithography

    E-print Network

    Wafer-Scale Fabrication of Plasmonic Crystals from Patterned Silicon Templates Prepared Supporting Information ABSTRACT: By combining nanosphere lithography with template stripping, silicon wafers then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic

  12. Block-level Designs of Die-to-Wafer Bonded 3D ICs and Their Design Quality Tradeoffs

    E-print Network

    Lim, Sung Kyu

    the footprint of the dies in the stack are different. This happens in case of die-to-wafer bonding, which technology provides extremely high memory bandwidth and very short core-to- memory connections [1. 1This stacking allows better power delivery and potentially better cooling if the top die consumes

  13. Ultra-Low Noise HEMT Device Models: Application of On-Wafer Cryogenic Noise Analysis and Improved Parameter Extraction Techniques

    NASA Technical Reports Server (NTRS)

    Bautista, J. J.; Hamai, M.; Nishimoto, M.; Laskar, J.; Szydlik, P.; Lai, R.

    1995-01-01

    Significant advances in the development of HEMT technology have resulted in high performance cryogenic low noise amplifiers whose noise temperatures are within an order of magnitude of the quantum noise limit. Key to the identification of optimum HEMT structures at cryogenic temperatures is the development of on-wafer noise and device parameter extraction techniques. Techniques and results are described.

  14. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  15. Thermal Warpage of Large Diameter Czochralski-Grown Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Shimizu, Hirofumi; Aoshima, Takaaki

    1988-12-01

    Thermal warping of large diameter Czochralski-grown silicon wafers as affected by oxygen precipitation is investigated both experimentally and theoretically. The difference of wafer warpage and its shape between the heating and cooling processes is clarified by thermal stresses calculated from temperature gradients in wafers for each process. The critical temperatures for the slip occurrence are determined for the heating and cooling processes as a function of the microdefect density. Then, the optimized process conditions to avoid slip dislocations are obtained experimentally. The critical stress curve for the processed wafers in MOS devices is determined by comparison with the thermal stress curves calculated under various process conditions, and thereby predicting the slip-free conditions for wafers in a row with various diameters from 100 to 200 mm.

  16. Highly Uniform Electroluminescence from 150 and 200 mm GaN-on-Si-Based Blue Light-Emitting Diode Wafers

    NASA Astrophysics Data System (ADS)

    Pinos, Andrea; Tan, Wei-Sin; Chitnis, Ashay; Nishikawa, Atsushi; Groh, Lars; Hu, Cheng-Yu; Murad, Saad; Lutgen, Stephan

    2013-09-01

    We report on the on-wafer device characteristics of 150 and 200 mm GaN-on-Si-based blue LED wafers grown by metalorganic chemical vapor deposition on Si(111) substrates with electroluminescence at 447 nm. Excellent uniformity was achieved with standard deviations of 3.9% for the electroluminescence intensity, 0.6-0.8% for the peak wavelength and 1.3% for the forward voltage. The high uniformity confirms the viability of the GaN-on-Si technology on large-diameter substrates for next-generation LED manufacturing. The reverse bias current leakage mechanism is also investigated to provide an insight into improving device reliability.

  17. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  18. Piezoresistive stress sensors on (110) silicon wafers

    NASA Technical Reports Server (NTRS)

    Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

    1992-01-01

    Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

  19. Wafer Mapping Using Deuterium Enhanced Defect Characterization

    NASA Astrophysics Data System (ADS)

    Hossain, K.; Holland, O. W.; Hellmer, R.; Vanmil, B.; Bubulac, L. O.; Golding, T. D.

    2010-07-01

    Deuterium (as well as other hydrogen isotopes) binds with a wide range of morphological defects in semiconductors and, as such, becomes distributed similarly to those defects. Thus, the deuterium profile within the sample serves as the basis of a technique for defect mapping known as amethyst wafer mapping (AWM). The efficiency of this technique has been demonstrated by evaluation of ion-induced damage in implanted Si, as well as as-grown defects in HgCdTe (MCT) epilayers. The defect tagging or decoration capability of deuterium is largely material independent and applicable to a wide range of defect morphologies. A number of analytical techniques including ion channeling and etch pit density measurements were used to evaluate the AWM results.

  20. Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon wafers

    E-print Network

    Akin, Tayfun

    Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon September 2010 Keywords: Diamond-on-insulator Plasma activation Ultrananocrystalline diamond Direct bonding Diamond-on-insulator (DOI) wafers featuring ultrananocrystalline diamond are studied via atomic force

  1. 200-mm GaN-on-Si Based Blue Light-Emitting Diode Wafer with High Emission Uniformity

    NASA Astrophysics Data System (ADS)

    Nishikawa, Atsushi; Groh, Lars; Solari, William; Lutgen, Stephan

    2013-08-01

    We investigated the emission wavelength uniformity of 200-mm GaN-on-Si based blue light-emitting diode (LED) wafer grown by metalorganic vapor phase epitaxy (MOVPE). The larger the Si substrate diameter becomes, the more difficult to obtain uniform distribution of the emission wavelength because of the larger bow during growth, resulting in larger on-wafer inhomogeneity in growth temperature. Owing to the GaN-on-Si buffer strain management, optimized gas flow condition, and precise control of temperature balance in a reactor, we have achieved high thickness and crystal quality uniformity over the 200-mm GaN-on-Si based blue LED wafer. As a result, excellent blue photoluminescence emission wavelength uniformity from the InGaN-multi-quantum wells can be demonstrated on a 200-mm wafer with a standard deviation of 2.53 nm (0.57%). Less wavelengths binning with these highly uniform emission over the 200-mm wafer show the capability of sustainable cost reduction in LED fabrication based on GaN-on-Si technology.

  2. Noise-margin limitations on gallium-arsenide VLSI

    NASA Technical Reports Server (NTRS)

    Long, Stephen I.; Sundaram, Mani

    1988-01-01

    Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

  3. Fault model development for fault tolerant VLSI design

    NASA Astrophysics Data System (ADS)

    Hartmann, C. R.; Lala, P. K.; Ali, A. M.; Visweswaran, G. S.; Ganguly, S.

    1988-05-01

    Fault models provide systematic and precise representations of physical defects in microcircuits in a form suitable for simulation and test generation. The current difficulty in testing VLSI circuits can be attributed to the tremendous increase in design complexity and the inappropriateness of traditional stuck-at fault models. This report develops fault models for three different types of common defects that are not accurately represented by the stuck-at fault model. The faults examined in this report are: bridging faults, transistor stuck-open faults, and transient faults caused by alpha particle radiation. A generalized fault model could not be developed for the three fault types. However, microcircuit behavior and fault detection strategies are described for the bridging, transistor stuck-open, and transient (alpha particle strike) faults. The results of this study can be applied to the simulation and analysis of faults in fault tolerant VLSI circuits.

  4. High density circuit technology, part 1

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

  5. CME 342.3 (3L-1.5P) VLSI Circuit Design

    E-print Network

    Saskatchewan, University of

    CME 342.3 (3L-1.5P) VLSI Circuit Design Department of Electrical and Computer Engineering Fall 2013 Description: This is an introductory course in VLSI Systems and Design. CMOS logic circuits and fabrication digital circuits. They should be able to design for low power and speed, and testability. Prerequisites

  6. A NEW TEST METRIC AND A NEW SCAN ARCHITECTURE FOR EFFICIENT VLSI TESTING

    E-print Network

    Stanford University

    A NEW TEST METRIC AND A NEW SCAN ARCHITECTURE FOR EFFICIENT VLSI TESTING A DISSERTATION SUBMITTED. To overcome the difficulty and cost of VLSI testing, we need to search for better testing techniques. Chip testing can be classified into two categories: production testing and characterization testing

  7. Tier-Partitioning for Power Delivery vs Cooling Tradeoff in 3D VLSI for Mobile Applications

    E-print Network

    Lim, Sung Kyu

    Tier-Partitioning for Power Delivery vs Cooling Tradeoff in 3D VLSI for Mobile Applications delivery to the tier farthest away from the package in 3D VLSI is challenging. This is because the current provided by the package on the bottom is (1) first used by other tiers before it reaches the top, and (2

  8. Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite

    E-print Network

    Liu, Bao

    1 Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite-scale VLSI design demands reliable on- chip power/ground (P/G) supply. Decoupling capacitors effec- tively decoupling capacitor insertion techniques are based on sensitivity analysis and greedy optimization

  9. A VLSI design of a pipeline Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

    1985-01-01

    A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

  10. 32-bit VLSI chip set chops mainframe to four boards

    SciTech Connect

    Costlow, T.

    1983-03-17

    In a move to shrink the size of its mainframe computer without sacrificing power, NCR Corp. Has taken advantage of a VLSI chip set, including a proprietary 32-bit CPU, to develop a compact mainframe that comprises only four boards. The modular 9300 system-containing a processor board, a link-level communications card, and two 2-mbyte memory board-lowers heat and power dissipation by a factor of 10 over its 35-board predecessor.

  11. 1.55 ?m hybrid waveguide laser made by ion-exchange and wafer bonding

    NASA Astrophysics Data System (ADS)

    Casale, Marco; Bucci, Davide; Bastard, Lionel; Broquin, Jean-Emmanuel

    2012-01-01

    Distributed Feed Back (DFB) lasers working in the third telecom window are essential for optical communications, eyesafe sensors and lab-on-chip devices. Glass integrated optics technology allows realizing such devices by using rareearth doped substrates. Despite their good output power and spectral characteristic, DFB lasers still present some reliability issues concerning the Bragg grating protection. Moreover Erbium doped glasses are not compatible with the realization of passive optical functions. In order to solve the DFB lasers reliability issues and to ensure a monolithic integration between active and passive functions, we propose an hybrid-device architecture based on ion-exchange technology and wafer bonding. The Ag+/Na+ ion-exchange in the silicate glass wafer is used to realize the passive functions and the lateral confinement of the electromagnetic field. Through a second ion exchange step, a slab waveguide is made on the Erbium-Ytterbium doped glass wafer. The Bragg grating is processed on the passive substrate and the two glasses are bonded. The potential of this structure has been demonstrated through the realization of a DFB hybrid laser with a fully encapsulated Bragg grating.

  12. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  13. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    PubMed Central

    Devi, T. Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25?µm, 65?nm, and 180?nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475?MHz. PMID:26558289

  14. Plasma-activated wafer bonding: the new low-temperature tool for MEMS fabrication

    NASA Astrophysics Data System (ADS)

    Dragoi, V.; Mittendorfer, G.; Thanner, C.; Lindner, P.

    2007-05-01

    Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stress-free, aligned substrates without warpage. Achieving wafer level bonding at low temperature employs a little magic and requires new technology development. The cornerstone of low temperature bonding is plasma activation. The plasma is chosen to compliment existing interface conditions and can result in conductive or insulating interfaces. A wide range of materials including semiconductors, glasses, quartz and even plastics respond favorably to plasma activated bonding. The annealing temperatures required to create permanent bonds are typically ranging from room temperature to 400°C for process times ranging from 15-30 minutes and up to 2-3 hours. This new technique enables integration of various materials combinations coming from separate production lines.

  15. Wafer-level Au-Au bonding in the 350-450 °C temperature range

    NASA Astrophysics Data System (ADS)

    Tofteberg, Hannah R.; Schjølberg-Henriksen, Kari; Fasting, Eivind J.; Moen, Alexander S.; Taklo, Maaike M. V.; Poppe, Erik U.; Simensen, Christian J.

    2014-08-01

    Metal thermocompression bonding is a hermetic wafer-level packaging technology that facilitates vertical integration and shrinks the area used for device sealing. In this paper, Au-Au bonding at 350, 400 and 450 °C has been investigated, bonding wafers with 1 µm Au on top of 200 nm TiW. Test Si laminates with device sealing frames of 100, 200, and 400 µm in width were realized. Bond strengths measured by pull tests ranged from 8 to 102 MPa and showed that the bond strength increased with higher bonding temperatures and decreased with increasing frame width. Effects of eutectic reactions, grain growth in the Au film and stress relaxation causing buckles in the TiW film were most pronounced at 450 °C and negligible at 350 °C. Bond temperature below the Au-Si eutectic temperature 363 °C is recommended.

  16. Cost-effective, high-volume molecular beam epitaxy using a multi 6-in wafer reactor

    NASA Astrophysics Data System (ADS)

    Leung, Larry; Davison, Damian; Cornfeld, Arthur; Towner, Frederick; Hartzell, Dave

    2001-07-01

    The rapidly expanding market of wireless communication has drastically increased the demand for GaAs-based devices and circuits. This demand has driven the industry to increasingly larger diameter substrates for cost-effective, high-volume production. IQE Inc., a division of IQE plc has recently developed the technology to grow epitaxial structures on 150 mm (6-in) GaAs substrates using a multi 6-in wafer MBE platform with material characteristics exceeding those achieved on a multi 4-in platform. The new platform is configured to produce four 6-in epiwafers per platen and is projected to produce up to 21 000 wafers per year. This paper presents the methodology that was chosen to qualify the reactor for production. Discussions focus on machine performance, material quality, and capability. In-depth discussions of capacity, throughput, and reproducibility are included. The advantages of using statistical process control for high-volume production are presented.

  17. ULYSSES - an expert-system-based VLSI design environment

    SciTech Connect

    Bushnell, M.L.

    1987-01-01

    Ulysses is a VLSI computer-aided design (CAD) environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation (DA) system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment employs artificial intelligence techniques, functions as an interactive expert system, and interprets descriptions of design tasks encoded in the scripts language. An integrated-circuit silicon compilation task is presented as an example of the ability of Ulysses to automatically execute CAD tools to solve a problem where inferencing is required to obtain a viable VLSI layout. The inferencing mechanism, in the form of a controlled production system, allows Ulysses to recover when routing channel congestion or over-constrained leaf-cell boundary conditions make it impossible for CAD tools to complete layouts. Also, Ulysses allows the designer to intervene while design activities are being carried out. Consistency-maintenance rules encoded in the scripts language enforce geometric floor-plan consistency when CAD tools fail and when the designer makes adjustments to a VLSI chip layout.

  18. High density circuit technology, part 3

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations.

  19. Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards. [Very Large Scale Integration (VLSI)

    SciTech Connect

    Pin, F.G.; Watanabe, Y.

    1992-01-01

    This paper discusses the sensor-based driving of a car in a-priori unknown environments using human-like'' reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver's aid using the new fuzzy inferencing VLSI hardware and human-like'' reasoning schemes.

  20. Techniques for the evaluation of outgassing from polymeric wafer pods

    SciTech Connect

    McIntyre, D.C.; Liang, A.; Thornberg, S.M.; Bender, S.F.; Lujan, R.D.; Blewer, R.S.; Bowers, W.D.

    1994-03-01

    In recent years there has been increasing interest in using wafer-level isolation environments or pods (microenvironments) to provide a more controllable, cleaner wafer environment during wafer processing. It has been shown that pods can be effective in reducing the amount of particulate contamination on wafers during manufacturing. However, there have also been studies that indicate that pods and wafer boxes can be the source of condensible, molecular organic contamination. This paper summarizes the work that has been performed during the past year at Sandia National Laboratories` Contamination Free Manufacturing Research Center (CFMRC) on (1) devising standard, low-temperature, high sensitivity techniques to detect outgassing of volatile organic compounds (VOCs) from polymers used to construct wafer pods and (2) development of a technique that can be used to continuously measure the condensible contamination within pods so that the pod environment can be monitored during manufacturing. Although these techniques have been developed specifically for assessing contamination threats from wafer pods, they can be used to evaluate other potential contamination sources. The high sensitivity outgassing techniques can be used to evaluate outgassing of volatiles from other clean-room materials and the real-time outgassing sensor can be used to monitor contamination condensation in non-pod environments such as ballroom-type cleanrooms and minienvironments.

  1. Direct to Digital Holography for Semiconductor Wafer Defect Detection and Review

    SciTech Connect

    ThomasJr., C. E.; Bahm, Tracy M.; Baylor, Larry R; Bingham, Philip R.; Burns, Steven W.; Chidley, Matthew D; Dai, Xiaolong; Delahanty, Robert J.; Doti, Christopher J.; El-Khashab, Ayman; Fisher, Robert L.; Gilbert, Judd M.; Cui, Hongtao; Goddard Jr, James Samuel; Hanson, Gregory R; Hickson, Joel D.; Hunt, Martin A.; Hylton, Kathy W; John, George C.; Jones, Michael L.; McDonald, Kenneth R.; Mayo, Michael W.; McMackin, Ian; Patek, David; Price, John H.; Rasmussen, David A; Schaefer, Louis J.; Scheidt, Thomas R.; Schulze, Mark A.; Schumaker, Philip D.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin Jr, Kenneth William; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Jones, Paul G.; Owen, Robert W.

    2002-01-01

    A method for recording true holograms (not holographic interferometry) directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional to wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for finding defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep ultra-violet light.

  2. On-Wafer Testing of Circuits Through 220 GHz

    NASA Technical Reports Server (NTRS)

    Gaier, Todd; Samoska, Lorene; Oleson, Charles; Boll, Greg

    1999-01-01

    We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.

  3. The uses of Man-Made diamond in wafering applications

    NASA Technical Reports Server (NTRS)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  4. Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

    NASA Technical Reports Server (NTRS)

    Aanstoos, J. V.; Snyder, W. E.

    1981-01-01

    Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

  5. Low-temperature full wafer adhesive bonding

    NASA Astrophysics Data System (ADS)

    Niklaus, Frank; Enoksson, Peter; Kälvesten, Edvard; Stemme, Göran

    2001-03-01

    We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 µm and 18 µm. The tested polymer materials were benzocyclobutene (BCB) from Dow Chemical, a negative photoresist (ULTRA-i 300) and a positive photoresist (S1818) from Shipley, a polyimide (HTR3) from Arch Chemical and two different polyimides (PI2555 and PI2610) from DuPont. The polymer material, the bonding pressure and the pre-curing time and temperature for the polymer significantly influence void formation at the bond interface. High bonding pressure and optimum pre-curing times/temperatures counteract void formation. We present the process parameters to achieve void-free bonding with the BCB coating and with the ULTRA-i 300 photoresist coating as adhesive materials. Excellent void-free and strong bonds have been achieved by using BCB as the bonding material which requires a minimum bonding temperature of 180 °C.

  6. Infrared backwards laser melting of a silicon wafer

    NASA Astrophysics Data System (ADS)

    Lill, Patrick C.; Köhler, Jürgen R.

    2015-11-01

    We investigate a method for melting a silicon wafer's rear side with a pulsed infrared laser (1064 nm) impinging onto the front side. The targeted application for this method is deep laser doping. Our numerical model simulates the evolution of the two-dimensional temperature distribution in the wafer caused by pulsed infrared laser irradiation. The model incorporates the temperature dependent material properties of silicon and the enthalpy-based phase change by means of finite volumes. The simulation yields spacial temperature distributions of the wafer's cross section at defined time steps. We obtain the laser parameters for a continuous melt depth of 40 µm in a 200 µm thick wafer from the analysis of the simulation results.

  7. Surface defects in GaAs wafer processes

    NASA Astrophysics Data System (ADS)

    Matsushita, H.; Ishida, M.; Kikawa, J.

    1990-06-01

    The causes of micro- and macro-irregularities observed on GaAs(100) polished wafers were investigated. From the results, the wafer processes were improved so that a high-quality surface was obtained without orange peel, haze, or pits. For 3-inch wafers the flatness was improved to less than 2 ?m in TTV and the warp to less than 5 ?m. Improvements in the wafer processes were: development of a better polishing solution, filtering of this solution with maintenance of the pad conditions, thereby eliminating scratches, annealing at high temperature to eliminate pits, advances in slicing and lapping to reduce warp, and three-stage double-sided polishing to eliminate dimples and to improve TTV.

  8. Estimation of wafer warpage profile during thermal processing in microlithography

    NASA Astrophysics Data System (ADS)

    Tay, Arthur; Ho, Weng Khuen; Hu, Ni; Chen, Xiaoqi

    2005-07-01

    Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps. Early detection will minimize cost and processing time. We propose in this article an in situ approach for estimating wafer warpage profile during the thermal processing steps in the microlithography process. The average air gap between wafer and bake-plate at multiple locations of a multizone bake-plate can be estimated and a profile can be obtained by joining these points. Experimental results demonstrate the feasibility and repeatability of the approach. This is a major improvement over our previously developed approach, in which only the average warpage could be obtained. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods.

  9. Efficient data transmission from silicon wafer strip detectors

    SciTech Connect

    Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

    1991-12-31

    An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

  10. Hybrid wafer-scale processor. Final report, 15 July 1988-14 January 1989

    SciTech Connect

    Jacobi, W.J.

    1989-03-14

    The basic goal of this project is to develop and demonstrate techniques for the reduction of power consumption of space-based processors for infrared-surveillance systems. The primary technique is to minimize the capacitive loading encountered in off-chip communications for highly concurrent processing architectures. Both processing architecture and chip packaging are simultaneously considered to maximize MOPS per watt by increasing throughput while reducing system capacitance, signal delay, noise, voltage swing, and power consumption (the costs of system communications). With conventional packaging technology, highly concurrent processing architectures result in hardware implementations that are extremely large, very heavy, and that consume excessive power. Monolithic wafer-scale integration is theoretically ideal but requires an extensive amount of redundant circuitry and provisions for circuit reconstructurability because of manufacturing yield problems. In the hybrid wafer-scale integration (HWSI) approach, individual pre-tested chips are bonded to a fine-line interconnect structure fabricated on the surface of a wafer-scale substrate. With this technique, high yields can be achieved without redundancy.

  11. Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

    NASA Astrophysics Data System (ADS)

    Goto, Tetsuya; Kuroda, Rihito; Akagawa, Naoya; Suwa, Tomoyuki; Teramoto, Akinobu; Li, Xiang; Obara, Toshiki; Kimoto, Daiki; Sugawa, Shigetoshi; Ohmi, Tadahiro; Kamata, Yutaka; Kumagai, Yuki; Shibusawa, Katsuhiko

    2015-04-01

    By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate-source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

  12. Low-energy silicon-on-insulator ion implanted gratings for optical wafer scale testing

    NASA Astrophysics Data System (ADS)

    Loiacono, Renzo; Reed, Graham T.; Mashanovich, Goran Z.; Gwilliam, Russell M.; Lulli, Giorgio; Feldesh, Ran; Jones, Richard

    2011-01-01

    Silicon photonics shows tremendous potential for the development of the next generation of ultra fast telecommunication, tera-scale computing, and integrated sensing applications. One of the challenges that must be addressed when integrating a "photonic layer" onto a silicon microelectronic circuit is the development of a wafer scale optical testing technique, similar to that employed today in integrated electronics industrial manufacturing. This represents a critical step for the advancement of silicon photonics to large scale production technology with reduced costs. In this work we propose the fabrication and testing of ion implanted gratings in sub micrometer SOI waveguides, which could be applied to the implementation of optical wafer scale testing strategies. An extinction ratio of over 25dB has been demonstrated for ion implanted Bragg gratings fabricated by low energy implants in submicron SOI rib waveguides with lengths up to 1mm. Furthermore, the possibility of employing the proposed implanted gratings for an optical wafer scale testing scheme is discussed in this work.

  13. Imprinted laminate wafer-level packaging for SAW ID-tags and SAW delay line sensors.

    PubMed

    Kuypers, Jan H; Tanaka, Shuji; Esashi, Masayoshi

    2011-02-01

    We have developed a wafer-level packaging solution for surface acoustic wave devices using imprinted dry film resist (DFR). The packaging process involves the preparation of an imprinted dry film resist that is aligned and laminated to the device wafer and requires one additional lithography step to define the package outline. Two commercial dry film solutions, SU-8 and TMMF, have been evaluated. Compared with traditional ceramic packages, no detectable RF parasitics are introduced by this packaging process. At the same time, the miniature package dimensions allow for wafer-level probing. The packaging process has the great advantage that the cavity formation does not require any sacrificial layer and no liquids, and therefore prevents contamination or stiction of the packaged device. This non-hermetic packaging process is ideal for passive antenna modules using polymer technology for low-cost SAW identification (ID)-tags or lidding in low-temperature cofired ceramic (LTCC) antenna substrates for high-performance wireless sensors. This technique is also applicable to SAW filters and duplexers for module integration in cellular phones using flip-chip mounting and hermetic overcoating. PMID:21342826

  14. Tool procurement planning for wafer fabrication facilities: a scenario-based approach

    E-print Network

    Swaminathan, Jayashankar M.

    Tool procurement planning for wafer fabrication facilities: a scenario-based approach JAYASHANKAR M addresses the issue of tool procurement planning at a semiconductor wafer fabrication facility which makes be divided into four basic steps: (i) wafer fabrication; (ii) wafer probe; (iii) assembly; and (iv) ®nal

  15. An accurate method for calibrating photoluminescence-based lifetime images on multi-crystalline silicon wafers

    E-print Network

    -crystalline silicon wafers H.C. Sio a,n , S.P. Phang a , T. Trupke b , D. Macdonald a a Research School of Engineering for silicon wafers with inhomogeneous lifetime distributions, such as multi-crystalline silicon wafers, based on a calibration factor extracted from a separate, homogeneous, mono-crystalline calibration wafer and simple

  16. Zinc Oxide Nanowires Low-Temperature Wafer-Scale Production of

    E-print Network

    Cohen, Ronald C.

    Zinc Oxide Nanowires Low-Temperature Wafer-Scale Production of ZnO Nanowire Arrays** Lori E. Greene aqueous conditions. We present data for arrays on four-inch (ca. 10 cm) silicon wafers and two) wafer to form a 50­200-nm thick film of crystal seeds. Between coatings, the wafer was annealed at 1508C

  17. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  18. In-Situ Investigation of Wafer-Slurry-Pad Interactions during CMP , A. Mueller

    E-print Network

    White, Robert D.

    In-Situ Investigation of Wafer-Slurry-Pad Interactions during CMP N. Braun 1 , C. Gray 1 , A) including slurry film thickness and flow, wafer-pad contact, wafer- scale friction, and small-scale shear measurements were taken on a modified Struers RotoPol-31 table top polisher in which the wafer carrier has been

  19. Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas

    E-print Network

    Kushner, Mark

    Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas Natalia Y the edge of the wafer and wafer terminating structures, such as focus rings. The intended purpose of these structures is to make the reactant fluxes uniform to the edge of the wafer and so prevent a larger than

  20. APPLICATION OF REDUCED-RANK MULTIVARIATE METHODS TO THE MONITORING OF SPATIAL UNIFORMITY OF WAFER ETCHING

    E-print Network

    Nikolaou, Michael

    1 APPLICATION OF REDUCED-RANK MULTIVARIATE METHODS TO THE MONITORING OF SPATIAL UNIFORMITY OF WAFER wafers. An industrial case study is discussed. 1 INTRODUCTION Spatially uniformity is necessary for high on 300-mm wafer surface, interpolated over 49 measurement points (black dots). Both wafers correspond

  1. Silicon Wafer Transport in a High Vacuum, Microgravity Environment Nick Pfeiffer(1)

    E-print Network

    Chapman, Glenn H.

    are studying a system based upon magnetic levitation for the transport and fixturing of wafers in the orbital of freedom through magnetic levitation. In this system, the wafer is produced with a series of circular eddy of wafers in the orbital environment. While magnetic levitation has been utilized for the transport of wafer

  2. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  3. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  4. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  5. Three dimensional integration technology using copper wafer bonding

    E-print Network

    Fan, Andy, 1976-

    2006-01-01

    With 3-D integration, the added vertical component could theoretically increase the device density per footprint ratio of a given chip by n-fold, provide a means of heterogeneous integration of devices fabricated from ...

  6. Fabrication of a mechanically aligned single-wafer MEMS turbine with turbocharger

    NASA Astrophysics Data System (ADS)

    Pelekies, S. O.; Schuhmann, T.; Gardner, W. G.; Camacho, A.; Protz, J. M.

    2010-10-01

    We describe the fabrication of a turbocharged, microelectromechanical system (MEMS) turbine. The turbine will be part of a standalone power unit and includes extra layers to connect the turbine to a generator. The project goal is to demonstrate the successful combination of several features, namely: silicon fusion bonding (SFB), a micro turbocharger [2], two rotors, mechanical alignment between two wafers [1], and the use of only one 5" silicon wafer. The dimension of the actual turbine casing will be 14mm. The turbine rotor will have a diameter of 8mm. Given these dimensions, MEMS processes are an adequate way to fabricate the device, but it will be necessary to stack up seven different layers to build the turbine, as it is not possible to construct it out of one thick wafer. SFB will be used for bonding because it permits the great precision necessary for high quality alignment. Yet a more precise alignment will be necessary between the layers that contain the turbine rotor, to decrease imbalance and guarantee operation at a very high rpm. To achieve these tight tolerances, a mechanical alignment feature announced by Liudi Jiang [1] is used. The alignment accuracy is expected to be around 200nm. Despite the fact that the turbine consists of multiple layers, it will be fabricated on only one silicon-on-insulator (SOI) wafer. As a result, all layers are exposed to the same process flow. The fabrication process includes MEMS technology as photolithography, nine deep reactive ion etching (DRIE) steps, and six SFB operations. A total of 14 masks are necessary for the fabrication.

  7. Micromachining of a fiber-to-waveguide coupler using grayscale lithography and through-wafer etch

    NASA Astrophysics Data System (ADS)

    Dillon, Thomas; Zablocki, Mathew; Shi, Shouyan; Murakowski, Janusz; Prather, Dennis

    2008-02-01

    For some time, the micro-optics and photonics fields have relied on fabrication processes and technology borrowed from the well-established silicon integrated circuit industry. However, new fabrication methodologies must be developed for greater flexibility in the machining of micro-optic devices. To this end, we have explored grayscale lithography as an enabler for the realization of such devices. This process delivers the ability to sculpt materials arbitrarily in three dimensions, thus providing the flexibility to realize optical surfaces to shape, transform, and redirect the propagation of light efficiently. This has opened the door for new classes of optical devices. As such, we present a fiber-to-waveguide coupling structure utilizing a smoothly contoured lensing surface in the device layer of a silicon-on insulator (SOI) wafer, fabricated using grayscale lithography. The structure collects light incident normally to the wafer from a singlemode optical fiber plugged through the back surface and turns the light into the plane of the device layer, focusing it into a single-mode waveguide. The basis of operation is total internal reflection, and the device therefore has the potential advantages of providing a large bandwidth, low polarization sensitivity, high efficiency, and small footprint. The structure was optimized with a simulated annealing algorithm in conjunction with two-dimensional finite-difference time-domain (FDTD) simulation accelerated on the graphics processing unit (GPU), and achieves a theoretical efficiency of approximately seventy percent, including losses due to Fresnel reflection from the oxide/silicon interface. Initial fabrication results validate the principle of operation. We discuss the grayscale fabrication process as well as the through-wafer etch for mechanical stabilization and alignment of the optical fiber to the coupling structure. Refinement of the through-wafer etch process for high etch rate and appropriate sidewall taper are addressed.

  8. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  9. High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production

    SciTech Connect

    Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

  10. Auto Defect Classification (ADC) Value for Patterned Wafer Inspection Systems in PLY Within a High Volume Wafer Manufacturing Fabrication Facility

    E-print Network

    Durniak, John

    2010-05-14

    The purpose of this investigation is to demonstrate value for Auto Defect Classification (ADC) for patterned wafer inspection systems within a high volume manufacturing fabrication in the Process Limited Yield (PLY) defect area. Process excursions...

  11. Packaging solution for VLSI electronic photonic chips

    E-print Network

    Lee, Chieh-feng

    2007-01-01

    As the demand of information capacity grows, the adoption of optical technology will increase. The issue of resistance and capacitance is limiting the electronic transmission bandwidth while fiber optic delivers data at ...

  12. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    NASA Technical Reports Server (NTRS)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  13. Image and Video Compression with VLSI Neural Networks

    NASA Technical Reports Server (NTRS)

    Fang, W.; Sheu, B.

    1993-01-01

    An advanced motion-compensated predictive video compression system based on artificial neural networks has been developed to effectively eliminate the temporal and spatial redundancy of video image sequences and thus reduce the bandwidth and storage required for the transmission and recording of the video signal. The VLSI neuroprocessor for high-speed high-ratio image compression based upon a self-organization network and the conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results.

  14. Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

    NASA Technical Reports Server (NTRS)

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

    1986-01-01

    The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

  15. Development of a Wafer Positioning System for the Sandia Extreme Ultraviolet Lithography Tool

    NASA Technical Reports Server (NTRS)

    Wronosky, John B.; Smith, Tony G.; Darnold, Joel R.

    1996-01-01

    A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

  16. 100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices

    SciTech Connect

    OLIVER,ANDREW D.; MATZKE,CAROLYN M.

    2000-04-06

    A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

  17. Development of a wafer positioning system for the Sandia extreme ultraviolet lithography tool

    SciTech Connect

    Wronosky, J.B.; Smith, T.G.; Darnold, J.R.

    1995-12-01

    A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

  18. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    NASA Astrophysics Data System (ADS)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  19. Parallel VLSI architecture emulation and the organization of APSA/MPP

    NASA Technical Reports Server (NTRS)

    Odonnell, John T.

    1987-01-01

    The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.

  20. CSCE 613: Fundamentals of VLSI Chip Design Department of Computer Science and Engineering

    E-print Network

    Bakos, Jason D.

    University of South Carolina This course is designed to tightly couple the teaching of VLSI design fundamentals with a comprehensive, industry-standard IC design flow spanning tools from the three largest

  1. Preliminary Design of the APIARY for VLSI Support of Knowledge-Based Systems

    E-print Network

    Hewitt, Carl

    Knowledge-based applications will require vastly increased computational resources to achieve their goals. We are working on the development of a VLSI Message Passing Architecture to meet this need. As a first step we ...

  2. Voltage and Timing Adaptation for Variation and Aging Tolerance in Nanometer VLSI Circuits 

    E-print Network

    Shim, Kyu-Nam 1978-

    2012-09-10

    Process variations and circuit aging continue to be main challenges to the power-efficiency of VLSI circuits, as considerable power budget must be allocated at design time to mitigate timing variations. Modern designs incorporate adaptive techniques...

  3. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  4. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  5. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    NASA Technical Reports Server (NTRS)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  6. A novel post exposure bake technique to improve CD uniformity over product wafers

    NASA Astrophysics Data System (ADS)

    Takeishi, Tomoyuki; Hayasaki, K.; Shibata, Tsuyoshi

    2005-05-01

    The impact of wafer warpage on critical dimension (CD) control is getting larger in ArF lithography. The product wafers with stacked films are warped due to the stress caused by the difference in the film stack structure between the top side and the back side of the wafers. A typical warpage of the product wafers is of convex shape, and the amount of the warpage is larger than 50 ?m for 200mm wafer. On the other hand, proximity bake method is widely used in the Post Exposure Bake (PEB). When the warped wafer is placed on the hot plate, the gap between the wafer and the hot plate varies across the wafer. That is, the temperature of the wafer center is lower than that of wafer edge. Such a temperature variation affects CD uniformity within wafer. In particular the fact is obvious in ArF chemical amplified resist because PEB sensitivity of ArF resist is larger than 5nm/degree. In this study we optimize PEB zone temperature within wafer to suit the wafer warpage. This method is based on controlling zone temperature of the PEB hot plate with concentrically divided heaters. We carry out that the CD uniformity for the warped wafer is improved by 70% compared with the conventional process.

  7. RELAXED SIGE ON INSULATOR FABRICATED VIA WAFER BONDING AND LAYER TRANSFER: ETCH-BACK AND SMART-CUT ALTERNATIVES

    E-print Network

    RELAXED SIGE ON INSULATOR FABRICATED VIA WAFER BONDING AND LAYER TRANSFER: ETCH-BACK AND SMART.25. The substrate is bonded to an oxidized Si handle wafer, and the Si backside of the SiGe wafer is ground. Various, for the Smart-cut approach, the CMPed SiGe wafer is transferred onto an oxidized Si handle wafer. In particular

  8. 232 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 16, NO. 2, APRIL 2007 Glass Blowing on a Wafer Level

    E-print Network

    Chen, Zhongping

    232 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 16, NO. 2, APRIL 2007 Glass Blowing on a Wafer--A fabrication process for the simultaneous shaping of arrays of glass shells on a wafer level is introduced wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature

  9. Negative Photolithography Process Procedure with SU -8 Lithography consists of the following basic steps: Wafer preparation, photoresist

    E-print Network

    Kassegne, Samuel Kinde

    steps: Wafer preparation, photoresist coating, softbaking, exposing to UV light, post-exposure baking, and developing. 1. Prepare Wafer I. Simple Cleaning To remove contaminants from the wafer surface. a. Clean all equipment (wafer holders, tweezers, etc.) with acetone to avoid wafer contamination. b. Cover the surface

  10. Positive Photolithography Process Procedure with Shipley's 1813 Lithography consists of the following basic steps: Wafer preparation, photo resist

    E-print Network

    Kassegne, Samuel Kinde

    of the following basic steps: Wafer preparation, photo resist Coating, soft baking, exposing to UV light, post-exposure baking, and developing. 1. Prepare Wafer I. Simple Cleaning To remove contaminants from the wafer surface. a. Clean all equipment (wafer holders, tweezers, etc.) with acetone to avoid wafer contamination. b

  11. Case studies on lithography-friendly vlsi circuit layout 

    E-print Network

    Shah, Pratik Jitendra

    2009-05-15

    to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual wafer feature sizes. However, the layout which affects the printability of a circuit can be modified in a manner which can make it more...

  12. Noble approach for mask-wafer measurement by design-based metrology integration system

    NASA Astrophysics Data System (ADS)

    Mito, Hiroaki; Hayano, Katsuya; Maeda, Tatsuya; Mohri, Hiroshi; Sato, Hidetoshi; Matsuoka, Ryoichi; Sukegawa, Shigeki

    2009-10-01

    OPC technique is getting more complicated toward 32nm and below technology node, i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and then the manufacturing process of them is complicated now. In order to shorten TAT (Turn around time) time, mask technique need be considered in addition to lithography technique. Furthermore, the lens aberration of the exposure system is getting smaller, so the current performance of it is very close to the ideal. On the other hand, when down sizing goes down to 32nm technology node, it starts to be reported that there are cases that size cannot be matched between a mask pattern and the corresponding printed pattern. Therefore, it is very indispensable to understand the pattern sizes correlation between a mask and the corresponding printed wafer in order to improve the accuracy and the quality, in the situation that the device size is so small that low k1 lithography had been developed and widely used in a production. Then it is thought that it is one of the approaches to improve an estimated accuracy of lithography by using contour that was extracted from mask SEM image in addition to mask model. This paper describes a newly developed integration system in order to solve issues above, and the applications. This is a system which integrates CG4500; CD-SEM for mask and CG4000; CD SEM for wafer; using DesignGauge; OPC evaluation system by Hitachi High-Technologies. It was investigated that a measurement accuracy improvement by executing a mask-wafer same point measurement with same measurement algorithm utilizing the new system. At first, we measured patterns described on a mask and verified the validity based on a measurement value, picture, measurement parameter and the coordinate. Then create a job file for a wafer CD-SEM using the system so as to measure the same patterns that were exposed using the mask. In addition, average CD measurement was tried in order to improve the correlation. Also, in order to estimate very accurate pattern shape, a contour was calculated from a mask SEM image, the result and the design data was used in a litho simulation. This realizes verification including mask error. It is thought that it is beneficial for both mask maker and device maker to use this system.

  13. Wafer heating mechanisms in a molecular gas, inductively coupled plasma: in situ, real time wafer surface measurements and three-dimensional thermal modeling

    SciTech Connect

    Titus, M. J.; Graves, D. B.

    2008-09-15

    The authors report measurements and modeling of wafer heating mechanisms in an Ar/O{sub 2} inductively coupled plasma (ICP). The authors employed a commercially available on-wafer sensor system (PlasmaTemp developed by KLA-Tencor) consisting of an on-board electronics module housing battery power and data storage with 30 temperature sensors embedded onto the wafer at different radial positions. This system allows for real time, in situ wafer temperature measurements. Wafer heating mechanisms were investigated by combining temperature measurements from the PlasmaTemp sensor wafer with a three-dimensional heat transfer model of the wafer and a model of the ICP. Comparisons between pure Ar and Ar/O{sub 2} discharges demonstrated that two additional wafer heating mechanisms can be important in molecular gas plasmas compared to atomic gas discharges. The two mechanisms are heating from the gas phase and O-atom surface recombination. These mechanisms were shown to contribute as much as 60% to wafer heating under conditions of low bias power. This study demonstrated how the 'on-wafer' temperature sensor not only yields a temperature profile distribution across the wafer, but can be used to help determine plasma characteristics, such as ion flux profiles or plasma processing temperatures.

  14. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  15. Optical evaluation of ingot fixity in semiconductor wafer slicing

    NASA Astrophysics Data System (ADS)

    Ng, T. W.; Nallathamby, R.

    2004-11-01

    The fixity of an ingot may greatly affect the quality of wafers produced during a wire saw process and improved mechanical clamping is a means for improving ingot fixity. Here, an optical technique that is based on laser beam deflection is described. The technique was demonstrated on ingot assemblies subjected to impulse loads within a prescribed range using an original and improved clamping system. The technique revealed that the ingot assembly had lower degrees of mean displacement and standard displacement deviation under the improved clamping system. The data on warp obtained from the actual production of wafers corroborates this finding. The technique described is an effective method of quantitatively evaluating the fixity of ingots in a wafer wire saw process.

  16. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  17. Temperature influence in confocal techniques for a silicon wafer testing

    NASA Astrophysics Data System (ADS)

    Litwin, D.; Galas, J.; Sitarek, S.; Surma, B.; Piatkowski, B.; Miros, A.

    2007-05-01

    The paper discusses problems of Silicon wafer measurements accuracy in context of the scanning helium atom microscope, which is a new technique currently under development. In the microscope the helium atom beam is used as a probe. The overall microscope resolution depends on a deflecting element, which shapes the beam and focuses it onto a sample's surface. The most promising focusing component appears to be an ultra thin silicon wafer that is deformed under a precise electric field. Thus its quality is decisive for the project success. Flatness and thickness uniformity of the wafer must be measured in order to select the best plate to be used in the microscope. A scanning measurement system consists of two coaxially positioned confocal heads. Recent studies have revealed that the system is very sensitive to temperature variation. The compensation algorithms and further measures designed to suppress the temperature effect are presented and discussed.

  18. Minority lifetime degradation of silicon wafers after electric zone melting

    NASA Astrophysics Data System (ADS)

    Wu, M. C.; Yang, C. F.; Lan, C. W.

    2015-06-01

    The degradation of minority lifetime of mono- and multi-crystalline silicon wafers after electric zone melting, a simple and contamination-free process, was investigated. The thermal-stress induced dislocations were responsible to the degradation; however, the grain size also played a crucial role. It was believed that the grain boundaries helped the relaxation of thermal stress, so that the degradation was reduced as the grain size decreased. In addition to lifetime mapping and etch pit density, photoluminescence mapping was also used to examine the electrically active defects after zone melting. Factors affecting lifetime degradation of silicon wafers after electric zone melting were examined. Small-grain multi-crystalline wafers showed better lifetime after zone melting. Twining area showed better lifetime. The formation of new grains relaxed the thermal stress mitigating lifetime degradation.

  19. The Relationship between the Bending Stress in Silicon Wafers and the Mechanical Strength of Silicon Crystals

    NASA Astrophysics Data System (ADS)

    Fukuda, Tetsuo

    1995-06-01

    Silicon wafers horizontally stacked in a vertical furnace bend downward due to their weight. Using a linear elastic theory, we calculated the shear stress caused by the wafer bending and investigated the mechanical strength by comparing the shear stress with the upper yield stress of silicon crystals. We concluded that the maximum shear stress increased with the increase in the wafer diameter, 0.20, 0.30, and 0.55 MPa for 6, 8, and 12 inch wafers. In bending the 12 inch wafers, oxygen precipitates, lowering the upper yield stress, caused serious wafer warping because the shear stress exceeded the lowered yield stress.

  20. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  1. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, Theodoer F. (31843 Miwok Trail, P.O. Box 1453, Evergreen, CO 80439)

    1995-01-01

    Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

  2. VLSI processor with a configurable processing element array for balanced feature extraction in high-resolution images

    NASA Astrophysics Data System (ADS)

    Zhu, Hongbo; Shibata, Tadashi

    2014-01-01

    A VLSI processor employing a configurable processing element array (PEA) is developed for a newly proposed balanced feature extraction algorithm. In the algorithm, the input image is divided into square regions and the number of features is determined by noise effect analysis in each region. Regions of different sizes are used according to the resolutions and contents of input images. Therefore, inside the PEA, processing elements are hierarchically grouped for feature extraction in regions of different sizes. A proof-of-concept chip is fabricated using a 0.18 µm CMOS technology with a 32 × 32 PEA. From measurement results, a speed of 7.5 kfps is achieved for feature extraction in 128 × 128 pixel regions when operating the chip at 45 MHz, and a speed of 55 fps is also achieved for feature extraction in 1920 × 1080 pixel images.

  3. On the viscoplastic response of a composite wafer

    NASA Technical Reports Server (NTRS)

    Valanis, K. C.; Landel, R. F.; Peng, S. T. J.

    1988-01-01

    In the present treatment of a viscoplastic composite wafer formed from a viscoplastic matrix that is reinforced by elastic or viscoplastic fibers attached to its plane surfaces, one constitutive equation is established by considering the viscoplastic behavior of the matrix as determined by an integral-type constitutive law whose intrinsic time-measure is pertinent to endochronic viscoplasticity. Attention is given to asymptotic cases where fiber stiffnesses and the hydrostatic modulus of the wafer are much larger than the latter's shear modulus. An explicit calculation is used when the stress field is uniaxial.

  4. Computational Modeling in Plasma Processing for 300 mm Wafers

    NASA Technical Reports Server (NTRS)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  5. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  6. Rayleigh surface wave in a piezoelectric wafer with subsurface damage

    NASA Astrophysics Data System (ADS)

    Cao, Xiaoshan; Jin, Feng; Jeon, Insu

    2009-12-01

    An analytical study is carried out on the propagation of Rayleigh surface waves in a piezoelectric wafer with subsurface damage. The region of subsurface damage is considered to be a functionally graded piezoelectric thin film. The findings show the influence of the gradient parameter, thickness of the region of subsurface damage, and three different types of damage on the properties of surface-wave propagation, including the phase velocity and electromechanical coupling factor. They can provide theoretical guidance in nondestructive evaluation for the analysis of the reliability and durability of electronic devices made of piezoelectric wafers.

  7. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease

    PubMed Central

    Niu, Chuanxin M.; Nandyala, Sirish K.; Sanger, Terence D.

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin–Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems. PMID:25538613

  8. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    PubMed

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems. PMID:25538613

  9. The influence of wafer elasticity on acoustic waves during LIGA development.

    SciTech Connect

    Ting, Aili

    2003-12-01

    During acoustically stimulated LIGA development, a wafer receives sound waves from both sides at a wide variety of incidence angles that vary in time depending on the orientation of the wafer relative to the multiple transducers that are typically actuated in a periodic sequence. It is important to understand the influence of these variables on the transmission of energy through the wafer as well as the induced motion of the wafer itself because these processes impact the induced acoustic streaming of the fluid within features, the mechanism presently thought responsible for enhanced development of LIGA features. In the present work, the impact of wafer elasticity on LIGA development is investigated. Transmission waves, wafer bending waves, and the related concepts such as critical bending frequency, mechanical impedance, coincidence, and resonance, are discussed. Supercritical-frequency incident waves induce supersonic bending waves in the wafer. Incident wave energy is channeled into three components, transmitted, reflected and energy deposited to the wafer, depending on the wafer material, thickness and wave incidence angle. Results show at normal incidence for a 1-mm PMMA wafer, about 47% of the wave energy is deposited in the wafer. The wafer gains almost half of the incident energy, a result that agrees well with the Bankert et a1 measurements. In LIGA development, transmitted waves may sometimes produce strong acoustic motion of the developer on the wafer backside, especially for the so-called coincidence case in which almost all incident wave energy transfers to the backside. Wafer bending waves cause wafer oscillation at high frequency, promoting the development process, but features shaking may weaken their attachments to the substrate. Resonance is not likely for the entire wafer, but may occur in short and wide wafer feature columns, which are least likely to break away from the substrate, perhaps resulting in good agitation of the fluid in adjacent feature cavities.

  10. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

    PubMed Central

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-01-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

  11. Wafer and reticle positioning system for the Extreme Ultraviolet Lithography Engineering Test Stand

    SciTech Connect

    WRONOSKY,JOHN B.; SMITH,TONY G.; CRAIG,MARCUS J.; STURGIS,BEVERLY R.; DARNOLD,JOEL R.; WERLING,DAVID K.; KINCY,MARK A.; TICHENOR,DANIEL A.; WILLIAMS,MARK E.; BISCHOFF,PAUL

    2000-01-27

    This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EUVL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100nm. EUVL research and development includes development of capabilities for demonstrating key EUV technologies. The ETS is under development at the EUV Virtual National Laboratory, to demonstrate EUV full-field imaging and provide data that supports production-tool development. The stages and their associated metrology operated in a vacuum environment and must meet stringent outgassing specifications. A tight tolerance is placed on the stage tracking performance to minimize image distortion and provide high position repeatability. The wafer must track the reticle with less than {+-}3nm of position error and jitter must not exceed 10nm rms. To meet these performance requirements, magnetically levitated positioning stages utilizing a system of sophisticated control electronics will be used. System modeling and experimentation have contributed to the development of the positioning system and results indicate that desired ETS performance is achievable.

  12. Design and implementation of moment invariants for pattern recognition in VLSI (very large scale integration)

    SciTech Connect

    Armstrong, G.A.; Simpson, M.L. ); Bouldin, D.W. )

    1990-01-01

    This paper describes the design of a very large scale integration (VLSI) application specific integrated circuit (ASIC) for use in pattern recognition. The pattern recognition scheme uses Hu and Maitra's algorithms for moment invariants. A prototype design was generated that resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain. Use of the Manchester carry chain effectively incorporated the lookahead carry function into the adder cells. The prototype ASIC is currently being fabricated in 2.0-mm compiled simulator for metal oxide semiconductor (CMOS) technology (simulated at 20 MHz). The prototype consisted of a 4 {times} 8 multiplier and a 12-bit accumulator stage. The present ASIC design consists of a 9 {times} 26 multiplier (maximum propagation time of 50 ns) and a 48-bit accumulator stage. The final ASICs will be used in parallel at the board level to achieve the 56 MegaPixels/s (230 million operations per second (MOPs)) necessary to perform the moment invariant algorithms in real time on 512 {times} 512 pixel images with 256 grey scales. 11 refs., 3 figs., 7 tabs.

  13. An architecture for an analog VLSI neural network for early computer vision processing

    NASA Astrophysics Data System (ADS)

    Haule, D. D.; Malowany, M. E.; Lambidonis, D.; Nemawarkar, S.; Sayegh, S.; Malowany, A. S.

    A two-stage early vision algorithm for curve description in images has been targeted for an analog very large scale integration (VLSI) implementation. Similarity between the processing in the two algorithm stages is exploited, resulting in a single modular chip capable of performing either processing stage. The core of the circuitry is a parallel convolution array modeled after connectionist artificial neural network structures. Pipelining of the image data is applied, using on-chip temporary analog storage to implement neighborhood operations. On-chip long-term analog storage for algorithm parameters is proposed using floating-gate electronically erasable programmable read-only memory technology. The chip, whose approximate transistor count is 15,000, is designed for a complementary metal oxide semiconductor (CMOS) 1.2 micron double-metal process. An effort is made to maintain the transistors in the subthreshold region of operation to decrease power requirements, particularly in the analog convolution array which forms the bulk of the chip and is of concern for scaling up the array size in the future.

  14. Investigation of VLSI Bipolar Transistors Irradiated with Electrons, Ions and Neutrons for Space Application

    NASA Astrophysics Data System (ADS)

    D'Angelo, P.; Fallica, G.; Galbiati, A.; Mangoni, R.; Modica, R.; Pensotti, S.; Rancoita, P. G.

    2006-04-01

    A systematic investigation of radiation effects on a BICMOS technology manufactured by STM has been undertaken. Bipolar transistors were irradiated by neutrons, C, Ar and Kr ions, and recently by electrons. Fast neutrons, as well as other types of particles, produce defects mainly by displacing silicon atoms from their lattice positions to interstitial locations, i.e. generating vacancy-interstitial pairs (the so-called Frenkel pairs). Although imparted doses differ largely, the experimental results indicate that the gain (?) variation is mostly related to the non-ionizing energy-loss (NIEL) deposition for neutrons, ions and electrons. The variation of the inverse of the gain degradation, ?(1/?), is found to be linearly related (as predicted by the Messenger-Spratt equation for neutron irradiations) to the concentrations of the Frenkel pairs generated independently of the kind of incoming particle. For space applications, this linear dependence on the concentration of Frenkel pairs allows to evaluate the total amount of the gain degradation of VLSI components due to the flux of charged particles during the full life of operation of any pay-load. In fact, the total amount of expected Frenkel pairs can be estimated taking into account the isotopic spectra. It has to be point out that in cosmic rays there is relevant flux of electrons and isotopes up to Ni, which are within the range of particles presently investigated.

  15. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

  16. Characteristics and issues of haze management in a wafer fabrication environment

    NASA Astrophysics Data System (ADS)

    Woo, Sung Ha; Hwang, Dae Ho; Jeong, Goo Min; Lee, Young Mo; Kim, Sang Pyo; Yim, Dong Gyu

    2014-10-01

    The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been promoted in the semiconductor industry which has been shown to suppress or minimize the propensity for haze formation, but none of these technologies can stop every instance of haze. Fortunately, a novel technology which uses a dry (no chemical effluents) removal system, laser-based, through pellicle process has been reported recently. The technology presented here avoids many of the shortcomings of the wet clean process mentioned previously. The dry clean process extends the life of the photomask; maintains more consistent CD's, phase, and transmission; avoids adjustment to the exposure dose to account for photomask changes, reduces the number of required inspections and otherwise improves the efficiency and predictability of the lithography cell. We report on the performance of photomask based on a design developed to study the impact of metrology variations on dry clean process. In a first step we focus on basic characteristics: CD variation, phase, Cr/MoSi transmission, pellicle transmission, registration variations. In a second step, we evaluate haze removal and prevention performance and wafer photo margin. Haze removal is studied on the masks for several haze types and various exposure conditions. The results of this study show that some of metrology variation are likely to be a problem at high technology node, and haze removal performance is determined whether the component of haze is remained or not after treatment.

  17. Multi-wafer slicing with a fixed abrasive

    NASA Technical Reports Server (NTRS)

    Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

    1988-01-01

    A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

  18. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  19. Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements

    E-print Network

    Kao, Imin

    Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements I. Kao (PI), S the yield per crystal and to reduce the cost. In this paper, the vibration model of wiresaw system of vibration indicate the interference of excitation and natural frequencies in the vibration patterns

  20. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  1. Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence

    E-print Network

    Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence H. C. Sio, Z-mediated nonclassical crystal growth of sodium fluorosilicate nanowires and nanoplates AIP Advances 1, 042165 (2011) Crystal phase and growth orientation dependence of GaAs nanowires on NixGay seeds via vapor

  2. Efficient VLSI architecture for training radial basis function networks.

    PubMed

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  3. VLSI-based Video Event Triggering for Image Data Compression

    NASA Technical Reports Server (NTRS)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  4. A laser plotting system for VLSI chip layouts

    NASA Technical Reports Server (NTRS)

    Deutsch, L. J.; Harding, J. A.

    1985-01-01

    One of the most time consuming facets of custom Very Large Scale Integration (VLSI) design is obtaining hardcopy plots of the mask geometries of cells and chips. The traditional method of generating these plots is to use a multicolor pen plotter. Pen plotters are inherently slow and the plotting speed increases linearly with the number of edges that must be plotted. A moderate custom chip design at the Jet Propulsion Laboratory (JPL) now consists of more than 200,000 such edges and can take as much as eight hours to plot using a pen plotter. Software is described that was written at JPL to produce similar plots using a laser printer. It is shown that, for rather small layouts, the laser printer can provide nearly instantaneous turnaround. For moderate to large chip designs, the laser printer provides a factor of five or more improvement is speed over pen plotting.

  5. A Wafer-Scale Etching Technique for High Aspect Ratio Implantable MEMS Structures

    PubMed Central

    Bhandari, R; Negi, S; Rieth, L.; Solzbacher, F

    2010-01-01

    Microsystem technology is well suited to batch fabricate microelectrode arrays, such as the Utah electrode array (UEA), intended for recording and stimulating neural tissue. Fabrication of the UEA is primarily based on the use of dicing and wet etching to achieve high aspect ratio (15:1) penetrating electrodes. An important step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Traditional etching processes are performed on a single array, and the etching conditions are not optimized. As a result, the process leads to variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. This report presents a wafer-scale etching method for the UEA. The method offers several advantages, such as substantial reduction in the processing time, higher throughput and lower cost. More importantly, the method increases the geometrical uniformity from electrode to electrode within an array (1.5 ± 0.5 % non-uniformity), and from array to array within a wafer (2 ± 0.3 % non-uniformity). Also, the etching rate of silicon columns, produced by dicing, are studied as a function of temperature, etching time and stirring rate in a nitric acid rich HF-HNO3 solution. These parameters were found to be related to the etching rates over the ranges studied and more-importantly affect the uniformity of the etched silicon columns. An optimum etching condition was established to achieve uniform shape electrode arrays on wafer-scale. PMID:20706618

  6. Integrated optical MEMS using through-wafer vias and bump-bonding.

    SciTech Connect

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  7. Spike-driven synaptic plasticity: theory, simulation, VLSI implementation.

    PubMed

    Fusi, S; Annunziato, M; Badoni, D; Salamon, A; Amit, D J

    2000-10-01

    We present a model for spike-driven dynamics of a plastic synapse, suited for aVLSI implementation. The synaptic device behaves as a capacitor on short timescales and preserves the memory of two stable states (efficacies) on long timescales. The transitions (LTP/LTD) are stochastic because both the number and the distribution of neural spikes in any finite (stimulation) interval fluctuate, even at fixed pre- and postsynaptic spike rates. The dynamics of the single synapse is studied analytically by extending the solution to a classic problem in queuing theory (Takacs process). The model of the synapse is implemented in aVLSI and consists of only 18 transistors. It is also directly simulated. The simulations indicate that LTP/LTD probabilities versus rates are robust to fluctuations of the electronic parameters in a wide range of rates. The solutions for these probabilities are in very good agreement with both the simulations and measurements. Moreover, the probabilities are readily manipulable by variations of the chip's parameters, even in ranges where they are very small. The tests of the electronic device cover the range from spontaneous activity (3-4 Hz) to stimulus-driven rates (50 Hz). Low transition probabilities can be maintained in all ranges, even though the intrinsic time constants of the device are short (approximately 100 ms). Synaptic transitions are triggered by elevated presynaptic rates: for low presynaptic rates, there are essentially no transitions. The synaptic device can preserve its memory for years in the absence of stimulation. Stochasticity of learning is a result of the variability of interspike intervals; noise is a feature of the distributed dynamics of the network. The fact that the synapse is binary on long timescales solves the stability problem of synaptic efficacies in the absence of stimulation. Yet stochastic learning theory ensures that it does not affect the collective behavior of the network, if the transition probabilities are low and LTP is balanced against LTD. PMID:11032032

  8. Damascene patterned metal/adhesive wafer bonding for three-dimensional integration

    NASA Astrophysics Data System (ADS)

    McMahon, J. Jay

    Wafer bonding of damascene patterned metal/adhesive surfaces is explored for a new three-dimensional (3D) integration technology platform. By bonding a pair of damascene patterned metal/adhesive layers, high density micron-sized vias can be formed for interconnection of fully fabricated integrated circuit (IC) dies at the wafer-level. Such via dimensions increase the areal interconnect density by at least two orders of magnitude over current package and die-stacking approaches to 3D integration. The adhesive field-dielectric produces a high critical adhesion energy bond and has the potential to produce void-free bonded interfaces. This new technology platform has been demonstrated by fabricating and characterizing inter-wafer via-chains on 200 mm diameter Si wafers. Copper and partially cured divinylsiloxane bis-benzocyclobutene (BCB) are selected as the metal and adhesive, respectively, and unit processes for this demonstration are described. Typical alignment tolerance is ˜2 mum, and baseline bonding conditions include vacuum of 5x10-4 mbar, bonding force of 10 kN, and two step bonding temperature of 250°C for 60 min followed by 350°C for 60 min. Integration issues associated with the damascene patterning and the wafer bonding processes are discussed, particularly the resulting topography of damascene patterned Cu/BCB. Cross-sectional investigation of bonded and annealed inter-wafer interconnections provides insight into the Cu-Cu and BCB-BCB bonding interfaces. Inter-wafer specific contact resistance is measured to be on the order of 10-7 O-cm 2 for these via-chains. Several material characterization techniques have been explored to evaluate partially cured BCB as an adhesive field-dielectric. To investigate the critical adhesion energy, Gc, four-point bending is utilized to compare surfaces bonded after chemical-mechanical planarization (CMP) and various post-CMP treatments. The Gc of bonded 50% partially cured BCB is measured to be in the range of 32--44 J/m2. The elastic modulus of the BCB is investigated by monitoring film stress behavior for temperatures just below that needed for crosslinking (i.e. the temperature where BCB-BCB bonding begins). The film-stress temperature dependence is then used as an indicator for phase transitions in the BCB that affect elastic modulus. Surface analysis techniques are used to explore the surface chemistry of the BCB and measure its surface energy over the temperature range required for bonding. The surface energy of partially cured BCB at both 50 and 90% crosslinking is measured to decrease by ˜30% when the temperature is raised from 35°C to 230°C. The surface analysis and mechanical properties studies provide insight into the capability of BCB to close gaps when in contact during bonding, a necessary condition for forming void-free bonding interfaces. One important aspect for implementing wafer-level 3D integration is the ability of a technology platform to accommodate topography on fully fabricated wafers. The aforementioned metal/adhesive 3D platform has strict requirements in this regard if void-free surfaces are to be attained. A bonding protocol that eliminates the copper and tantalum interconnect structure is utilized to investigate the deformation capability of partially cured BCB during bonding. The results indicate that the defect density of such BCB-BCB bonds depends on material parameters such as the degree of crosslinking and surface energy, the pitch of the features, and the depth of the topography to be accommodated. For 70--90% crosslinked BCB, accommodation was observed for lines ˜120 nm deep and ˜100 mum in pitch. Furthermore, 70--90% crosslinked BCB lines with pitch ˜1 mum and depth ˜12 nm were accommodated during bonding. When the BCB crosslinking is reduced to 50%, additional accommodation is observed. In such cases, lines with pitch ˜100 mum and depth ˜500 nm, and those with pitch ˜1 mum and depth ˜50 nm were accommodated. Additional work has shown that accommodation of some topography is possible even with zero down-force during bonding. Th

  9. Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR versus NCR Sagar S. Sabade*

    E-print Network

    Walker, Duncan M. "Hank"

    Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR versus NCR Sagar S. Sabade* D. M. H in IDDQ at the wafer level for estimating fault-free IDDQ of a chip are proposed. This paper compares two its sensitivity is a topic of research in recent years [1][2]. Several methods that use wafer

  10. Integration of Self-Assembled Three-Dimensional Photonic Crystals onto Structured Silicon Wafers

    E-print Network

    Jonsson, Fredrik

    Integration of Self-Assembled Three-Dimensional Photonic Crystals onto Structured Silicon Wafers silica spheres (diameter of 890 nm), self-assembled in hydrophilic trenches of silicon wafers by using a spatial selectivity of opal crystallization without special treatment of the wafer surface, a filling

  11. Improved Wafer-level Spatial Analysis for IDDQ Limit Setting Sagar Sabade D. M. H. Walker

    E-print Network

    Walker, Duncan M. "Hank"

    Improved Wafer-level Spatial Analysis for IDDQ Limit Setting Sagar Sabade D. M. H. Walker methodology for estimating the upper bound on the IDDQ of defect free chips by using wafer level spatial data. Such a methodology accounts for the change in IDDQ due to process variations across wafers

  12. Integrated Modeling of Wiresaw in Wafer Slicing I. Kao (PI), M. Bhagavat, V. Prasad

    E-print Network

    Kao, Imin

    Integrated Modeling of Wiresaw in Wafer Slicing I. Kao (PI), M. Bhagavat, V. Prasad Department of an integrated model of the wiresaw manufacturing processes in wafer slicing. The wiresaw, utilizing the "Free) and large diameter ( 200 mm) wafers required in photovoltaic and semiconductor industries, respectively. FAM

  13. MultiProject Reticle Design and Wafer Dicing under Uncertain Demand #

    E-print Network

    Kahng, Andrew B.

    Multi­Project Reticle Design and Wafer Dicing under Uncertain Demand # Andrew B. Kahng, Ion M wafers (MPW) have been proposed as an effective technique for sharing the cost of mask tooling among up optimizations that arise in this context: reticle design under demand uncertainty and on­ demand wafer dicing

  14. wafer bonding approach allows point de-fects and potentially also waveguides to be

    E-print Network

    Zhuang, Xiaowei

    188 wafer bonding approach allows point de- fects and potentially also waveguides to be introduced parallel to the layers by proper lithography. In addition, wafer bonding can incorporate a layer that acts implica- tions? In principle, the combination of li- thography, etching, and wafer bonding could

  15. Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels

    E-print Network

    Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels Wei. wafers using NIL at all lithography levels. The nanotransistors exhibit excellent operational characteristics across the wafer. The statistics from consecutive multiwafer processing show an average overlay

  16. Mechanically flexible thin-film transistors that use ultrathin ribbons of silicon derived from bulk wafers

    E-print Network

    Rogers, John A.

    wafers S. Mack, M. A. Meitl, A. J. Baca, Z.-T. Zhu, and J. A. Rogersa Department of Materials Science created by lithographic patterning and anisotropic etching of bulk silicon 111 wafers. Devices described top-down methods5­11 generate semicon- ductor wires, ribbons, and sheets from wafer based sources

  17. Wafer Topography-Aware Optical Proximity Correction for Better DOF Margin and CD Control

    E-print Network

    Kahng, Andrew B.

    Wafer Topography-Aware Optical Proximity Correction for Better DOF Margin and CD Control Puneet are oblivious to the predictable nature of focus variation arising from wafer topography. As a result, designers that is generated by CMP simulation. The wafer topography variations result in local defocus, which we explicitly

  18. Megasonic cleaning of wafers in electrolyte solutions: Possible role of electro-acoustic and cavitation effects

    E-print Network

    Deymier, Pierre

    Megasonic cleaning of wafers in electrolyte solutions: Possible role of electro Keywords: Wafer Cleaning Electrolyte Megasonic Electro-acoustic Cavitation Pressure amplitude a b s t r a c t Investigations have been conducted on the feasibility of removal of particles from silicon wafers in elec

  19. Noncontact semiconductor wafer characterization with the terahertz Hall D. M. Mittleman,a)

    E-print Network

    Natelson, Douglas

    Noncontact semiconductor wafer characterization with the terahertz Hall effect D. M. Mittleman,a) J wafers with roughly 250 m spatial resolution, using polarization rotation of focused beams of terahertz carrier density and mobility of a doped semiconductor wafer have been obtained. © 1997 American Institute

  20. Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand*

    E-print Network

    Kahng, Andrew B.

    Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand* Andrew B. Kahng, Ion leads to dramatic increases in mask costs. In response to this trend, mUltiple project wafers (MPW) have in this context: reticle design under demand uncertainty and on demand wafer dicing. Preliminary experiments

  1. Behaviour of Natural and Implanted Iron during Annealing of Multicrystalline Silicon Wafers

    E-print Network

    Behaviour of Natural and Implanted Iron during Annealing of Multicrystalline Silicon Wafers Daniel, recombination Abstract. Changes in the concentration of interstitial iron in multicrystalline silicon wafers-grown multicrystalline silicon wafers. Introduction Iron is a common impurity in multicrystalline silicon (mc

  2. Supplemental Information for "Variations in properties of atomic force microscope cantilevers fashioned from the same wafer"

    E-print Network

    Chan, Derek Y C

    fashioned from the same wafer" Grant B. Webber1,2 , Geoffrey W. Stevens1 , Franz Grieser2 , Raymond R microscopy of 101 V-shaped cantilevers derived from the same wafer as received from the manufacturer by the thermal method and optical microscopy of 101 V-shaped cantilevers derived from the same wafer as received

  3. Theoretical calculation of the acoustic force on a patterned silicon wafer during megasonic cleaning

    E-print Network

    Deymier, Pierre

    Theoretical calculation of the acoustic force on a patterned silicon wafer during megasonic wafer immersed in water subjected to a megasonic beam. The method of calculation is based on a Green as a function of frequency and the angle the incident megasonic beam makes with the wafer surface

  4. Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand

    E-print Network

    Zelikovsky, Alexander

    Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand Andrew B. Kahng, Ion Mandoiu leads to dramatic increases in mask costs. In response to this trend, multiple project wafers (MPW) have in this context: reticle design under demand uncertainty and on- demand wafer dicing. Preliminary experiments

  5. Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs

    E-print Network

    Lü, James Jian-Qiang

    Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs J Montopolis Drive, Austin TX 78741 Abstract -- Electrical and mechanical impacts of wafer bonding and thinning interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer

  6. A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer

    E-print Network

    Müftü, Sinan

    A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer Dinçer, Massachusetts 02115, USA Applied pressure in chemical mechanical polishing CMP is shared by the two-body pad­wafer and the three-body pad­abrasive­ wafer contacts. The fraction of applied pressure transferred through

  7. Spatio-Temporal Wafer-Level Correlation Modeling with Progressive Sampling: A Pathway to HVM

    E-print Network

    Makris, Yiorgos

    Spatio-Temporal Wafer-Level Correlation Modeling with Progressive Sampling: A Pathway to HVM Yield Abstract--Wafer-level spatial correlation modeling of probe- test measurements has been explored of a popular Gaussian process-based wafer-level spatial correlation method through two key enhancements: (i

  8. Multilevel nanoimprint lithography with submicron alignment over 4 in. Si wafers

    E-print Network

    Multilevel nanoimprint lithography with submicron alignment over 4 in. Si wafers Wei Zhanga that multilevel nanoimprint lithography NIL with submicron alignment over an entire 4 in. Si wafer can be achieved in ten consecutive tests of multilevel NIL. The multilevel alignment was achieved by aligning the wafer

  9. Test Cost Analysis for 3D Die-to-Wafer Stacking Mottaqiallah Taouil1

    E-print Network

    Test Cost Analysis for 3D Die-to-Wafer Stacking Mottaqiallah Taouil1 Said Hamdioui1 Kees Beenakker2 footprint. Several 3D stacking approaches are under development. From a yield point of view, Die-to-Wafer (D the stack yield is the best approach to use. Keywords: 3D test flow, 3D test cost, Die-to-Wafer stack- ing

  10. Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques

    E-print Network

    Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques Gianni-insulator include SIMOX, Ge condensation and wafer bonding. In this paper, a brief introduction of each method is presented, with a detailed discussion of wafer bonding approaches for strained Si, SiGe, and Ge on

  11. Numerical Simulation of a Single-Wafer Isothermal Plasma Etching Reactor

    E-print Network

    Economou, Demetre J.

    Numerical Simulation of a Single-Wafer Isothermal Plasma Etching Reactor Sang-Kyu Parkand Demetre J-plate single- wafer isothermal reactor was conducted. The oxygen plasma etching of polymer under high pressure as the flow rate increased. Etching rate increased but etching uniformity degraded as the wafer reactivity

  12. Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests

    E-print Network

    Makris, Yiorgos

    Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests Ke of wafer-level measurements has recently attracted increased attention. Exist- ing approaches for capturing spatial correlation modeling of wafer- level analog/RF tests to handle such effects and, thereby

  13. Determining Pad-Wafer Contact using Dual Emission Laser Induced Fluorescence Caprice Gray1

    E-print Network

    White, Robert D.

    Determining Pad-Wafer Contact using Dual Emission Laser Induced Fluorescence Caprice Gray1 , Chris operating during CMP requires knowledge of the nature of the pad-wafer contact. Dual Emission Laser Induced Fluorescence (DELIF) can be used to study the fluid layer profile between the polishing pad and the wafer

  14. Mask blank defect printability comparison using optical and SEM mask and wafer inspection and bright field actinic mask imaging

    NASA Astrophysics Data System (ADS)

    Mangat, Pawitter; Verduijn, Erik; Wood, Obert R.; Benk, Markus P.; Wojdyla, Antoine; Goldberg, Kenneth A.

    2015-07-01

    Despite significant enhancements in defect detection using optical and e-beam methodology, the smaller length scales and increasing challenges of future technology nodes motivate ongoing research into the need and associated cost of actinic inspection for EUV masks. This paper reports an extensive study of two EUV patterned masks, wherein the mask blank defectivity was characterized using optical (mask and wafer) methods and bright-field mask imaging (using the SHARP actinic microscope) of previously identified blank defects. We find that the bright field actinic imaging tool microscope captures and images many defects that are not seen by the automated optical inspection of patterned masks and printed wafers. In addition, actinic review reveals the impact of multilayer damage and depicts the printability profile which can be used as an added metric to define the patterned mask repair and defect compensation strategies.

  15. Kinematical and mechanical aspects of wafer slicing

    NASA Technical Reports Server (NTRS)

    Werner, P. G.

    1982-01-01

    Some recently achieved results concerning the technological fundamentals of slurry sawing are presented. The specific material removal process and the related kinematic and geometric contact conditions between workpiece and saw blade are described. The result of a functional description of the slurry sawing process is presented, expressing the main process criteria, such as infeed per stroke, specific removal rate, specific tool wear, and vertical stroke intensity, in terms of the dominating process parameters, such as stroke length, width of workpiece, stroke frequency, specific cutting force and slurry specification.

  16. Wafer bonding process for building MEMS devices

    NASA Astrophysics Data System (ADS)

    Pabo, Eric F.; Meiler, Josef; Matthias, Thorsten

    2014-06-01

    The technology for the measurement of colour rendering and colour quality is not new, but many parameters related to this issue are currently changing. A number of standard methods were developed and are used by different specialty areas of the lighting industry. CIE 13.3 has been the accepted standard implemented by many users and used for many years. Light-emitting Diode (LED) technology moves at a rapid pace and, as this lighting source finds wider acceptance, it appears that traditional colour-rendering measurement methods produce inconsistent results. Practical application of various types of LEDs yielded results that challenged conventional thinking regarding colour measurement of light sources. Recent studies have shown that the anatomy and physiology of the human eye is more complex than formerly accepted. Therefore, the development of updated measurement methodology also forces a fresh look at functioning and colour perception of the human eye, especially with regard to LEDs. This paper includes a short description of the history and need for the measurement of colour rendering. Some of the traditional measurement methods are presented and inadequacies are discussed. The latest discoveries regarding the functioning of the human eye and the perception of colour, especially when LEDs are used as light sources, are discussed. The unique properties of LEDs when used in practical applications such as luminaires are highlighted.

  17. Enhanced capture rate for haze defects in production wafer inspection

    NASA Astrophysics Data System (ADS)

    Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

    2010-03-01

    Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

  18. Anodic bonding using SOI wafer for fabrication of capacitive micromachined ultrasonic transducers

    NASA Astrophysics Data System (ADS)

    Bellaredj, M.; Bourbon, G.; Walter, V.; Le Moal, P.; Berthillier, M.

    2014-02-01

    In medical ultrasound imaging, mostly piezoelectric crystals are used as ultrasonic transducers. Capacitive micromachined ultrasonic transducers (CMUTs) introduced around 1994 have been shown to be a good alternative to conventional piezoelectric transducers in various aspects, such as sensitivity, transduction efficiency or bandwidth. This paper focuses on a fabrication process for CMUTs using anodic bonding of a silicon on insulator wafer on a glass wafer. The processing steps are described leading to a good control of the mechanical response of the membrane. This technology makes possible the fabrication of large membranes and can extend the frequency range of CMUTs to lower frequencies of operation. Silicon membranes having radii of 50, 70, 100 and 150 µm and a 1.5 µm thickness are fabricated and electromechanically characterized using an auto-balanced bridge impedance analyzer. Resonant frequencies from 0.6 to 2.3 MHz and an electromechanical coupling coefficient around 55% are reported. The effects of residual stress in the membranes and uncontrolled clamping conditions are clearly responsible for the discrepancies between experimental and theoretical values of the first resonance frequency. The residual stress in the membranes is determined to be between 90 and 110 MPa. The actual boundary conditions are between the clamped condition and the simply supported condition and can be modeled with a torsional stiffness of 2.10-7 Nm rad-1 in the numerical model.

  19. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  20. Measurement and modeling of time- and spatial-resolved wafer surface temperature in inductively coupled plasmas

    SciTech Connect

    Hsu, C. C.; Titus, M. J.; Graves, D. B.

    2007-05-15

    The transient temperature profile across a commercial wafer temperature sensor device in an inductively coupled Ar plasma is reported. The measured temperatures are compared to model predictions, based on a coupled plasma-wafer model. The radial temperature profile is the result of the radial profile in the ion energy flux. The ion energy flux profile is obtained by combining the Langmuir probe measurement, the ion wall flux probe measurement, and a plasma model. A methodology to estimate the ion flux profile using the sensor measurements has been validated by combining the plasma measurements, the wafer temperature measurements, and the plasma-wafer model. It is shown that with minimal heat transfer between the wafer and the chuck, the initial transient wafer temperature profile after plasma ignition can be used to estimate the ion energy flux profile across the wafer.

  1. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  2. Wafer Alignment marks Wx, Wy, W . Also called Search marks or WGA marks. These are used to establish wafer position on the stage and orients the X and Y alignment

    E-print Network

    Reif, Rafael

    Wafer Alignment marks Wx, Wy, W . Also called Search marks or WGA marks. These are used to establish wafer position on the stage and orients the X and Y alignment marks on wafer, making them parallel to the Y stage mirror. This is called Wafer Global Alignment (WGA). Wy and W were once separate marks. Now

  3. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    SciTech Connect

    Montoya, Angela C.; Maji, Arup K.

    2010-02-22

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  4. Chemical method for producing smooth surfaces on silicon wafers

    DOEpatents

    Yu, Conrad (Antioch, CA)

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  5. Sputter deposition of SiC coating on silicon wafers

    NASA Technical Reports Server (NTRS)

    Robson, M. T.; Blue, C. A.; Warrier, S. G.; Lin, R. Y.

    1992-01-01

    A study is conducted of the effect of substrate temperature during coating on the properties of coated SiC films on Si wafers, using a scratch test technique. While specimen temperature during coating has little effect on deposition rate, it significantly affects the durability of the coating. Scratch test damage to both film coating and substrate decreased with increasing deposition temperature, perhaps due to the rapid diffusion of the deposited atoms.

  6. Cost of Czochralski wafers as a function of diameter

    NASA Technical Reports Server (NTRS)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-01-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  7. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 ?m AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 ?m pixel size and 160x120, 52 ?m pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  8. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  9. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    SciTech Connect

    Daix, N. Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup ?2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  10. Influence of gas composition on wafer temperature in a tungsten chemical vapor deposition reactor: Experimental measurements, model

    E-print Network

    Rubloff, Gary W.

    Influence of gas composition on wafer temperature in a tungsten chemical vapor deposition reactor 13 April 2000; accepted 23 October 2000 Experimental measurements of wafer temperature in a single-wafer, lamp-heated chemical vapor deposition system were used to study the wafer temperature response to gas

  11. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, C.M.; Hui, W.C.

    1996-11-19

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

  12. Physical mechanisms of copper-copper wafer bonding

    NASA Astrophysics Data System (ADS)

    Rebhan, B.; Hingerl, K.

    2015-10-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing.

  13. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, Conrad M. (Antioch, CA); Hui, Wing C. (Campbell, CA)

    1996-01-01

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

  14. Wafer-scale aluminum plasmonics for fluorescence based biodetection

    NASA Astrophysics Data System (ADS)

    Farhang, Arash; George, Matthew C.; Williamson, Brent; Black, Mike; Wangensteen, Ted; Fraser, James; Petrova, Rumyana; Prestgard, Kent

    2015-08-01

    Moxtek has leveraged existing capabilities in wafer-scale patterning of sub-wavelength wire grid polarizers into the fabrication of 1D and 2D periodic aluminum plasmonic structures. This work will discuss progress in 200 mm diameter wafer-scale fabrication, with detailed emphasis within the realm of microarray based fluorescence detection. Aluminum nanohole arrays in a hexagonal lattice are first numerically investigated. The nanohole array geometry and periodicity are specifically tuned to coincide both with the excitation of the fluorophore Cy3, and to provide a high field enhancement within the nanoholes where labeled biomolecules are captured. This is accomplished through numerical modelling, nanofabrication, SEM imaging, and optical characterization. A 200mm diameter wafer, patterned with the optically optimized nanohole array, is cut into standard 1x3 inch microscope slide pieces and then subsequently printed with various antigens at 9 different concentrations. A sandwich bioassay is then carried out, using the corresponding conjugate antibodies in order to demonstrate specificity. The nanohole array exhibit a 3-4 times total fluorescence enhancement of Cy3, when compared to a leading commercial microarray glass slide.

  15. Wafer-scale nanowell array patterning based electrochemical impedimetric immunosensor.

    PubMed

    Lee, JuKyung; Cho, SiHyeong; Lee, JungHwan; Ryu, HeonYul; Park, JinGoo; Lim, SunHee; Oh, ByungDo; Lee, ChangWoo; Huang, Wilber; Busnaina, Ahmed; Lee, HeaYeon

    2013-12-01

    We have reported that nanowell array (NWA) can enhance electrochemical detection of molecular binding events by controlling the binding sites of the captured molecules. Using NWA biosensor based amperometric analysis, we have detected biological macromolecules such as DNA, protein or aptamers at low concentrations. In this research, we developed an impedimetric immunosensor based on wafer-scale NWA for electrochemical detection of stress-induced-phosphoprotein-1 (STIP-1). In order to develop NWA sensor through the cost-effective combination of high-throughput nanopattern, the NWA electrode was fabricated on Si wafer by krypton-fluoride (KrF) stepper semiconductor process. Finally, 12,500,000 ea nanowell with a 500 nm diameter was fabricated on 4 mm × 2 mm substrate. Next, by using these electrodes, we measured impedance to quantify antigen binding to the immunoaffinity layer. The limit of detection (LOD) of the NWA was improved about 100-fold compared to milli-sized electrodes (4 mm × 2 mm) without an NWA. These results suggest that wafer-scale NWA immunosensor will be useful for biosensing applications because their interface response is appropriate for detecting molecular binding events. PMID:24013070

  16. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

    NASA Technical Reports Server (NTRS)

    Shao, Howard M.; Reed, Irving S.

    1988-01-01

    A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

  17. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Deutsch, L. J.; Reed, I. S.

    1987-01-01

    A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

  18. A procedural method for the efficient implementation of full-custom VLSI designs

    NASA Technical Reports Server (NTRS)

    Belk, P.; Hickey, N.

    1987-01-01

    An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system.

  19. TSV processing of Medipix3 wafers by CEA-LETI: a progress report

    NASA Astrophysics Data System (ADS)

    Tick, T.; Campbell, M.

    2011-11-01

    The next generation of hybrid pixel detectors in particle physics experiments require reduced material budget, increased interconnection density and, ideally, they should be tileable to cover large areas seamlessly. These criteria cannot be fulfilled with present day interconnection techniques. As a result the particle physics community has recently put in a lot of effort to investigate and evaluate a variety of novel interconnection technologies. This paper focuses on describing a recently launched Through Silicon Via process development project with CEA-LETI. The project aims to use Medipix3 wafers and an existing ``via last'' TSV process made available by CEA-LETI to demonstrate the feasibility of TSVs on functional detector chips. The status of the project, TSV design and future plans are presented.

  20. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ?50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (? 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III

  1. Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas

    SciTech Connect

    Babaeva, Natalia Y.; Kushner, Mark J.

    2007-06-01

    In plasma etching equipment for microelectronics fabrication, there is an engineered gap between the edge of the wafer and wafer terminating structures, such as focus rings. The intended purpose of these structures is to make the reactant fluxes uniform to the edge of the wafer and so prevent a larger than desired edge exclusion where useful products cannot be obtained. The wafer-focus ring gap (typically<1 mm) is a mechanical requirement to allow for the motion of the wafer onto and off of the substrate. Plasma generated species can penetrate into this gap and under the beveled edge of the wafer, depositing films and possibly creating particles which produce defects. In this paper, we report on a computational investigation of capacitively coupled plasma reactors with a wafer-focus ring gap. The penetration of plasma generated species (i.e., ions and radicals) into the wafer-focus ring gap is discussed. We found that the penetration of plasma into the gap and under the wafer bevel increases as the size of the gap approaches and exceeds the Debye length in the vicinity of the gap. Deposition of, for example, polymer by neutral species inside the gap and under the wafer is less sensitive to the size of the gap due the inability of ions, which might otherwise sputter the film, to penetrate into the gap.

  2. A knowledge-based overflow embedder for VLSI routing

    SciTech Connect

    Chang, Hyun-Taek.

    1988-01-01

    Auto-routing is a time-consuming but essential step in the physical design of an integrated circuit. Most auto-routers yield very high connection ratio, but the last few remaining nets, termed as overflows, which must be connected manually are stumbling blocks in the overall routing process. Several attempts to automate this time-consuming manual rework have been made. However, no robust performance has been reported in embedding of real-world overflows. This is mainly due to impractical brute-force solution approaches suffering from lack of underlying formalisms representing a robust solution model. The research described in this thesis considers a knowledge-based approach to overflow embedding in gate-array VLSI design. The approach embodies the human way of overflow embedding by incorporating human experts' experience and heuristics in solution process. It is motivated by the fact that there are numerous cases where conventional approaches fail to resolve all overflows while human experts can easily complete the same design. To develop an overflow embedder capable of solving real-world overflows, a new overflow embedding formalism based on the gridless routing paradigm is first developed. This includes an efficient connection blockage identification scheme which detects existing nets causing an overflow. The formal approach is then coupled with domain-specific knowledge acquired from human experts and careful analysis of preliminary experimental results. This yields a very powerful and versatile overflow embedder, named AROWS (A Rule-based Overflow Wiring System).

  3. Incremental VLSI design systems based on circular attribute grammars

    SciTech Connect

    Jones, L.G.

    1986-01-01

    It is shown that attribute grammar techniques, used in the field of programming languages, form an efficient basis for the implementation of systems supporting hierarchical and incremental VLSI design. Such systems can interactively compute estimates for the speed and power dissipation of a circuit, check adherence to clocking disciplines, and recompute these quantities at reasonable cost as the designer changes the circuit, uses new modules, subsystems or standard cells. The bidirectional properties of devices and wires and the frequent use of signal feedback as a design technique imply that many properties of circuits are circular. Previous research has dealt almost exclusively with noncircular attribute grammars since this condition easily guarantees the existence and uniqueness of a consistent assignment of attribute values. It is noted that the noncircularity condition for attribute grammars is not a necessary one, it is sufficient that all circular attributes have a least fixed point obtainable with finite (and efficient) computation. Efficient algorithms are presented for exhaustive and incremental evaluation of circular attributes under any conditions that guarantee finite convergence.

  4. Fast VLSI architecture for 8 x 8 2D DCT

    NASA Astrophysics Data System (ADS)

    de Perthuis, Hughes; Bercovici, E.; de Grandmaison, A.; Akil, Mohamed

    1995-04-01

    Discrete Cosine Transform (DCT) is one of the most popular lossy techniques used today in video compression schemes. It allows to take advantage of the properties of natural images. Indeed thanks to their continuity for small surfaces (typically 8 X 8 pixels), they ask for a more compact description in the frequential plan than in the spatial one. A coupled quantization also brings further compression gain as it is now possible to degrade more the high frequencies of the image to which human eye is less sensitive. The drawback is that DCT puts heavy stress on computational resources and can be a bottleneck to cheap real time video. We here introduce a VLSI architecture which combines excellent performance with a small die size as we use an algorithm which maps very well on silicon. Through a reordering of the samples, regularity and complexity of the computations involved are greatly improved. This allows to divide the process into two parallel parts, one for even samples, the other for odd ones. As the number of coefficients required is decreased, fixed multipliers can be used. A simple join of the two parts' results followed by a normalization merged with quantization will give 8 X 8 2D DCT after a total of 64 cycles.

  5. VLSI array processor R&D status report

    NASA Astrophysics Data System (ADS)

    Greenwood, E.

    1982-01-01

    Detail design of the Arithmetic Processor Unit (APU) chip has been completed. All cell types (100) have been run through the design rule check (DRC) programs, corrected and verified. DRC runs on the entire chip have been run and all corrections have been made. Fifteen out of eighteen of the chip DRC corrections have been verified. The metal, polysilicon and information data layers of the APU layout is shown. The attached drawings, titled 'VLSI Array Processor Arithmetic Processor Unit Chip Plan' is a detail drawing of the APU Chip Plan. The functional level simulator of the APU has been built and verified using a set of APU diagnostic code. A gate level logic simulation of the APU has been built. The APU breadboard modules have been fabricated and check out has been initiated. The Array Processor Demonstration System (APDS) modules are in the wire-wrap process. The APDS and APU microcode assembler have been built and checked out. The linker and loader for the APDS have also been built.

  6. A VLSI decomposition of the deBruijn graph

    NASA Technical Reports Server (NTRS)

    Collins, O.; Dolinar, S.; Mceliece, R.; Pollara, F.

    1990-01-01

    A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

  7. Warpage Analysis of Silicon Wafer in Ingot Slicing by Wire-Saw Machine

    NASA Astrophysics Data System (ADS)

    Yamada, Toshiro; Kinai, Fumiaki; Ichikawa, Takesh; Yokoyama, Atsushi; Fukunaga, Moritaka; Ohshita, Takashi

    2004-06-01

    It is possible thermal expansion from heat generation by slicing deforms a single-crystal silicon ingot but the authors can find no report on the point. In addition, numerical analysis is useful to clarify the mechanism of wafer warping but no paper has been reported the numerical analysis from the start to end of the wafer slicing process. The authors carried out experiments for the wafer slicing. In addition, a finite element analysis was carried out in order to solve the warping mechanism from the start to end of the wafer slicing process. The warp of wafer in the vertical direction was 6.05 ? m in the experiment whereas the warp in the finite element analysis was 5.30 ? m. The result by the finite element analysis gave good agreement with experimental one. This paper suggests that thermal expansion of the ingot has great influence on the warp of wafer.

  8. On the residual stress and fracture strength of crystalline silicon wafers

    NASA Astrophysics Data System (ADS)

    Yang, Chris; Mess, Frank; Skenes, Kevin; Melkote, Shreyes; Danyluk, Steven

    2013-01-01

    This letter reports on residual stress measurement in thin crystalline silicon wafers with a full-field near-infrared polariscope. Residual stress is analyzed in combination with observed surface defects, and the results are related to measured fracture strength variation in the wafers. Measurements indicate that there is a sawing process-related residual stress in the as-cut wafers, and that etch-removal of ˜5 ?m from the wafer surface eliminates a damage layer that can significantly reduce the residual stress in the wafer, and therefore increases the observed fracture strength. There is a corresponding 2 to 3 ?m reduction in the observed characteristic defect size after etching. Fracture strength anisotropy observed in the wafers is related to defect orientation (scratching grooves and microcracks) caused by the sawing process.

  9. A VLSI implementation of a correlator/digital-filter based on distributed arithmetic

    NASA Technical Reports Server (NTRS)

    Zohar, Shalhav

    1989-01-01

    The design of a VLSI chip which applies the ideas of distributed arithmetic to a nonrecursive digital filter is described. The main features of this design are very high precision and a high degree of flexibility, which allows one chip to implement a large number of quite different digital filters and correlators.

  10. Biophysical Synaptic Dynamics in an Analog VLSI Network of Hodgkin-Huxley Neurons

    E-print Network

    Cauwenberghs, Gert

    in the design of artificial neural systems in silicon integrated circuits, based upon function and structural--We study synaptic dynamics in a biophysical net- work of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a gen- eralized Hodgkin-Huxley model

  11. A BIOMIMETIC VLSI ARCHITECTURE FOR SMALL TARGET TRACKING Vivek Pant1

    E-print Network

    A BIOMIMETIC VLSI ARCHITECTURE FOR SMALL TARGET TRACKING Vivek Pant1 and Charles M. Higgins1,2 1. Biomimetic algorithms suggest a novel way of looking at this problem. In the lobula plate of a fly's brain of biomimetic algorithms for target fixation and pursuit. Insect visual systems exhibit efficient tracking

  12. ARTICLE Communicated by Misha Tsodyks Spike-Driven Synaptic Plasticity: Theory, Simulation, VLSI

    E-print Network

    Columbia University

    . The dynamicsofthesinglesynapseisstudiedanalyticallybyextendingtheso- lution to a classic problem in queuing theory (Tak`acs process). The model of the synapseARTICLE Communicated by Misha Tsodyks Spike-Driven Synaptic Plasticity: Theory, Simulation, VLSI of stimulation. Yet stochastic learning theory ensures that it does not affect the collective behavior of the net

  13. Extreme Delay Sensitivity and the WorstCase Switching Activity in VLSI Circuits y

    E-print Network

    Najm, Farid N.

    Extreme Delay Sensitivity and the Worst­Case Switching Activity in VLSI Circuits y Farid N. Najm, IL 61801 Abstract -- We observe that the switching ac­ tivity at a circuit node, also called the transition density, can be extremely sensitive to the circuit inter­ nal delays. As a result, slight delay

  14. Digitally Tuned Analog VLSI Controllers Bodgan M. Wilamowski*, John Y. Hung*, and Ramraj Gottiparthy*

    E-print Network

    Wilamowski, Bogdan Maciej

    Digitally Tuned Analog VLSI Controllers Bodgan M. Wilamowski*, John Y. Hung*, and Ramraj@auburn.edu Abstract-- Digital controllers have historically enjoyed many advantages over those synthesized by analog processing algorithms: costly conversion of analog signals to digital and back, quantization errors, digital

  15. 2001 Special issue Spike-based VLSI modeling of the ILD system in the echolocating bat

    E-print Network

    Boahen, Kwabena

    2001 Special issue Spike-based VLSI modeling of the ILD system in the echolocating bat Timothy by echolocating bats is based on the difference of echo intensity received at the two ears, known as the interaural level difference (ILD). Mimicking the neural circuitry in the bat associated with the computation

  16. VLSI chip-set for data compression using the Rice algorithm

    NASA Technical Reports Server (NTRS)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  17. Analogue VLSI leaky integrateandfire neurons and their use in a sound analysis system.

    E-print Network

    Smith, Leslie S.

    , Stirling FK9 4LA, Scotland, UK Abstract. Integrate­and­fire neurons are simple model neurons which can.1. Integrate­and­fire neurons Integrate ­and­fire neurons have been proposed as model neurons for a long timeAnalogue VLSI leaky integrate­and­fire neurons and their use in a sound analysis system. Mark

  18. Nanometer InP Electron Devices for VLSI and THz Applications M. J. W. Rodwell1

    E-print Network

    Rodwell, Mark J. W.

    Nanometer InP Electron Devices for VLSI and THz Applications M. J. W. Rodwell1 , S. Lee1 , C, Thousand Oaks, CA, 91360, USA . While the growth of III-As and III-P semiconductors is well difficulties in the growth and fabrication of small structures, key challenges include extremely low

  19. Form specifies function: Robust spike-based computation in analog VLSI without precise

    E-print Network

    adaptive learning on short time scales, and circuits for driving the weight to one of two possible analog to perform highly selective simulated odor recognition, using induced synchronization within a population of neurons as the key to computation. The success of this scheme shows that the analog VLSI circuits used can

  20. Spike-based learning in VLSI networks of integrate-and-fire neurons

    E-print Network

    Columbia University

    it is important to design spike-based learning algorithms and circuits, compatible with existing solutions neuromorphic circuits that support its VLSI implementation. We describe the architecture of a spike-based learning neural network, the analog circuits that implement the synaptic learning mechanism, and present

  1. VLSI Architecture and Chip for Combined Invisible Robust and Fragile Watermarking

    E-print Network

    Mohanty, Saraju P.

    1 VLSI Architecture and Chip for Combined Invisible Robust and Fragile Watermarking Saraju P. Mohanty Computer Science and Engineering University of North Texas, Denton, TX 76203. E-mail: smohanty-mail: eliask@unt.edu N. Ranganathan Computer Science and Engineering University of South Florida, Tampa, FL

  2. An Efficient Reliability Simulation Flow for Evaluating the Hot Carrier Injection Effect in CMOS VLSI Circuits

    E-print Network

    Pedram, Massoud

    and an efficient full chip simulation method, to analyze the HCI-induced transistor aging with a fast run time of the major concerns in VLSI circuits and systems designs. Hot carrier injection (HCI) effect, which causes MOSFET aging due to the deleterious effect on threshold voltage and the driving current, becomes one

  3. Abstract--This paper describes the development of visualization aids for VLSI Computer-Aided Design

    E-print Network

    Nestor, John A.

    Abstract--This paper describes the development of visualization aids for VLSI Computer-Aided Design. Chip designs of this complexity would be impossible without the extensive use of Computer-Aided Design is to adapt ideas from software visualization and algorithm animation [5], [6] to aid students, designers

  4. Fault Diagnosis of VLSI Circuits with Cellular Automata based Pattern Classifier

    E-print Network

    Ganguly, Niloy

    Fault Diagnosis of VLSI Circuits with Cellular Automata based Pattern Classifier Biplab K Sikdar 1 Niloy Ganguly 2 P Pal Chaudhuri 3 1 Department of Computer Science & Tech, Bengal Engineering & Science. A special class of Cellular Automata (CA) referred to as Multiple Attractor CA (MACA) is employed

  5. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

    1979-01-01

    A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

  6. Alternative fabrication process for edgeless detectors on 6 in. wafers

    NASA Astrophysics Data System (ADS)

    Kalliopuska, Juha; Eränen, Simo; Virolainen, Tuula

    2011-05-01

    VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 ?m thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 ?m from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

  7. Advanced Ceramic Wafer Seals Demonstrated at 2000 deg. F

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Durable, high-temperature sliding seals are required in advanced hypersonic engines and around movable control surfaces on future vehicles. These seals must operate at temperatures of 2000 to 2500 F, limit hot gas flow, remain resilient for multiple cycles, and resist scrubbing damage against rough surfaces. Current seal designs do not meet these demanding requirements, so the NASA Glenn Research Center is developing advanced seals and preload devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests.

  8. Propagation of Nd-laser pulses through crystalline silicon wafers

    SciTech Connect

    Kirichenko, N A; Kuzmin, P G; Shcherbina, M E

    2011-07-31

    Propagation of pulses from an Nd:YAG laser (wavelength, 1.064 {mu}m; pulse duration, 270 ns; pulse energy, 225 {mu}J) through crystalline silicon wafers is studied experimentally. Mathematical modelling of the process is performed: the heat conduction equation is solved numerically, the temperature dependences of the absorption and refraction of a substance, as well as generation of nonequilibrium carriers by radiation are taken into account. The constructed model satisfactorily explains the experimentally observed intensity oscillations of transmitted radiation. (interaction of laser radiation with matter)

  9. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  10. FDTD simulation of an 1x2 beam splitter using photonic bandgap on SOI wafer

    NASA Astrophysics Data System (ADS)

    Tsao, Shyh-Lin; Yang, Lan-Chih; Huang, Hsin-Chun; Hu, Shu-Fen

    2003-12-01

    In recent years, SOI optical waveguide is an attractive component of optical waveguide elements. Because fabrication of complementary metal oxide semiconductor (CMOS) electronic devices on SOI wafers shows promising results in the future low-power, high speed electronic device, and SOI opto-electronic integrated devices becomes an important issue[1]. Owing to the presence of periodically positioned scatters, the PBG theory is based on the principle of localization. If periodicity is equal or near a wavelength, the frequency of lightwave within the bandgap is stuck inside the material and not allowed to propagation. Recently, PBG have been suggested for a variety of optoelectronic applications, such as ultra low threshold lasers, high transmission waveguides with a bending radius comparable to the light wavelength[2]. In this paper, we design and analyze the 3 db 1x2 PBG splitter on SOI wafer, we simulated the 1x2 PBG splitter by finite difference time domain ( FDTD ) technology. In this work, our designed SOI wafer waveguide includes a 0.4 ?m oxide layer and a 1.5 ?m crystal silicon surface layer. The buried oxide structure is a planar slab working as the lower cladding ( nsio2 = 1.5 ) layer, the surface silicon layer (nsi = 3.5 ) is the waveguide core and the top cladding is air ( nair = 1 ). The width of rib waveguide is 4?m. The device is less than 30?m2, the input lightwave is separated into two opposite directions. In the future, we expect such a novel device can be applied in many very large scale opto-electronic integrated circuits. Reference [1] A. Layadi, A. Vonsovical, R. Orobtchouk, D. Pascal, and A. Koster, 'Low loss optical waveguide on standard SOI/SIMOX substrate', Optical Communication, vol. 146, pp. 31-33, 1998. [2] Park Young-Jin, A. Herschlein and W. Wiesbeck, 'A photonic bandgap (PBG) structure for guiding and suppressing surface waves in millimeter-wave antennas', IEEE Transactions on Microwave Theory and Techniques, vol. 49, pp. 1854-1859, 2001.

  11. A practical approach to LWIR wafer-level optics for thermal imaging systems

    NASA Astrophysics Data System (ADS)

    Symmons, Alan; Pini, Ray

    2013-06-01

    The development and implementation of wafer level packaging for commercial microbolometers has opened the pathway towards full wafer-based thermal imaging systems. The next challenge in development is moving from discrete element LWIR imaging systems to a wafer based optical system, similar to lens assemblies found in cell phone cameras. This paper will compare a typical high volume thermal imaging design manufactured from discrete lens elements to a similar design optimized for manufacture through a wafer based approach. We will explore both performance and cost tradeoffs as well as review the manufacturability of all designs.

  12. Improved quality control of silicon wafers using novel off-line air pocket image analysis

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Sanna, M. Cristina

    2014-08-01

    Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

  13. Journal of VLSI Signal Processing 26, 119131, 2000 c 2000 Kluwer Academic Publishers. Manufactured in The Netherlands.

    E-print Network

    Freitas, Nando de

    Journal of VLSI Signal Processing 26, 119­131, 2000 c 2000 Kluwer Academic Publishers. Manufactured Division, 387 Soda Hall, University of California, Berkeley, CA 94720-1776, USA M. NIRANJAN Department

  14. Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies Man L Mui Kaustav Banerjee Amit Mehrotra

    E-print Network

    Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies Man L Mui Kaustav Banerjee a methodology for systematically optimizing the power supply voltage for maximizing the performance of VLSI cir- cuits in technologies where leakage power is not an insignificant fraction of the total power

  15. Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding

    SciTech Connect

    Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Kim, Moon J.; Klie, Robert F.

    2013-12-16

    The single twin boundary with crystallographic orientation relationship (1{sup ¯}1{sup ¯}1{sup ¯})//(111) [01{sup ¯}1]//[011{sup ¯}] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

  16. Photonic crystal preparation by a wafer bonding approach

    NASA Astrophysics Data System (ADS)

    Yamamoto, Noritsugu; Ogawa, Shinpei; Imada, Masahiro; Noda, Susumu

    2001-10-01

    Various important scientific and engineering applications, such as control of spontaneous emission, zero-threshold lasing, sharp bending of light, and trapping of photons, are expected by using photonic bandgap (PBG) crystals with artificially introduced defect states and/ or light-emitters. Realizing the maximum potential of photonic crystals requires the following steps: (i) construct a three-dimensional (3D) crystal with a complete photonic bandgap in the optical wavelength region; (ii) introduce an arbitrary defect into the crystal at an arbitrary position; (iii) introduce an efficient light-emitter; and, (iv) use an electronically conductive crystal, as this is desirable for actual device application. Although various approaches to constructing 3D crystals have been proposed and investigated, none of these reports satisfies the above requirements simultaneously. To develop complete 3D crystals at infrared (5-10um) to near-infrared wavelengths (1-2um), we stacked III-V semiconductor gratings into a diamond structure by means of wafer bonding and a laser-beam-assisted very precise alignment technique. Since the crystal is constructed with III-V semiconductors, which are widely used for optoelectronic devices, requirement (iii) is satisfied. Moreover, as the wafer bonding enables us to construct an arbitrary structure and to form an electronically conductive interface, all the above requirements (i)-(iv) will be satisfied. In this paper, we review our approach for creating full 3D photonic bandgap crystals at near-infrared wavelengths.

  17. Patterning of photocleavable zwitterionic polymer brush fabricated on silicon wafer.

    PubMed

    Kamada, Tomohiro; Yamazawa, Yuka; Nakaji-Hirabayashi, Tadashi; Kitano, Hiromi; Usui, Yuki; Hiroi, Yoshiomi; Kishioka, Takahiro

    2014-11-01

    Brushes of a polymer, namely poly(carboxymethylbetaine) (PCMB), were fabricated on silicon wafers by reversible addition-fragmentation chain-transfer (RAFT) polymerization using a surface-confined RAFT agent having an aromatic group at its bottom. The polymer brush showed effective suppression of the non-specific adsorption of bovine serum albumin (BSA) and adhesion of fibroblasts (3T3 cells). In contrast, BSA and 3T3 cells significantly adsorbed on and adhered to positively or negatively charged polymer brushes fabricated by the same procedure. Upon UV irradiation at 193 nm, the thickness of the PCMB brush with an aromatic group at its bottom decreased significantly whereas PCMB prepared using a surface-confined RAFT agent without an aromatic group needed a much higher irradiation dose to afford a comparable decrease in thickness. These results indicate a preferential cleavage of the PCMB brush due to photodecomposition of the phenyl group at the bottom. BSA and 3T3 cells non-specifically adsorbed on and adhered to the UV irradiation-induced hollow spaces, respectively. Furthermore, a designed pattern with a resolution of 5 ?m was successfully made on the PCMB brush above the silicon wafer by simple UV irradiation. These results suggest that the surface-confined aromatic RAFT agent will be quite useful for simple photolithography in biomedical fields. PMID:25466462

  18. Formation of silver nanoparticles and nanocraters on silicon wafers.

    PubMed

    He, Junhui; Kunitake, Toyoki

    2006-08-29

    Silver nanocraters and monodisperse nanoparticles were formed on silicon wafers by spin-coating of an aqueous AgNO3/PVA solution and calcination of the resulting Ag+/PVA composite film. The monodisperse Ag nanoparicles were formed from small Ag+/PVA aggregates and were uniformly and stably distributed on the substrate surface. They were located as close as 2.8 nm apart (edge to edge) without coalescence. This nanoparticle stability was apparently derived from their interaction with the oxidized wafer surface. On the other hand, Ag metallic nanocraters with and without nanodots at their centers were produced from large Ag+/PVA aggregates. The explosive decomposition of AgNO3 and PVA by calcination could explain their formation. When Ag+ ions were reduced to Ag nanoparticles prior to calcination, larger Ag nanoparticles were produced probably due to aggregation of closely situated nanoparticles. Those nanoparticles that were located far enough stayed intact. Perspectives are discussed in terms of potential applications. PMID:16922578

  19. Using wafer-scale epitaxial graphene for producing twisted bilayers with controlled twist angle for electronics applications (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Dimitrakopoulos, Christos D.

    2015-09-01

    Graphene's exceptional properties make it attractive for technological applications in many areas, including high-speed electronics. The establishment of processes for producing high quality, large-scale graphene is necessary for such applications. Large area growth of epitaxial graphene on the Si-face of hexagonal SiC (0001) wafers exhibits manageable growth kinetics, and most importantly, its azimuthal orientation is fixed, as it is determined by the structure of the single crystal substrate. Therefore, this is a viable method for producing graphene with uniform coverage and structural coherence at wafer-scale.[1],[2] Semi-insulating SiC is a good substrate for graphene RF transistors, however, its cost is so high that potentially only niche applications of graphene on SiC (e.g. defense or space related) can be viable. Furthermore, to enable hybrid electronics, where standard circuits built on Si perform digital logic functions while graphene that does not exhibit a band gap is used for ultrafast analog devices, we would need to transfer epitaxial graphene onto Si wafers. To address these issues, we have developed a method in which a graphene film grown on a 4" SiC wafer is exfoliated via the stress induced by an overgrown Ni film and transferred to other substrates, resulting in a wafer-scale monolayer of graphene that is continuous and has a single azimuthal orientation.[3] This growth and transfer process can be repeated on the same SiC wafer hundreds to thousands of times, dramatically reducing the cost per wafer-sized graphene layer. The characterization of the transferred films shows that they are of quality similar to the pristine films on SiC. Capitalizing on this new method for single crystal epitaxial graphene transfer, we have initiated a project to produce bilayers of graphene with deterministically controlled twist angles. The inspiration for this experimental work is recent theoretical work by Maroudas and coworkers4 that predicts the opening of substantial band gaps at specific twist angles in bilayer graphene. We will report our methods for producing twisted bilayers with controlled twist angle, their characterization and device results. [1] C. Dimitrakopoulos, Y.-M. Lin, A. Grill, D. B. Farmer, M. Freitag, Y. Sun, S.-J. Han, Z. Chen, K. A. Jenkins, Y. Zhu, Z. Liu, T. J. McArdle, J. A. Ott, R. Wisnieff, Ph. Avouris J. Vac. Sci. Technol. B 28, 985-992, (2010). [2] Y.-M. Lin, C. Dimitrakopoulos, K. A. Jenkins, D. B. Farmer, H.-Y. Chiu, Ph. Avouris Science 327, 662 (2010). [3] J. Kim, H. Park, J. B. Hannon, S. W. Bedell, K. Fogel, D. K. Sadana, C. Dimitrakopoulos Science 342, 833-836 (2013). [4] A. R. Muniz, D. Maroudas Phys. Rev. B 86, 075404 (2012)

  20. On the generation of bulk microdefects in phosphorus-diffused monocrystalline silicon solar wafers after a high-thermal treatment studied by X-ray topography

    NASA Astrophysics Data System (ADS)

    González-Mañas, M.; Vallejo, B.; Caballero, M. A.

    2014-09-01

    Oxygen is the most important impurity in free dislocation Czochralski silicon single crystals incorporated interstitially during the growth. The knowledge of oxygen behavior after thermal processes is of great technological importance, since different kinds of bulk microdefects such us SiO2 precipitates, dislocation loops and stacking faults can be generated. In monocrystalline silicon solar cell manufacturing fabrication, there are several high-thermal treatments. The first is the diffusion process at 850-900 °C. Three different kinds of phosphorus diffusion wafers, standard PO3Cl liquid, spray-on and screen printing, were comparatively studied by X-ray topography showing that phosphorus diffusion improves the crystal quality by a gettering process whose best efficiency is in PO3Cl-diffused wafers. Later, another fabrication high-thermal step is for instance the rear surface passivation taking place at temperatures from 800 to 1,050 °C. For this reason, it is important to study how a high-thermal treatment at 1,000 °C affects the different phosphorus-diffused wafers mentioned above. To evaluate and characterize the possible defects induced by the oxygen precipitation, X-ray topography has been employed. Results show that annealed wafers are not perfect crystals; the oxygen precipitation induces the generation of bulk microdefects whose kind, size and density depend on the diffusion method employed. In PO3Cl and spray-on diffused wafers, retardation in the oxygen precipitation process takes place after annealing, while in screen printing this process is recovered and a kind of mixed defects between dislocation loops and platelet precipitates is generated.