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Sample records for vlsi technology wafers

  1. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

  2. Evaluation of VLSI technology

    NASA Astrophysics Data System (ADS)

    Surace, G.; Prior, B. J.; Beasley, K.; Taylor, D. G.; Pengelly, R. S.

    1984-04-01

    Silicon and GaAs VLSI parameters are tabulated. The capability of Europe, America, and Japan in VLSI technology are compared and trends are outlined. Integrated circuit (IC) custom design methodologies; gate arrays, standard cell, and full custom are highlighted and foreseen development costs with each design route are shown. Use of VLSI technology in satellite subsystems is considered. A time division multiple access system is discussed. The front end GaAs regenerative repeater and the baseband processor systems are considered with chip counts and power dissipation estimates given for each subsystem. Further systems include a multicarrier demodulator and a transmitter and soft decision receiver structures for correlative phase modulation techniques. The performance of functional blocks such as ROMs, and multipliers is studied. Work necessary to carry the subsystems to implementation in IC form, and development routes for each IC are identified.

  3. High speed synchronizer card utilizing VLSI technology

    NASA Technical Reports Server (NTRS)

    Speciale, Nicholas; Wunderlich, Kristin

    1988-01-01

    A generic synchronizer card capable of providing standard NASA communication block telemetry frame synchronization and quality control was fabricated using VLSI technology. Four VLSI chip sets are utilized to shrink all the required functions into a single synchronizer card. The application of VLSI technology to telemetry systems resulted in an increase in performance and a decrease in cost and size.

  4. Full custom VLSI - A technology for high performance computing

    NASA Technical Reports Server (NTRS)

    Maki, Gary K.; Whitaker, Sterling R.

    1990-01-01

    Full custom VLSI is presented as a viable technology for addressing the need for the computing capabilities required for the real-time health monitoring of spacecraft systems. This technology presents solutions that cannot be realized with stored program computers or semicustom VLSI; also, it is not dependent on current IC processes. It is argued that, while design time is longer, full custom VLSI produces the fastest and densest VLSI solution and that high density normally also yields low manufacturing costs.

  5. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  6. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    ERIC Educational Resources Information Center

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  7. GaAs VLSI technology and circuit elements for DSP

    NASA Astrophysics Data System (ADS)

    Mikkelson, James M.

    1990-10-01

    Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

  8. Deep sub-micron stud-via technology for superconductor VLSI circuits

    NASA Astrophysics Data System (ADS)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-05-01

    A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.

  9. Deep sub-micron stud-via technology of superconductor VLSI circuits

    NASA Astrophysics Data System (ADS)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-02-01

    A fabrication process has been developed for fully planarized Nb-based superconducting interlayer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of etched contact holes in the interlayer dielectric it employs etched and planarized Nb pillars (studs) as connectors between adjacent wiring layers. Detailed results are presented for one version of the process that utilizes Nb/Al/Nb trilayers for each wiring layer instead of single Nb wiring layers. Nb studs are etched in the top layer of the trilayer to provide vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A μm-2 and approaches the depairing current density of Nb films.

  10. A VLSI implementation of DCT using pass transistor technology

    NASA Technical Reports Server (NTRS)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  11. Dry Cleaning Technology of Silicon Wafer with a Line Beam for Semiconductor Fabrication by KrF Excimer Laser

    NASA Astrophysics Data System (ADS)

    Kim, Dae-Jin; Kim, Yong-Kee; Ryu, Je-Kil; Kim, Hyun-Jung

    2002-07-01

    The contaminants on a bare wafer or a patterned wafer can seriously impact the yield of manufacturing devices in semiconductor fabrication. In very large scale integrated circuit (VLSI) technology, as the device density increases, particularly for flat panel displays, the importance of cleaning also increases. The removal of particles and the Photoresist (PR) layer on a silicon wafer was investigated by a line beam of a KrF excimer laser in a cleanroom condition. This paper reports the effects of a high-energy laser beam onto the electrical, structural and morphological properties of the wafer and introduces a practical line beam laser cleaning method for particle removal and PR stripping. The removal of particles and the PR layer on a silicon wafer was performed using a KrF excimer laser in the cleanroom condition. The results of surface morphology were observed using a scanning electron microscope (SEM) and atomic force microscopy (AFM). The crystallization of the silicon wafer was observed by X-ray diffraction (XRD) studies. The electrical properties of the silicon wafer before and after laser irradiation were characterized by Hall measurements. The compositions of the PR covered wafers were determined by energy dispersive X-ray diffraction (EDX). The carrier concentration and resistivity of the bare silicon wafer were 1.4 1015 cm-3 and 17.7 ?{\\cdot}cm, respectively, before laser irradiation. The carrier concentration of the silicon wafers after laser irradiation was in the range of 1.1 1015-1.6 1015 cm-3, and the resistivity was in the range of 17.0-18.2 ?{\\cdot}cm. The carrier concentration and resistivity of the bare silicon wafers were not changed even after high-energy laser irradiation of up to 600 mJ/cm2. After 6-pulse laser irradiation, the PR layer of 0.82 ?m thickness was stripped perfectly with an energy density of 300 mJ/cm2 without the aid of any chemical or solvent. The ablation rates were 0.06 ?m/pulse for 100 mJ/cm2, 0.10 ?m/pulse for 200 mJ/cm2 and 0.13 ?m/pulse for 300 mJ/cm2. Dry laser cleaning technology shows that particles and organic compounds, like PR, on the bare silicon wafer can be effectively removed without any damage to the silicon substrate.

  12. Product assurance technology for custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

    1985-01-01

    The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

  13. Advanced FTIR technology for the chemical characterization of product wafers

    NASA Astrophysics Data System (ADS)

    Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

    2001-01-01

    Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

  14. Post exposure bake unit equipped with wafer-shape compensation technology

    NASA Astrophysics Data System (ADS)

    Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

    2007-03-01

    In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

  15. VLSI neuroprocessors

    NASA Technical Reports Server (NTRS)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional techniques and enables multiple assignments, (many to many), not achievable with standard statistical approaches. Tactical movement planning (finding the best path from A to B) is accomplished with a digital two-dimensional concurrent processor array. By exploiting the natural parallel decomposition of the problem in silicon, a four order of magnitude speed-up over optimized software approaches has been demonstrated.

  16. Automotive SOI-BCD Technology Using Bonded Wafers

    NASA Astrophysics Data System (ADS)

    Himi, H.; Fujino, S.

    2008-11-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N+ layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  17. Automotive SOI-BCD Technology Using Bonded Wafers

    SciTech Connect

    Himi, H.; Fujino, S.

    2008-11-03

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N{sup +} layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  18. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  19. Science and technology of plasma activated direct wafer bonding

    NASA Astrophysics Data System (ADS)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600spC), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100spC). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  20. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  1. Linearization techniques for nth-order sensor models in MOS VLSI technology

    NASA Astrophysics Data System (ADS)

    Khachab, Nabil I.; Ismail, Mohammed

    1991-12-01

    The authors present new linearization techniques and introduce novel circuits for second- and third-order sensor models. Furthermore, a general framework as well as circuit techniques for linearization of sensor models of any order are presented. The new techniques are based on subtle circuit design of simple and compact multiplier/divider and vector multiplier circuits that comprise op-amps and MOS transistors. The design is programmable using DC control voltages and is capable of implementing different values of model parameters using identically sized devices without altering physical circuit layout. The resulting continuous-time signal processing circuits are completely compatible with MOS VLSI technology and easy to incorporate in a computer-aided design environment. The circuit design details are given and nonideal effects due to op-amp dynamics and MOS parasitic capacitances are investigated. Experimental results for the new second-order sensor models, obtained from a MOSIS 2-micron process test chip, and SPICE simulation results of third-order models verify the validity of the proposed linearization techniques.

  2. New dynamic FET logic and serial memory circuits for VLSI GaAs technology

    NASA Technical Reports Server (NTRS)

    Eldin, A. G.

    1991-01-01

    The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

  3. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  4. Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

    2015-02-01

    The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

  5. VLSI array processor

    NASA Astrophysics Data System (ADS)

    Greenwood, E.

    1982-07-01

    The Arithmetic Processor Unit (APU) data base design check was completed. Minor design rule violations and design improvements were accomplished. The APU mask set has been fabricated and checked. Initial checking of all mask layers revealed a design rule problem in one layer. That layer was corrected, refabricated and checked out. The mask set has been delivered to the chip fabrication area. The fabrication process has been initiated. All work on the Array Processor Demonstration System (APDS) has been suspended at CHI until the additionally requested funding was received. That funding has been authorized and CHI will begin work on the APDS in July. The following activities are planned in the following quarter: 1) Complete fabrication of the first lot of VLSI APU devices. 2) Complete integration and check-out of the APDS simulator. 3) Complete integration and check-out of the APU breadboard. 4) Verify the VLSI APU wafer tests with the APU breadboard. 5) Complete check-out of the APDS using the APU breadboard.

  6. Fast integral rigorous modeling applied to wafer topography effect prediction on 2x nm bulk technologies

    NASA Astrophysics Data System (ADS)

    Michel, J.-C.; Le Denmat, J.-C.; Tishchenko, A.; Jourlin, Y.

    2014-03-01

    Reflection by wafer topography and underlying layers during optical lithography can cause unwanted overexposure in the resist [1]. In most cases, the use of bottom anti reflective coating limits this effect. However, this solution is not always suitable because of process complexity, cost and cycle time penalty, as for ionic implantation lithography process in 28nm bulk technology. As a consequence, computational lithography solutions are currently under development to simulate and correct wafer topographical effects [2], [3]. For ionic implantation source drain (SD) photolithography step, wafer topography influences resulting in implant pattern variation are various: active silicon areas, Poly patterns, Shallow Trench Isolation (STI) and topographical transitions between these areas. In 28nm bulk SD process step, the large number of wafer stack variations involved in implant pattern modulation implies a complex modeling of optical proximity effects. Furthermore, those topography effects are expected to increase with wafer stack complexity through technology node downscaling evolution. In this context, rigorous simulation can bring significant value for wafer topography modeling evolution in R and D process development environment. Unfortunately, classical rigorous simulation engines are rapidly run time and memory limited with pattern complexity for multiple under layer wafer topography simulation. A presentation of a fast rigorous Maxwell's equation solving algorithm integrated into a photolithography proximity effects simulation flow is detailed in this paper. Accuracy, run time and memory consumption of this fast rigorous modeling engine is presented through the simulation of wafer topography effects during ionic implantation SD lithography step in 28nm bulk technology. Also, run time and memory consumption comparison is shown between presented fast rigorous modeling and classical rigorous RCWA method through simulation of design of interest. Finally, integration opportunity of such fast rigorous modeling method into OPC flow is discussed in this paper.

  7. High transmittance silicon terahertz polarizer using wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Yu, Ting-Yang; Tsai, Hsin-Cheng; Wang, Shiang-Yu; Luo, Chih-Wei; Chen, Kuan-Neng

    2015-08-01

    Due to the difficulties faced in fabricating robust Terahertz (THz) optical components with low Fresnel reflection loss, the need to increase the efficiency of THz system with reduced cost is still considered as one of the most essential tasks. In this report, a new low cost THz polarizer with robust structure is proposed and demonstrated. This new THz wire grid polarizer was based on an anti-reflection (AR) layer fabricated with low temperature metal bonding and deep reactive ion etching (DRIE). After patterning Cu wire gratings and the corresponding In/Sn solder ring on the individual silicon wafers, the inner gratings were sealed by wafer-level Cu to In/Sn guard ring bonding, providing the protection against humidity oxidation and corrosion. With the low eutectic melting point of In/Sn solder, wafers could be bonded face to face below 150°C. Two anti-reflection layers on both outward surfaces were fabricated by DRIE. With the mixing of empty holes and silicon, the effective refractive index was designed to be the square root of the silicon refractive index. The central frequency of the anti-reflection layers was designed between 0.5THz to 2THz with an approximate bandwidth of 0.5THz. The samples were measured with a commercial free-standing wire grid polarizer by a THz time domain spectroscopy (THz-TDS) from 0.2THz to 2.2THz. The power transmittance is close to 100% at central frequency. Extinction ratio of the polarizer is between 20dB to 40dB depending on the frequency. The advantages of this new polarizer include high transmittance, robust structure and low cost with no precision optical alignment required.

  8. 3D micro-optical lens scanner made by multi-wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Bargiel, S.; Gorecki, C.; Bara?ski, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frmel, J.

    2013-03-01

    We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

  9. All-glass wafer-level lens technology for array cameras

    NASA Astrophysics Data System (ADS)

    Dinesen, Palle G.

    2014-03-01

    We present a novel all-glass wafer-level lens manufacturing technology. Compared to existing wafer-level lens manufacturing technologies, we realize lenses all in glass, which has a number of distinct advantages, including the availability of different glass types with largely varying dispersion for efficient achromatic lens design. Another advantage of all-glass solutions is the ability to dice the lens stack to match the form factor of a rectangular sensor area without compromising the optical performance of the lens, thereby allowing to significantly reducing the footprint of an array camera.

  10. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  11. A new VLSI compatible rapid thermal processing system

    NASA Astrophysics Data System (ADS)

    Aitken, D.; Mehta, S.; Parisi, N.; Russo, C. J.; Schwartz, V.

    Rapid thermal processing (RTP) is increasingly becoming a significant tool to meet the challenge of fabricating miniaturized MOS and bipolar devices. The primary advantages of RTP over conventional furnace annealing include the shorter heat cycle, well-controlled soak times at peak temperatures and the capability to rapidly change anneal ambients, thereby enhancing its flexibility as a process tool. The major applications of RTP in VLSI technology that are presently being pursued include: (i) implant-damage annealing/dopant activation, (ii) silicide formation, (iii) glass reflow, (iv) thin film growth/deposition (oxides, nitrides, oxy-nitrides) and (v) contact alloying. This paper discusses a new rapid thermal processor, RTP-800/8000, recently introduced by Varian. The discussion will include mechanical and electrical design, software, heating process compatibility, process uniformity and repeatability, process setup and noncontact temperature measurement. The heating system consists of a tungsten lamp array surrounded by a highly reflective mirror system designed to provide good temperature uniformity for wafer sizes up to 200 mm. The RTP-8000 has a serial cassette-to-cassette automatic wafer handling system. The RTP-800 possesses a single wafer, operator-assisted wafer handling system. The RTP-800/8000 has an automated multiple gas flow control and also has the optional capability of processing wafers in vacuum. An infrared optical pyrometer measures the wafer temperature from the backside of the wafer. In the RTP-8000, touch screen operation of the menu-driven recipes is easy with user-friendly software. A separate electroluminescent flat panel display provides information for maintenance and servicing and reports the system status. Process information is provided on this display in the RTP-800.

  12. Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias

    NASA Astrophysics Data System (ADS)

    Khne, Stphane; Hierold, Christofer

    2011-08-01

    The presented wafer-level packaging technology enables the direct integration of electrical interconnects during low-temperature wafer bonding of a cap substrate featuring through silicon vias (TSVs) onto a MEMS device wafer. The hybrid bonding process is based on hydrophilic direct bonding of plasma-activated Si/SiO2 surfaces and the simultaneous interconnection of the device metallization layers with Cu TSVs by transient liquid phase (TLP) bonding of ultra-thin AuSn connects. The direct bond enables precise geometry definition between device and cap substrate, whereas the TLP bonding does not require a planarization of the interconnect metallization before bonding. The complete process flow is successfully validated and the fabricated devices' characterization evidenced ohmic interconnects without interfacial voids in the TLP bond.

  13. VLSI research

    NASA Astrophysics Data System (ADS)

    Brodersen, R. W.

    1984-04-01

    A scaled version of the RISC II chip has been fabricated and tested and these new chips have a cycle time that would outperform a VAX 11/780 by about a factor of two on compiled integer C programs. The architectural work on a RISC chip designed for a Smalltalk implementation has been completed. This chip, called SOAR (Smalltalk On a RISC), should run program s4-15 times faster than the Xerox 1100 (Dolphin), a TTL minicomputer, and about as fast as the Xerox 1132 (Dorado), a $100,000 ECL minicomputer. The 1983 VLSI tools tape has been converted for use under the latest UNIX release (4.2). The Magic (formerly called Caddy) layout system will be a unified set of highly automated tools that cover all aspects of the layout process, including stretching, compaction, tiling and routing. A multiple window package and design rule checker for this system have just been completed and compaction and stretching are partially implemented. New slope-based timing models for the Crystal timing analyzer are now fully implemented and in regular use. In an accuracy test using a dozen critical paths from the RISC II processor and cache chips it was found that Crystal's estimates were within 5-10% of SPICE's estimates, while being a factor of 10,000 times faster.

  14. Full-wafer technology - A new approach to large-scale laser fabrication and integration

    NASA Astrophysics Data System (ADS)

    Vettiger, Peter; Bona, Gian-Luca; Buchmann, Peter; Daetwyler, Kurt; Dietrich, Hans-Peter; Moser, Andreas; Seitz, Hugo K.; Benedict, Melvin K.; Cahoon, Edward C.; Voegeli, Otto

    1991-06-01

    A concept for full-wafer processing (FWP) and full-wafer testing (FWT) for semiconductor laser fabrication in the AlGaAs-GaAs material system is presented. The approach is based on chemically assisted ion beam etching for the laser-mirror formation. Record values for mirror scattering, optimum mirror reflectivity, and equivalence to cleaved mirrors in terms of laser threshold and efficiency have been achieved. Promising results for uniformity and reproducibility for major laser diode characteristics on processed 2-inch wafers have been found. The FWP technology has been extensively used for designing test sites to determine various materials, process, and laser parameters, such as sheet resistance, ridge dimensions, lithographic alignment errors, mirror surface leakage, etc. FWP improves process yield and throughput by reducing bar and chip handling to an absolute minimum. In addition to FWP, an FWT concept has been developed which allows a complete on-wafer characterization of laser diodes, including their beam characteristics, without any cleaving.

  15. Diamond MEMS: wafer scale processing, devices, and technology insertion

    NASA Astrophysics Data System (ADS)

    Carlisle, J. A.

    2009-05-01

    Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

  16. Customizable VLSI artificial neural network chips based on a novel technology

    SciTech Connect

    Fu, C. Y.; Law, B.; Chapline, G.; Swenson, D.

    1993-09-14

    The human cerebral cortex contains approximately 10{sup 11} neurons and 10{sup 14} synapses. It thus seems logical that any technology intended to mimic human capabilities should have the ability to fabricate a very large number of neurons and even larger numbers of synapses. This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems.

  17. A novel technology for fabricating customizable VLSI artificial neural network chips

    SciTech Connect

    Fu, C.Y.; Law, B.; Chapline, G.; Swenson, D.

    1992-02-05

    This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems. These neural networks are programmed using precision laser cutting and deposition. The fast turnaround of laser-based customization allows us to explore different neural network architectures and to rapidly program the synaptic weights. Our customizable chip allows us to expand an artificial network laterally and vertically. This flexibility permits us to build very large neural network systems.

  18. VLSI-circuit techniques technologies for ultrahigh-speed data-conversion interfaces. Final report, 28 Sep 87-28 Feb 91

    SciTech Connect

    Wooley, B.A.

    1991-04-29

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  19. VLSI Universal Noiseless Coder

    NASA Technical Reports Server (NTRS)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  20. VLSI and parallel computation

    SciTech Connect

    Suaya, R.; Birtwistle, G.

    1988-01-01

    This volume presents a cross-section of the most current research in parallel computation encompassing theoretical models, VLSI design, routing, and machine implementations. The book comprises a series of invited tutorial chapters on advanced topics in VLSI and concurrency. The chapters have been revised and updated to form a coherent volume exploring issues of fundamental importance in parallel computation, as well as significant research results in the contributor's specialties. Topics include load sharing models, PRAM models of computation, neural networks, Cochlea models, the design of algorithms for explicit concurrency, and VLSI CAD.

  1. Technological platform for vertical multi-wafer integration of miniature imaging instruments

    NASA Astrophysics Data System (ADS)

    Bargiel, S.; Baranski, M.; Passilly, N.; Gorecki, C.; Wiemer, M.; Frmel, J.; Wnsch, D.; Wang, W.-.

    2015-02-01

    We describe a technological platform developed for miniaturization of optical imaging instruments, such as laser scanning confocal microscopes or Optical Coherence Tomography devices. The platform employs multi-wafer vertical integration approach, combined with integrated glass-based micro-optics and heterogeneous bonding and interconnecting technologies. In this paper we focus on the unconventional fabrication methods of monolithic micro-optical structures and components in borosilicate glass (e.g. micro beamsplitters, refractive microlenses) for optical beam shaping and routing. In addition, we present hybrid laser-assisted integration of glass ball microlenses on the silicon MEMS actuators for transmissive beam scanning as well as methods of electrical signals distribution through thick glass substrates, based on HF etched via holes.

  2. Ablation and cleaning of wafer surface by excimer laser

    NASA Astrophysics Data System (ADS)

    Kim, Yong-Kee; Kim, Dae-Jin; Ryu, Je-Kil; Pak, Sung-Sik

    2001-06-01

    The importance of surface cleaning is an essential factor in VLSI technology, flat panel display, and data storage devices. The results of laser cleaning technology were studied using KrF excimer laser (248 nm) irradiation in cleanroom environment. The applied energy density was 200 - 800 mJ/cm2 at a repetition rate of 10 - 40 Hz with various focused beam widths. Results of photoresist stripping were made before and after laser irradiation with PR covered wafers and comparison of laser cleaning results were investigated as well with bare wafers. The atomic force microscopy (AFM) images of laser cleaning results were also presented and compared before and after laser irradiation. The surface roughness of AFM image of contaminated wafer surface before laser irradiation was 192 angstrom and that of after laser irradiation was 16.2 angstrom. The mechanism of laser cleaning and ablation is rapid thermal expansion of substrate surface induced by an instantaneous temperature rising due to laser irradiation. It is found that the temperature rising of the substrate surface was about 297 degree(s)C with a fluence of 400 mJ/cm2 at 300K. Laser dry cleaning technology easily removed fingerprints, submicron Al2O3 and SiO2 particulates intentionally contaminated on the top of the wafer surface without aids of toxic chemicals and deionized water.

  3. Sensitivity analysis of add-on price estimate for select silicon wafering technologies

    NASA Technical Reports Server (NTRS)

    Mokashi, A. R.

    1982-01-01

    The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

  4. Thin-film encapsulation technology for above-IC MEMS wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Zhang, Qing; Cicek, Paul-Vah; Nabki, Frederic; El-Gamal, Mourad

    2013-12-01

    This work presents a low-cost and low-temperature wafer-level packaging solution for microelectromechanical systems (MEMS) devices. Heat-sensitive polymer poly(propylene carbonate) is used as the sacrificial material to release the capping layer in a clean and fast manner. Free-standing caps made of amorphous silicon carbide films and as large as 450 m in diameter are successfully fabricated. To demonstrate the validity of this technology, surface-micromachined Pirani vacuum gauges are fabricated as an example of MEMS devices and encapsulated. Capped Pirani gauges respond to pressure between 1 mTorr and 1 atm. The Pirani gauges are sealed with Parylene C films that exhibit near-hermetic properties and the initial sealing pressure for 300 m diameter cavities is characterized to be in the range of tens of torr.

  5. Innovative design methodology for implementing heterogeneous multiprocessor architectures in VLSI

    SciTech Connect

    Tientien Li

    1983-01-01

    Considering the design cost of today's VLSI systems, advanced VLSI technology may not be cost-effective for implementing complex computer systems. In the paper, an innovative design approach which can drastically reduce the cost of implementing heterogeneous multiprocessor architectures in VLSI is presented. The author introduces high-level architectural design tools for assisting the design of multiprocessor systems with distributed memory modules and communication networks, and presents a logic/firmware synthesis scheme for automatically implementing multitasking structures and system service functions for multiprocessor architectures. Furthermore, the importance of the firmware synthesis aspect of VLSI system design is emphasized. Most logic of complex VLSI systems can be implemented very easily in firmware using the design approach introduced here. 10 references.

  6. Technology for integrated circuit micropackages for neural interfaces, based on gold-silicon wafer bonding

    NASA Astrophysics Data System (ADS)

    Saeidi, N.; Schuettler, M.; Demosthenous, A.; Donaldson, N.

    2013-07-01

    Progress in the development of active neural interface devices requires a very compact method for protecting integrated circuits (ICs). In this paper, a method of forming micropackages is described in detail. The active areas of the chips are sealed in gas-filled cavities of the cap wafer in a wafer-bonding process using Au-Si eutectic. We describe the simple additions to the design of the IC, the post-processing of the active wafer and the required features of the cap wafer. The bonds, which were made at pressure and temperature levels within the range of the tolerance of complementary metal-oxide-semiconductor ICs, are strong enough to meet MIL STD 883G, Method 2019.8 (shear force test). We show results that suggest a method for wafer-scale gross leak testing using FTIR. This micropackaging method requires no special fabrication process and is based on using IC compatible or conventional fabrication steps.

  7. The 1992 4th NASA SERC Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  8. Integrating III-V compound semiconductors with silicon using wafer bonding

    NASA Astrophysics Data System (ADS)

    Zhou, Yucai

    2000-12-01

    From Main Street to Wall Street, everyone has felt the effects caused by the Internet revolution. The Internet has created a new economy in the New Information Age and has brought significant changes in both business and personal life. This revolution has placed strong demands for higher bandwidth and higher computing speed due to high data traffic on today's information highway. In order to alleviate this problem, growing interconnection bottlenecks in digital designs have to be solved. The most feasible and practical way is to replace the conventional electrical interconnect with an optical interconnect. Since silicon does not have the optical properties necessary to accommodate these optical interconnect requirements, III-V based devices, most of which are GaAs-based or InP-based, must be intimately interconnected with the Si circuit at chip level. This monolithic integration technology enables the development of both intrachip and interchip optical connectors to take advantage of the enormous bandwidth provided by both high-performance very-large-scale integrated (VLSI) circuits and allied fiber and free-space optical technologies. However, lattice mismatch and thermal expansion mismatches between III-V materials and Si create enormous challenges for developing a feasible technology to tackle this problem. Among all the available approaches today, wafer bonding distinguishes itself as the most promising technology for integration due to its ability to overcome the constraints of both lattice constant mismatch and thermal expansion coefficient differences and even strain due to the crystal orientation. We present our development of wafer bonding technology for integrating III-V with Si in my dissertation. First, the pick-and-place multiple-wafer bonding technology was introduced. Then we systematically studied the wafer bonding of GaAs and InP with Si. Both high temperature wafer fusion and low/room temperature (LT/RT) wafer bonding have been investigated for different applications. We also systematically studied the electrical properties of bonding interfaces for high temperature wafer fusion of GaAs/Si and InP/Si. Room temperature and low temperature wafer bonding technology has been invented primarily for bonding GaAs with Si due to larger thermal expansion coefficient mismatches. Finally, we showed the feasibility and practicality of our wafer bonding technologies by fabricating high performance devices. A high performance InP-based avalanche photodetector on Si was fabricated utilizing the high temperature wafer fusion of InP and Si. And a 0.85 μm GaAs-based vertical cavity surface emitting lasers (VCSELs) were fabricated by utilizing the low temperature wafer bonding of GaAs and Si.

  9. NASA Space Engineering Research Center for VLSI System Design

    NASA Technical Reports Server (NTRS)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  10. Wafer bonding technology for new generation vacuum MEMS: challenges and promises

    NASA Astrophysics Data System (ADS)

    Dragoi, V.; Pabo, E.

    2015-05-01

    Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding process and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding processes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glass frit bonding and metal-based bonding. The outgassing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgassing. Additionally the selected bonding process must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each process for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for process characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addressed will be introduced with examples.

  11. Freestanding GaN Wafers by Hydride Vapor Phase Epitaxy Using Void-Assisted Separation Technology

    NASA Astrophysics Data System (ADS)

    Oshima, Y.; Yoshida, T.; Eri, T.; Watanabe, K.; Shibata, M.; Mishima, T.

    An outline is presented of the fabrication technique of freestanding GaN wafers by hydride vapor phase epitaxy using the void-assisted separation method and the properties of resulting crystals. A thick GaN layer of large area can be separated with excellent reproducibility from a base substrate by the application of thermal stress. This process is assisted by numerous voids formed near the interface between the thick GaN layer and the base substrate. By using this method, high-quality GaN wafers of large area with diameters of over 3 in. have been prepared.

  12. Interaction of algorithm and implementation for analog VLSI stereo vision

    NASA Astrophysics Data System (ADS)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  13. Dictionary machine (for VLSI)

    SciTech Connect

    Ottmann, T.A.; Rosenberg, A.L.; Stockmeyer, L.J.

    1982-09-01

    The authors present the design of a dictionary machine that is suitable for VLSI implementation, and discusses how to realize this implementation efficiently. The machine supports the operations of search, insert, delete, and extractment on an arbitrary ordered set. Each of these operations takes time o(logn), where n is the number of entries present when the operation is performed. Moreover, arbitrary sequences of these instructions can be pipelined through the machine at a constant rate (i.e. independent of n and the capacity of the machine). The time o(logn) is an improvement over previous VLSI designs of dictionary machines which require time o(log n) per operation, where n is the maximum number of keys that can be stored. 10 references.

  14. Verification of VLSI designs

    NASA Technical Reports Server (NTRS)

    Windley, P. J.

    1991-01-01

    In this paper we explore the specification and verification of VLSI designs. The paper focuses on abstract specification and verification of functionality using mathematical logic as opposed to low-level boolean equivalence verification such as that done using BDD's and Model Checking. Specification and verification, sometimes called formal methods, is one tool for increasing computer dependability in the face of an exponentially increasing testing effort.

  15. VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.

    PubMed

    Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip

    2014-01-01

    Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (?1 /s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology. PMID:24628497

  16. High Energy IED measurements with MEMs based Si grid technology inside a 300mm Si wafer

    NASA Astrophysics Data System (ADS)

    Funk, Merritt

    2012-10-01

    The measurement of ion energy at the wafer surface for commercial equipment and process development without extensive modification of the reactor geometry has been an industry challenge. High energy, wide frequency range, process gases tolerant, contamination free and accurate ion energy measurements are the base requirements. In this work we will report on the complete system developed to achieve the base requirements. The system includes: a reusable silicon ion energy analyzer (IEA) wafer, signal feed through, RF confinement, and high voltage measurement and control. The IEA wafer design required carful understanding of the relationships between the plasma Debye length, the number of grids, intergrid charge exchange (spacing), capacitive coupling, materials, and dielectric flash over constraints. RF confinement with measurement transparency was addressed so as not to disturb the chamber plasma, wafer sheath and DC self-bias as well as to achieve spectral accuracy The experimental results were collected using a commercial parallel plate etcher powered by a dual frequency (VHF + LF). Modeling and Simulations also confirmed the details captured in the IED.

  17. Fundamental aspects of particulate contamination of tungsten and thermal oxide wafers during chemical-mechanical polishing

    NASA Astrophysics Data System (ADS)

    Chilkunda, Raghunath R.

    Chemical-mechanical polishing (CMP) has emerged as a new processing technique for achieving a high degree of planarity (<10 mum) for submicron devices in very large scale integrated (VLSI) process technology. Metal as well dielectic films can be planarized using CMP. Polishing of tungsten (W) and interlayer dielectric (SiOsb2) films is carried out using alumina (Alsb2Osb3) based slurries which typically contain acids, complexing and oxidizing agents. One of the challenges of CMP is the effective removal of slurry particles (e.g., Alsb2Osb3) that are deposited on the wafer (e.g., W) surface during polishing. Control of particulate deposition during CMP as well as the development of post CMP cleaning techniques to remove deposited particles require an understanding of the surface and solution chemistry of the wafers and particles under polishing conditions. In this research, an attempt is made to develop an understanding of the importance of the electrostatic interactions in particle deposition using electrokinetic potential data, particle deposition results from small scale polishing experiments and calculated interaction energies between a particle and wafer surface. The electrokinetic potential of tungsten, thermal oxide (SiOsb2) wafers and alumina particles were measured as a function of solution chemistry. The measured electrokinetic potential data was used to calculate the interaction energy between an alumina particle and a wafer (e.g., W) surface using the well known DLVO (Derjaguin-Landau-Verwey-Overbeek) theory.

  18. Very Large Scale Integration (VLSI).

    ERIC Educational Resources Information Center

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be

  19. UW VLSI chip tester

    NASA Astrophysics Data System (ADS)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  20. VLSI physical design analyzer: A profiling and data mining tool

    NASA Astrophysics Data System (ADS)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  1. Large array VLSI filter

    NASA Technical Reports Server (NTRS)

    Nathan, R.

    1983-01-01

    A 35 by 35 element pipelined convolutional kernel is being fabricated using VLSI chips, each containing a 5 by 1 segment of the kernel. Three levels of printed circuitry are used: the first level is used for the VLSI chips, the second level connects seven chips together on one platform, and the third level connects seven platforms with associated delay lines, all fitting on one board. Therefore, on each board there are seven rows of the kernel containing 245 multipliers and adders, and five such boards complete the kernel array. Each multiplier accepts an 8 bit picture element which is multiplied by a 16 bit weight. A truncated 22 bit product is added to a previously stored product sum and the results are shifted to the following multiplier as the next picture element is read in. The multiplier uses a modified Booth algorithm to reduce the number of shift add operations nearly in half. The filter box is presently configured as an ancillary box to a VAX 11/780, but can be connected to essentially any CPU. The I/O bandwidth is easily compatible with most CPU devices.

  2. Mixed voltage VLSI design

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  3. Noise investigations of 90-nm VLSI CMOS technologies for analog integrated circuits at millimeter-wave frequencies

    NASA Astrophysics Data System (ADS)

    Ellinger, Frank; Schmatz, Martin L.; Jaeckel, Heinz

    2004-05-01

    In this paper, the noise properties of transistors on 90 nm silicon on insulator (SOI) and bulk CMOS technologies are investigated. At 20 GHz, the SOI and bulk devices have minimum noise figures of 1 dB and 2.3 dB, respectively, demonstrating the superior performance of the SOI technology. The corresponding maximum available gain is 13 dB and 12 dB, respectively. For the first time, the drain and gate noise coefficients of shortchannel SOI devices are extracted yielding values of 2.15 and 1.7, respectively. Theoretical aspects are discussed to identify the main noise sources and to gain insights for optimizations. Furthermore, examples of analog monolithic integrated circuits fabricated on SOI technology are presented. Measured results are a noise figure of 4 dB for a low noise amplifier (LNA) at 40 GHz, a single side band noise figure of 9 dB for a passive mixer at 40 GHz and a phase noise of -90 dBc at 1 MHz offset for an voltage controlled oscillator (VCO) at 60 GHz. To the knowledge of the authors, these are the best noise performances achieved to date for CMOS based transistors and circuits at millimeter wave frequencies.

  4. VLSI Architectures for Computing DFT's

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  5. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Luo, Xianshu; Cao, Yulian; Song, Junfeng; Hu, Xiaonan; Cheng, Yungbing; Li, Chengming; Liu, Chongyang; Liow, Tsung-Yang; Yu, Mingbin; Wang, Hong; Wang, Qijie; Lo, Patrick Guo-Qiang

    2015-04-01

    Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS) fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W) bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP) laser, lateral-coupled distributed feedback (LC-DFB) laser with side wall grating, and mode-locked laser (MLL). From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC).

  6. Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies

    NASA Astrophysics Data System (ADS)

    Tanake, Katsuaki

    We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of InP/Si substrates for bulk InP in the fabrication of such a four-junction solar cell could significantly reduce the substrate cost since the current prices for commercial InP substrates are much higher than those for Si substrates by two orders of magnitude. Direct heteroepitaxial growth of InP thin films on Si substrates has not produced the low dislocation-density high quality layers required for active InGaAs/InP in optoelectronic devices due to the ˜8% lattice mismatch between InP and Si. We successfully fabricated InP/Si substrates by He implantation of InP prior to bonding to a thermally oxidized Si substrate and annealing to exfoliate an InP thin film. The thickness of the exfoliated InP films was only 900 nm, which means hundreds of the InP/Si substrates could be prepared from a single InP wafer in principle. The photovoltaic current-voltage characteristics of the In0.53Ga0.47As cells fabricated on the wafer-bonded InP/Si substrates were comparable to those synthesized on commercially available epi-ready InP substrates, and had a ˜20% higher short-circuit current which we attribute to the high reflectivity of the InP/SiO2/Si bonding interface. This work provides an initial demonstration of wafer-bonded InP/Si substrates as an alternative to bulk InP substrates for solar cell applications. We have observed photocurrent enhancements up to 260% at 900 nm for a GaAs cell with a dense array of Ag nanoparticles with 150 nm diameter and 20 nm height deposited through porous alumina membranes by thermal evaporation on top of the cell, relative to reference GaAs cells with no metal nanoparticle array. This dramatic photocurrent enhancement is attributed to the effect of metal nanoparticles to scatter the incident light into photovoltaic layers with a wide range of angles to increase the optical path length in the absorber layer. GaAs solar cells with metallic structures at the bottom of the photovoltaic active layers, not only at the top, using semiconductor-metal direct bonding have been fabricated. These metallic back structures could incouple the incident light into surface plasmon mode propagating at the semiconductor/metal interface to increase the optical path, as well as simply act as back reflector, and we have observed significantly increased short-circuit current relative to reference cells without these metal components. (Abstract shortened by UMI.)

  7. Systolic algorithms and VLSI implementations for graph-matching problems

    SciTech Connect

    Liu, H.L.C.

    1985-01-01

    With the advances of current microcircuit technologies, VLSI implementations reveal characteristics distinct from earlier digital systems. To fully utilize the tremendous computation power of a silicon surface, VLSI algorithms need to be carefully and systematically derived. Systolic algorithms and event-driven networks are the keys to future VLSI performance. Based on these distinct requirements, fundamental mathematical tools such as linear algebra, relational algebra, group theory, random variables, and graph theory are applied toward the derivation and analysis of a representative problem, the graph-matching problem, and its implementation. Because of the systematic development based on mathematics, as opposed to human heuristics, the major computations of the derived algorithms are systematic matrix operations, and hence are easily mapped to asynchronous systolic implementations. An extended branch-and-bound formulation of the algorithm is also discussed. Finally, extensions to attributed graph matching and noisy graph matching are studied and a real world application is presented.

  8. VLSI MIL-STD-1750A processor development

    NASA Astrophysics Data System (ADS)

    Gaertner, M.; Winter, T.; Brauchmann, W.

    An American company is developing a VLSI program to design, fabricate, characterize, and deliver a family of General Purpose Computers optimized to execute MIL-STD-1750A Notice 1. The CPU architecture is fashioned in an extensible functional module configuration with a performance range from 0.9 MIPS to 1.5 MIPS (DAIS-type Mix). The three configurations which have emerged include baseline CPU, baseline CPU plus floating point accelerator, and 32-bit data path CPU (ISA Invisible). It is pointed out that these machines will employ multisource VLSI low power CMOS technology and will be fully qualified to meet military environmental specifications.

  9. Titanic: a VLSI based content addressable parallel array processor

    SciTech Connect

    Weems, C.; Levitan, S.; Foster, C.

    1982-01-01

    A design is presented for a content addressable parallel array processor (CAPAP) which is both practical and feasible. Its practicality stems from an extensive program of research into real applications of content addressability and parallelism. The feasibility of the design stems from development under a set of conservative engineering constraints tied to limitations of VLSI technology. 1 ref.

  10. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  11. Algorithms for VLSI artwork

    SciTech Connect

    Wu, San-Yuan.

    1989-01-01

    The specific problems that the author studies in this thesis are painting and drawing of rectilinear polygons, covering rectilinear polygons by rectangles, and partitioning rectilinear polygons into rectangles. These problems have application to VLSI design, computer graphics, etc. He considers three display devices, one-dimensional and two dimensional pen plotters, and video screens, for the problem of painting and covering. An 0 (n log n) time algorithm to obtain an optimal drawing strategy on one-dimensional plotters is obtained (n is the number of the vertices of the polygons). Fore the case of a two-dimensional plotter, the strategy to optimally draw the contour of a rectilinear polygon can be found in linear time. However, for a collection of rectilinear polygons, this problem is NP-hard. For screen type displays, he formulates three strategies to paint a rectilinear polygon using a rectangle as a primitive. For two of these, he shows the problem NP-hard. Performance bounds for these strategies are also obtained. Three approximation algorithms to cover a rectilinear polygon that is neither horizontally nor vertically convex by rectangles are developed. All three guarantee covers that have at most twice as many rectangles as in an optimal cover. The complexities of those algorithms are O (n log n), O(n{sup 2}), and O(n{sup 4}), respectively. Finally, he develops two algorithms to obtain the optimal partition of simple rectilinear polygons. Their time complexities are {approximately} O (kn) and O (n log k), where k is the number of the inversions of the polygon. Both are significantly faster than the existing best algorithm on polygons whose size is large relative to k.

  12. Research in VLSI systems

    NASA Astrophysics Data System (ADS)

    1983-11-01

    The parametric test facility provides two essential support functions for the Fast Turn-Around Laboratory - feedback of process-control information to the fabrication line, and characterization of active devices and parasitics for circuit design. The basic parametric tester, consisting of a Rucker and Kolls model 1032 stepping wafer prober, an HP 4145 semiconductor parameter analyzer, and an HP 6942A switching matrix controlled by an HP 9845 calculator, has been upgraded by addition of an HP 3456 system, DVM, an HP 5316 frequency counter, and an HP 4271 capacitance bridge. The DVM gives increased system flexibility while the frequency counter provides for the direct measurement of ring oscillator performance. Custom hardware has been designed and built for the rapid extraction of MOS transistor threshold and capacitor breakdown voltages. The system includes the necessary software to measure such process control parameters as line widths, sheet resistances, and threshold and breakdown voltages. Software has also been developed for the statistical analysis of these data on the HP 9845 computer. This software can produce maps of parameter variations across a wafer as well as the usual means, standard deviations, and histograms.

  13. An efficient interpolation filter VLSI architecture for HEVC standard

    NASA Astrophysics Data System (ADS)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  14. 3D integration approaches for MEMS and CMOS sensors based on a Cu through-silicon-via technology and wafer level bonding

    NASA Astrophysics Data System (ADS)

    Hofmann, L.; Dempwolf, S.; Reuter, D.; Ecke, R.; Gottfried, K.; Schulz, S. E.; Knechtel, R.; Geßner, T.

    2015-05-01

    Technologies for the 3D integration are described within this paper with respect to devices that have to retain a specific minimum wafer thickness for handling purposes (CMOS) and integrity of mechanical elements (MEMS). This implies Through-Silicon Vias (TSVs) with large dimensions and high aspect ratios (HAR). Moreover, as a main objective, the aspired TSV technology had to be universal and scalable with the designated utilization in a MEMS/CMOS foundry. Two TSV approaches are investigated and discussed, in which the TSVs were fabricated either before or after wafer thinning. One distinctive feature is an incomplete TSV Cu-filling, which avoids long processing and complex process control, while minimizing the thermomechanical stress between Cu and Si and related adverse effects in the device. However, the incomplete filling also includes various challenges regarding process integration. A method based on pattern plating is described, in which TSVs are metalized at the same time as the redistribution layer and which eliminates the need for additional planarization and patterning steps. For MEMS, the realization of a protective hermetically sealed capping is crucial, which is addressed in this paper by glass frit wafer level bonding and is discussed for hermetic sealing of MEMS inertial sensors. The TSV based 3D integration technologies are demonstrated on CMOS like test vehicle and on a MEMS device fabricated in Air Gap Insulated Microstructure (AIM) technology.

  15. Minimum silicon wafer thickness for ID wafering

    NASA Technical Reports Server (NTRS)

    Chen, C. P.

    1982-01-01

    An analytical model, based on fracture mechanics analysis, is proposed for estimating the minimum wafer thickness as a function of the diameter requirement for solar cells. The conditions under which the model can be applied are discussed with reference to the critical flaw size, the applied force, and the width of the side support. It is shown that the equivalent cantilever force applied during ID slicing can be estimated from the wafering mechanical yield data. The width of the wafer side support was found to be a significant factor in controlling the minimum allowable wafer thickness during slicing. Wafer side support width requirements were found to increase with decreasing wafer thickness.

  16. The Fifth NASA Symposium on VLSI Design

    SciTech Connect

    Not Available

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design. Separate abstracts have been prepared for articles from this report.

  17. The Fifth NASA Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  18. The synthesis and validation of experimental VLSI design using decoupled behavioral, structural and physical specifications

    NASA Astrophysics Data System (ADS)

    Dallen, J. A., Jr.

    The era of VLSI has transformed the discipline of integrated circuit design into digital systems design. The complexity of these systems has been the primary hindrance in taking advantage of VLSI potential. A myriad of design approaches and design techniques were both suggested and implemented for VLSI design, but as of this time an optimal design methodology is not known. Nowhere is the problem more acute than in the domains of custom and experimental design. To address this challenge a strategy is defined for the design of custom and experimental VLSI systems. To place this strategy in perspective, a structure is presented by which alternative design methodologies and design languages are categorized. With this structure, different levels of design abstraction are defined and different design representations are identified as having behavioral, structural and/or physical properties. Using this structure, the requirements for a design strategy are generated, including a multilevel, technology-independent design language that supports hierarchical design.

  19. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  20. Research in VLSI systems. Heuristic programming project and VLSI theory project. A fast turn around facility for very large scale integration (VLSI)

    NASA Astrophysics Data System (ADS)

    Hennessy, J.; Matthews, R.; Newkirk, J.; Shott, J.; Ullman, J. D.; Brown, H.

    1983-11-01

    This report summarizes progress in the DARPA funded VLSI Systems Research Projects from May 1983 to November 1983, inclusive. The major areas under investigation have included: analysis and synthesis design aids, applications of VLSI, special purpose chip design, VLSI computer architectures, signal processing algorithms and architectures, reliability studies, hardware specification and verification, VLSI theory, and VLSI fabrication. The major research problems are introduced and progress is discussed; the Appendix contains a list of published research papers from these projects.

  1. SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    NASA Astrophysics Data System (ADS)

    Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

    2010-10-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

  2. VLSI Processor For Vector Quantization

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  3. Fast and area-efficient VLSI adders

    SciTech Connect

    Han, T.D.

    1987-01-01

    Area-time tradeoffs have been an important topic in VLSI research. This is because the cost of fabricating a circuit is an exponential function of its area. As a result, optimizing the area of a VLSI design is much more important than optimizing the speed of an algorithm. This dissertation examines area-time tradeoffs in VLSI for prefix computation using graph representations of the problem. Since the problem is intimately related to binary addition, results obtained lead to design of area-time efficient VLSI adders. This is a major goal of the work: to design very low latency-addition circuitry that is also area-efficient. To this end, a new graph representation is presented for prefix computation that leads to the design of a fast, area-efficient binary adder. The new graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, the author designed VLSI adders having area A = O(n log n) whose delay time is the lowest possible value, i.e., the fastest possible area-efficient VLSI adder. For the large number of inputs, the pipelined model of prefix circuit is presented. Also presented is a fault-tolerant model for the developed prefix circuit, based on the partitioning of the network.

  4. Fracture of silicon wafers

    NASA Astrophysics Data System (ADS)

    McLaughlin, J. C.; Willoughby, A. F. W.

    1987-11-01

    In spite of the increasing use of silicon in applications where mechanical stresses are deliberately applied to the material, such as in transducers, and the fatal nature of cracking in silicon devices, there is very limited characterisation and understanding of the fracture behaviour of silicon wafers at room temperature. This understanding is of increasing importance with the use of larger diameter wafers in modern technology. This paper examines the fracture strength of a wide range of silicon material both as-grown and after processing. The wafers tested were from crystals grwon by float-zone and Czochralski techniques and the effects of oxidation, ion-implantation and annealing in various environments have been studied. The technique used to measure the fracture stress involved simply supporting the wafer on an aluminium ring concentric to the load axis. The load was gradually increased until the wafer fractured. This method was chosen to avoid edge effects, and has proved to have adequate reproducibility. Typical values of the fracture stress obtained by this method, for different crystals, vary between 2 and 3.5 GPa. In the first part of the study, the role of the surface on the fracture behaviour has been investigated in detail. While the surface perfection of the tensile surface has a major effect on the fracture stress (as shown in previous studies), some of the results were found to be sensitive to the compressive surface as well. In the case where the results are sensitive to the compressive surface finish the fracture stress rose from 3.7 to 8.8 GPa as the surface finish was improved while in the cases where they were not sensitive the fracture stress remained at about 3.5-4.6 GPa. Only in the float-zone material were fracture stresses approaching 8.8 GPa observed. At this level of fracture stress, the behaviour is believed to be sensitive to surface defects less than 0.01 ?m in size. These results can be analyzed in terms of surface controlled defects under conditions where surface defects are dominant and bulk controlled defects where these defects are dominant. In this manner bulk effects can be isolated from surface ones. This gives the opportunity to study the effects of specific defects on the fracture stress and the results in this paper are discussed in terms of the role of surface and internal defects on the fracture stress.

  5. Quality procedures for VLSI/VHSIC (Very Large Scale Integrated and Very High Speed Integrated Circuits) type devices

    NASA Astrophysics Data System (ADS)

    Cohen, S.

    1985-11-01

    Procedures for microcircuit screening and qualification to ensure the reliability and uniformity of VLSI/VHSIC devices were prepared. The use of Process Control Monitors (PCM) and Reliability Evaluation Modules (REM) were incorporated in the procedures. In addition, recommended guidelines for the evaluation of Computer-Aided-Manufacturing (CAM) facilities were generated in this study. A proposed replacement was provided for existing Method 5007 to MIL-STD-883, Wafer Acceptance Procedure which incorporates reliability screening, process quality evaluation, and electrical parameter testing of each wafer in a lot.

  6. Reconfigurable VLSI architecture for a database processor

    SciTech Connect

    Oflazer, K.

    1983-01-01

    This work brings together the processing potential offered by regularly structured VLSI processing units and the architecture of a database processor-the relational associative processor (RAP). The main motivations are to integrate a RAP cell processor on a few VLSI chips and improve performance by employing procedures exploiting these VLSI chips and the system level reconfigurability of processing resources. The resulting VLSI database processor consists of parallel processing cells that can be reconfigured into a large processor to execute the hard operations of projection and semijoin efficiently. It is shown that such a configuration can provide 2 to 3 orders of magnitude of performance improvement over previous implementations of the RAP system in the execution of such operations. 27 refs.

  7. Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

    NASA Technical Reports Server (NTRS)

    Offord, Bruce W.

    1992-01-01

    In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

  8. A second generation 50 Mbps VLSI level zero processing system prototype

    NASA Technical Reports Server (NTRS)

    Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

    1994-01-01

    Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

  9. Constant fan-in digital neural networks are VLSI-optimal

    SciTech Connect

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  10. Designing of Low-Power VLSI Circuits using Non-Clocked Logic Style

    NASA Astrophysics Data System (ADS)

    Sharma, Vishal; Srivastava, Jitendra Kaushal

    2012-08-01

    Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the vlsi circuits with the performance upto the acceptable level. The dominant term in a well designed vlsi circuit is the switching power and low-power design thus becomes the task of minimizing this switching power. So, to design a low-power vlsi circuit, it is preferable to use Nonclocked logic styles as they have less switching power. In this work various Non-clocked logic styles are compared by performing transistor level simulations for half adder circuit using TSMC 0.18 m Technology and Eldo simulator of Mentor graphics.

  11. Development of a 2 micrometer silicon-gate-CMOS-technology for microcomputer oriented VLSI circuits with a supply voltage range between 1.5 and 5 V

    NASA Astrophysics Data System (ADS)

    Fischer, G.; Kiss, T.; Kummerow, K.; Link, M.; Scharzmann, U.

    1984-10-01

    The processes necessary for a 2 micron CMOS-technology were developed, including projection lithography, the oxidation process, the fabrication of thin oxides, and dry etching techniques for patterning silicon nitride, polysilicon, silicon oxide, and aluminum. With the aid of process simulations and experimental results, a process flow chart was established. A test chip with a large number of single structures and circuit blocks was designed in 2 micron tubes. Different runs of this test chip are produced. The success of the developed technology is demonstrated on different logic circuit blocks.

  12. The 1991 3rd NASA Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Maki, Gary K.

    1991-01-01

    Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

  13. Advanced CD Linearity Improvement for Multi-Project Wafers and SoC at 95 nm Technology Node

    NASA Astrophysics Data System (ADS)

    Lu, Jeremy; Sandlin, Nicole L.; Sato, Hidetoshi; Lu, Colbert; Cheng, Nicole; Huang, Torey; Su, Clyde; Buie, Melisa J.

    2002-12-01

    The continuous shrinking of design rules results in tighter specifications for linearity in advanced mask processing. Specifically, the increasing need for multiple devices on a single reticle set, e.g., multiproject wafers (MPWs) and systems on a chip (SoC), drives development in this area. Advanced masks were prepared with positive and negative chemically amplified resist (CAR) written on the Hitachi HL-950M. Post-exposure bake was performed in a double-sided proximity baking system; development was done using a spray-puddle method. Etch experiments were performed in the Etec Systems Tetra photomask etch chamber. Linearity measurements were performed using the Hitachi S-7840 CD SEM and the Leica LWM 250 DUV. Both clear and dark isolated and dense features were measured. The current work examines the impact of various etch process parameters (Cl2/O2 ratio, gas flow, pressure, source power) on CD linearity between 400 nm and 1.25 ?m. A full factorial-designed orthogonal experiment was performed to determine the main effects and any interactions that might impact the linearity performance. Pressure and total flow showed a strong influence on linearity.

  14. The VLSI design of error-trellis syndrome decoding for convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

    1985-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  15. The VLSI design of an error-trellis syndrome decoder for certain convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

    1986-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  16. Wafer capping of MEMS with fab-friendly metals

    NASA Astrophysics Data System (ADS)

    Martin, Jack

    2007-01-01

    Inertial MEMS (Micro Electro Mechanical System) sensors are normally sealed in hermetic enclosures. Some are assembled in hermetic packages but wafer level packaging has become much more important in recent years. Anodic bonding can be used to achieve wafer level seals between silicon and glass but most suppliers of inertial sensors screen print glass frit onto silicon cap wafers. After removing the organic vehicle, these patterned cap wafers are sealed to device wafer prior to wafer singulation and plastic packaging. Anodic and glass frit bonding are both cost-effective. However, they impose size, quality and performance limitations. Wafer level sealing with a metal removes some of these limitations but introduces other concerns. This paper will review the current wafer level hermetic processes followed by a description of a thermocompression metal seal technology that is compatible with IC fabrication.

  17. MIL-STD-1553 VLSI components

    NASA Astrophysics Data System (ADS)

    Friedman, Steven N.

    The performance, physical and electrical characteristics of novel VLSI components which will support all MIL-STD-1553 terminals are described. A transceiver, protocol, and computer interface set of chips supports remote terminal unit, bus controller, and bus monitor modes of operation. A discussion of these VLSI components is given, and their special features are explored. These features include size and packaging options, radiation hardness, power, and reliability considerations. The special capabilities of these devices are highlighted, along with programming options that facilitate a broad array of applications.

  18. Associative Pattern Recognition In Analog VLSI Circuits

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  19. VLSI complexity of parallel Fourier transform algorithms

    SciTech Connect

    Baradaran Seyed, T.

    1989-01-01

    Scope and method of study. The purpose of this study is to present a set of new parallel algorithms for discrete Fourier transform and compare the VLSI time and area complexity of the associated designs with the existing designs. The proposed parallel algorithms may be implemented easily in pipeline and mesh-connected parallel processing systems. Findings and conclusions. Several parallel algorithms have been proposed and associated cell layout for VLSI implementation have been presented. Comparative analysis shows that two of the designs presented by this study have better area-time performance than the existing designs in their architectural category.

  20. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  1. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020from $0.15 per kilowatt hour to less than $0.07. 1366s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with todays state-of-the-art technologies. 1366s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366s technology, the cost of silicon wafers could be reduced by 80%.

  2. Image quality and wafer level optics

    NASA Astrophysics Data System (ADS)

    Dagan, Y.; Humpston, G.

    2010-05-01

    Increasing demand from consumers to integrate camera modules into electronic devices, such as cell phones, has driven the cost of camera modules down very rapidly. Now that most cell phones include at least one camera, consumers are starting to ask for better image quality - without compromising on the cost. Wafer level optics has emerged over the past few years as an innovative technology enabling simultaneous manufacturing of thousands of lenses, at the wafer level. Using reflow-compatible materials to manufacture these lenses permits a reduction in the cost and size of camera module, thus answering the market demand for lowering the cost. But what about image quality? The author will present image quality analysis that was conducted for both VGA and megapixel camera resolutions. Comparison between conventional camera modules and wafer level camera modules shows wafer level technology brings equivalent, if not better, image quality performance compared to conventional camera modules.

  3. Extremely long life and low-cost 193nm excimer laser chamber technology for 450mm wafer multipatterning lithography

    NASA Astrophysics Data System (ADS)

    Tsushima, Hiroaki; Katsuumi, Hisakazu; Ikeda, Hiroyuki; Asayama, Takeshi; Kumazaki, Takahito; Kurosu, Akihiko; Ohta, Takeshi; Kakizaki, Kouji; Matsunaga, Takashi; Mizoguchi, Hakaru

    2014-04-01

    193nm ArF excimer lasers are widely used as light sources for the lithography process of semiconductor production. 193nm ArF exicmer lasers are expected to continue to be the main solution in photolithography, since advanced lithography technologies such as multiple patterning and Self-Aligned Double Patterning (SADP) are being developed. In order to apply these technologies to high-volume semiconductor manufacturing, the key is to reduce the total operating cost. To reduce the total operating cost, life extension of consumable part and reduction of power consumption are an important factor. The chamber life time and power consumption are a main factor to decide the total operating cost. Therefore, we have developed the new technology for extension of the chamber life time and low electricity consumption. In this paper, we will report the new technology to extend the life time of the laser chamber and to reduce the electricity consumption.

  4. Wafer LMC accuracy improvement by adding mask model

    NASA Astrophysics Data System (ADS)

    Lo, Wei Cyuan; Cheng, Yung Feng; Chen, Ming Jui; Haung, Peter; Chang, Stephen; Tsujimoto, Eiji

    2010-04-01

    Mask effect will be more sensitive for wafer printing in high-end technology. For advance only using current wafer model can not predict real wafer behavior accurately because it do not concern real mask performance (CD error, corner rounding..). Generally, we use wafer model to check whether our OPC results can satisfy our requirements (CD target). Through simulation on post-OPC patterns by using wafer model, we can check whether these post-OPC patterns can meet our target. Hence, accuracy model can help us to predict real wafer printing results and avoid OPC verification error. To Improve simulation verification accuracy at wafer level and decrease false alarm. We must consider mask effect like corner rounding and line-end shortening...etc in high-end mask. UMC (United Microelectronics Corporation) has cooperated with Brion and DNP to evaluate whether the wafer LMC (Lithography Manufacturability Check) (Brion hot spots prediction by simulation contour) accuracy can be improved by adding mask model into LMC verification procedure. We combine mask model (DNP provide 45nm node Poly mask model) and wafer model (UMC provide 45nm node Poly wafer model) then build up a new model that called M-FEM (Mask Focus Energy Matrix model) (Brion fitting M-FEM model). We compare the hotspots prediction between M-FEM model and baseline wafer model by LMC verification. Some different hotspots between two models were found. We evaluate whether the hotspots of M-FEM is more close to wafer printing results.

  5. Reliability of small geometry VLSI devices for microelectronics

    NASA Astrophysics Data System (ADS)

    White, Marvin H.

    1992-02-01

    This proposal is a continuation of a project which began in August 1986. The goal of the project, in a broad sense, is to perform exploratory research into the physics of carriers in silicon inversion layers with a focus on the issues which affect the reliability of small geometry VLSI devices. This project permits us to study the physical electronics of silicon surfaces and the overlying insulators. In the proposed project we stress the application of this research to the area of Wafer Scale Integration where reliability and fault tolerance are key issues for the SDI program. The extensive signal processing and data storage required to implement high-resolution, sensor-based systems demands that consideration be given to the area of system and component reliability. At the component level the issues revolve around the reliability of the scaled MOS Transistor with nanometric feature sizes. One important area is the susceptibility of the gate insulator to (1) hot electron trapping, (2) premature dielectric breakdown, and (3) space radiation environment considerations which can limit the MTTF of the SDIO mission. A second issue at the component level is the SDI need for low-power, high-density, nonvolatile data storage with nondestructive readout (NDRO), radiation tolerance and immunity to single event upsets (SEU's).

  6. SSI/MSI/LSI/VLSI/ULSI.

    ERIC Educational Resources Information Center

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  7. SSI/MSI/LSI/VLSI/ULSI.

    ERIC Educational Resources Information Center

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future

  8. VLSI Unit for Two-Dimensional Convolutions

    NASA Technical Reports Server (NTRS)

    Liu, K. Y.

    1983-01-01

    Universal logic structure allows same VLSI chip to be used for variety of computational functions required for two dimensional convolutions. Fast polynomial transform technique is extended into tree computational structure composed of two units: fast polynomial transform (FPT) unit and Chinese remainder theorem (CRT) computational unit.

  9. A single-supply, monolithic, MIL-STD-1553 transceiver implemented in BiCMOS wafer fabrication technology

    NASA Astrophysics Data System (ADS)

    Albrecht, Thomas L.; Molinari, Lou

    An integrated circuit has been designed for use as a single supply, MIL-STD-1553 transceiver using BiCMOS technology. Use of the BiCMOS fabrication process has advantages over both Bipolar and CMOS technologies. These advantages include: reduced standby current drain, increased flexibility in mating the transceiver to various remote terminals, increased control over output amplitude and rise/fall times, easier methods for adjusting filter response and residual voltage, and reduced chip size (over a CMOS transceiver). Development of this monolithic transceiver opens the door to future advances in remote terminal design. By combining the current driving capacity of Bipolar with the digital design capability of CMOS, the next probable step in the progression of MIL-STD-1553 technology would be a fully monolithic remote terminal. This device would combine a transceiver with the encoder/decoder and protocol logic on a single semiconductor device.

  10. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  11. Scriber for silicon wafers

    NASA Technical Reports Server (NTRS)

    Yamakawa, K. A.; Fortier, E. P. (inventors)

    1981-01-01

    A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

  12. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L. (Denver, CO)

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  13. Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

    NASA Astrophysics Data System (ADS)

    Lin, Chiung-Wen; Yang, Hsueh-An; Wang, Wei Chung; Fang, Weileun

    2007-06-01

    Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.

  14. Reciprocating Saw for Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.; Collins, E. R., Jr.

    1985-01-01

    Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

  15. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  16. AWV: high-throughput cross-array cross-wafer variation mapping

    NASA Astrophysics Data System (ADS)

    Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

    2008-03-01

    Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

  17. Leak detection utilizing analog binaural (VLSI) techniques

    NASA Technical Reports Server (NTRS)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  18. Modular VLSI Reed-Solomon Decoder

    NASA Technical Reports Server (NTRS)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  19. Systolic VLSI Reed-Solomon Decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.

    1986-01-01

    Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

  20. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    NASA Technical Reports Server (NTRS)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  1. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  2. Innovative metrology for wafer edge defectivity in immersion lithography

    NASA Astrophysics Data System (ADS)

    Pollentier, I.; Iwamoto, F.; Kocsis, M.; Somanchi, A.; Burkeen, F.; Vedula, S.

    2007-03-01

    In semiconductor manufacturing, the control of defects at the edge of the wafer is a key factor to keep the number of yielding die on a wafer as high as possible. Using dry lithography, this control is typically done by an edge bead removal (EBR) process, which is understood well. Immersion lithography however changes this situation significantly. During this exposure, the wafer edge is locally in contact with water from the immersion hood, and particles can then be transported back and forth from the wafer edge area to the scanner wafer stage. Materiel in the EBR region can also potentially be damaged by the dynamic force of the immersion hood movement. In this paper, we have investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to the inspection of the flat top part of the wafer edge, due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. This study utilized KLA-Tencor's VisEdge, a new automated edge inspection system, that provides full wafer edge imaging (top, side, bottom) using laser-based optics and multi-sensor detection, and where defects of interest can be classified with Automated Defect Classification (ADC) software. Using the VisEdge technology, the impact from the immersion lithography towards wafer edge defectivity is investigated. The work revealed several key challenges to keep the wafer edge related defectivity under control : choice of resist, optimization of EBR recipes, scanner pollution and related memory effects, wafer handling, device processing, etc... Contributing to the understanding of the mechanisms of wafer edge related immersion defects and to the optimization the die yield level, this technology is believed to be important when the immersion processes are introduced in semiconductor manufacturing.

  3. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  4. Cascaded VLSI Chips Help Neural Network To Learn

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  5. VLSI readout for imaging with polycrystalline mercuric iodide detectors

    NASA Astrophysics Data System (ADS)

    Turchetta, Renato; Dulinski, Wojtek; Husson, D.; Klein, N.; Riester, J. L.; Schieber, Michael M.; Zuck, A.; Braiman, M.; Melekhov, L.; Nissenbaum, J.; Sanguinetti, S.

    1998-11-01

    Recently polycrystalline mercuric iodide have become available, for room temperature radiation detectors over large areas at low cost. Though the quality of this material is still under improvement, ceramic detectors have been already been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors used are of different kinds: microstrips and pixels; of different sizes, up to about 1 square inch; and of different thickness, up to 600 microns. The properties of this first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed.

  6. Replacing design rules in the VLSI design cycle

    NASA Astrophysics Data System (ADS)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  7. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  8. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  9. Parallel optimization algorithms and their implementation in VLSI design

    NASA Technical Reports Server (NTRS)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  10. Image Compression on a VLSI Neural-Based Vector Quantizer.

    ERIC Educational Resources Information Center

    Chen, Oscal T.-C.; And Others

    1992-01-01

    Describes a modified frequency-sensitive self-organization (FSO) algorithm for image data compression and the associated VLSI architecture. Topics discussed include vector quantization; VLSI neural processor architecture; detailed circuit implementation; and a neural network vector quantization prototype chip. Examples of images using the FSO

  11. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  12. A synergistic solution to the problem of packaging and interconnecting VLSI/VHSIC chips

    NASA Astrophysics Data System (ADS)

    Gioia, J. C.

    1982-10-01

    Solutions are required for the many problems faced by the chip packaging and interconnection systems industry for effectively meeting the demanding application requirements of the rapidly emerging very-large scale integration/very-high speed integrated circuits (VLSI/VHSIC) chips. Present packaging technologies are being stretched beyond their original concepts thus requiring a new approach to the problem solution. The Military Electronics Systems Operations (MESO) has developed a new packaging approach, based on the Direct Bond Copper Process, which addressed these problems providing a completely integrated system. The problem solution starts at the chip level where en masse connections are made to the chip, chip heat is more effectively managed, low-cost chip hermetic seals accomplished, and then continues providing improved means for interconnecting many VLSI/VHSIC chips.

  13. VLSI architectures for geometrical mapping problems in high-definition image processing

    NASA Technical Reports Server (NTRS)

    Kim, K.; Lee, J.

    1991-01-01

    This paper explores a VLSI architecture for geometrical mapping address computation. The geometric transformation is discussed in the context of plane projective geometry, which invokes a set of basic transformations to be implemented for the general image processing. The homogeneous and 2-dimensional cartesian coordinates are employed to represent the transformations, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme for a processor, which utilizes full-pipelining at the macro-level and parallel constant-factor-redundant arithmetic and full-pipelining at the micro-level, is assessed to produce a single VLSI chip for HDTV applications using state-of-art MOS technology.

  14. An artificial intelligence approach to VLSI routing

    SciTech Connect

    Joobbani, R.

    1985-01-01

    An Artificial Intelligence Approach to VLSI Routing presents a system that performs routing close to what human designers do. As is carefully outlined in the book, the proposed system heavily capitalizes on the knowledge of human expertise in this area. Included in this test is background of some representative techniques for routing, and a summary of their characteristics. A detailed study is also included of the different factors that affect the routing quality and the criteria that can e used to optimize these factors.

  15. Optimal VLSI dictionary machines without compress instructions

    SciTech Connect

    Li, H.F.; Probst, D.K. )

    1990-05-01

    The authors present several designs for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The authors' initial design objectives included: single-cycle operability of host-issued modify and query commands (no compress instructions), complete processor utilization (no wasted processors), and optimal 2 log {ital n} response times, where {ital n} is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously.

  16. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  17. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  18. 30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology

    NASA Technical Reports Server (NTRS)

    Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

    1986-01-01

    An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

  19. Design automation tools for testable VLSI circuits

    NASA Astrophysics Data System (ADS)

    Adhem, Saman M. I.

    A very large scale integration (VLSI) circuit is assumed to contain a number of modules such as random logic circuits and read-only memories. By modifying the subcircuits locally, via selecting a design for testability (DFT) scheme, and monitoring the whole test globally the VLSI circuit is made testable. Following this framework, two problems are recognized: selection of the proper DFT technique to optimize the testability aspects of the macro cell, and modification of the macro cell to conform with the chosen DFT scheme. A generalized selection methodology has been developed to solve the selection problem employing an optimization technique and a satisfaction procedure to arrive at a solution that meets the user constraints. A knowledge based system that implements the selection mechanism has been developed to choose a built-in self-test (BIST) technique for random logic circuits. Modifying a circuit to comply with a given DFT scheme has also been studied for two DFT techniques and a number of tools have been developed. A new scan design methodology has been introduced which has simple design rules and employs two area efficient memory elements as internal storage. A comprehensive design tool has been developed to check circuits for design rule violations, check and correct scan design rule violations, and synthesize the scan path.

  20. Wavelength-encoded OCDMA system using opto-VLSI processors

    NASA Astrophysics Data System (ADS)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  1. VLSI Implementations of Neural Networks

    NASA Astrophysics Data System (ADS)

    Hollis, Paul William

    1992-01-01

    The purpose of this research is to explore various methods of implementing neural network architectures in hardware, with emphasis on learning networks and their associated algorithms. The approach taken utilizes hybrid (analog and digital circuitry) architectures which can benefit from the speed of parallel analog hardware, and from the ease of communication and control available with digital hardware. There are several areas of research which are highlighted in this manuscript. Three neuron models are described which have been characterized through simulation. Two of the models utilize traditional CMOS technology, while the third uses a newer BiCMOS technology. Test results are presented for hardware implementations of two of the models. The implications of the nonidealities inherent in these neuron circuits are examined, and methods of minimizing their effects are presented. It is demonstrated that the well-known backpropagation algorithm for training networks can be derived using an alternate neuron model to compensate for some of these nonidealities. The effects of precision constraints in hardware implementations are examined in the context of a hybrid architecture, and minimum precision requirements for effective learning are established for certain kinds of problems. A learning algorithm, designed to perform optimally when implemented in hardware, is introduced and verified with simulation data. This algorithm uses a perturbation method to implement gradient-descent learning, and to allow much simpler hardware than would be required by an implementation of standard backpropagation. A dynamic gain-adaption algorithm is used to maximize the effective resolution of the bounded weights which accompany any physical implementation. The use of the infinity-norm error measure facilitates the measurement of network error with simple hardware. Evidence is presented that network error information with a wide dynamic range can be coarsely encoded for weight updates without significantly affecting the quality of learning. This encoding method allows digital weight update calculations to be performed without using multipliers. Simulations of the full algorithm show that the quality and characteristics of learning are comparable between this algorithm and the standard backpropagation algorithm.

  2. A coherent VLSI design environment

    NASA Astrophysics Data System (ADS)

    Penfield, P., Jr.

    1986-03-01

    This report covers the period from October 1, 1985 through March 31, 1986. The research discussed here is described in more detail in several published and unpublished reports cited below. The CAD frame Schema has received limited but instructive applications. Connections to remote simulation servers are transparent to the user. More substantial uses are anticipated during the next half year. Waveform bounding results have been extended to ECL technology, and a variety of the results are being applied to an analog application in early vision. Many of the previous results have been transferred to industry and are being used in commercial simulators. Fundamental speed limits of collections of active devices with parasitics have been found. These are independent of how the devices are interconnected. A reliability simulator has been written, and models are being developed for it, to describe three important effects, namely mental migration, hot-electron trapping, and time-dependent dielectric breakdown. Work continues on the fat-tree architecture, and on the efficient realization of various classes of circuits. New results in graph bisection and routing were made during this period. It is now known how to imbed some classes of communications networks in others, for example binary trees in hypercubes.

  3. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  4. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 ?m after thinning down to the nominal thickness of 75 ?m and 50 ?m. The measurement precision is better than 2 um.

  5. Interferometric metrology of wafer nanotopography for advanced CMOS process integration

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

    2001-12-01

    According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

  6. Periodic binary sequence generators: VLSI circuits considerations

    NASA Technical Reports Server (NTRS)

    Perlman, M.

    1984-01-01

    Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

  7. VLSI Design of a Turbo Decoder

    NASA Technical Reports Server (NTRS)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  8. Finite element computation with parallel VLSI

    NASA Technical Reports Server (NTRS)

    Mcgregor, J.; Salama, M.

    1983-01-01

    This paper describes a parallel processing computer consisting of a 16-bit microcomputer as a master processor which controls and coordinates the activities of 8086/8087 VLSI chip set slave processors working in parallel. The hardware is inexpensive and can be flexibly configured and programmed to perform various functions. This makes it a useful research tool for the development of, and experimentation with parallel mathematical algorithms. Application of the hardware to computational tasks involved in the finite element analysis method is demonstrated by the generation and assembly of beam finite element stiffness matrices. A number of possible schemes for the implementation of N-elements on N- or n-processors (N is greater than n) are described, and the speedup factors of their time consumption are determined as a function of the number of available parallel processors.

  9. Analog VLSI neural network integrated circuits

    NASA Technical Reports Server (NTRS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  10. Analog VLSI system for active drag reduction

    SciTech Connect

    Gupta, B.; Goodman, R.; Jiang, F.; Tai, Y.C.; Tung, S.; Ho, C.M.

    1996-10-01

    In today`s cost-conscious air transportation industry, fuel costs are a substantial economic concern. Drag reduction is an important way to reduce costs. Even a 5% reduction in drag translates into estimated savings of millions of dollars in fuel costs. Drawing inspiration from the structure of shark skin, the authors are building a system to reduce drag along a surface. Our analog VLSI system interfaces with microfabricated, constant-temperature shear stress sensors. It detects regions of high shear stress and outputs a control signal to activate a microactuator. We are in the process of verifying the actual drag reduction by controlling microactuators in wind tunnel experiments. We are encouraged that an approach similar to one that biology employs provides a very useful contribution to the problem of drag reduction. 9 refs., 21 figs.

  11. VLSI processors for signal detection in SETI

    NASA Technical Reports Server (NTRS)

    Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

    1989-01-01

    The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

  12. A generalized extraction system for VLSI

    NASA Astrophysics Data System (ADS)

    Dukes, Michael A.; Markham, Frank; Degroat, Joanne E.

    1990-10-01

    A Generalized Extraction System for VLSI (GES, pronounced guess) is described. GES, which is written in Prolog, performs logic extraction from transistor netlists, identification of logic errors within and between components, and generation of VHDL. The input to GES consists of a transistor netlist using format from extract in magic. Logic extraction has been performed, on transistor netlists extracted from design layouts in magic, up to the level of 32-bit adders and 32-bit registers. GES reports typical errors in the construction and interconnection of components. An error-report identifies the component and specifies its location within the magic layout, making it easy to locate the offending circuitry. GES also provides a hierarchical VHDL description of the layout-design that is verified to be free of a large class of design errors.

  13. Augmented reality for wafer prober

    NASA Astrophysics Data System (ADS)

    Gilgenkrantz, Pascal

    2011-03-01

    The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

  14. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers

    NASA Astrophysics Data System (ADS)

    Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

    2009-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

  15. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  16. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

  17. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  18. Development of a monolithic, multi-MEMS microsystem on a chip demonstrating iMEMS{trademark} VLSI technology. R and D status report number 10, January 1--March 31, 1996

    SciTech Connect

    1996-04-17

    This quarter saw the first silicon from the iMEMS{reg_sign} test chip, with complete circuits and beam structures. The wafers looked fine cosmetically and the circuits functioned as designed, but the beams suffered an anomaly that the authors have never seen before. Diagnostic work is under way to sort out the root cause, and other wafers are coming out this quarter to see if it was a one-time anomaly. Work on the process-development front has slowed because of the construction of a dedicated fabrication line for the last-generation process. With the current robust market place for ADI`s business, the existing fabrication line has been operating at 100% capacity. On the device front, great progress has been made by both Berkeley and ADI in the area of gyroscopes. Measurements of close to a degree per second or better have been made for gyros of all three axes and of both single- (linear) and double- (rotary) axis devices. In addition, ADI has designed a gyro that can be packaged in air that very well might meet some of the low-precision needs. Accelerometers of several new formats have been designed and several have been implemented in silicon. First samples of the ADXL 181 designed especially for the fuzing, safe and arming application have been assembled and are in characterization by ADI and others. In addition, 2-axis, Z-axis and digital output designs have been demonstrated. A 3-axis micro-watt accelerometer has been designed and is in fabrication. A 2-axis design for tilt applications is also nearing silicon realization. This portfolio of linear accelerometers, and even angular versions of the same provide, an arsenal of capability for specialized needs as they arise in both commercial and military applications.

  19. A bioinspired collision detection algorithm for VLSI implementation

    NASA Astrophysics Data System (ADS)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  20. Design and implementation of highly parallel pipelined VLSI systems

    NASA Astrophysics Data System (ADS)

    Delange, Alphonsus Anthonius Jozef

    A methodology and its realization as a prototype CAD (Computer Aided Design) system for the design and analysis of complex multiprocessor systems is presented. The design is an iterative process in which the behavioral specifications of the system components are refined into structural descriptions consisting of interconnections and lower level components etc. A model for the representation and analysis of multiprocessor systems at several levels of abstraction and an implementation of a CAD system based on this model are described. A high level design language, an object oriented development kit for tool design, a design data management system, and design and analysis tools such as a high level simulator and graphics design interface which are integrated into the prototype system and graphics interface are described. Procedures for the synthesis of semiregular processor arrays, and to compute the switching of input/output signals, memory management and control of processor array, and sequencing and segmentation of input/output data streams due to partitioning and clustering of the processor array during the subsequent synthesis steps, are described. The architecture and control of a parallel system is designed and each component mapped to a module or module generator in a symbolic layout library, compacted for design rules of VLSI (Very Large Scale Integration) technology. An example of the design of a processor that is a useful building block for highly parallel pipelined systems in the signal/image processing domains is given.

  1. A VLSI architecture for high performance CABAC encoding

    NASA Astrophysics Data System (ADS)

    Shojania, Hassan; Sudharsanan, Subramania

    2005-07-01

    One key technique for improving the coding e+/-ciency of H.264 video standard is the entropy coder, context- adaptive binary arithmetic coder (CABAC). However the complexity of the encoding process of CABAC is signicantly higher than the table driven entropy encoding schemes such as the Human coding. CABAC is also bit serial and its multi-bit parallelization is extremely di+/-cult. For a high denition video encoder, multi-giga hertz RISC processors will be needed to implement the CABAC encoder. In this paper, we provide an e+/-cient, pipelined VLSI architecture for CABAC encoding along with an analysis of critical issues. The solution encodes a binary symbol every cycle. An FPGA implementation of the proposed scheme capable of 104 Mbps encoding rate and test results are presented. An ASIC synthesis and simulation for a 0.18 m process technology indicates that the design is capable of encoding 190 million binary symbols per second using an area of 0.35 mm2.

  2. A High Performance VLSI Computer Architecture For Computer Graphics

    NASA Astrophysics Data System (ADS)

    Chin, Chi-Yuan; Lin, Wen-Tai

    1988-10-01

    A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

  3. Automatic inspection of silicon wafers

    NASA Technical Reports Server (NTRS)

    Martin, M.

    1980-01-01

    Laser machine scans wafers for contaminating particles which cause open circuits, short circuits, and other defects in integrated circuits and transfers good wafers to integrated circuit processing equipment. Machine is faster and more accurate than human operator using lightfield/dark field microscope.

  4. High-Speed Wafer Slicer

    NASA Technical Reports Server (NTRS)

    Schmid, F.; Khattak, C. P.; Smith, M. B.

    1982-01-01

    Multiblade cutter slices silicon ingots into solar-cell wafers quickly and with little waste. Speed and blade pressure ensure high wafer-production rate. Lightweight, balanced construction minimizes blade vibration and reduces sideways motion that would otherwise widen kerf and waste silicon.

  5. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  6. A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

    1986-01-01

    A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

  7. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Hsu, I. S.; Chang, J. J.; Shyu, H. C.; Reed, I. S.

    1986-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.

  8. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    NASA Technical Reports Server (NTRS)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  9. Performance optimization of digital VLSI circuits

    SciTech Connect

    Marple, D.P.

    1987-01-01

    Designers of digital VLSI circuits have virtually no computer tools available for the optimization of circuit performance. Instead, a designer relies extensively on circuit-analysis tools, such as circuit simulation (SPICE) and/or critical-delay-path analysis. A circuit-analysis approach to digital design is very labor-intensive and seldom produces a circuit with optimum area/delay or power/delay trade off. The goal of this research is to provide a synthesis approach to the design of digital circuits by finding the sizes of transistors that optimize circuits by finding the sizes of transistors that optimize circuit performance (delay, area, power). Solutions are found that are optimum for all possible delay paths of a given circuit and not for just a single path. The approach of this research is to formulate the problem of area/delay or power/delay optimization as a nonlinear program. Conditions for optimality are then established using graph theory and Kuhn-Tucker conditions. Finally, the use of augmented-Lagrangian and projected-Lagrangian algorithms are reviewed for the solution of the nonlinear programs. Two computer programs, PLATO and COP, were developed by the author to optimize CMOS PLA's (PLATO) and general CMOS circuits (COP). These tools provably find the globally optimum transistor sizes for a given circuit. Results are presented for PLA's and small- to medium-sized cells.

  10. An electron undulating ring for VLSI lithography

    SciTech Connect

    Tomimasu, T.; Mikado, T.; Noguchi, T.; Sugiyama, S.; Yamazaki, T.

    1985-10-01

    The development of the ETL storage ring ''TERAS'' as an undulating ring has been continued to achieve a wide area exposure of synchrotron radiation (SR) in VLSI lithography. Stable vertical and horizontal undulating motions of stored beams are demonstrated around a horizontal design orbit of TERAS, using two small steering magnets of which one is used for vertical undulating and another for horizontal one. Each steering magnet is inserted into one of the periodic configulation of guide field elements. As one of useful applications of undulaing electron beams, a vertically wide exposure of SR has been demonstrated in the SR lithography. The maximum vertical deviation from the design orbit nCcurs near the steering magnet. The maximum vertical tilt angle of the undulating beam near the nodes is about + or - 2mrad for a steering magnetic field of 50 gauss. Another proposal is for hith-intensity, uniform and wide exposure of SR from a wiggler installed in TERAS, using vertical and horizontal undulating motions of stored beams. A 1.4 m long permanent magnet wiggler has been installed for this purpose in this April.

  11. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  12. On testing VLSI chips for the big Viterbi decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.

    1989-01-01

    A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

  13. System for slicing wafers

    NASA Technical Reports Server (NTRS)

    1982-01-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  14. Wafer Fusion for Integration of Semiconductor Materials and Devices

    SciTech Connect

    Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

    1999-05-01

    We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

  15. NASA Space Engineering Research Center for VLSI systems design

    NASA Technical Reports Server (NTRS)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  16. Wafer Replacement Cluster Tool (Presentation);

    SciTech Connect

    Branz, H. M.

    2008-04-01

    This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

  17. Wafer handling and placement tool

    DOEpatents

    Witherspoon, Linda L. (22 Cottonwood La., Los Lunas, NM 87031)

    1988-01-05

    A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

  18. Spinner For Etching Of Semiconductor Wafers

    NASA Technical Reports Server (NTRS)

    Lombardi, Frank

    1989-01-01

    Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

  19. Wafer level test solutions for IR sensors

    NASA Astrophysics Data System (ADS)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  20. Role for optical signal and image processing in the VLSI era

    NASA Astrophysics Data System (ADS)

    Roberts, J. B. G.

    1986-02-01

    Likely areas for applications of optical signal processing (OSP) in the near-term, which is now dominated by VLSI technologies, are discussed. VLSI devices have the attributes of arbitrary accuracy, predictability of performance and versatility. The devices can be manufactured before extensive definition of their possible applications. Optical devices are analog and suffer inflexibility of application, variations in performance due to, e.g., temperature, and limited dynamic range. Optical devices can carry extremely high bandwidths at ultra-high speeds, significant factors in remote sensing and parallel processing applications. The range of applications for Fourier optics is limited by the capabilities of peripheral systems, e.g., the ability to adjust the FOV for SAR systems and computer memory storage. Although the range of OSP applications is limited by a lack of suitable peripherals, digital devices are approaching maximum complexity, size and processing speeds. It is speculated that the first nominal application of OSP devices will be where optical inputs are specified and where an acousto-optic analyzer are necessary. The usage of the technology will, in any case, be limited for at least a decade.

  1. Warpage Measurement of Thin Wafers by Reflectometry

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moir Methods and Novel Techniques in Reflection Moir, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

  2. Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

    NASA Astrophysics Data System (ADS)

    Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

    2015-04-01

    In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 A/m for n-type 149 A/m for p-type), low off-leakage current (28.1 pA/m for n-type and 79.6 pA/m for p-type), and excellent on-off ratio (1 107 for n-type and 2 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 m2/Hz for n-type and 10-12-10-10 m2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

  3. Wafer-level optics enables low cost camera phones

    NASA Astrophysics Data System (ADS)

    Dagan, Yehudit

    2009-02-01

    To meet market demand and enable the proliferation of camera phones for developing countries, manufacturers must be able to meet requirements for camera modules that are reduced in size and cost. Conventional camera-module technology is heading towards an asymptote, where the optics no longer scale with the required size, performance, and cost. Using wafer-level techniques and reflow compatible materials to manufacture the optics together with wafer-level chip scale packaging (WLCSP) of image sensors enables manufacturing of smaller-size, lower-cost, reflow-compatible camera modules. Focusing on VGA resolution, this paper will present a comparison between optical modules that were built using conventional technology and wafer-level technology.

  4. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  5. Hybrid VLSI/QCA Architecture for Computing FFTs

    NASA Technical Reports Server (NTRS)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  6. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  7. Single-Chip VLSI Reed-Solomon Decoder

    NASA Technical Reports Server (NTRS)

    Shao, Howard M.; Truong, Trieu-Kie; Hsu, In-Shek; Deutsch, Leslie J.

    1988-01-01

    Efficient utilization of computing elements reduces size while preserving throughput. VLSI architecture is pipeline Reed-Solomon decoder for correction of errors and erasures. Uses transform circuit to compute syndrome polynomial. Erasure information enters decoder as binary sequence. Applied to variety of digital communications involving error-correcting RS codes.

  8. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    ERIC Educational Resources Information Center

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used

  9. A special purpose silicon compiler for designing supercomputing VLSI systems

    NASA Technical Reports Server (NTRS)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  10. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  11. Wafer sampling by regression for systematic wafer variation detection

    NASA Astrophysics Data System (ADS)

    Moon, Byungsool; McNames, James; Whitefield, Bruce; Rudolph, Paul; Zola, Jeff

    2005-05-01

    In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an expensive and slow process. The number of sites measured on a wafer must be minimized while still providing sufficient data to monitor the process. We address two key challenges to effective wafer-level monitoring. The first challenge is to select a small sample of inspection sites that maximize detection sensitivity to the patterns of interest, while minimizing the confounding effects of other types of wafer variation. The second challenge is to develop a detection algorithm that maximizes sensitivity to the patterns of interest without exceeding a user-specified false positive rate. We propose new sampling and detection methods. Both methods are based on a linear regression model with distinct and orthogonal components. The model is flexible enough to include many types of systematic spatial variation across the wafer. Because the components are orthogonal, the degree of each type of variation can be estimated and detected independently with very few samples. A formal hypothesis test can then be used to determine whether specific patterns are present. This approach enables one to determine the sensitivity of a sample plan to patterns of interest and the minimum number of measurements necessary to adequately monitor the process.

  12. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L. (Denver, CO)

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  13. A multi coding technique to reduce transition activity in VLSI circuits

    NASA Astrophysics Data System (ADS)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  14. On VLSI Design of Rank-Order Filtering using DCRAM Architecture

    PubMed Central

    Lin, Meng-Chun; Dung, Lan-Rong

    2009-01-01

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 ?m 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 427.7?m2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply. PMID:19865599

  15. The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Shao, H. M.; Deutsch, L. J.

    1987-01-01

    The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.

  16. BCB wafer bonding for microfluidics

    NASA Astrophysics Data System (ADS)

    Hwang, Taejoo; Popa, Dan; Sin, Jeongsik; Stephanou, Harry E.; Leonard, Eric M.

    2004-01-01

    In this paper we show that BCB wafer bonding, combined with deep-reactive-ion-etching (DRIE) for silicon, and HF etching for FOTURAN glass are viable methods to fabricate three-dimensional microfluidics. The BCB film is patterned by dry-etching technique with a photoresist mask and the target wafer is then bulk-micromachined together with the BCB mask. The two micromachined wafers are then bonded together under vacuum or nitrogen gas environment, at low temperature. Silicon-glass, silicon-silicon and glass-glass are all possible bonding pairs using thermocompressive bonding with BCB. It was found that hard-cured BCB bonding is more suitable for microfluidic channel fabrications than soft-cured BCB bonding, due to adhesive overflows in microfluidic channels and delamination during wet etching.

  17. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  18. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R. (Berkeley, CA)

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  19. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  20. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  1. Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001

    SciTech Connect

    Beetz, C.P.; Steinbeck, J.; Hsueh, K.L.

    2001-03-31

    The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.

  2. Allowable silicon wafer thickness versus diameter for ingot rotation ID wafering

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1982-01-01

    Inner diameter (ID) wafering of ingot rotation reduce the ID saw blade diameter was investigated. The blade thickness can be reduced, resulting in minimal kerf loss. However, significant breakage of wafers occurs during the rotation wafering as the wafer thickness decreases. Fracture mechanics was used to develop an equation relating wafer thickness, diameter and fracture behavior at the point of fracture by using a model of a wafer, supported by a center column and subjected to a cantilever force. It is indicated that the minimum allowable wafer thickness does not increase appreciably with increasing wafer diameter and that fracture through the thickness rather than through the center supporting column limits the minimum allowable wafer thickness. It is suggested that the minimum allowable wafer thickness can be reduced by using a vacuum chuck on the wafer surface to enhance cleavage fracture of the center core and by using 111 ingots.

  3. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  4. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  5. Characterization of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  6. Fault model development for fault tolerant VLSI design

    NASA Astrophysics Data System (ADS)

    Hartmann, C. R.; Lala, P. K.; Ali, A. M.; Visweswaran, G. S.; Ganguly, S.

    1988-05-01

    Fault models provide systematic and precise representations of physical defects in microcircuits in a form suitable for simulation and test generation. The current difficulty in testing VLSI circuits can be attributed to the tremendous increase in design complexity and the inappropriateness of traditional stuck-at fault models. This report develops fault models for three different types of common defects that are not accurately represented by the stuck-at fault model. The faults examined in this report are: bridging faults, transistor stuck-open faults, and transient faults caused by alpha particle radiation. A generalized fault model could not be developed for the three fault types. However, microcircuit behavior and fault detection strategies are described for the bridging, transistor stuck-open, and transient (alpha particle strike) faults. The results of this study can be applied to the simulation and analysis of faults in fault tolerant VLSI circuits.

  7. Design and performance of VLSI based parallel multiplier

    SciTech Connect

    Agrawal, D.P.; Pathak, G.C.; Swain, N.K.; Agrawal, B.K.

    1983-01-01

    The VLSI design and layout of a (log /sup 2/n) time n-bit binary parallel multiplier for two unsigned operands is introduced. The proposed design consists of partitioning the multiplier and multiplicand bits into four groups of n/4 bits each and then reducing the matrix of sixteen product terms using three to two parallel counters and a brent-kung (log n) time parallel adder. Area-time performance of the present scheme has been compared with the existing schemes for parallel multipliers. Regular and recursive design of the multiplier is shown to be suitable for vlsi implementation and an improved table lookup multiplier has been used to form the basis of the recursive design scheme. 17 references.

  8. Noise-margin limitations on gallium-arsenide VLSI

    NASA Technical Reports Server (NTRS)

    Long, Stephen I.; Sundaram, Mani

    1988-01-01

    Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

  9. VLSI architectures for the new (T,L) algorithm

    NASA Astrophysics Data System (ADS)

    Bengough, P. A.; Simmons, S. J.

    Trellis coding techniques have seen much use in error correction codes for space and satellite applications. When long sequences of data are encoded, the number of possible paths through the trellis becomes great and a trellis search algorithm must be used to determine the path that best matches the received data sequence. The (T,L) algorithm is a new reduced complexity trellis search algorithm, applicable to data sequence estimation in digital communications, that adapts to changing channel conditions. Its simplicity and inherent parallelism suits it well for very large scale integration (VLSI) implementation. A number of alternative VLSI architectures are presented which can be used to realize this algorithm. While one uses a simple nonsorting structure, two other sorting designs based on parallel insertion and weavesorting algorithms are proposed. The area-time performance of the various architectures is compared.

  10. NREL Core Program; Session: Wafer Silicon (Presentation)

    SciTech Connect

    Wang, Q.

    2008-04-01

    This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

  11. A VLSI design of a pipeline Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

    1985-01-01

    A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

  12. A VLSI architecture of a binary updown counter

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Hsu, I. S.; Truong, T. K.

    1987-01-01

    A pipeline binary updown counter with many bits is developed which can be used in a variety of applications. One such application includes the design of a digital correlator for very long baseline interferometry (VLBI). The advantage of the presently conceived approach over the previous techniques is that the number of logic operations involved in the design of the binary updown counter can be reduced substantially. The architecture design using these methods is regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  13. Drift chamber tracking with a VLSI neural network

    SciTech Connect

    Lindsey, C.S.; Denby, B.; Haggerty, H. ); Johns, K. . Dept. of Physics)

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers.

  14. Drift chamber tracking with a VLSI neural network

    SciTech Connect

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We`ll briefly discuss possible applications in high energy physics detector triggers.

  15. A VLSI single chip 8-bit finite field multiplier

    NASA Technical Reports Server (NTRS)

    Deutsch, L. J.; Shao, H. M.; Hsu, I. S.; Truong, T. K.

    1985-01-01

    A Very Large Scale Integration (VLSI) architecture and layout for an 8-bit finite field multiplier is described. The algorithm used in this design was developed by Massey and Omura. A normal basis representation of finite field elements is used to reduce the multiplication complexity. It is shown that a drastic improvement was achieved in this design. This multiplier will be used intensively in the implementation of an 8-bit Reed-Solomon decoder and in many other related projects.

  16. High-accuracy inspection of defects and profile of wafers by phase measuring deflectometry

    NASA Astrophysics Data System (ADS)

    Yue, Huimin; Wu, Yuxiang; Zhao, Biyu; Ou, Zhonghua; Liu, Yong

    2014-09-01

    The demands of the less-defective and high-flatness wafers are urgent in many wafer based technologies ranging from micro-electronics to the current photovoltaic industry. As the wafer becomes thinner and larger to cope with the advances in those industries, there is an increasing possibility of the emerging of crack and warp on the wafer surface. High-accuracy inspection of defects and profile are thus necessary to ensure the reliability of device. Phase measuring deflectometry(PMD) is a fast, cost-effective and high accuracy measurement technology which has been developed in recent years. As a slope measurement technology, PMD possesses a high sensitivity. Very small slope variation will lead to a large variation of the phase. PMD is very possible to have a good performance in the wafer inspection. In this paper, the requirements of the wafer inspection in the industries are discussed, and compatibility of PMD and those requirements is analyzed. In the experimental work, PMD gets the slope information of the wafer surface directly. The curvature or height information can be acquired simply by the derivation or integral of the slope. PMD is proved to make a superior result in high-precision defect detecting and shape measurement of wafer by the analysis of experiment results.

  17. ULYSSES - an expert-system-based VLSI design environment

    SciTech Connect

    Bushnell, M.L.

    1987-01-01

    Ulysses is a VLSI computer-aided design (CAD) environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation (DA) system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment employs artificial intelligence techniques, functions as an interactive expert system, and interprets descriptions of design tasks encoded in the scripts language. An integrated-circuit silicon compilation task is presented as an example of the ability of Ulysses to automatically execute CAD tools to solve a problem where inferencing is required to obtain a viable VLSI layout. The inferencing mechanism, in the form of a controlled production system, allows Ulysses to recover when routing channel congestion or over-constrained leaf-cell boundary conditions make it impossible for CAD tools to complete layouts. Also, Ulysses allows the designer to intervene while design activities are being carried out. Consistency-maintenance rules encoded in the scripts language enforce geometric floor-plan consistency when CAD tools fail and when the designer makes adjustments to a VLSI chip layout.

  18. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  19. On-wafer magnetic resonance of magnetite nanoparticles

    NASA Astrophysics Data System (ADS)

    Little, Charles A. E.; Russek, Stephen E.; Booth, James C.; Kabos, Pavel; Usselman, Robert J.

    2015-11-01

    Magnetic resonance measurements of ferumoxytol and TEMPO were made using an on-wafer transmission line technique with a vector network analyzer, allowing for broadband measurements of small sample volumes (4 nL) and small numbers of spins (1 nmol). On-wafer resonance measurements were compared with standard single-frequency cavity-based electron paramagnetic resonance (EPR) measurements using a new power conservation approach and the results show similar line shape. On-wafer magnetic resonance measurements using integrated microfluidics and microwave technology can significantly reduce the cost and sample volumes required for EPR spectral analysis and allow for integration of EPR with existing lab-on-a-chip processing and characterization techniques for point-of-care medical diagnostic applications.

  20. Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards. [Very Large Scale Integration (VLSI)

    SciTech Connect

    Pin, F.G.; Watanabe, Y.

    1992-01-01

    This paper discusses the sensor-based driving of a car in a-priori unknown environments using human-like'' reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver's aid using the new fuzzy inferencing VLSI hardware and human-like'' reasoning schemes.

  1. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    NASA Astrophysics Data System (ADS)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2015-02-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  2. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    PubMed

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-01-01

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

  3. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    PubMed Central

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-01-01

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

  4. Impact of VLSI/VHSIC on satellite on-board signal processing

    NASA Technical Reports Server (NTRS)

    Aanstoos, J. V.; Ruedger, W. H.; Snyder, W. E.; Kelly, W. L.

    1981-01-01

    Forecasted improvements in IC fabrication techniques, such as the use of X-ray lithography, are expected to yield submicron circuit feature sizes within the decade of the 1980s. As dimensions decrease, reliability, cost, speed, power consumption and density improvements will be realized which have a significant impact on the capabilities of onboard spacecraft signal processing functions. This will in turn result in increases of the intelligence that may be deployed on spaceborne remote sensing platforms. Among programs oriented toward such goals are the silicon-based Very High Speed Integrated Circuit (VHSIC) researches sponsored by the U.S. Department of Defense, and efforts toward the development of GaAs devices which will compete with silicon VLSI technology for future applications. GaAs has an electron mobility which is five to six times that of silicon, and promises commensurate computation speed increases under low field conditions.

  5. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-01-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  6. Deposition uniformity inspection in IC wafer surface

    NASA Astrophysics Data System (ADS)

    Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

    2014-03-01

    This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

  7. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  8. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    ERIC Educational Resources Information Center

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.

  9. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    ERIC Educational Resources Information Center

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  10. A VLSI Reed-Solomon decoder architecture for concatenate-coded space and spread spectrum communications

    NASA Technical Reports Server (NTRS)

    Liu, K. Y.

    1983-01-01

    In this paper, a VLSI Reed-Solomon (RS) decoder architecture for concatenate-coded space and spread spectrum communications, is presented. The known decoding procedures for RS codes are exploited and modified to obtain a repetitive and recursive decoding technique which is suitable for VLSI implementation and pipeline processing.

  11. Ultrathin silicon wafer bonding: Physics and applications

    NASA Astrophysics Data System (ADS)

    Beggans, Michael Howard

    Ultrathin silicon wafer bonding is an emerging process that simplifies device fabrication, reduces manufacturing costs, increases yield, and allows the realization of novel devices. Ultrathin silicon wafers are between 3 and 200 microns thick with all the same properties of the thicker silicon wafers (greater than 300 microns) normally used by the semiconductor electronics industry. Wafer bonding is one technique by which multiple layers are formed. In this thesis, the history and practice of wafer bonding is described and applied to the manufacture of microelectomechanical systems (MEMS) devices with layer thickness on the scale of microns. Handling and processing problems specific to ultrathin silicon wafers and their bonding are addressed and solved. A model that predicts the conformal nature of these flexible silicon wafers and its impact on bonding is developed in terms of a relatively new description of surface quality, the Power Spectral Density (PSD). A process for reducing surface roughness of silicon is elucidated and a model of this process is described. A method of detecting particle contamination in chemical baths and other processes using wafer bonding is detailed. A final section highlights some recent work that has used ultrathin silicon wafer bonding to fabricate MEMS devices that have reduced existing design complexity and made possible novel, and otherwise difficult to produce, sensors. A new fabrication process that can reduce the required time for "proof-of-principle" devices using ultrathin silicon wafers is also described.

  12. High performance LWIR microbolometer with Si/SiGe quantum well thermistor and wafer level packaging

    NASA Astrophysics Data System (ADS)

    Roer, Audun; Lapadatu, Adriana; Bring, Martin; Wolla, Erik; Hohler, Erling; Kittilsland, Gjermund

    2011-11-01

    An uncooled microbolometer with peak responsivity in the long wave infrared region of the electromagnetic radiation is developed at Sensonor Technologies. It is a 384 x 288 focal plane array with a pixel pitch of 25?m, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The high sensitivity (TCR) and low 1/f noise are the main performance characteristics of the product. The frame rate is maximum 60Hz and the output interface is digital (LVDS). The quantum well thermistor material is transferred to the read-out integrated circuit (ROIC) by direct wafer bonding. The ROIC wafer containing the released pixels is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. The resulting wafer stack is mounted in a standard ceramic package. In this paper the architecture of the pixels and the ROIC, the wafer packaging and the electro-optical measurement results are presented.

  13. Wafer CD variation for random units of track and polarization

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

    2012-03-01

    After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

  14. Accurate surface profilometry of ultrathin wafers

    NASA Astrophysics Data System (ADS)

    Weeks, A. E.; Litwin, D.; Galas, J.; Surma, B.; Piatkowski, B.; MacLaren, D. A.; Allison, W.

    2007-09-01

    Geometric characterization of 50 mm diameter, 50 m thick single-crystal Si(1 1 1) wafers has been performed using complementary methods: industry-standard capacitance measurements of warp and total thickness variation (TTV), and a technique we term scanned chromatic confocal profilometry (SCCP). We compare the measurements made by the two techniques and demonstrate the limitations of capacitance measurements when applied to ultrathin wafers. The two-dimensional SCCP measurements are shown to enhance the description of wafer thickness variations beyond that generated by the standard test method. We discuss a Fourier transform-based analysis and show it to be useful in wafer quality assessment. Adding a summary of spatial frequencies in a wafer's thickness map to the conventional measures of warp and TTV provides a more complete summary of the salient features of a wafer's geometry.

  15. A VLSI R = 1/2, K = 7 Viterbi decoder

    NASA Astrophysics Data System (ADS)

    Cain, J. B.; Kriete, R. A.

    Convolutional coding with Viterbi decoding has become a very important component in many communication systems. Specifically, the R = 1/2, K = 7 machine has become a de facto standard in many applications because of its high coding gain (5.0 dB at Pb = 0.00001 with PSK) relative to implementation complexity. In this paper a description is given of the design and implementation of the fastest known (10 Mb/s) single-chip design of this machine. It is implemented in CMOS VLSI. Naturally, the availability of such a chip will greatly increase the application of this technique in communication systems.

  16. Image and Video Compression with VLSI Neural Networks

    NASA Technical Reports Server (NTRS)

    Fang, W.; Sheu, B.

    1993-01-01

    An advanced motion-compensated predictive video compression system based on artificial neural networks has been developed to effectively eliminate the temporal and spatial redundancy of video image sequences and thus reduce the bandwidth and storage required for the transmission and recording of the video signal. The VLSI neuroprocessor for high-speed high-ratio image compression based upon a self-organization network and the conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results.

  17. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    NASA Technical Reports Server (NTRS)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  18. Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis

    SciTech Connect

    Tobin, K.W.

    2003-05-22

    This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

  19. Wafer Resection of the Distal Ulna.

    PubMed

    Griska, Adam; Feldon, Paul

    2015-11-01

    The wafer procedure is an effective treatment for ulnar impaction syndrome, which decompresses the ulnocarpal junction through a limited open or arthroscopic approach. In comparison with other common decompressive procedures, the wafer procedure does not require bone healing or internal fixation and also provides excellent exposure of the proximal surface of the triangular fibrocartilage complex. Results of the wafer procedure have been good and few complications have been reported. PMID:26518323

  20. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  1. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    PubMed

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25?m, 65?nm, and 180?nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475?MHz. PMID:26558289

  2. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    PubMed Central

    Devi, T. Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz. PMID:26558289

  3. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOEpatents

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  4. Stress Voiding During Wafer Processing

    SciTech Connect

    Yost, F.G.

    1999-03-01

    Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

  5. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2010-03-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  6. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2009-12-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  7. Full wafer metrology for chemically graded thin films

    NASA Astrophysics Data System (ADS)

    Jobin, Marc; Jotterand, Stphane; Pellodi, Cdric; dos Santos, Sergio; Sandu, Cosmin Silviu; Wagner, Estelle; Benvenuti, Giacomo

    2012-04-01

    Combinatorial CBVD (Chemical Beam Vapor Deposition) is a thin film deposition technology which has the ability to produce multi-element thin films with large controlled composition spread gradients. If functional characterizations can be carried out systematically and rapidly on such graded films over full wafers, they enable to identify precisely the best film composition for a given application, and CBVD then easily allows for the deposition of the optimized film homogeneously on large wafers. In this article, we demonstrate the efficiency of such a process development based on the optimization of new Transparent Conductive Oxide thin films (TCO) of few % Nb doped TiO2. We have developed a full wafer metrology instrument which maps the optical thickness and the sheet resistance with a lateral resolution below 400um. We discuss the performance of various algorithms to extract the optical thickness from the white light reflectance measurement in the case of very small thickness. The sheet resistance is measured with an array of four AFM-like conductive cantilevers, allowing accurate sheet resistance (R) measurement where the standard tungsten four probes destroy porous thin oxide films. Application of these measurements to several Nb doped TiO2 films deposited on 4" wafer by CBVD is presented.

  8. A reclaiming process for solar cell silicon wafer surfaces.

    PubMed

    Pa, P S

    2011-01-01

    The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost. PMID:21446525

  9. MUSE - a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer-scale integration. Technical report

    SciTech Connect

    Rader, C.M.; Allen, D.L.; gLASCO , D.B.; Woodward, C.E.

    1990-05-18

    This report describes an architecture for a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which we call MUSE (Matrix Update Systolic Experiment), and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 decibel of signal-to-noise improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI (Very Large Scale Integration). The complete design of such a wafer is described.

  10. Across-wafer CD uniformity control through lithography and etch process: experimental verification

    NASA Astrophysics Data System (ADS)

    Zhang, Qiaolin; Tang, Cherry; Cain, Jason; Hui, Angela; Hsieh, Tony; Maccrae, Nick; Singh, Bhanwar; Poolla, Kameshwar; Spanos, Costas J.

    2007-03-01

    Process variation on lot-to-lot and wafer-to-wafer level has been well addressed using R2R control in advanced process control, however, to tackle the ever increasing die-to-die (i.e. across-wafer) level process variation at the 65nm technology node and beyond, the process control must be extended into finer domain: across-wafer level. A novel model based process control approach [2] was proposed to reduce the critical dimension (CD) variation on across-wafer level. The central idea of the proposed approach is to compensate for upstream and downstream systematic CD variation by adjusting the across-wafer Post-Exposure Bake (PEB) temperature profile of a multi-zone bake plate. A temperature-to-offset model relating the PEB temperature profile of multi-zone bake plate to its heater zone offsets was constructed experimentally using wireless temperature sensors from OnWafer Technologies. The baseline post-etch CD signature and plasma etch bias signature were extracted to characterize the lithography and etch processes. And a post-etch CD variation reduction of 40% was realized in the verification experiment, which validated the efficacy of the proposed approach.

  11. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  12. New VLSI complexity results for threshold gate comparison

    SciTech Connect

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  13. Designing DWDM multiplexers on SiON wafers

    NASA Astrophysics Data System (ADS)

    Dragnea, Laurentiu

    2010-11-01

    I propose an integrated multiplexer/demultiplexer that use a concave blazed diffraction grating on SiON wafer. The paper presents a technology that overcome existing issues regarding implementation of such a microoptic device. Two types of similar integrated systems were developed but both of them have not minimized chromatic, astigmatism and spherical aberrations. Both systems use gold coating for vertical walls of diffraction grating that has reflection index lower than aluminum for wavelength used. Technology proposed in this paper minimizes the chromatic, astigmatism and spherical aberrations. Also is used aluminum for coating of vertical walls of diffraction grating. SiON wafer is etched with Argon plasma through photoresist mask with thickness of 0,8 ?m for grating configuration allowing reusing of the photoresist in next stage of coating. This makes possible that coating through liftoff to be aligned to vertical walls of concave diffraction grating, eliminating positioning errors due to coating mask.

  14. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  15. Preparation and Characterization of PZT Wafers

    NASA Astrophysics Data System (ADS)

    Seal, A.; Rao, B. S. S. Chandra; Kamath, S. V.; Sen, A.; Maiti, H. S.

    2008-07-01

    Piezoelectric materials have recently attracted a lot of attention for ultrasonic structural health monitoring (shm) in aerospace, defence and civilian sectors, where they can act as both actuators and sensors. Incidentally, piezoelectric materials in the form of wafers (pwas-piezoelectric wafer active sensor, approx. 5-10 mm square and 0.2-0.3 mm thickness) are inexpensive, non intrusive and non-resonant wide band devices that can be surface-mounted on existing structures, inserted between the layers of lap joints or embedded inside composite materials. The material of choice for piezoelectric wafers is lead zirconate titanate (PZT) of composition close to morphotropic phase boundary [pb(zr0.52 ti0.48)o3]. However, an excess pbo is normally added to pzt as a densification aid and also to make up for the lead loss during high temperature sintering. Hence, it is of paramount importance to know how the shift of the lead content from the morphotropic composition affects the piezoelectric and mechanical properties of the sintered wafers, keeping in view the importance of mechanical properties of wafers in shm. In the present study, we observed that with the increase in the lead content of the sintered wafers, the dielectric and piezoelectric constants decreased. However, the elastic modulus, hardness and fracture toughness of the wafers increased with increasing lead content in the composition. Hence, the lead content in the sintered wafers should be optimized to get acceptable piezoelectric and mechanical

  16. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices

    NASA Astrophysics Data System (ADS)

    Kim, Dae Jong; Yoo, Hyung Won; Kim, Chul Hong; Lee, Hak Kwon; Kim, Sung Su; Bae, Koon Ho; Spielberg, Hedvi; Lee, Yun Ho; Levi, Shimon; Bustan, Yariv; Rozentsvige, Moshe

    2010-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

  17. Stress measurement of thin wafer using reflection grating method

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand K.

    2010-08-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress measurement. The system was developed from our earlier works on Computer Aided Moir Methods and Novel Techniques in Reflection Moir, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this research, the system is calibrated with reference to stress measurement equipment from KLA-Tencor. Some initial results based on a joint project with Infineon Technologies are re-examined. The stress distribution of the wafers are derived with the aid of Stoney's equation. Finally, the results from our proposed system are compared and contrasted with data obtained from KLA-Tencor equipment.

  18. Methane production using resin-wafer electrodeionization

    SciTech Connect

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  19. A comparison of wafer resistivity probing tools

    NASA Astrophysics Data System (ADS)

    Larson, L. A.

    1989-02-01

    A comparative study of four-point probing systems has been carried out by measuring a large group of wafers. The wafers were produced by multiple donors for a Greater Silicon Valley Implant Users' Group round-robin experiment on dosing accuracy. Three implant conditions were represented in 139 wafers. These wafers were all measured by five vendors in this study. This data has been analyzed as scatterplots by paired vendors which has produced several interesting results. The general spread between the database means runs about 1% for systems using configuration switching. Single configuration measurements were somewhat worse. It is noted that each particular system had trouble probing different wafers. This implies that the method of probing is important even for the routine measurement of "easy" layers.

  20. CDU improvement with wafer warpage control oven for high-volume manufacturing

    NASA Astrophysics Data System (ADS)

    Tomita, T.; Weichert, H.; Hornig, S.; Trepte, S.; Shite, H.; Uemura, R.; Kitano, J.

    2009-03-01

    Immersion lithography has been developed for 45nm technology node generation during the last several years. Currently, IC manufacturers are moving to high volume production using immersion lithography. Due to the demand of IC manufactures, as the critical dimension (CD) target size is shrinking, there are more stringent requirements for CD control. Post Exposure Bake (PEB) process, which is the polymer de-protection process after exposure, is one of the important processes to control the CD in the 193nm immersion lithography cluster. Because of the importance of the PEB process for CD uniformity, accurate temperature control is a high priority. Tokyo Electron LTD (TEL) has been studying the temperature control of PEB plates. From our investigation, total thermal history during the PEB process is a key point for controlling intra wafer and inter wafer CD [1]. Further, production wafers are usually warped, which leads to a nonuniform thermal energy distribution during the PEB process. So, it is necessary to correct wafer warpage during the baking process in order to achieve accurate CD control on production wafers. TEL has developed a new PEB plate for 45nm technology node mass production, which is able to correct wafer warpage. The new PEB plate succeeded in controlling the wafer temperature on production wafers using its warpage control function. In this work, we evaluated CD process capability using the wafer warpage control PEB plate, which is mounted on a CLEAN TRACKTM LITHIUS ProTM-i (TEL) linked with the latest immersion exposure tool. The evaluation was performed together with an IC manufacturer on their 45nm production substrates in order to determine the true performance in production.

  1. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

  2. Parallel VLSI architecture emulation and the organization of APSA/MPP

    NASA Technical Reports Server (NTRS)

    Odonnell, John T.

    1987-01-01

    The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.

  3. The VLSI design of a single chip Reed-Solomon encoder

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Deutsch, L. J.; Reed, I. S.

    1982-01-01

    A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

  4. Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

    NASA Technical Reports Server (NTRS)

    Aanstoos, J. V.; Snyder, W. E.

    1981-01-01

    Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

  5. Efficient VLSI architecture for training radial basis function networks.

    PubMed

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  6. A laser plotting system for VLSI chip layouts

    NASA Technical Reports Server (NTRS)

    Deutsch, L. J.; Harding, J. A.

    1985-01-01

    One of the most time consuming facets of custom Very Large Scale Integration (VLSI) design is obtaining hardcopy plots of the mask geometries of cells and chips. The traditional method of generating these plots is to use a multicolor pen plotter. Pen plotters are inherently slow and the plotting speed increases linearly with the number of edges that must be plotted. A moderate custom chip design at the Jet Propulsion Laboratory (JPL) now consists of more than 200,000 such edges and can take as much as eight hours to plot using a pen plotter. Software is described that was written at JPL to produce similar plots using a laser printer. It is shown that, for rather small layouts, the laser printer can provide nearly instantaneous turnaround. For moderate to large chip designs, the laser printer provides a factor of five or more improvement is speed over pen plotting.

  7. Aspects of full-custom VLSI microprocessor design and implementation

    SciTech Connect

    Lee, Daebum.

    1989-01-01

    There is a broad spectrum of design styles that have proven successful for the construction of VLSI circuits and systems. Semi-custom to full-custom design styles offer a wide range of resulting performance, expected turn-around time, and required design effort. Implementation alternatives, such as replacing dynamic memory for static memory to implement a denser on-chip memory, also exist at all levels of design hierarchy. To make the best use of scarce resources on a single chip microprocessor and to make the emerging CAD tools truly useful, alternatives in the implementation of a microprocessor must be carefully evaluated. The research reported in this thesis focuses on issues concerning these alternatives, especially in the areas of on-chip memory design and automated control logic design.

  8. Opto-VLSI-based reconfigurable photonic RF filter

    NASA Astrophysics Data System (ADS)

    Xiao, Feng; Shen, Mingya; Juswardy, Budi; Alameh, Kamal

    2009-08-01

    Radio frequency (RF) signal processors based on photonics have several advantages, such as broadband capability, immunity to electromagnetic interference, flexibility, and light weight in comparison to all-electronics RF filters. It still requires innovative research and development to achieve high-resolution reconfigurable photonic RF signal processors featuring high selectivity, resolution, wide tunability, and fast reconfigurability. In this paper, we propose and experimentally demonstrate the concept of a reconfigurable photonic RF filter structure integrating an Amplified Spontaneous Emission (ASE) source, an Opto-VLSI processor that generates arbitrary phase-only steering and multicasting holograms for wavelength selection and attenuation, arrayed waveguide gratings (AWGs) for waveband multiplexing and demultiplexing, high-dispersion fibres for RF delay synthesis, and a balanced photodetector for generating positive and negative processor weights. Independent control of the weights of a reconfigurable photonic RF filter is experimentally demonstrated.

  9. VLSI-based Video Event Triggering for Image Data Compression

    NASA Technical Reports Server (NTRS)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  10. VLSI-based video event triggering for image data compression

    NASA Astrophysics Data System (ADS)

    Williams, Glenn L.

    1994-02-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  11. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    NASA Astrophysics Data System (ADS)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  12. Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

    NASA Technical Reports Server (NTRS)

    Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

    1989-01-01

    The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

  13. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    SciTech Connect

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; Castellanos, Sergio; Buonassisi, Tonio

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled to effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.

  14. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    DOE PAGESBeta

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; Castellanos, Sergio; Buonassisi, Tonio

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

  15. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  16. Subsea template leveling wafer and leveling method

    SciTech Connect

    Bunnell, R.L.; Miller, H.W.; Padilla, J.R

    1989-05-16

    This patent describes a monopile supported subsea hydrocarbon production platform having a monopile driven into the sea bottom with a non-level ring girder secured thereto and a machinery supporting template supported by the ring girder. The improvement consists of a leveling wafer between the ring girder and the template, the wafer comprising upper and lower wedge portions, each portion having two non-parallel principal surfaces, the lower principal surface of the upper wedge portion being in face-to-face contact with the upper principal surface of the lower wedge portion so as to form a composite wafer having a taper suitable to level the non-level ring girder, the taper being adjustable by rotating one wedge portion in relation to the other; means between the bottom surface of the template and the upper surface of the upper wedge portion for securing rotational alignment thereof when the template is placed on the leveling wafer.

  17. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  18. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  19. Multiproject wafers: not just for million-dollar mask sets

    NASA Astrophysics Data System (ADS)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task dictates careful consideration of the alternative methods.

  20. Critical dimension control for prevention of wafer-to-wafer and module-to-module difference

    NASA Astrophysics Data System (ADS)

    Deguchi, Masatoshi; Tanaka, Kouichirou; Nagatani, Naohiko; Miyata, Yuichiro; Yamashita, Mitsuo; Minami, Yoshiaki; Matsuyama, Yuji

    2004-05-01

    In recent years, the worldwide semiconductor market has changed drastically, and it is expected that the digital device market will continue to expand towards general consumer electronics and away from the personal computers that have been the core of the market. To accommodate this shift, the new devices will be diversified with improved productivity, higher process yield, and higher precision. Clean Track (LITHIUS) design also has been changed drastically to maintain equal productivity with new high throughput exposure equipment. Design changes include increasing the number of processing chambers by stacking reduced size modules in order to meet high throughput and small footprint requirements. However, this design change concept raises concerns about increased wafer-to-wafer difference (WtW) and module-to-module different (MtM). These variations can result in lower process yield and have a negative effect on design rule shrinkage. The primary causes of WtW difference and MtM difference stem from minute module hardware variations, module height differences, and module parameter adjustment differences during the installation of the tool. Previous Clean Track development focused mainly on reduction of module hardware difference as an approach to reduce WtW variation. However, to further improve lot level uniformity, it is necessary to reduce module height difference factors within the system and module adjustment disparities such as plate temperature calibrations. Highly temperature sensitive ArF processes have necessitated precise manual PEB temperature adjustments. These calibrations are labor intensive and require many field hours to ensure optimal CD uniformity. Therefore, an auto temperature measurement and adjustment tool is developed to eliminate the human error due to manual adjustment and minimize adjustment time. In order to meet demands for design rules shrinkage and increased process uniformity we minimized the WtW and MtM difference by using thermal history adjustment and transfer time control. This method is also used to improve within wafer CD control technology resulting in a more stable process. In this report, we introduce improved features to reduce WtW and MtM variation and their effect on CD uniformity with 193nm (ArF) resist and 248nm (KrF) resist.

  1. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  2. Analyzes Data from Semiconductor Wafers

    Energy Science and Technology Software Center (ESTSC)

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore » of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  3. Commercial production of QWIP wafers by molecular beam epitaxy

    NASA Astrophysics Data System (ADS)

    Fastenau, J. M.; Liu, W. K.; Fang, X. M.; Lubyshev, D. I.; Pelzel, R. I.; Yurasits, T. R.; Stewart, T. R.; Lee, J. H.; Li, S. S.; Tidrow, M. Z.

    2001-06-01

    As the performance of quantum well infrared photodetectors (QWIPs) and QWIP-based imaging systems continues to improve, their demand will undoubtedly grow. This points to the importance of a reliable commercial supplier of semiconductor QWIP material on three inch and, in the near future, four-inch substrates. Molecular beam epitaxy (MBE) is the preferred technique for growing the demanding QWIP structure, as tight control is required over the material composition and layer thickness. We report the current status of MBE-grown GaAs-based QWIP structures in a commercial production environment at IQE. Uniformity data and run-to-run reproducibility on both three-inch and four-inch GaAs substrates are quantified using alloy composition and QW thickness. Initial results on growth technology transfer to a multi-wafer MBE reactor are also presented. High-resolution X-ray diffraction measurements demonstrate GaAs QW thickness variations and AlGaAs barrier compositions changes to be less than 4% and 1% Al, respectively, across four-inch QWIP wafers from both single- and multiple-wafer MBE platforms.

  4. Theory and implementation of a VLSI stray insensitive switched capacitor composite operational amplifier

    NASA Astrophysics Data System (ADS)

    Anestis, Raphael

    1994-06-01

    In this research, improved analog circuits are implemented using VLSI technology by combining the properties of switched capacitors and composite amplifiers. This combined design solves some of the problems of the single operational amplifier (OA) such as finite dc gain, limited bandwidth and lower slew rate, as well as enhancing the overall network passive and active sensitivities. For the first time, a theoretical analysis was conducted in a newly-defined discrete transform domain. The analysis was used to justify the circuits that were first designed in the continuous domain and also debug the initial attempts that were made to build an analog chip. The switched capacitor design is implemented using both the toggle switched inverter and the modified open floating resistor techniques. The composite OA is implemented using the C20A-1 design out of all the CNOA-i possibilities. The two alternatives, together with two single CMOS OA's that were added for comparison reasons, are produced on a single analog/digital microchip. The digital part includes the two-phase non-overlapping clock and programmable switches. It is isolated from the analog part using a low-noise design technique. Sufficient simulations were made to anticipate results in positive and negative finite gain configurations, and also to evaluate the two different techniques. Finally, neural networks applications of the chip are suggested evoking thoughts for the advantages of this promising technique.

  5. An architecture for an analog VLSI neural network for early computer vision processing

    NASA Astrophysics Data System (ADS)

    Haule, D. D.; Malowany, M. E.; Lambidonis, D.; Nemawarkar, S.; Sayegh, S.; Malowany, A. S.

    A two-stage early vision algorithm for curve description in images has been targeted for an analog very large scale integration (VLSI) implementation. Similarity between the processing in the two algorithm stages is exploited, resulting in a single modular chip capable of performing either processing stage. The core of the circuitry is a parallel convolution array modeled after connectionist artificial neural network structures. Pipelining of the image data is applied, using on-chip temporary analog storage to implement neighborhood operations. On-chip long-term analog storage for algorithm parameters is proposed using floating-gate electronically erasable programmable read-only memory technology. The chip, whose approximate transistor count is 15,000, is designed for a complementary metal oxide semiconductor (CMOS) 1.2 micron double-metal process. An effort is made to maintain the transistors in the subthreshold region of operation to decrease power requirements, particularly in the analog convolution array which forms the bulk of the chip and is of concern for scaling up the array size in the future.

  6. VLSI processor with a configurable processing element array for balanced feature extraction in high-resolution images

    NASA Astrophysics Data System (ADS)

    Zhu, Hongbo; Shibata, Tadashi

    2014-01-01

    A VLSI processor employing a configurable processing element array (PEA) is developed for a newly proposed balanced feature extraction algorithm. In the algorithm, the input image is divided into square regions and the number of features is determined by noise effect analysis in each region. Regions of different sizes are used according to the resolutions and contents of input images. Therefore, inside the PEA, processing elements are hierarchically grouped for feature extraction in regions of different sizes. A proof-of-concept chip is fabricated using a 0.18 µm CMOS technology with a 32 × 32 PEA. From measurement results, a speed of 7.5 kfps is achieved for feature extraction in 128 × 128 pixel regions when operating the chip at 45 MHz, and a speed of 55 fps is also achieved for feature extraction in 1920 × 1080 pixel images.

  7. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  8. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    PubMed

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365 faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365 real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems. PMID:25538613

  9. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease

    PubMed Central

    Niu, Chuanxin M.; Nandyala, Sirish K.; Sanger, Terence D.

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365 faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the HodgkinHuxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365 real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems. PMID:25538613

  10. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    SciTech Connect

    Emanuel Sachs Tonio Buonassisi

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the wafer. In addition, it was found to be suitable for growing very large crystals. The equipment used was simple and inexpensive to operate. Reasonable solar cells were fabricated on re-crystallized material.

  11. Wafer and wafer-lug check valves, fourth edition, May 1991

    SciTech Connect

    Not Available

    1991-01-01

    This book covers cast iron, ductile iron, carbon steel alloy steel, and nickel-alloy wafer and wafer-lug, single and dual plate check valves with dimensions that permit installation between flanges complying with ASME B16.1, B16.5, or B16.42; MSS SP-44, or API Standard 605. Such values may be used in petroleum refineries.

  12. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  13. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

  14. A VLSI decomposition of the deBruijn graph

    NASA Technical Reports Server (NTRS)

    Collins, O.; Dolinar, S.; Mceliece, R.; Pollara, F.

    1990-01-01

    A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

  15. VLSI array processor R&D status report

    NASA Astrophysics Data System (ADS)

    Greenwood, E.

    1982-01-01

    Detail design of the Arithmetic Processor Unit (APU) chip has been completed. All cell types (100) have been run through the design rule check (DRC) programs, corrected and verified. DRC runs on the entire chip have been run and all corrections have been made. Fifteen out of eighteen of the chip DRC corrections have been verified. The metal, polysilicon and information data layers of the APU layout is shown. The attached drawings, titled 'VLSI Array Processor Arithmetic Processor Unit Chip Plan' is a detail drawing of the APU Chip Plan. The functional level simulator of the APU has been built and verified using a set of APU diagnostic code. A gate level logic simulation of the APU has been built. The APU breadboard modules have been fabricated and check out has been initiated. The Array Processor Demonstration System (APDS) modules are in the wire-wrap process. The APDS and APU microcode assembler have been built and checked out. The linker and loader for the APDS have also been built.

  16. Advanced technologies for Mission Control Centers

    NASA Technical Reports Server (NTRS)

    Dalton, John T.; Hughes, Peter M.

    1991-01-01

    Advance technologies for Mission Control Centers are presented in the form of the viewgraphs. The following subject areas are covered: technology needs; current technology efforts at GSFC (human-machine interface development, object oriented software development, expert systems, knowledge-based software engineering environments, and high performance VLSI telemetry systems); and test beds.

  17. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  18. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    NASA Technical Reports Server (NTRS)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  19. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  20. Metallic nanowires by full wafer stencil lithography.

    PubMed

    Vazquez-Mena, O; Villanueva, G; Savu, V; Sidler, K; van den Boogaart, M A F; Brugger, J

    2008-11-01

    Aluminum and gold nanowires were fabricated using 100 mm stencil wafers containing nanoslits fabricated with a focused ion beam. The stencils were aligned and the nanowires deposited on a substrate with predefined electrical pads. The morphology and resistivity of the wires were studied. Nanowires down to 70 nm wide and 5 mum long have been achieved showing a resistivity of 10 microOmegacm for Al and 5 microOmegacm for Au and maximum current density of approximately 10(8) A/cm(2). This proves the capability of stencil lithography for the fabrication of metallic nanowires on a full wafer scale. PMID:18817451

  1. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  2. Seasoning of Plasma Reactors: Feedback Control Strategies to Counter Wafer-to-Wafer Drifts

    NASA Astrophysics Data System (ADS)

    Agarwal, Ankur; Kushner, Mark J.

    2007-10-01

    Seasoning of plasma etching reactors is the deposition of materials on wafers and surfaces of the chamber resulting in process or wafer-to-wafer drift in etch rates or uniformity. Feedback control with in situ diagnostics is being investigated to combat this drift. The Virtual Plasma Equipment Model, an implementation of sensors, actuators and control algorithms in the HPEM, was used to investigate real-time and wafer-to-wafer control strategies. The model system is Ar/Cl2 etching of Si in an inductively coupled plasma reactor. The passivation of surfaces in contact with the plasma, including the deposition of etch products, change reactive sticking coefficients and produce etch blocks which in turn affect etch rate. Sputtering of dielectrics may introduce additional etch-block capable species. A PID controller was used to vary the bias voltage in response to an etch rate monitor to enable control of etch rate. We found that control is problematic at high bias voltages where the flux of etch products from the wafer is sufficiently large that plasma properties are affected and redeposition increases etch blocks on the wafer. Multiple sensors-and-actuators may be necessary when sputtering of dielectrics produce additional etch-block species.

  3. Thermal Behavior of Large-Diameter Silicon Wafers during High-Temperature Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Yokoyama, Ichiro; Kang, Kitaek; Takahashi, Nobuaki

    2002-07-01

    Thermal behavior of 200-mm- and 300-mm-diameter Si (100) wafers during high-temperature rapid thermal processing (RTP) in a single wafer furnace (SWF) is investigated as a function of temperature, pressure, process time, wafer handling method and speed. Significant elastic wafer shape deformation was observed during wafer temperature ramp-up. Slip generation was frequently observed in wafers processed above 1050°C. Size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in reducing defect generation during RTP at the given process conditions. Highly reproducible, slip-free RTP results were achieved in 200-mm- and 300-mm-diameter Si (100) wafers processed at 1100°C by optimizing the wafer handling method and speed.

  4. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

    NASA Technical Reports Server (NTRS)

    Shao, Howard M.; Reed, Irving S.

    1988-01-01

    A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

  5. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Deutsch, L. J.; Reed, I. S.

    1987-01-01

    A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

  6. A procedural method for the efficient implementation of full-custom VLSI designs

    NASA Technical Reports Server (NTRS)

    Belk, P.; Hickey, N.

    1987-01-01

    An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system.

  7. A fast lightstripe rangefinding system with smart VLSI sensor

    NASA Technical Reports Server (NTRS)

    Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

    1989-01-01

    The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

  8. Simultaneous dose and focus monitoring on product wafers

    NASA Astrophysics Data System (ADS)

    Eichelberger, Brad J.; Dinu, Berta; Pedut, H.

    2003-05-01

    As the design rules shrink below 130nm it will become increasingly important to monitor and control focus and dose in-line, on product wafers to maintain the ever-decreasing process window. On process layers today, it is not uncommon to see focus related errors equaling between 50-100nm in magnitude. Today these errors go undetected and CD changes are typically corrected by making a dose correction to the exposure tool. However, corrections using dose can lead to significantly smaller process latitude and therefore, products out of spec. Using a technique that was first developed by Christopher Ausschnitt at IBM Microelectronics it is possible to monitor focus and dose on production layers with a single compact target. Extending this technology on an advanced optical tool allows for precise measurements of focus and dose errors. This paper will describe the methodology of inline focus and dose monitoring using this technique on 130nm process technology with an outlook on the expectations for future nodes. Results, including focus and dose sensitivity from multiple process steps on production wafers will be shown.

  9. High resolution interferometric metrology for patterned wafers

    NASA Astrophysics Data System (ADS)

    Tang, Shouhong; Freischlad, Klaus; Yam, Petrie

    2007-09-01

    The precision metrology of patterned wafer is increasingly demanded by the semiconductor device manufacturers. The most common methods include scanning probe microscopy (SPM) techniques such as stylus profilometry and Atomic Force Microscopy (AFM). These methods acquire data by contacting the surface over a sequence of one-dimensional scans. While high lateral resolution can be achieved in this way, such processes are time-consuming and can have the potential to deform the surface under test. An alternative non-contact interferometric method is presented here. The method uses the white-light interferometry (WLI) to provide wafer topography quickly in a direct three-dimensional format. The improved measurement throughput suggests that it is feasible to use this method for production monitoring. Most commercial interferometers with WLI are capable of measuring opaque surfaces with sub-nanometer precision. The described method extends this capability to determine the top surface topography of structured surfaces in the presence of varying phase shifts on reflection. The phase shift on reflection may be due to the material properties of bulk surfaces, single or multi-layer film stacks on a substrate, or other micro-structures on the wafer. Furthermore, this method simultaneously or separately provides additional parameters of the test piece e.g. layer thickness and/or material refractive index for film stacks, or line width and structure depth of micro-structures. The measurement results on various types of the wafer surfaces will be presented in this paper.

  10. Apparatus for edge etching of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Casajus, A.

    1986-01-01

    A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

  11. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  12. High density circuit technology, part 3

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations.

  13. MIL-STD-1553 VLSI components supports a variety of multiplex applications

    NASA Astrophysics Data System (ADS)

    Friedman, Steven N.

    The performance as well as the physical and electrical characteristics of a series of new VLSI components are described. These devices are capable of supporting MIL-STD-1553 and a variety of computer/microprocessor based subsystems. VSLI features such as size, packaging options, radiation hardness, and power and reliability considerations are discussed.

  14. A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

    NASA Technical Reports Server (NTRS)

    Fang, W.

    1994-01-01

    For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

  15. VLSI chip-set for data compression using the Rice algorithm

    NASA Technical Reports Server (NTRS)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  16. A VLSI implementation of a correlator/digital-filter based on distributed arithmetic

    NASA Technical Reports Server (NTRS)

    Zohar, Shalhav

    1989-01-01

    The design of a VLSI chip which applies the ideas of distributed arithmetic to a nonrecursive digital filter is described. The main features of this design are very high precision and a high degree of flexibility, which allows one chip to implement a large number of quite different digital filters and correlators.

  17. Characterization of Charging Control of a Single Wafer High Current Spot Beam Implanter

    SciTech Connect

    Schmeide, Matthias; Bukethal, Christoph

    2008-11-03

    This paper focuses on the characterization of charging control of an Axcelis Optima HD single wafer high current spot beam implanter using MOS capacitors with attached antennas of different size and shape. Resist patterns are implemented on Infineon Technologies own charging control wafers to investigate the influence of photo resist on charging damage. Compared to batch high current implanters the design of the beamline and the beam shape are comparable to single wafer high current spot beam implanters, however due to the different scanning architecture the dose rate of the single wafer high current spot beam implanters is significantly higher compared to the batch tools. Therefore, the risk of charging damage will be higher. The charging damage was studied as a function of the energy, the beam current and the most important plasma flood gun parameters. The results have shown that for very high antenna ratios the charging damage for single wafer implanters, even spot or ribbon beam implanters, is higher than for high current batch implanters.

  18. First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

    NASA Technical Reports Server (NTRS)

    Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

    2008-01-01

    Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

  19. Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer

    SciTech Connect

    Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

    1999-09-07

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

  20. Wafer sub-layer impact in OPC/ORC models for advanced node implant layers

    NASA Astrophysics Data System (ADS)

    Le-Denmat, Jean-Christophe; Michel, Jean-Christophe; Sungauer, Elodie; Yesilada, Emek; Robert, Frederic; Lan, Song; Feng, Mu; Wang, Lei; Depre, Laurent; Kapasi, Sanjay

    2014-03-01

    From 28 nm technology node and below optical proximity correction (OPC) needs to take into account light scattering effects from prior layers when bottom anti-reflective coating (BARC) is not used, which is typical for ionic implantation layers. These effects are complex, especially when multiple sub layers have to be considered: for instance active and poly structures need to be accounted for. A new model form has been developed to address this wafer topography during model calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification (using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction and verification. This paper discusses an exploration of this new model results using extended wafer measurements (including SEM). Current results show good accuracy on various representative structures.

  1. Study of Ag-In solder as low temperature wafer bonding intermediate layer

    NASA Astrophysics Data System (ADS)

    Made, Riko I.; Gan, Chee Lip; Lee, Chengkuo; Yan, Li Ling; Yu, Aibin; Yoon, Seung Wook; Lau, John H.

    2008-02-01

    Indium-silver as solder materials for low temperature bonding had been introduced earlier. In theory the final bonding interface composition is determined by the overall materials composition. Wafer bonding based multiple intermediate layers facilitates precise control of the formed alloy composition and the joint thickness. Thus the bonding temperature and post-bonding re-melting temperature could be easily designed by controlling the multilayer materials. In this paper, a more fundamental study of In-Ag solder materials is carried out in chip-to-chip level by using flip-chip based thermocompression bonding. Bonding at 180C for various time duration under various bonding pressure is studied. Approaches of forming Ag IIIn with re-melting temperature higher than 400C at the bonding interface are proposed and discussed. Knowledge learned in this process technology can support us to develop sophisticated wafer level packaging process based wafer bonding for applications of MEMS and IC packages.

  2. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

  3. A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

    NASA Astrophysics Data System (ADS)

    Richstein, James K.

    1993-12-01

    Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.

  4. Steel bridge fatigue crack detection with piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Yu, Lingyu; Giurgiutiu, Victor; Ziehl, Paul; Ozevin, Didem; Pollock, Patrick

    2010-04-01

    Piezoelectric wafer active sensors (PWAS) are well known for its dual capabilities in structural health monitoring, acting as either actuators or sensors. Due to the variety of deterioration sources and locations of bridge defects, there is currently no single method that can detect and address the potential sources globally. In our research, our use of the PWAS based sensing has the novelty of implementing both passive (as acoustic emission) and active (as ultrasonic transducers) sensing with a single PWAS network. The combined schematic is using acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since methods such as ultrasonics are unable to quantify the initial condition of crack growth since most of the fatigue life for these details is consumed while the fatigue crack is too small to be detected. Hence, combing acoustic emission with ultrasonic active sensing will strengthen the damage detection process. The integration of passive acoustic emission detection with active sensing will be a technological leap forward from the current practice of periodic and subjective visual inspection, and bridge management based primarily on history of past performance. In this study, extensive laboratory investigation is performed supported by theoretical modeling analysis. A demonstration system will be presented to show how piezoelectric wafer active sensor is used for acoustic emission. Specimens representing complex structures are tested. The results will also be compared with traditional acoustic emission transducers to identify the application barriers.

  5. Towards Wafer-Scale Monocrystalline Graphene Growth and Characterization.

    PubMed

    Nguyen, Van Luan; Lee, Young Hee

    2015-08-01

    Since its discovery in 2004, graphene has boosted numerous fundamental sciences and technological applications due to its massless Dirac particle-like linear band dispersion, that causes unprecedented physical properties. Among the various methods for synthesizing graphene, chemical vapor deposition is the most suitable approach for scalable production on a wafer scale, which is a critical step for practical applications. Graphene grain boundaries (GGBs), consisting of nonhexagonal carbon rings and therefore modulating the properties of graphene films, are inevitably formed via the merging of adjacent graphene domains with different orientations. Large-area monocrystalline graphene synthesis without forming GGBs has been challenging, let alone observing such boundaries. Here, an up-to-date review is presented of how to grow wafer-scale monocrystalline graphene without GGBs. One approach is to make single domain sizes as large as possible by reducing or passivating the number of nucleation sites. Another approach is to align graphene domains in identical orientations, and then merge them atomically. The recently developed methods for observing graphene orientation and GGBs both at the atomic and macro-scales are also presented. Finally, perspectives for future research in graphene growth are discussed. PMID:25903119

  6. A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

    PubMed

    Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

    2013-01-01

    This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time. PMID:24110095

  7. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  8. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  9. Elimination of wafer edge die yield loss for accelerometers

    NASA Astrophysics Data System (ADS)

    Zhang, Zhenjun; Eskes, Kim A.

    2000-08-01

    Residual stresses from deposition of several micron thick polysilicon film on accelerometer wafers caused wafer to warp towards edge of wafer. The average peak to valley difference for wafer flat across wafer is 16 +/- 1 micrometers . The photo layer following the thick polysilicon deposition process is a CD critical layer with 1 micrometers spacing to be resolved. With standard stepper configuration, wafer non- flatness from residual stresses reduced overall depth of focus and made the 1 (mu) spacing in edge dies not resolved, resulting in stiction and yield loss for edge dies. To minimize the effect of wafer non-flatness on across wafer CD control and edge die CD definition at photo, three different focus algorithms as well as two different wafer chuck styles were evaluated on 1X steppers. Results showed that both oblong wafer chuck and two step focus option significantly improved CD definition and resolution of the 1 micrometers spacing in edge dies. Two step focus combined with oblong chuck offered the best CD control edge dies. Edge die yield loss was eliminated for accelerometer wafers ran with oblong chuck and two step focus. Oblong chuck, and two step focus combination have been released to full production at Poly2 layer of accelerometers.

  10. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  11. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  12. High density circuit technology, part 1

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

  13. Wafer weak point detection based on aerial images or WLCD

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Philipp, Peter; Litt, Lloyd C.; Ackmann, Paul; Crell, Christian; Chen, Norman

    2015-10-01

    Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

  14. Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size

    NASA Astrophysics Data System (ADS)

    Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

    2013-06-01

    For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

  15. Wafer surface pre-treatment study for micro bubble free of lithography process

    NASA Astrophysics Data System (ADS)

    Yang, Xiaosong; Zhu, XiaoZheng; Cai, Spencer

    2014-04-01

    Photo resist micro bubble and void defect is reported as a typical and very puzzle defect type in photo lithography process, it becomes more and more significantly and severely with the IC technology drive towards 2 node. Introduced in this paper, we have studied the mechanism of photo resist micro bubble at different in-coming wafer surface condition and tested a series of pre treatment optimization method to resolve photo resist micro bubble defect on different wafer substrate, including in the standard flat and smooth wafer surface and also in special wafer surface with high density line/space micro-structure substrate as is in logic process FinFET tri-gate structure and Nor type flash memory cell area Floating Gate/ONO/Control Gate structure. As is discovered in our paper, in general flat and smooth wafer surface, the photo resist micro bubble is formed during resist RRC coating process (resist reduction coating) and will easy lead to Si concave defect after etch; while in the high density line/space micro-structure substrate as FinFET tri-gate, the photo resist void defect is always formed after lithography pattern formation and will final cause the gate line broken after the etching process or localized over dose effect at Ion IMP layers. The 2nd type of photo resist micro bubble is much more complicated and hard to be eliminated. We try to figure out the interfacial mechanism between different type of photo resist (ArF, KrF and I-line) and pre-wet solvent by systematic methods and DOE splits. And finally, we succeeded to dig out the best solution to eliminate the micro bubble defect in different wafer surface condition and implement in the photolithography process.

  16. Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process

    NASA Astrophysics Data System (ADS)

    Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

    2013-09-01

    Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

  17. Nanotribology of nanooxide materials in ionic liquids on silicon wafers

    NASA Astrophysics Data System (ADS)

    Hamidunsani, Ahmad Termizi; Radiman, Shahidan; Hassan, Masjuki Haji; Rahman, Irman Abdul

    2015-09-01

    Nanotribological properties have a significant impact on daily life. Ionic liquids (ILs) are becoming new favourable lubricants currently in researches. Addition of nanooxide materials in lubricants provide improvements to new technology. In this study, we determine nanotribological properties of BMIM+BF4- IL addition of different amount of ZnO nanomaterial on single crystals silicon wafer (Si110). The viscosity changes of IL samples against temperature increase were determined by rheological method. Nanotribological properties were determined by changes in friction coefficient and wear rate on silicon substrate surfaces using a reciprocating friction and wear monitor in 1 hour duration time. Aluminium cylinders acted as pins used to rub Si (110) substrate sample surfaces. Thus, on range between 0 mg to 3.5 mg of ZnO nanooxide material dispersed in 10ml BMIM+BF4- showed a good friction coefficient, wear and surface roughness reduction.

  18. Characterization of semiconductor surface-emitting laser wafers

    SciTech Connect

    Gourley, P.L.; Vawter, G.A.; Brennan, T.M.; Hammons, B.E.

    1990-01-01

    The development of epitaxial semiconductor surface-emitting lasers has begun in recent years. These lasers are ultra-short (few {mu}m) Fabry-Perot resonators comprising epitaxial multilayer semiconductor mirrors and quantum well active regions. The resonators are single crystals grown along the lasing axis by molecular beam epitaxy (MBE) or chemical vapor deposition (CVD). They offer significant advances over conventional cleaved, edge-emitting lasers for creating lasers with single elements of 2 dimensional arrays, low beam divergence, engineered active regions, single longitudinal modes, and improved temperature characteristics. To realize the high potential of these new laser structures, techniques for characterizing the laser wafer after growth and between fabrication steps must be developed. In this paper we discuss several optical techniques that we have developed for this emerging surface-emitting laser technology.

  19. Electrooptic shutter devices utilizing PLZT ceramic wafers

    SciTech Connect

    Thornton, A.L.

    1981-01-01

    Optical transparency was achieved in lead zirconate-titanate ferroelectric ceramics by substituting moderate amounts of the element lanthanum (8 to 12%) for lead. These compositions exhibit the quadratic (Kerr) electrooptic effect. The excellent optical qualities of these materials (designated PLZT) has permitted the practical utilization of their electrooptic properties in a number of devices. All of these devices utilize the classic Kerr cell arrangement. A PLZT wafer with optical axis oriented at 45/sup 0/ with respect to the axes of polarization is sandwiched between crossed polarizers. Application of an electric field via an interdigital array of electrodes on opposing wafer surfaces forces the PLZT material into a tetragonal state with the resulting induced birefringence proportional to the square of the applied electric field. Hence, the electrooptic wafer provides a retardation of light so that a component is passed by the second crossed polarizer to achieve an ON or open state. Maximum transmission is achieved when the retardation is half-wave. Shutter devices developed by Sandia and those in continuing development are described with respect to operational characteristics and physical configuration. The devices range in size from very small apertures of 50 ..mu..m x 2 mm with center-to-center repeat dimensions of 125 ..mu..m - to very large - apertures of 15.2 cm in single pieces and mosaics with apertures of 15.2 cm x 20.3 cm. Major efforts have centered on shutter development for the protection of aircrew from eye-damaging weapon effects. Other devices are also described which: provide eye protection for welders, protect vidicon tubes, function as page composers for holographic memories serve as large aperture photographic shutters, provide stereoscopic three-dimensional TV displays, and serve as data links in a fiber-optic transmission path.

  20. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

  1. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  2. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  3. Slip-Free Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-06-01

    Defect generation phenomena in Si wafers during atmospheric pressure rapid thermal processing (RTP) in a single wafer furnace (SWF) are investigated as a function of temperature, process time, wafer handling method and speed. The size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in controlling defect generation during RTP under given process conditions. Highly reproducible slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100°C for 60 s (up to 5 times) by optimizing the wafer handling method and speed.

  4. Resonance ultrasonic vibrations for crack detection in photovoltaic silicon wafers

    NASA Astrophysics Data System (ADS)

    Dallas, W.; Polupan, O.; Ostapenko, S.

    2007-03-01

    The resonance ultrasonic vibrations (RUV) technique is adapted for non-destructive crack detection in full-size silicon wafers for solar cells. The RUV methodology relies on deviation of the frequency response curve of a wafer, ultrasonically stimulated via vacuum coupled piezoelectric transducer, with a periphery crack versus regular non-cracked wafers as detected by a periphery mounted acoustic probe. Crack detection is illustrated on a set of cast wafers. We performed vibration mode identification on square-shaped production-grade Si wafers and confirmed by finite element analyses. The modelling was accomplished for the different modes of the resonance vibrations of a wafer with a periphery crack to assess the sensitivity of the RUV method relative to crack length and crack location.

  5. A new VLSI architecture for a single-chip-type Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.

    1989-01-01

    A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.

  6. Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

    NASA Astrophysics Data System (ADS)

    Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

    2011-09-01

    Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

  7. A subthreshold aVLSI implementation of the Izhikevich simple neuron model.

    PubMed

    Rangan, Venkat; Ghosh, Abhishek; Aparin, Vladimir; Cauwenberghs, Gert

    2010-01-01

    We present a circuit architecture for compact analog VLSI implementation of the Izhikevich neuron model, which efficiently describes a wide variety of neuron spiking and bursting dynamics using two state variables and four adjustable parameters. Log-domain circuit design utilizing MOS transistors in subthreshold results in high energy efficiency, with less than 1pJ of energy consumed per spike. We also discuss the effects of parameter variations on the dynamics of the equations, and present simulation results that replicate several types of neural dynamics. The low power operation and compact analog VLSI realization make the architecture suitable for human-machine interface applications in neural prostheses and implantable bioelectronics, as well as large-scale neural emulation tools for computational neuroscience. PMID:21096884

  8. VLSI architectures for computing multiplications and inverses in GF(2m)

    NASA Technical Reports Server (NTRS)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  9. A VLSI chip set for real time vector quantization of image sequences

    NASA Technical Reports Server (NTRS)

    Baker, Richard L.

    1989-01-01

    The architecture and implementation of a VLSI chip set that vector quantizes (VQ) image sequences in real time is described. The chip set forms a programmable Single-Instruction, Multiple-Data (SIMD) machine which can implement various vector quantization encoding structures. Its VQ codebook may contain unlimited number of codevectors, N, having dimension up to K = 64. Under a weighted least squared error criterion, the engine locates at video rates the best code vector in full-searched or large tree searched VQ codebooks. The ability to manipulate tree structured codebooks, coupled with parallelism and pipelining, permits searches in as short as O (log N) cycles. A full codebook search results in O(N) performance, compared to O(KN) for a Single-Instruction, Single-Data (SISD) machine. With this VLSI chip set, an entire video code can be built on a single board that permits realtime experimentation with very large codebooks.

  10. WARP: Weight Associative Rule Processor. A dedicated VLSI fuzzy logic megacell

    NASA Technical Reports Server (NTRS)

    Pagni, A.; Poluzzi, R.; Rizzotto, G. G.

    1992-01-01

    During the last five years Fuzzy Logic has gained enormous popularity in the academic and industrial worlds. The success of this new methodology has led the microelectronics industry to create a new class of machines, called Fuzzy Machines, to overcome the limitations of traditional computing systems when utilized as Fuzzy Systems. This paper gives an overview of the methods by which Fuzzy Logic data structures are represented in the machines (each with its own advantages and inefficiencies). Next, the paper introduces WARP (Weight Associative Rule Processor) which is a dedicated VLSI megacell allowing the realization of a fuzzy controller suitable for a wide range of applications. WARP represents an innovative approach to VLSI Fuzzy controllers by utilizing different types of data structures for characterizing the membership functions during the various stages of the Fuzzy processing. WARP dedicated architecture has been designed in order to achieve high performance by exploiting the computational advantages offered by the different data representations.

  11. A cost-effective methodology for the design of massively-parallel VLSI functional units

    NASA Technical Reports Server (NTRS)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  12. Learning and optimization with cascaded VLSI neural network building-block chips

    NASA Technical Reports Server (NTRS)

    Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

    1992-01-01

    To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

  13. In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system

    NASA Astrophysics Data System (ADS)

    Yang, Yi-Bin; Liu, Ming-Gang; Chen, Wei-Jie; Han, Xiao-Biao; Chen, Jie; Lin, Xiu-Qi; Lin, Jia-Li; Luo, Hui; Liao, Qiang; Zang, Wen-Jie; Chen, Yin-Song; Qiu, Yun-Ling; Wu, Zhi-Sheng; Liu, Yang; Zhang, Bai-Jun

    2015-09-01

    In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2″ Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), the International Science and Technology Collaboration Program of Guangdong Province, China (Grant No. 2013B051000041), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), the National High Technology Research and Development Program of China (Grant No. 2014AA032606), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics, China (Grant No. IOSKL2014KF17).

  14. Wafer warpage characterization measurement with modified fringe reflection method

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2015-05-01

    We have demonstrated a modified fringe reflection method to compensate the warpage measurement errors caused by the height difference between optical reference mirror and wafer sample surface. We have used a linearity analysis approach to obtain the parabolic height errors for a 4-inch sapphire wafer warpage measurement, which is around 1.48 ?m of 100 ?m height difference. The experimental results shows the warp discrepancy of 6-inch sapphire wafer is less than 1 ?m compared with the reference Tropel instrument.

  15. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  16. A Systolic VLSI Design of a Pipeline Reed-solomon Decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

    1984-01-01

    A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

  17. A VLSI single chip (255,223) Reed-Solomon encoder with interleaver

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Deutsch, L. J.; Truong, T. K.; Reed, I. S.

    1987-01-01

    A single-chip implementation of a Reed-Solomon encoder with interleaving capability is described. The code used was adapted by the CCSDS (Consulative Committee on Space Data Systems). It forms the outer code of the NASA standard concatenated coding system which includes a convolutional inner code of rate 1/2 and constraint length 7. The architecture, leading to this single VLSI chip design, makes use of a bit-serial finite field multiplication algorithm due to E.R. Berlekamp.

  18. VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network

    NASA Astrophysics Data System (ADS)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2011-11-01

    This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 ?m 1P6M CMOS process. Post-layout simulation results are reported.

  19. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  20. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  1. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.

    PubMed

    Bill, Johannes; Schuch, Klaus; Brderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices. PMID:21031027

  2. Characterization Of The Ultratech Wafer Stepper

    NASA Astrophysics Data System (ADS)

    Hershel, Ron; Voison, Ron

    1982-09-01

    A brief characterization of the Ultratech Model 900 wafer stepper is presented. Excellent control critical dimensions for 1-gum minimum features is accomplished by using a broad spectral bandwidth for exposure which minimizes standing wave effects and by using numerical aperture of 0.315 illuminated with coherence factor of 0.45. Minimal variation in linewidth is seen over 5000A to 8000A poly and metal steps with little evidence of standing wave patterns in the resist profiles. A large depth of focus is obtained with a highly corrected 1:1 lens design which keeps astigmatism and field curvature below 0.5um. The automatic site-by-site alignment system on the Model 900 has proven extremely reliable at all wafer levels with a repeatability better than 0.16um (2 sigma). Lens-to-lens distortion below 0.2um (2 sigma) results from the inherent symmetry in the folded 1:1 design and from careful lens fabrication. A precision lenedistortion test is described with a 2 sigma error below 0.04um and the overlay distortion for the three Ultratech lenses is presented.

  3. Laser soft marking on silicon wafer

    NASA Astrophysics Data System (ADS)

    Khoong, L. E.; Lam, Y. C.; Zheng, H. Y.; Chen, X.

    2010-03-01

    A laser soft marking technique is developed for laser markings on a silicon wafer. Due to negligible surface modification, the laser soft wafer markings are invisible by naked eyes under room condition and are undetectable using sophisticated instruments. However, these laser markings are found to be visible to naked eyes through a differential condensation of water droplets on the laser-marked and unmarked silicon surfaces. To understand this phenomenon, a model is established to study the condensation of water droplets on laser-marked and unmarked silicon surfaces. Experimental observations and simulation results indicate that the laser soft marking could have modified the silicon surface with a thin polycrystalline silicon layer which has a much lower conductivity than the crystalline silicon. In addition, this thin layer exhibits a thermal conductivity which is approximately two orders of magnitude lower than that of its equivalent bulk material. As a result, heat transfer on the laser-marked silicon surface is much lower than the crystalline silicon and thus makes these laser soft markings easily visible visually under condensation.

  4. Development of Fixture Element for Vacuum Transportation of Silicon Wafer Using Electro-Rheological Gel

    NASA Astrophysics Data System (ADS)

    Tanaka, Masayuki; Kakinuma, Yasuhiro; Aoyama, Tojiro; Anzai, Hidenobu; Kawaguchi, Takafumi

    Semiconductor process technology increasingly requires high accuracy and efficiency. In the case of processing thin fragile substrate such as silicon wafer, it has to be fixed with low strain. In addition, its fixture device can be used under vacuum condition because some processes are carried out in vacuum. It is required to develop a new fixture device for vacuum transportation of silicon wafer. ERG is the functional material whose friction characteristic varies according to the intensity of applied electric field. The surface friction of ERG can be changed quickly and reversibly applying the electric field. In other words, it becomes easy to fix and release a substrate by control of electric field. In this study, ERG is applied to a fixture element of silicon wafer available for vacuum process. The ERG fixture element was trial-manufactured and its performance under vacuum condition was evaluated experimentally. The result shows that the ERG effect emerges in vacuum and ERG can fix silicon wafer sufficiently. Moreover, numerical analysis of electric filed was carried out to obtain the optimal pattern of the one-sided electrodes used for the ERG fixture element. It is clear that the optimal width of electrodes exists according to the gap of electrodes and the thickness of ERG.

  5. Direct To Digital Holography For High Aspect Ratio Inspection of Semiconductor Wafers

    NASA Astrophysics Data System (ADS)

    Thomas, C. E. (Tommy); Hunt, Martin A.; Bahm, Tracy M.; Baylor, Larry R.; Bingham, Philip R.; Chidley, Matthew D.; Dai, Xiaolong; Delahanty, Robert J.; El-Khashab, Ayman; Gilbert, Judd M.; Goddard, James S.; Hanson, Gregory R.; Hickson, Joel D.; Hylton, Kathy W.; John, George C.; Jones, Michael L.; Mayo, Michael W.; Marek, Christopher; Price, John H.; Rasmussen, David A.; Schaefer, Louis J.; Schulze, Mark A.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin, Kenneth W.; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Owen, Robert W.

    2003-09-01

    Direct to Digital Holography (DDH) has been developed as a semiconductor wafer inspection tool and in particular as a tool for seeing defects in high aspect ratio (HAR) structures on semiconductor wafers and also for seeing partial-height defects. While the tool works very well for general wafer inspection, it has unusual capabilities for high aspect ratio inspection (HARI) and for detecting thin residual film defects (partial height defects). Inspection of HAR structures is rated as one of the highest unmet priorities of the member companies of International SEMATECH, and finding residual thin film defects (in some cases called "stringers") is also a very difficult challenge. The capabilities that make DDH unusually sensitive include: 1) the capture of the whole waveboth the classical amplitude captured by traditional optical systems, and the phase of the wave, with phase potentially measured to 1/1000'th of a wavelength or 2 to 3 Angstroms for a deep ultra-violet (DUV) laser; 2) heterodyne detectionthis allows it to capture very low signal levels; and 3) a head-on geometry using a collimated laser beam that allows best penetration of HAR structures. The basic features and methods of this patented technology are presented, along with simple calculations of signal strength and expected noise levels for various circumstances. Full-wave numerical calculations of electromagnetic field penetration into HAR contacts and experimental results from various wafer types and structures are also presented.

  6. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  7. Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

    PubMed Central

    Thomson, Stephen R. D.; Perron, Justin K.; Kimball, Mark O.; Mehta, Sarabjit; Gasparini, Francis M.

    2014-01-01

    Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 m thick Si wafers with about 1 m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale. PMID:24457563

  8. Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint

    SciTech Connect

    Rupnowski, P.; Sopori, B.

    2008-05-01

    This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

  9. Piezoresistive stress sensors on (110) silicon wafers

    NASA Technical Reports Server (NTRS)

    Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

    1992-01-01

    Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

  10. Wafer Mapping Using Deuterium Enhanced Defect Characterization

    NASA Astrophysics Data System (ADS)

    Hossain, K.; Holland, O. W.; Hellmer, R.; Vanmil, B.; Bubulac, L. O.; Golding, T. D.

    2010-07-01

    Deuterium (as well as other hydrogen isotopes) binds with a wide range of morphological defects in semiconductors and, as such, becomes distributed similarly to those defects. Thus, the deuterium profile within the sample serves as the basis of a technique for defect mapping known as amethyst wafer mapping (AWM). The efficiency of this technique has been demonstrated by evaluation of ion-induced damage in implanted Si, as well as as-grown defects in HgCdTe (MCT) epilayers. The defect tagging or decoration capability of deuterium is largely material independent and applicable to a wide range of defect morphologies. A number of analytical techniques including ion channeling and etch pit density measurements were used to evaluate the AWM results.

  11. Low-temperature vacuum hermetic wafer-level package for uncooled microbolometer FPAs

    NASA Astrophysics Data System (ADS)

    Garcia-Blanco, S.; Topart, P.; Desroches, Y.; Caron, J. S.; Williamson, F.; Alain, C.; Jerominek, H.

    2008-02-01

    Micro-Electro-Mechanical Systems (MEMS) packaging constitutes most of the cost of such devices. For the integration of MEMS with microelectronics systems to be widespread, a drastic reduction of the overall price is required. Wafer-level-packaging allows a fundamental reduction of the packaging cost by combining wafer-level microfabrication techniques with wafer-to-wafer bonding. To achieve the vacuum atmosphere required for the operation of many MEMS devices, bonding techniques such as anodic bonding, eutectic bonding, fusion bonding and gold to gold thermocompression bonding have been utilized, which require relatively high temperatures (>300C) being in some cases incompatible with MEMS and microelectronics devices. Furthermore, to maintain vacuum integrity over long periods of time, getters requiring high activation temperatures are usually employed. INO has developed a hybrid wafer-level micropackaging technology based on low temperature fluxless solder joints in which the micropackaged MEMS device is not exposed to a temperature over 150C. The micropackages have been designed for 160120 microbolometer FPAs. Ceramic spacers are patterned by standard microfabrication techniques followed by laser micromachining. AR-coated floatzone silicon IR windows are patterned with a solderable layer. Both, microbolometer dies and windows are soldered to the ceramic tray by a combination of solder paste stencil printing, reflow and fluxless flip-chip bonding. A low temperature getter is also introduced to control outgassing of moisture and CO II during the lifetime of the package. Vacuum sealing is carried out by locally heating the vacuum port after bake out of the micropackages. In this paper, the vacuum integrity of micropackaged FPA dies will be reported. Base pressures as low as 5 mTorr and equivalent flow rates at room temperature of 410 -14 Torr.l/s without getter incorporation have been demonstrated using integrated micro-pressure gauges. A study of the influence of different packaging parameters on the lifetime of micropackages will be presented.

  12. High-performance long wave infrared bolometer fabricated by wafer bonding

    NASA Astrophysics Data System (ADS)

    Lapadatu, Adriana; Kittilsland, Gjermund; Elfving, Anders; Hohler, Erling; Kvistery, Terje; Bakke, Thor; Ericsson, Per

    2010-04-01

    A novel microbolometer with peak responsivity in the longwave infrared region of the electromagnetic radiation is under development at Sensonor Technologies. It is a focal plane array of pixels with a 25?m pitch, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The novelty of the proposed 3D process integration comes from the choice of several of the materials and key processes involved, which allow a high fill factor and provide improved transmission/absorption properties. Together with the high TCR and low 1/f noise provided by the thermistor material, they will lead to bolometer performances beyond those of existing devices. The thermistor material is transferred from the handle wafer to the read-out integrated circuit (ROIC) by wafer bonding. The low thermal conductance legs that connect the thermistor to the ROIC are fabricated prior to the transfer bonding and are situated under the pixel. Depending on the type of the transfer bonding used, the plugs connecting the legs to the thermistor are made before or after this bonding, resulting in two different configurations of the final structure. Using a low temperature oxide bonding and subsequent plugs formation result in through-pixel plugs. Pre-bonding plugs formation followed by thermo-compression bonding result in under-pixel plugs. The pixels are subsequently released by anhydrous vapor HF of the sacrificial oxide layer. The ROIC wafer containing the released FPAs is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. Antireflection coatings and a thin layer getter are deposited on the cap wafer prior to bonding, ensuring high performance of the bolometer.

  13. Research News: Are VLSI Microcircuits Too Hard to Design?

    ERIC Educational Resources Information Center

    Robinson, Arthur L.

    1980-01-01

    This research news article on microelectronics discusses the scientific challenge the integrated circuit industry will have in the next decade, for designing the complicated microcircuits made possible by advancing miniaturization technology. (HM)

  14. Thermal Warpage of Large Diameter Czochralski-Grown Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Shimizu, Hirofumi; Aoshima, Takaaki

    1988-12-01

    Thermal warping of large diameter Czochralski-grown silicon wafers as affected by oxygen precipitation is investigated both experimentally and theoretically. The difference of wafer warpage and its shape between the heating and cooling processes is clarified by thermal stresses calculated from temperature gradients in wafers for each process. The critical temperatures for the slip occurrence are determined for the heating and cooling processes as a function of the microdefect density. Then, the optimized process conditions to avoid slip dislocations are obtained experimentally. The critical stress curve for the processed wafers in MOS devices is determined by comparison with the thermal stress curves calculated under various process conditions, and thereby predicting the slip-free conditions for wafers in a row with various diameters from 100 to 200 mm.

  15. A novel technique for cleaning semiconductor wafers using ultrasonic transducer

    NASA Astrophysics Data System (ADS)

    Nakade, Rugved; Yow, Raylon; Sayka, Tony; Sardar, Dhiraj

    2006-10-01

    An experiment was designed based on U.S. Patent no. 6,766,813 which describes a process that effectively cleans a semiconductor wafer with the help of ultrasonic vibrations. The semiconductor wafer was freely supported by a hollow cylindrical box made of foam. Two commonly occurring contaminants found on wafers in the industry are silicon and silicon dioxide. Micrometer sizes of these two materials were used to replicate contaminants that commonly occur in the industry. The wafer was then excited with the help of an ultrasonic transducer in the aim of knocking off these contaminants from the surface of the semiconductor wafer. Particle counts were taken with the help of a modified optical microscope before and after applying the ultrasonic vibration in order to determine the effectiveness of this technique.

  16. Backside EBR process performance with various wafer properties

    NASA Astrophysics Data System (ADS)

    Goto, Tomohiro; Shigemori, Kazuhito; Vangheluwe, Rik; Erich, Daub; Sanada, Masakazu

    2009-03-01

    In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled film edge position and good uniformity around the wafer circumference is needed. We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse system has a good controllability of film edge position and good uniformity around the wafer circumference. The results indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to provide a suitable film stacking architecture for immersion lithography mass production process.

  17. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  18. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  19. Step and flash imprint process integration techniques for photonic crystal patterning: template replication through wafer patterning irrespective of tone

    NASA Astrophysics Data System (ADS)

    Miller, Mike; Brooks, Cindy; Lentz, David; Doyle, Gary; Resnick, Doug; LaBrake, Dwayne

    2008-02-01

    Photonic crystal structures in for example light emitting diodes (LED) have been demonstrated to improve performance by preferential mode coupling near the surface of the diode.1 Such demonstrations were limited by using direct write e-beam lithography due to long write times, a single tone and only small areas patterned for study. S-FIL technology provides a means to pattern entire wafers in a single imprint step using templates replicated by step and repeat (S&R) imprint2. Large area template replication by S-FIL/R has been described using S&R templates 3. Photonic crystal based LED manufacturers prefer holes in substrates requiring pillar tone templates for S-FIL patterning. Pillar tone templates are not easily derived from the preferred e-beam tone for sub-200 nm template fabrication. Therefore step and repeat and/or whole wafer template replication by the combination of S-FIL and/or S-FIL/R can be used to produce the desired working template tone. These processes further enable the desired tone and wafer die layout for fully patterning wafers to their edge with no missing die or edge fields. The advantages of using S-FIL processes for template and wafer patterning are clear in that there is no tone preference required by the original e-beam generated pattern, which allows the preferred positive tone to be used for e-beam patterning of templates. The present work will describe template replication processes for the fabrication of either pillar or hole tone templates and subsequent wafer pattern processes, through oxide hard mask, producing both pillar and hole tone patterns. In summary process flows exist so that any e-beam written template tone can be used to produce either tone in replicated templates and/or patterned wafers.

  20. Capacitive micromachined ultrasonic transducers with through-wafer interconnects

    NASA Astrophysics Data System (ADS)

    Zhuang, Xuefeng

    Capacitive micromachined ultrasonic transducer (CMUT) is a promising candidate for making ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with through-wafer interconnects, a CMUT array can be directly integrated with a front-end integrated circuit (IC) to achieve compact packaging and to mitigate the effects of the parasitic capacitance from the connection cables. Through-wafer via is the existing interconnect scheme for CMUT arrays, and many other types of micro-electro-mechanical system (MEMS) devices. However, to date, no successful through-wafer via fabrication technique compatible with the wafer-bonding method of making CMUT arrays has been demonstrated. The through-wafer via fabrication steps degrade the surface conditions of the wafer, reduce the radius of curvature, thus making it difficult to bond. This work focuses on new through-wafer interconnect techniques that are compatible with common MEMS fabrication techniques, including both surface-micromachining and direct wafer-to-wafer fusion bonding. In this dissertation, first, a through-wafer via interconnect technique with improved characteristics is presented. Then, two implementations of through-wafer trench isolation are demonstrated. The through-wafer trench methods differ from the through-wafer vias in that the electrical conduction is through the bulk silicon instead of the conductor in the vias. In the first implementation, a carrier wafer is used to provide mechanical support; in the second, mechanical support is provided by a silicon frame structure embedded inside the isolation trenches. Both implementations reduce fabrication complexity compared to the through-wafer via process, and result in low series resistance and small parasitic capacitance. Two-dimensional CMUT arrays incorporating trench-isolated interconnects show high output pressure (2.9 MPa), wide bandwidth (95%), small pulse-echo amplitude variation (sigma = 6.6% of the mean amplitude), and excellent element yield (100% in 16x16-element array). Volumetric ultrasound imaging was demonstrated by flip-chip bonding one of the fabricated 2D arrays to a custom-designed IC. An important added benefit of the trench-isolated interconnect is the capability to realize flexible arrays. A flexible 2D CMUT array is demonstrated by filling the trenches with polydimethylsiloxane (PDMS). The results presented in this dissertation show that through-wafer trench-isolation is a viable solution for providing electrical interconnects to CMUT elements. These techniques are potentially useful for providing through-wafer interconnects to many other types of MEMS sensors and actuators because of their post-process nature. The results also show that 2D CMUT arrays fabricated using wafer-bonding deliver good performance.

  1. Ultra-Low Noise HEMT Device Models: Application of On-Wafer Cryogenic Noise Analysis and Improved Parameter Extraction Techniques

    NASA Technical Reports Server (NTRS)

    Bautista, J. J.; Hamai, M.; Nishimoto, M.; Laskar, J.; Szydlik, P.; Lai, R.

    1995-01-01

    Significant advances in the development of HEMT technology have resulted in high performance cryogenic low noise amplifiers whose noise temperatures are within an order of magnitude of the quantum noise limit. Key to the identification of optimum HEMT structures at cryogenic temperatures is the development of on-wafer noise and device parameter extraction techniques. Techniques and results are described.

  2. Highly Uniform Electroluminescence from 150 and 200 mm GaN-on-Si-Based Blue Light-Emitting Diode Wafers

    NASA Astrophysics Data System (ADS)

    Pinos, Andrea; Tan, Wei-Sin; Chitnis, Ashay; Nishikawa, Atsushi; Groh, Lars; Hu, Cheng-Yu; Murad, Saad; Lutgen, Stephan

    2013-09-01

    We report on the on-wafer device characteristics of 150 and 200 mm GaN-on-Si-based blue LED wafers grown by metalorganic chemical vapor deposition on Si(111) substrates with electroluminescence at 447 nm. Excellent uniformity was achieved with standard deviations of 3.9% for the electroluminescence intensity, 0.6-0.8% for the peak wavelength and 1.3% for the forward voltage. The high uniformity confirms the viability of the GaN-on-Si technology on large-diameter substrates for next-generation LED manufacturing. The reverse bias current leakage mechanism is also investigated to provide an insight into improving device reliability.

  3. Wafer-level filling of microfabricated atomic vapor cells based on thin-film deposition and photolysis of cesium azide

    SciTech Connect

    Liew, Li-Anne; Moreland, John; Gerginov, Vladislav

    2007-03-12

    The thin-film deposition and photodecomposition of cesium azide are demonstrated and used to fill arrays of miniaturized atomic resonance cells with cesium and nitrogen buffer gas for chip-scale atomic-based instruments. Arrays of silicon cells are batch fabricated on wafers into which cesium azide is deposited by vacuum thermal evaporation. After vacuum sealing, the cells are irradiated with ultraviolet radiation, causing the azide to photodissociate into pure cesium and nitrogen in situ. This technology integrates the vapor-cell fabrication and filling procedures into one continuous and wafer-level parallel process, and results in cells that are optically transparent and chemically pure.

  4. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    PubMed

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. PMID:24732237

  5. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  6. Development of optical automatic positioning and wafer defect detection system

    NASA Astrophysics Data System (ADS)

    Tien, Chuen-Lin; Lai, Qun-Huang; Lin, Chern-Sheng

    2016-02-01

    The data of a wafer with defects can provide engineers with very important information and clues to improve the yield rate and quality in manufacturing. This paper presents a microscope automatic positioning and wafer detection system with human-machine interface based on image processing and fuzzy inference algorithms. In the proposed system, a XY table is used to move the position of each die on 6 inch or 8 inch wafers. Then, a high-resolution CCD and one set of two-axis optical linear encoder are used to accurately measure the position on the wafer. Finally, the developed human-machine interface is used to display the current position of an actual wafer in order to complete automatic positioning, and a wafer map database can be created. In the process of defect detection, CCD is used for image processing, and during preprocessing, it is required to filter noise, acquire the defect characteristics, define the defective template, and then take the characteristic points of the defective template as the reference input for fuzzy inference. A high-accuracy optical automatic positioning and wafer defect detection system is thus constructed. This study focused on automatic detection of spots, scratches, and bruises, and attempted to reduce the time to detect defective die and improve the accuracy of determining the defects of semiconductor devices.

  7. Opto-VLSI-based photonic true-time delay architecture for broadband adaptive nulling in phased array antennas.

    PubMed

    Juswardy, Budi; Xiao, Feng; Alameh, Kamal

    2009-03-16

    This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each. PMID:19293907

  8. Plasma-activated wafer bonding: the new low-temperature tool for MEMS fabrication

    NASA Astrophysics Data System (ADS)

    Dragoi, V.; Mittendorfer, G.; Thanner, C.; Lindner, P.

    2007-05-01

    Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stress-free, aligned substrates without warpage. Achieving wafer level bonding at low temperature employs a little magic and requires new technology development. The cornerstone of low temperature bonding is plasma activation. The plasma is chosen to compliment existing interface conditions and can result in conductive or insulating interfaces. A wide range of materials including semiconductors, glasses, quartz and even plastics respond favorably to plasma activated bonding. The annealing temperatures required to create permanent bonds are typically ranging from room temperature to 400C for process times ranging from 15-30 minutes and up to 2-3 hours. This new technique enables integration of various materials combinations coming from separate production lines.

  9. Application of error correcting codes in fault-tolerant logic design for VLSI circuits

    NASA Astrophysics Data System (ADS)

    Lala, P. K.; Martin, H. L.

    1990-05-01

    It is now generally accepted that not all faults in VLSI logic can be represented by the stuck-at-0 and stuck-at-1 models used at the gate level. In order to ensure realistic modeling, faults should be considered at the transistor level, since only at the level the complete circuit structure is known. In other words, test for circuits should be derived based on possible shorts and opens at the transistor level. A stuck-open or stuck-closed transistor can be modeled by replacing the faulty transistor with an open connection or a direct short respectively between the transistor's source and drain.

  10. Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

    1985-01-01

    The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  11. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    SciTech Connect

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  12. Fault tolerant VLSI (Very Large-Scale Integration) design using error correcting codes

    NASA Astrophysics Data System (ADS)

    Hartmann, C. R.; Lala, P. K.; Ali, A. M.; Ganguly, S.; Visweswaran, G. S.

    1989-02-01

    Very Large-Scale Integration (VLSI) provides the opportunity to design fault tolerant, self-checking circuits with on-chip, concurrent error correction. This study determines the applicability of a variety of error-detecting, error-correcting codes (EDAC) in high speed digital data processors and buses. In considering both microcircuit faults and bus faults, some of the codes examined are: Berger, repetition, parity, residue, and Modified Reflected Binary codes. The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.

  13. Efficient VLSI parallel algorithm for Delaunay triangulation on orthogonal tree network in two and three dimensions

    SciTech Connect

    Saena, S.; Bhatt, P.C.P.; Prasad, V.C. )

    1990-03-01

    In this paper, a parallel algorithm for two- and three-dimensional Delaunay triangulation on an orthogonal tree network is described. The worst case time complexity of this algorithm is O(log {sup 2} N) in two dimensions and O(m {sup 1/2} log N) in three dimensions with N input points and m as the number of tetrahedra in tiangulation. The AT {sup 2} VLSI complexity on Thompson's logarithmic delay model is O(N {sup 2} log {sup 6} N) in two dimensions and O(m {sup 2} N log {sup 4} N) in three dimensions.

  14. A VLSI architecture for performing finite field arithmetic with reduced table look-up

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.; Reed, I. S.

    1986-01-01

    A new table look-up method for finding the log and antilog of finite field elements has been developed by N. Glover. In his method, the log and antilog of a field element is found by the use of several smaller tables. The method is based on a use of the Chinese Remainder Theorem. The technique often results in a significant reduction in the memory requirements of the problem. A VLSI architecture is developed for a special case of this new algorithm to perform finite field arithmetic including multiplication, division, and the finding of an inverse element in the finite field.

  15. The uses of Man-Made diamond in wafering applications

    NASA Technical Reports Server (NTRS)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  16. Applications of atomic force microscopy for silicon wafer characterization

    SciTech Connect

    Suhren, M.; Graef, D.; Schmolke, R.; Piontek, H.; Wagner, P.

    1996-12-01

    AFM (Atomic Force Microscopy) is a highly sensitive tool for the analysis of the microroughness of Si wafers and for the investigation of crystal defects. AFM images of atomic steps were used for verification of the vertical AFM calibration on slightly misoriented Si(111) wafers after chemical etching and epitaxial deposition. The roughness analysis of etched, polished and epitaxial Si(100) wafers shows a reduction of the surface roughness by chemomechanical polishing by more than two orders of magnitude compared to an etched surface. The morphology of crystal originated particles on Si(100) appears as smooth surface depression after polishing and sharply defined pit after SCI treatment.

  17. On-Wafer Testing of Circuits Through 220 GHz

    NASA Technical Reports Server (NTRS)

    Gaier, Todd; Samoska, Lorene; Oleson, Charles; Boll, Greg

    1999-01-01

    We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.

  18. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime τbulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various τbulk conditions. The modeling results show that for the IBC solar cell with high τbulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low τbulk (for instance, < 500 μs) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  19. Separating cluster contribution to improve CD distribution using simultaneous dose-focus monitoring on production wafers

    NASA Astrophysics Data System (ADS)

    Armellin, Louis-Pierre; Dureuil, Virginie; Guillaume, Olivier; Alet, Philippe; Eichelberger, Brad; Egreteau, Michel; Polli, Marco; Dinu, Berta

    2005-05-01

    As device dimensions shrink the number of parameters influencing CD increases (PEB dispersion, development uniformity, resist thickness, BARC thickness, +/- scan focus control, scanner focus control at edge of the wafer...). Separation between all these contributors is not easy using only CD-SEM measurement, and particularly with isolated lines. For high volume manufacturing (where "time is money") and in the case of litho cluster drift, a quick and accurate diagnostic capability is an advantage for minimizing tool unavailability. An important attribute of this diagnostic capability is that its implementation is on standard production wafers. The use of production wafers enables continuous monitoring and also allows a direct correlation between monitoring measurements and the impact on product. The technology that enables this type of diagnostic capability makes use of a compact dual tone line-end-shortening based target. A key benefit to this technology is that it provides a separation of the dose and focus parameters, which leads to quicker route cause determination. After building a calibration model and determining minimum dose and focus sensitivity, both short term and long term stability of the model is investigated. The impact of wafer topology on model prediction is also investigated in order to assess on-product monitoring capability. The main error contributors are then identified for both track and scanner and the impact on CD control is evaluated. These cluster error contributors are then varied, first separately, and then combined. Measurement results are compared to the input parameters in order to determine error detection ability, measurement accuracy and separation capability.

  20. Arthroscopic wafer procedure for ulnar impaction syndrome.

    PubMed

    Colantoni, Julie; Chadderdon, Christopher; Gaston, R Glenn

    2014-02-01

    Ulnar impaction syndrome is abutment of the ulna on the lunate and triquetrum that increases stress and load, causing ulnar-sided wrist pain. Typically, ulnar-positive or -neutral variance is seen on a posteroanterior radiograph of the wrist. The management of ulnar impaction syndrome varies from conservative, symptomatic treatment to open procedures to shorten the ulna. Arthroscopic management has become increasingly popular for management of ulnar impaction with ulnar-positive variance of less than 3 mm and concomitant central triangular fibrocartilage complex tears. This method avoids complications associated with open procedures, such as nonunion and symptomatic hardware. The arthroscopic wafer procedure involves debridement of the central triangular fibrocartilage complex tear, along with debridement of the distal pole of the ulna causing the impaction. Debridement of the ulna arthroscopically is taken down to a level at which the patient is ulnar neutral or slightly ulnar negative. Previous studies have shown good results with relief of patient symptoms while avoiding complications seen with open procedures. PMID:24749031

  1. Arthroscopic Wafer Procedure for Ulnar Impaction Syndrome

    PubMed Central

    Colantoni, Julie; Chadderdon, Christopher; Gaston, R. Glenn

    2014-01-01

    Ulnar impaction syndrome is abutment of the ulna on the lunate and triquetrum that increases stress and load, causing ulnar-sided wrist pain. Typically, ulnar-positive or -neutral variance is seen on a posteroanterior radiograph of the wrist. The management of ulnar impaction syndrome varies from conservative, symptomatic treatment to open procedures to shorten the ulna. Arthroscopic management has become increasingly popular for management of ulnar impaction with ulnar-positive variance of less than 3 mm and concomitant central triangular fibrocartilage complex tears. This method avoids complications associated with open procedures, such as nonunion and symptomatic hardware. The arthroscopic wafer procedure involves debridement of the central triangular fibrocartilage complex tear, along with debridement of the distal pole of the ulna causing the impaction. Debridement of the ulna arthroscopically is taken down to a level at which the patient is ulnar neutral or slightly ulnar negative. Previous studies have shown good results with relief of patient symptoms while avoiding complications seen with open procedures. PMID:24749031

  2. Low-temperature full wafer adhesive bonding

    NASA Astrophysics Data System (ADS)

    Niklaus, Frank; Enoksson, Peter; Klvesten, Edvard; Stemme, Gran

    2001-03-01

    We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 m and 18 m. The tested polymer materials were benzocyclobutene (BCB) from Dow Chemical, a negative photoresist (ULTRA-i 300) and a positive photoresist (S1818) from Shipley, a polyimide (HTR3) from Arch Chemical and two different polyimides (PI2555 and PI2610) from DuPont. The polymer material, the bonding pressure and the pre-curing time and temperature for the polymer significantly influence void formation at the bond interface. High bonding pressure and optimum pre-curing times/temperatures counteract void formation. We present the process parameters to achieve void-free bonding with the BCB coating and with the ULTRA-i 300 photoresist coating as adhesive materials. Excellent void-free and strong bonds have been achieved by using BCB as the bonding material which requires a minimum bonding temperature of 180 C.

  3. Direct to Digital Holography for Semiconductor Wafer Defect Detection and Review

    SciTech Connect

    ThomasJr., C. E.; Bahm, Tracy M.; Baylor, Larry R; Bingham, Philip R.; Burns, Steven W.; Chidley, Matthew D; Dai, Xiaolong; Delahanty, Robert J.; Doti, Christopher J.; El-Khashab, Ayman; Fisher, Robert L.; Gilbert, Judd M.; Cui, Hongtao; Goddard Jr, James Samuel; Hanson, Gregory R; Hickson, Joel D.; Hunt, Martin A.; Hylton, Kathy W; John, George C.; Jones, Michael L.; McDonald, Kenneth R.; Mayo, Michael W.; McMackin, Ian; Patek, David; Price, John H.; Rasmussen, David A; Schaefer, Louis J.; Scheidt, Thomas R.; Schulze, Mark A.; Schumaker, Philip D.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin Jr, Kenneth William; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Jones, Paul G.; Owen, Robert W.

    2002-01-01

    A method for recording true holograms (not holographic interferometry) directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional to wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for finding defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep ultra-violet light.

  4. An introduction GaAs microprocessor architecture for VLSI

    SciTech Connect

    Milutinovic, V.; Fura, D.; Helbig, W.

    1986-03-01

    Gallium arsenide, or GaAs, technology has recently shown rapid increases in maturity. In particular, the advances made in digital chip complexity have been enormous. This progress is especially evident in two types of chips: static rams and gate arrays. In 1983, static rams containing 1K bits were announced. One year later both a 4K-bit and a 16K-bit version were presented. Gate arrays have advanced from a 1000-gate design presented in 1984 to a 2000-gate design announced in 1985. With this enormous progress underway, it is now appropriate to consider the use of this new technology in the implementation of high-performance processors. GaAs technology generates high levels of enthusiasm primarily because of two advantages it enjoys over silicon: higher speed and greater resistance to adverse environmental conditions. GaAs gates switch faster than silicon transistor-transistor logic, or TTL, gates by nearly an order of magnitude. These switching speeds are even faster than those attained by the fastest silicon emitter-coupled logic, or ECL, but at power levels an order of magnitude lower. For this reason, GaAs is seen to have applications in computer design within several computationally intensive areas. In fact, it has been reported that the Cray-3 will contain GaAs parts. GaAs also enjoys greater resistance to radiation and temperature variations than does silicon. GaAs successfully operates in radiation levels of 10 to 100 million rads. Its operating temperature range extends from -200 to 200/sup 0/C. Consequently, GaAs has created great excitement in the military and aerospace markets.

  5. Fast wafer-level detection and control of interconnect reliability

    NASA Astrophysics Data System (ADS)

    Foley, Sean; Molyneaux, James; Mathewson, Alan

    2000-08-01

    Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterize particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure results. The Isothermal test method combine with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.

  6. Surface defects in GaAs wafer processes

    NASA Astrophysics Data System (ADS)

    Matsushita, H.; Ishida, M.; Kikawa, J.

    1990-06-01

    The causes of micro- and macro-irregularities observed on GaAs(100) polished wafers were investigated. From the results, the wafer processes were improved so that a high-quality surface was obtained without orange peel, haze, or pits. For 3-inch wafers the flatness was improved to less than 2 ?m in TTV and the warp to less than 5 ?m. Improvements in the wafer processes were: development of a better polishing solution, filtering of this solution with maintenance of the pad conditions, thereby eliminating scratches, annealing at high temperature to eliminate pits, advances in slicing and lapping to reduce warp, and three-stage double-sided polishing to eliminate dimples and to improve TTV.

  7. Estimation of wafer warpage profile during thermal processing in microlithography

    NASA Astrophysics Data System (ADS)

    Tay, Arthur; Ho, Weng Khuen; Hu, Ni; Chen, Xiaoqi

    2005-07-01

    Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps. Early detection will minimize cost and processing time. We propose in this article an in situ approach for estimating wafer warpage profile during the thermal processing steps in the microlithography process. The average air gap between wafer and bake-plate at multiple locations of a multizone bake-plate can be estimated and a profile can be obtained by joining these points. Experimental results demonstrate the feasibility and repeatability of the approach. This is a major improvement over our previously developed approach, in which only the average warpage could be obtained. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods.

  8. Infrared backwards laser melting of a silicon wafer

    NASA Astrophysics Data System (ADS)

    Lill, Patrick C.; Khler, Jrgen R.

    2015-11-01

    We investigate a method for melting a silicon wafer's rear side with a pulsed infrared laser (1064 nm) impinging onto the front side. The targeted application for this method is deep laser doping. Our numerical model simulates the evolution of the two-dimensional temperature distribution in the wafer caused by pulsed infrared laser irradiation. The model incorporates the temperature dependent material properties of silicon and the enthalpy-based phase change by means of finite volumes. The simulation yields spacial temperature distributions of the wafer's cross section at defined time steps. We obtain the laser parameters for a continuous melt depth of 40 m in a 200 m thick wafer from the analysis of the simulation results.

  9. Efficient data transmission from silicon wafer strip detectors

    SciTech Connect

    Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

    1991-12-31

    An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

  10. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    NASA Astrophysics Data System (ADS)

    Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu (Andy)

    2003-12-01

    The technique of orthogonal frequency division multiplexing (OFDM) is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the fast Fourier transform (FFT) and inverse FFT (IFFT) operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly processing element (PE) based on the coordinate rotation digital computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC[InlineEquation not available: see fulltext.]m 1P4M CMOS technology. The simulations results show that the chip can perform ([InlineEquation not available: see fulltext.]-[InlineEquation not available: see fulltext.])-point FFT/IFFT operations up to[InlineEquation not available: see fulltext.] operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL ([InlineEquation not available: see fulltext.]), DAB, and[InlineEquation not available: see fulltext.]-mode DVB.

  11. Particle-wafer interactions in semiaqueous silicon cleaning systems

    NASA Astrophysics Data System (ADS)

    Hupka, Lukasz

    During the semiconductor chip manufacturing process, a silicon wafer goes through a number of cycles in both hydrophilic and hydrophobic environments. As silicon chips become more sophisticated, the manufacturing process becomes more involved and new challenges are imposed by size reduction, increase in the aspect ratio and the formation of multilayer structures. Wafer cleaning processes emerge several times in one manufacturing cycle. By rule of thumb, it is necessary to remove wafer contamination by particles which are half of a feature size. This is an enormous challenge, keeping in mind that currently wafer structures are of nanometer size. The cleaning procedures which worked for the last 40 years are becoming ineffective and obsolete. The industry calls for more efficient cleaning procedures in terms of particle contamination removal, and at the same time less aggressive procedures to prevent damage/dissolution of the fragile and narrow wafer structures. Atomic Force Microscopy (AFM), besides being an imaging tool with nano resolution, proves to be an indispensable instrument to characterize interaction forces, lateral forces, and adhesion between micron and submicron contaminant particles and the wafer surfaces both in air and liquid. Using the AFM colloidal probe technique interaction forces were measured between a contaminant particle and a wafer surface. These measurements were done for the silica---silica hydrophilic system and for the silanated silica---silanated silica hydrophobic system. The influence of the nonaqueous component in semiconductor wafer cleaning solution on interaction forces was also investigated under both hydrophilic and hydrophobic conditions. In addition the effect of particle size on the interaction forces as well as particle removal rate under both conditions is addressed. While force/radius normalization of measured interaction forces works great for hydrophilic systems, it was found to significantly underestimate the influence of particle size in a hydrophobic system. A correction to the normalization of hydrophobic forces with respect to particle size has been proposed. The issue of nanobubble formation at hydrophobic surfaces under certain conditions has been investigated. The nanobubbles were observed under AFM and characterized with respect to size, shape and Laplace pressure. As wafer structures become smaller and more fragile, it is crucial to confront the impact of different manufacturing steps, including the process of cleaning, with the strength of wafer structures. The force required to remove a contaminant should be close to the force that damages a structure in order to maximize particle removal efficiency, but not higher than this force in order to avoid structure damage. Such measurements have been done with the AFM using lateral force mode of operation. Understanding and manipulation of the interaction forces has led to the design of novel semiconductor wafer cleaning solutions.

  12. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    NASA Technical Reports Server (NTRS)

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  13. Finite-field arithmetic operations in VLSI-algorithms, realizations, and applications

    SciTech Connect

    Shyu, H.C.

    1986-01-01

    Congruences and residue arithmetic are the basis for the arithmetic operations on a finite ring. A new symbol (am)/sub L/ is defined to determine whether an integer a is a quadratic residue, modulo m, where m is a positive odd integer. A new theorem is proved which establishes the relationship between this new symbol and the corresponding Legendre symbol for the prime factors of m. The diminished-1 representation performs the arithmetic operations over the finite ring, modulo a Fermat number. The diminished-1 representation and arithmetic operations are valid also over the finite ring, modulo 2/sup n/ + 1. A new pipeline architecture for a prime factor DFT is developed. Also, a new shuffling algorithm is developed to solve the problem of rearranging the data sequence when a one- to two-dimensional index mapping is applied. The general case of this shuffling algorithm is established in theorems. Finally, the VLSI architecture for the pipeline prime factor DFT that makes use of this new shuffling algorithm is presented. VLSI designs for a integer multiplier modulo 2/sup 4/ + 1 = 17, a complex multiplier modulo 17, etc., which use the algorithms developed in this dissertation are shown

  14. Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards

    SciTech Connect

    Pin, F.G.; Watanabe, Y.

    1992-09-01

    This paper discusses the sensor-based driving of a car in a-priori unknown environments using ``human-like`` reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver`s aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver`s aid using the new fuzzy inferencing VLSI hardware and ``human-like`` reasoning schemes.

  15. An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

    NASA Astrophysics Data System (ADS)

    Corliss, Walter F., II

    1989-03-01

    The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

  16. Optimized features allocation technique for improved automated alignment of wafers

    NASA Astrophysics Data System (ADS)

    Parshin, Michael; Zalevsky, Zeev

    2009-02-01

    In this paper we present a new fuzzy logic based approach for automatic optimized features allocation. The technique is used for improved automatic alignment and classification of silicon wafers and chips that are used in the electronic industry. The proposed automatic image processing approach was realized and experimentally demonstrated in real industrial application with typical wafers. The automatic features allocation and grading supported the industrial requirements and could replace human expert based inspection that currently is performed manually.

  17. Stress rate and proof-testing of silicon wafers

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1985-01-01

    Fracture mechanics test methods were applied to evaluate the proof-test characteristics of single-crystal silicon wafers. The results indicate that the strength distribution of silicon wafers is truncated by proof-testing. No subcritical crack growth occurred during proof-loading, as inferred from the lack of a stress-rate effect on strength. Mechanical proof-testing appears to be an effective method for eliminating weak samples before cell processing.

  18. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  19. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  20. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  1. Preparation of Thin Lithium Niobate Layer on Silicon Wafer for Wafer-level Integration of Acoustic Devices and LSI

    NASA Astrophysics Data System (ADS)

    Park, Kyeongdong; Esashi, Masayoshi; Tanaka, Shuji

    This paper describes UV adhesive bonding of lithium niobate (LN) and silicon (Si), and the following polishing of LN, which are key technologies in wafer-level integration processes for LN acoustic devices on LSI. Five UV adhesive candidates were investigated in terms of bonding-induced stress and removability by O2 plasma treatment. The latter is important because the UV polymer is used as a sacrificial layer in the above processes. Based on the results, we selected one usable UV adhesive, and obtained bending-free LN/Si hybrid substrates, overcoming a large difference in the coefficient of thermal expansion between LN (7.5 (c-axis) - 14.4 (a-axis) 10-6 /K) and Si (2.6 10-6 /K). The LN substrate on the Si substrate was thinned and surface-polished by an experimentally obtained recipe. Finally, a mirror-finished LN layer with a thickness of ca. 10 ?m was successfully obtained without noticeable cracks. It was confirmed that this thin LN layer survived in the fabrication process of surface acoustic wave (SAW) devices.

  2. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  3. Design and Implementation of VLSI Architecture for Generation of Ternary Pulse Compression Sequence Based on Characteristic Parameters

    NASA Astrophysics Data System (ADS)

    Rao, M. Srinivasa; Reddy, N. Madhusudhana

    2010-11-01

    This paper describes the VLSI implementation for identification of characteristic parameters of the given ternary pulse compression sequence and also generates the ternary pulse compression sequence for transmission purpose if the characteristic parameter satisfies certain required value. In this paper an efficient VLSI architecture is proposed to calculate the characteristic parameters of the given ternary pulse compression sequence simultaneously or separately. The hardware architectures reported in the literature till now have the capability of identification of only one characteristic parameter of the ternary pulse compression sequence. In this paper an effort is made for proposing an efficient VLSI architecture for identification of the characteristic parameters i.e. merit factor and discrimination of the ternary pulse compression sequence either simultaneously or separately. If the identified characteristic parameter satisfies certain required value then the proposed architecture in this paper automatically generates the ternary pulse compression sequence for transmission purpose. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogramability.

  4. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  5. Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

    NASA Astrophysics Data System (ADS)

    Goto, Tetsuya; Kuroda, Rihito; Akagawa, Naoya; Suwa, Tomoyuki; Teramoto, Akinobu; Li, Xiang; Obara, Toshiki; Kimoto, Daiki; Sugawa, Shigetoshi; Ohmi, Tadahiro; Kamata, Yutaka; Kumagai, Yuki; Shibusawa, Katsuhiko

    2015-04-01

    By introducing high-purity and low-temperature Ar annealing at 850 C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 m technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate-source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

  6. Imprinted laminate wafer-level packaging for SAW ID-tags and SAW delay line sensors.

    PubMed

    Kuypers, Jan H; Tanaka, Shuji; Esashi, Masayoshi

    2011-02-01

    We have developed a wafer-level packaging solution for surface acoustic wave devices using imprinted dry film resist (DFR). The packaging process involves the preparation of an imprinted dry film resist that is aligned and laminated to the device wafer and requires one additional lithography step to define the package outline. Two commercial dry film solutions, SU-8 and TMMF, have been evaluated. Compared with traditional ceramic packages, no detectable RF parasitics are introduced by this packaging process. At the same time, the miniature package dimensions allow for wafer-level probing. The packaging process has the great advantage that the cavity formation does not require any sacrificial layer and no liquids, and therefore prevents contamination or stiction of the packaged device. This non-hermetic packaging process is ideal for passive antenna modules using polymer technology for low-cost SAW identification (ID)-tags or lidding in low-temperature cofired ceramic (LTCC) antenna substrates for high-performance wireless sensors. This technique is also applicable to SAW filters and duplexers for module integration in cellular phones using flip-chip mounting and hermetic overcoating. PMID:21342826

  7. Energy aware VLSI architectures for mobile video applications

    NASA Astrophysics Data System (ADS)

    Darwish, Tarek Khaled

    The increased concern for energy aware system design has kept pace with current practices among circuit and system engineers like never before. The big thrusts for this concern are the excessive heat generation and the corresponding expensive cooling techniques, the devices reliability problems due to increased temperatures, and most importantly, the incapability of battery technology to supply systems with the anticipated amounts of energy, especially for portable devices. Multimedia applications, which are data-intensive applications, play a chief role in the wireless revolution, and the key requirements for the success of systems supporting multimedia applications will be suitable transmission/storage bandwidths and system power consumption. In this work, these two issues are addressed. A new DCT-based Algorithm, Coefficient Elimination, is proposed and implemented with three DCT architectures: NEDA, Direct-DCT, and LP-DCT. Simulation results show that this algorithm can reduce the DCT energy dissipation by 26--60%. In addition, new algorithms, Dynamic Profiling, are proposed for Low Bit-Rate video coding. Unlike many of the available LBR techniques, this technique is suitable for mobile devices with reduced sources such as computing power and energy resources. These algorithms not only outperform coarse quantization technique, but also result in a low energy implementation of the decoder where IQ-IDCT operations are replaced by simple buffer accessing operation.

  8. New i-line and deep-UV optical wafer stepper

    NASA Astrophysics Data System (ADS)

    Unger, Robert; Disessa, Peter A.

    1991-07-01

    A new line of optical wafer steppers is discussed. These tools, which have been developed in conjunction with Sematech and its member companies, feature new high-numerical aperture, widefield reduction lenses for operation at either i-line (365 nm) or deep-UV (248 nm) wavelengths. The i-line tool achieves practical resolution at the 0.50 micrometers level with usable working focal depth, while the deep-UV tool is capable of practical resolution at the 0.35 micrometers level with usable working focal depth. The design of these tools incorporates and expands upon optical wafer stepper technologies which have been field proven, particularly in the areas of alignment, focusing, INSITUTM metrology, automatic calibration, and diagnostic utilities. New features added to theses tools, to support their application at or below 0.50 micrometers , include a new system structure designed for inherent stability to maintain tight coupling among the imaging and alignment subsystems, and wafer stage advancements to achieve increased positioning accuracy, which supports obtaining overall tool overlay accuracy commensurate with sub-half-micron resolution. Of particular significance is the incorporation of a field-by-field leveling system, which optimizes the usable depth of focus over large image fields on product wafers. The tools also include an entirely new control system, which has been designed based on a new hierarchical control architecture, and incorporates digital servo controls and automated diagnostics. The control interface is designed as an intuitive graphic touch screen display, providing simplicity to the operator and significant job process flexibility, compatible with advanced memory and Application Specific Integrated Circuits (ASIC) fab operations. Design considerations for these tools are described together with performance results obtained in the field.

  9. Fabrication of a mechanically aligned single-wafer MEMS turbine with turbocharger

    NASA Astrophysics Data System (ADS)

    Pelekies, S. O.; Schuhmann, T.; Gardner, W. G.; Camacho, A.; Protz, J. M.

    2010-10-01

    We describe the fabrication of a turbocharged, microelectromechanical system (MEMS) turbine. The turbine will be part of a standalone power unit and includes extra layers to connect the turbine to a generator. The project goal is to demonstrate the successful combination of several features, namely: silicon fusion bonding (SFB), a micro turbocharger [2], two rotors, mechanical alignment between two wafers [1], and the use of only one 5" silicon wafer. The dimension of the actual turbine casing will be 14mm. The turbine rotor will have a diameter of 8mm. Given these dimensions, MEMS processes are an adequate way to fabricate the device, but it will be necessary to stack up seven different layers to build the turbine, as it is not possible to construct it out of one thick wafer. SFB will be used for bonding because it permits the great precision necessary for high quality alignment. Yet a more precise alignment will be necessary between the layers that contain the turbine rotor, to decrease imbalance and guarantee operation at a very high rpm. To achieve these tight tolerances, a mechanical alignment feature announced by Liudi Jiang [1] is used. The alignment accuracy is expected to be around 200nm. Despite the fact that the turbine consists of multiple layers, it will be fabricated on only one silicon-on-insulator (SOI) wafer. As a result, all layers are exposed to the same process flow. The fabrication process includes MEMS technology as photolithography, nine deep reactive ion etching (DRIE) steps, and six SFB operations. A total of 14 masks are necessary for the fabrication.

  10. Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects

    NASA Astrophysics Data System (ADS)

    Sharma, Himani; Krabbe, Joshua D.; Farsinezhad, Samira; van Popta, Andy C.; Wakefield, Nick G.; Fitzpatrick, Glen A.; Shankar, Karthik

    2015-04-01

    Electrical through-wafer interconnect technologies such as vertical through-silicon vias (TSVs) are essential in order to maximize performance, optimize usage of wafer real estate, and enable three-dimensional packaging in leading edge electronic and microelectromechanical systems (MEMS) products. Although copper TSVs have the advantage of low resistance, highly doped polysilicon TSVs offer designers a much larger range of processing options due to the compatibility of polysilicon with high temperatures and also with the full range of traditional CMOS processes. Large stresses are associated with both Cu and polysilicon TSVs, and their accurate measurement is critical for determining the keep-out zone (KOZ) of transistors and for optimizing downstream processes to maintain high yield. This report presents the fabrication and stress characterization of 400-?m deep, 20-? resistance, high aspect ratio (25:1) polysilicon TSVs fabricated by deep reactive ion etching (DRIE) followed by low-pressure chemical vapor deposition (LPCVD) of polysilicon with in-situ boron doping. Micro-Raman imaging of the wafer surface showed a maximum stress of 1.2 GPa occurring at the TSV edge and a KOZ of 9 to 11 ?m. For polysilicon TSVs, the stress distribution in the TSVs far from the wafer surface(s) was not previously well-understood due to measurement limitations. Raman spectroscopy was able to overcome this limitation; a TSV cross section was examined and stresses as a function of both depth and width of the TSVs were collected and are analyzed herein. An 1100C postanneal was found to reduce average stresses by 40%.

  11. An innovative platform for high-throughput high-accuracy lithography using a single wafer stage

    NASA Astrophysics Data System (ADS)

    Shibazaki, Yuichi; Kohno, Hirotaka; Hamatani, Masato

    2009-03-01

    For 32 nm half-pitch node, double patterning is recognized as the most promising technology since some significant obstacles still remain in EUV in terms of technology and cost. This means much higher productivity and overlay performance will be required for lithography tools. This paper shows the technical features of Nikon's new immersion tool, NSR-S620 based on newly developed platform "StreamlignTM" designed for 2nm overlay, 200wph throughput and 2week setup time. The S620 is built basically upon Nikon's Tandem Stage and Local Fill Nozzle technology, but has several additional features. For excellent overlay, laser encoders with short optical path are applied for wafer stage measurement in addition to interferometers. By using this hybrid metrology, the non-linearity of the encoder scale can be easily calibrated, while eliminating the air fluctuation error of interferometer. For high throughput, a method with a new alignment microscope system and a new auto focus mapping, called Stream Alignment is introduced. It makes it possible to reduce the overhead time between the exposures remarkably. The target productivity is 4,000 wafer outs per day. Accuracy is also improved because many more alignment points and a continuous wafer height map without stitching are available. Higher acceleration and faster scan velocity of the stages are also achieved by optimal vibration dynamics design and new control system. The main body, including the projection lens, is isolated by Sky Hook Technology used already on the NSR-SF150 and SF155 steppers, and also the reticle stage is mechanically isolated from the main body. With this new platform, the imaging performance can be maximized.

  12. High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production

    SciTech Connect

    Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

  13. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications.

    PubMed

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called "Si photonics"). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  14. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    PubMed Central

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  15. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    NASA Astrophysics Data System (ADS)

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, Sanghyeon; Choi, Won Jun

    2016-02-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  16. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    NASA Astrophysics Data System (ADS)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Bjrn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Gran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 ?m is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 ?m 25 ?m that are arranged on read-out-wafers in arrays with 320 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  17. Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

    NASA Technical Reports Server (NTRS)

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

    1986-01-01

    The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

  18. Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying; Tsai, Ming-Hsing; Yeh, Wen-Kuan; Jing, Ming-Haw; Chang, Yukon

    2009-12-01

    Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (?) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

  19. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  20. Enhancing direct laser patterning of Si wafers by polystyrene films

    NASA Astrophysics Data System (ADS)

    Haghizadeh, Anahita; Yang, Haeyeon; Peterson, Jacob; Kellar, Jon J.

    2015-03-01

    Interferential irradiation of high power laser pulses can produce arrays of periodic nanostructures on surfaces. Patterning Si wafers directly by high power laser pulses indicates that the trench depth is limited to the laser pulse intensity. We present our recent studies on direct laser patterning of polystyrene coated Si wafers, which are irradiated interferentially by high power laser pulses. Polystyrene films were formed on silicon wafers with thickness controlled based on a previously developed method. Interferential irradiations of laser pulses are applied on the polystyrene coated Si wafer. The laser pulse intensities are varied along with other interferential parameters such as interference angle and laser wavelengths of 532, 355, and 266nm. The polystyrene film is dissolved to expose the patterned Si surfaces. Atomic force microscopy (AFM) images from the patterned Si surfaces indicate that the area covered with the films has trenches deeper than those on bare Si wafers patterned at the same laser intensity. Furthermore, studies of AFM images indicate that the thicker the polystyrene coating, the deeper the trenches that are produced by direct laser patterning Si surfaces. The enhancement and modification due to polymer films may enhance the security features by improving the quality of holograms.

  1. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  2. Effective learning and feedback to designers through design and wafer inspection integration

    NASA Astrophysics Data System (ADS)

    Huang, Crockett; Liu, Hermes; Tzou, S. F.; Park, Allen; Young, Chris; Chang, Ellis

    2008-03-01

    As design rules continue to shrink beyond the lithography wavelength, pattern printability becomes a significant challenge in fabrication for 45nm and beyond. Model-based OPC and DRC checkers have been deployed using metrology data such as CD to fine-tune the model, and to predict and identify potential structures that may fail in a manufacturing environment. For advanced technology nodes with tighter process windows, it is increasingly important to validate the models with empirical data from both product and FEM wafers instead of relying solely on traditional metrology and simulations. Furthermore, feeding the information back to designers can significantly reduce the development efforts.

  3. Development of a Wafer Positioning System for the Sandia Extreme Ultraviolet Lithography Tool

    NASA Technical Reports Server (NTRS)

    Wronosky, John B.; Smith, Tony G.; Darnold, Joel R.

    1996-01-01

    A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

  4. Development of a wafer positioning system for the Sandia extreme ultraviolet lithography tool

    SciTech Connect

    Wronosky, J.B.; Smith, T.G.; Darnold, J.R.

    1995-12-01

    A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

  5. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    SciTech Connect

    Pin, F.G.; Pattay, R.S. ); Watanabe, H.; Symon, J. . Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  6. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    SciTech Connect

    Pin, F.G.; Pattay, R.S. ); Watanabe, Hiroyuki; Symon, J. . Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  7. Real-time motion detection using an analog VLSI zero-crossing chip

    NASA Astrophysics Data System (ADS)

    Bair, Wyeth; Koch, Christof

    1991-07-01

    The authors have designed and tested a one-dimensional 64 pixel, analog CMOS VLSI chip which localizes intensity edges in real-time. This device exploits on-chip photoreceptors and the natural filtering properties of resistive networks to implement a scheme similar to and motivated by the Difference of Gaussians (DOG) operator proposed by Marr and Hildreth (1980). The chip computes the zero-crossings associated with the difference of two exponential weighting functions and reports only those zero-crossings at which the derivative is above an adjustable threshold. A real-time motion detection system based on the zero- crossing chip and a conventional microprocessor provides linear velocity output over two orders of magnitude of light intensity and target velocity.

  8. A comparison of VLSI architectures for time and transform domain decoding of Reed-Solomon codes

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.; Deutsch, L. J.; Satorius, E. H.; Reed, I. S.

    1988-01-01

    It is well known that the Euclidean algorithm or its equivalent, continued fractions, can be used to find the error locator polynomial needed to decode a Reed-Solomon (RS) code. It is shown that this algorithm can be used for both time and transform domain decoding by replacing its initial conditions with the Forney syndromes and the erasure locator polynomial. By this means both the errata locator polynomial and the errate evaluator polynomial can be obtained with the Euclidean algorithm. With these ideas, both time and transform domain Reed-Solomon decoders for correcting errors and erasures are simplified and compared. As a consequence, the architectures of Reed-Solomon decoders for correcting both errors and erasures can be made more modular, regular, simple, and naturally suitable for VLSI implementation.

  9. Increase of the packaging density of Very Large Scale Integration (VLSI) circuits using automatic alignment

    NASA Astrophysics Data System (ADS)

    Fehling, H.

    1985-03-01

    Experiments in a production line were conducted to investigate the possible reduction of safety distances in VLSI circuits when an automatic alignment system is used. The test setup is described. With the very accurate alignment system of the Philips silicon repeater, the safety distance between a contact hole and a polysilicon-gate in a modified microcomputer circuit is reduced 0.7 micron without any yield loss. Design rules based on these experiments, and on lithography investigations were applied to redesign a 4 k static read-only memory. The area of a single memory cell in this redesign is 825 59 microns, compared to 1800 sq microns in the original version, and the final chip area is reduced to 8 sq mm compared to 13 sq mm.

  10. Design of a reliable and self-testing VLSI datapath using residue coding techniques

    NASA Astrophysics Data System (ADS)

    Sayers, I. L.; Kinniment, D. J.; Chester, E. G.

    1986-05-01

    The application of a residue code to check the data-path of a CPU is discussed. The structure of the data-path and the instruction set that it can perform are described, including the data-path registers, ALU, and control. The use of a mode 3 residue code to check the data-path is described in detail, giving logic diagrams and circuit layouts. The results are compared to those that might be obtained using Scan Path or BILBO techniques. The use of the residue code provides fault tolerance in a VLSI design at a small cost compared to triple modular redundancy and duplication techniques. A detailed evaluation of the increase in chip area required to produce a self-testing chip is also given.

  11. Opto-VLSI-based broadband true-time delay generation for phased array beamforming

    NASA Astrophysics Data System (ADS)

    Juswardy, Budi; Xiao, Feng; Alameh, Kamal

    2009-08-01

    Electronically controlled phased-array antennas can adaptively scan radiated beams in three-dimensional space without mechanically moving parts. While most of the research on phased-array antennas has been focusing on broadband beam steering less attention has been devoted to null steering. Broadband null steering requires a beamformer that can generate variable and frequency independent true time-delays (TTD). In this paper we propose and demonstrate the concept of an Opto-VLSI-based tunable true-time delay generation unit for adaptive null steering in phased array antennas, where arbitrary single or multiple true-time delays can simultaneously be synthesized. Simulated azimuth gain patterns for a 4- element antenna arrays is presented, and experimental results are shown, which demonstrate the principle of the proposed true-time delay unit.

  12. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    NASA Technical Reports Server (NTRS)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  13. VLSI architecture for MPEG-4 core profile video codec with accelerated bitstream processing

    NASA Astrophysics Data System (ADS)

    Stechele, Walter

    2003-04-01

    A VLSI architecture with flexible, application-specific coprocessors for object based video encoding/decoding is presented. The architecture consists of a standard embedded RISC core, as well as coprocessor modules for macroblock algorithms, motion estimation and bitstream processing. Bitstream decoding involves strong data dependencies, which requires optimized logical partitioning. An optimized instruction set can speed up bitstream decoding by a factor of two. This architecture combines high performance of dedicated ASIC architectures with the flexibility of programmable processors. Dataflow and memory access were optimized based on extensive studies of statistical complexity variations. Results on gate count and clock rate, required for realtime processing of MPEG-4 Core Profile video, are presented, as well as a comparison with software implementations on a standard RISC architecture.

  14. Complexity analysis of the emerging MPEG-4 standard as a basis for VLSI implementation

    NASA Astrophysics Data System (ADS)

    Kuhn, Peter M.; Stechele, Walter

    1998-01-01

    A complexity analysis of the video part of the emerging ISO/IEC MPEG-4 standard was performed as a basis for HW/SW partitioning for VLSI implementation of a portable MPEG-4 terminal. While the computational complexity of previously standardized video coding schemes was predictable for I-, P- and B-frames over time, the support of arbitrarily shaped visual objects as well as various coding options within MPEG-4 introduce now content dependent computational requirements with significant variance. In this paper the result of a time dependent complexity analysis of the encoding and decoding process of a binary shape coded video object (VO) and the comparison with a rectangular shaped VO is given for the complete codec as well as for the single tools of the encoding and decoding process. It is shown, that the average MB complexity per arbitrary shaped P-VOP depicts significant variation over time for the encoder and minor variations for the decoder.

  15. Damascene patterned metal/adhesive wafer bonding for three-dimensional integration

    NASA Astrophysics Data System (ADS)

    McMahon, J. Jay

    Wafer bonding of damascene patterned metal/adhesive surfaces is explored for a new three-dimensional (3D) integration technology platform. By bonding a pair of damascene patterned metal/adhesive layers, high density micron-sized vias can be formed for interconnection of fully fabricated integrated circuit (IC) dies at the wafer-level. Such via dimensions increase the areal interconnect density by at least two orders of magnitude over current package and die-stacking approaches to 3D integration. The adhesive field-dielectric produces a high critical adhesion energy bond and has the potential to produce void-free bonded interfaces. This new technology platform has been demonstrated by fabricating and characterizing inter-wafer via-chains on 200 mm diameter Si wafers. Copper and partially cured divinylsiloxane bis-benzocyclobutene (BCB) are selected as the metal and adhesive, respectively, and unit processes for this demonstration are described. Typical alignment tolerance is ˜2 mum, and baseline bonding conditions include vacuum of 5x10-4 mbar, bonding force of 10 kN, and two step bonding temperature of 250°C for 60 min followed by 350°C for 60 min. Integration issues associated with the damascene patterning and the wafer bonding processes are discussed, particularly the resulting topography of damascene patterned Cu/BCB. Cross-sectional investigation of bonded and annealed inter-wafer interconnections provides insight into the Cu-Cu and BCB-BCB bonding interfaces. Inter-wafer specific contact resistance is measured to be on the order of 10-7 O-cm 2 for these via-chains. Several material characterization techniques have been explored to evaluate partially cured BCB as an adhesive field-dielectric. To investigate the critical adhesion energy, Gc, four-point bending is utilized to compare surfaces bonded after chemical-mechanical planarization (CMP) and various post-CMP treatments. The Gc of bonded 50% partially cured BCB is measured to be in the range of 32--44 J/m2. The elastic modulus of the BCB is investigated by monitoring film stress behavior for temperatures just below that needed for crosslinking (i.e. the temperature where BCB-BCB bonding begins). The film-stress temperature dependence is then used as an indicator for phase transitions in the BCB that affect elastic modulus. Surface analysis techniques are used to explore the surface chemistry of the BCB and measure its surface energy over the temperature range required for bonding. The surface energy of partially cured BCB at both 50 and 90% crosslinking is measured to decrease by ˜30% when the temperature is raised from 35°C to 230°C. The surface analysis and mechanical properties studies provide insight into the capability of BCB to close gaps when in contact during bonding, a necessary condition for forming void-free bonding interfaces. One important aspect for implementing wafer-level 3D integration is the ability of a technology platform to accommodate topography on fully fabricated wafers. The aforementioned metal/adhesive 3D platform has strict requirements in this regard if void-free surfaces are to be attained. A bonding protocol that eliminates the copper and tantalum interconnect structure is utilized to investigate the deformation capability of partially cured BCB during bonding. The results indicate that the defect density of such BCB-BCB bonds depends on material parameters such as the degree of crosslinking and surface energy, the pitch of the features, and the depth of the topography to be accommodated. For 70--90% crosslinked BCB, accommodation was observed for lines ˜120 nm deep and ˜100 mum in pitch. Furthermore, 70--90% crosslinked BCB lines with pitch ˜1 mum and depth ˜12 nm were accommodated during bonding. When the BCB crosslinking is reduced to 50%, additional accommodation is observed. In such cases, lines with pitch ˜100 mum and depth ˜500 nm, and those with pitch ˜1 mum and depth ˜50 nm were accommodated. Additional work has shown that accommodation of some topography is possible even with zero down-force during bonding. The accommodation of topography has been evaluated by extending previously published models that focused on Si-Si bonding to this new 3D integration technology platform. Accommodation prediction through use of this first-order model is found to agree with experimentally observed results when the BCB is crosslinked to a degree of 70--90%, with increased accommodation observed in the experiments that use 50% crosslinked BCB. This disagreement is attributed to the elastic modulus of the 50% BCB decreasing when passing through its glass transition temperature. The feasibility of a new 3D integration technology platform has been demonstrated with critical unit processes characterized. Key results include the demonstration of inter-wafer via-chains, material characterization for partially cured BCB for this new bonding application, and quantification of topography accommodation.

  16. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    NASA Technical Reports Server (NTRS)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  17. Bubble-Free Silicon Wafer Bonding in a Non-Cleanroom Environment

    NASA Astrophysics Data System (ADS)

    Stengl, R.; Ahn, K.-Y.; Gsele, U.

    1988-12-01

    Bubble-free bonding of 4-inch silicon wafers on either silicon or quartz wafers is achieved outside a cleanroom. Two wafers are stacked horizontally in a rack with the two mirror-polished surfaces facing each other. In order to avoid wafer contact during hydrophilization, cleaning, and drying, the wafers are separated in the rack by teflon spacers introduced at the wafer edges. After drying the wafers by a spin dryer, the spacers are removed and bonding occurs. Using this procedure we are also able to monitor the bonding process between quartz and silicon wafers at different temperatures. We find that the initial wafer bonding process at room temperature stops operating at temperatures above 200C.

  18. A novel post exposure bake technique to improve CD uniformity over product wafers

    NASA Astrophysics Data System (ADS)

    Takeishi, Tomoyuki; Hayasaki, K.; Shibata, Tsuyoshi

    2005-05-01

    The impact of wafer warpage on critical dimension (CD) control is getting larger in ArF lithography. The product wafers with stacked films are warped due to the stress caused by the difference in the film stack structure between the top side and the back side of the wafers. A typical warpage of the product wafers is of convex shape, and the amount of the warpage is larger than 50 ?m for 200mm wafer. On the other hand, proximity bake method is widely used in the Post Exposure Bake (PEB). When the warped wafer is placed on the hot plate, the gap between the wafer and the hot plate varies across the wafer. That is, the temperature of the wafer center is lower than that of wafer edge. Such a temperature variation affects CD uniformity within wafer. In particular the fact is obvious in ArF chemical amplified resist because PEB sensitivity of ArF resist is larger than 5nm/degree. In this study we optimize PEB zone temperature within wafer to suit the wafer warpage. This method is based on controlling zone temperature of the PEB hot plate with concentrically divided heaters. We carry out that the CD uniformity for the warped wafer is improved by 70% compared with the conventional process.

  19. Optical evaluation of ingot fixity in semiconductor wafer slicing

    NASA Astrophysics Data System (ADS)

    Ng, T. W.; Nallathamby, R.

    2004-11-01

    The fixity of an ingot may greatly affect the quality of wafers produced during a wire saw process and improved mechanical clamping is a means for improving ingot fixity. Here, an optical technique that is based on laser beam deflection is described. The technique was demonstrated on ingot assemblies subjected to impulse loads within a prescribed range using an original and improved clamping system. The technique revealed that the ingot assembly had lower degrees of mean displacement and standard displacement deviation under the improved clamping system. The data on warp obtained from the actual production of wafers corroborates this finding. The technique described is an effective method of quantitatively evaluating the fixity of ingots in a wafer wire saw process.

  20. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  1. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  2. White-light interferometric microscopy for wafer defect inspection

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Christopher; Bryniarski, Casey; Dallmann, Marjorie F.; Popescu, Gabriel; Goddard, Lynford L.

    2015-03-01

    White-light imaging systems are free of laser-speckle. Thus, they offer high sensitivity for optical defect metrology, especially when used with interferometry based quantitative phase imaging. This can be a potential solution for wafer inspection beyond the 9 nm node. Recently, we built a white-light epi-illumination diffraction phase microscopy (epi-wDPM) for wafer defect inspection. The system is also equipped with an XYZ scanning stage and real-time processing. Preliminary results have demonstrated detection of 15 nm by 90 nm in a 9 nm node densely patterned wafer with bright-field imaging. Currently, we are implementing phase imaging with epi-wDPM for additional sensitivity.

  3. Wafer heating mechanisms in a molecular gas, inductively coupled plasma: in situ, real time wafer surface measurements and three-dimensional thermal modeling

    SciTech Connect

    Titus, M. J.; Graves, D. B.

    2008-09-15

    The authors report measurements and modeling of wafer heating mechanisms in an Ar/O{sub 2} inductively coupled plasma (ICP). The authors employed a commercially available on-wafer sensor system (PlasmaTemp developed by KLA-Tencor) consisting of an on-board electronics module housing battery power and data storage with 30 temperature sensors embedded onto the wafer at different radial positions. This system allows for real time, in situ wafer temperature measurements. Wafer heating mechanisms were investigated by combining temperature measurements from the PlasmaTemp sensor wafer with a three-dimensional heat transfer model of the wafer and a model of the ICP. Comparisons between pure Ar and Ar/O{sub 2} discharges demonstrated that two additional wafer heating mechanisms can be important in molecular gas plasmas compared to atomic gas discharges. The two mechanisms are heating from the gas phase and O-atom surface recombination. These mechanisms were shown to contribute as much as 60% to wafer heating under conditions of low bias power. This study demonstrated how the 'on-wafer' temperature sensor not only yields a temperature profile distribution across the wafer, but can be used to help determine plasma characteristics, such as ion flux profiles or plasma processing temperatures.

  4. On the viscoplastic response of a composite wafer

    NASA Technical Reports Server (NTRS)

    Valanis, K. C.; Landel, R. F.; Peng, S. T. J.

    1988-01-01

    In the present treatment of a viscoplastic composite wafer formed from a viscoplastic matrix that is reinforced by elastic or viscoplastic fibers attached to its plane surfaces, one constitutive equation is established by considering the viscoplastic behavior of the matrix as determined by an integral-type constitutive law whose intrinsic time-measure is pertinent to endochronic viscoplasticity. Attention is given to asymptotic cases where fiber stiffnesses and the hydrostatic modulus of the wafer are much larger than the latter's shear modulus. An explicit calculation is used when the stress field is uniaxial.

  5. Computational Modeling in Plasma Processing for 300 mm Wafers

    NASA Technical Reports Server (NTRS)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  6. Simulation of defect zones in scribed silicon wafers

    NASA Astrophysics Data System (ADS)

    Ogorodnikov, Alexey I.; Ogorodnikova, Olga M.; Tikhonov, Igor N.

    2010-11-01

    The paper presents the results of computer simulation of silicon wafers under scribe loading conditions. Finite Element (FE) analysis was applied to estimate a value of stresses and spread of defect zone around scratch line. It was revealed that due to impact of diamond tip, a complex stress-strain state is produced in the wafer, which is related to the appearance of defect zones in silicon. The approved methods of cutting simulation could be employed for various types of brittle materials to predict defects and damage of crystal during separation processing.

  7. Determination of stress in silicon wafers using Raman spectroscopy

    NASA Astrophysics Data System (ADS)

    De Biasio, M.; Neumaier, L.; Vollert, N.; Geier, E.; Roesner, M.; Hirschl, Ch.; Kraft, M.

    2015-06-01

    With a strong industrial trend towards using thin silicon in semiconductor devices, process legacy-induced stresses are matter of increasing practical importance. A key problem here is a lack of suitable metrology equipment for measuring inherent substrate material stresses in the manufacturing line. To overcome this, the use of Raman microspectrometry as a tool for measuring stress levels and distributions quantitatively on entire productive wafers was researched. Combining model cases, theoretical considerations and real-world samples, it could be shown that Raman can provide the necessary analytical accuracy and reliability, allowing to relate ensuing stress states e.g. to different wafer thinning process parameters.

  8. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  9. The Relationship between the Bending Stress in Silicon Wafers and the Mechanical Strength of Silicon Crystals

    NASA Astrophysics Data System (ADS)

    Fukuda, Tetsuo

    1995-06-01

    Silicon wafers horizontally stacked in a vertical furnace bend downward due to their weight. Using a linear elastic theory, we calculated the shear stress caused by the wafer bending and investigated the mechanical strength by comparing the shear stress with the upper yield stress of silicon crystals. We concluded that the maximum shear stress increased with the increase in the wafer diameter, 0.20, 0.30, and 0.55 MPa for 6, 8, and 12 inch wafers. In bending the 12 inch wafers, oxygen precipitates, lowering the upper yield stress, caused serious wafer warping because the shear stress exceeded the lowered yield stress.

  10. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  11. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, Theodoer F. (31843 Miwok Trail, P.O. Box 1453, Evergreen, CO 80439)

    1995-01-01

    Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

  12. The influence of wafer elasticity on acoustic waves during LIGA development.

    SciTech Connect

    Ting, Aili

    2003-12-01

    During acoustically stimulated LIGA development, a wafer receives sound waves from both sides at a wide variety of incidence angles that vary in time depending on the orientation of the wafer relative to the multiple transducers that are typically actuated in a periodic sequence. It is important to understand the influence of these variables on the transmission of energy through the wafer as well as the induced motion of the wafer itself because these processes impact the induced acoustic streaming of the fluid within features, the mechanism presently thought responsible for enhanced development of LIGA features. In the present work, the impact of wafer elasticity on LIGA development is investigated. Transmission waves, wafer bending waves, and the related concepts such as critical bending frequency, mechanical impedance, coincidence, and resonance, are discussed. Supercritical-frequency incident waves induce supersonic bending waves in the wafer. Incident wave energy is channeled into three components, transmitted, reflected and energy deposited to the wafer, depending on the wafer material, thickness and wave incidence angle. Results show at normal incidence for a 1-mm PMMA wafer, about 47% of the wave energy is deposited in the wafer. The wafer gains almost half of the incident energy, a result that agrees well with the Bankert et a1 measurements. In LIGA development, transmitted waves may sometimes produce strong acoustic motion of the developer on the wafer backside, especially for the so-called coincidence case in which almost all incident wave energy transfers to the backside. Wafer bending waves cause wafer oscillation at high frequency, promoting the development process, but features shaking may weaken their attachments to the substrate. Resonance is not likely for the entire wafer, but may occur in short and wide wafer feature columns, which are least likely to break away from the substrate, perhaps resulting in good agitation of the fluid in adjacent feature cavities.

  13. Wafer and reticle positioning system for the Extreme Ultraviolet Lithography Engineering Test Stand

    SciTech Connect

    WRONOSKY,JOHN B.; SMITH,TONY G.; CRAIG,MARCUS J.; STURGIS,BEVERLY R.; DARNOLD,JOEL R.; WERLING,DAVID K.; KINCY,MARK A.; TICHENOR,DANIEL A.; WILLIAMS,MARK E.; BISCHOFF,PAUL

    2000-01-27

    This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EUVL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100nm. EUVL research and development includes development of capabilities for demonstrating key EUV technologies. The ETS is under development at the EUV Virtual National Laboratory, to demonstrate EUV full-field imaging and provide data that supports production-tool development. The stages and their associated metrology operated in a vacuum environment and must meet stringent outgassing specifications. A tight tolerance is placed on the stage tracking performance to minimize image distortion and provide high position repeatability. The wafer must track the reticle with less than {+-}3nm of position error and jitter must not exceed 10nm rms. To meet these performance requirements, magnetically levitated positioning stages utilizing a system of sophisticated control electronics will be used. System modeling and experimentation have contributed to the development of the positioning system and results indicate that desired ETS performance is achievable.

  14. Multi-wafer slicing with a fixed abrasive

    NASA Technical Reports Server (NTRS)

    Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

    1988-01-01

    A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

  15. Automatically Dressing Blades in Silicon-Wafer Cutting

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1985-01-01

    Inserts incorporated in support beams for silicon ingots automatically "dress" cutting blade during wafer slicing. Segments of blade-dressing material placed at regular intervals in graphite beam. Blade cuts into segments and dressed without operator intervention and without interrupting regular machine operation. Manual dressing eliminated, and production rates increased.

  16. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  17. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  18. Interaction of an argon plasma jet with a silicon wafer

    NASA Astrophysics Data System (ADS)

    Engelhardt, Max; Pothiraja, Ramasamy; Kartaschew, Konstantin; Bibinov, Nikita; Havenith, Martina; Awakowicz, Peter

    2016-04-01

    A filamentary discharge is ignited in an argon plasma jet under atmospheric pressure conditions. The gas discharge is characterized with voltage-current measurements, optical emission spectroscopy and an ICCD-camera with a high temporal resolution down to 10 ns. In the effluent of the plasma jet, filaments come into contact with the surface of a silicon wafer and modify it, namely etching traces are produced and microcrystals are deposited. These traces are studied with optical and electron microscopes. The material of the deposited microcrystals and the surface modifications of the silicon wafer are analyzed with Raman microspectroscopy. Amorphous silicon is found within the etching traces. The largest part of the deposited microcrystals are composed of nitratine (NaNO3) and some of them are calcite (CaCO3). Analyzing the possible reasons for the silicon wafer modifications we come to the conclusion that plasmoids, which are produced near the substrate surface by interaction with ionization waves, are a plausible explanation for the observed surface modifications of the silicon wafer.

  19. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

  20. Face-to-face transfer of wafer-scale graphene films.

    PubMed

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene. PMID:24336218

  1. An efficient VLSI implementation of on-line recursive ICA processor for real-time multi-channel EEG signal separation.

    PubMed

    Shih, Wei-Yeh; Liao, Jui-Chieh; Huang, Kuan-Ju; Fang, Wai-Chi; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2013-01-01

    This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90 nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1 s frame is 0.9763. PMID:24111307

  2. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  3. Characteristics and issues of haze management in a wafer fabrication environment

    NASA Astrophysics Data System (ADS)

    Woo, Sung Ha; Hwang, Dae Ho; Jeong, Goo Min; Lee, Young Mo; Kim, Sang Pyo; Yim, Dong Gyu

    2014-10-01

    The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been promoted in the semiconductor industry which has been shown to suppress or minimize the propensity for haze formation, but none of these technologies can stop every instance of haze. Fortunately, a novel technology which uses a dry (no chemical effluents) removal system, laser-based, through pellicle process has been reported recently. The technology presented here avoids many of the shortcomings of the wet clean process mentioned previously. The dry clean process extends the life of the photomask; maintains more consistent CD's, phase, and transmission; avoids adjustment to the exposure dose to account for photomask changes, reduces the number of required inspections and otherwise improves the efficiency and predictability of the lithography cell. We report on the performance of photomask based on a design developed to study the impact of metrology variations on dry clean process. In a first step we focus on basic characteristics: CD variation, phase, Cr/MoSi transmission, pellicle transmission, registration variations. In a second step, we evaluate haze removal and prevention performance and wafer photo margin. Haze removal is studied on the masks for several haze types and various exposure conditions. The results of this study show that some of metrology variation are likely to be a problem at high technology node, and haze removal performance is determined whether the component of haze is remained or not after treatment.

  4. Wafer bonding process for building MEMS devices

    NASA Astrophysics Data System (ADS)

    Pabo, Eric F.; Meiler, Josef; Matthias, Thorsten

    2014-06-01

    The technology for the measurement of colour rendering and colour quality is not new, but many parameters related to this issue are currently changing. A number of standard methods were developed and are used by different specialty areas of the lighting industry. CIE 13.3 has been the accepted standard implemented by many users and used for many years. Light-emitting Diode (LED) technology moves at a rapid pace and, as this lighting source finds wider acceptance, it appears that traditional colour-rendering measurement methods produce inconsistent results. Practical application of various types of LEDs yielded results that challenged conventional thinking regarding colour measurement of light sources. Recent studies have shown that the anatomy and physiology of the human eye is more complex than formerly accepted. Therefore, the development of updated measurement methodology also forces a fresh look at functioning and colour perception of the human eye, especially with regard to LEDs. This paper includes a short description of the history and need for the measurement of colour rendering. Some of the traditional measurement methods are presented and inadequacies are discussed. The latest discoveries regarding the functioning of the human eye and the perception of colour, especially when LEDs are used as light sources, are discussed. The unique properties of LEDs when used in practical applications such as luminaires are highlighted.

  5. Flat-Plate Solar Array Project: Final report: Volume 3, Silicon sheet: Wafers and Ribbons

    SciTech Connect

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison A.

    1986-10-01

    The primary objective of the Silicon Sheet Task of the FSA Project was the development of one or more low-cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high-purity crystalline silicon of size and thickness for fabrication into solar cells. The Task effort began with state-of-the-art sheet technologies and then solicited and supported any new silicon sheet alternatives that had the potential to achieve the Project goals. A total of 48 contracts were awarded that covered work in the areas of ingot growth and casting, wafering, ribbon growth, other sheet technologies, and programs of supportive research. Periodic reviews of each sheet technology were held, assessing the technical progress and the long-range potential. Technologies that failed to achieve their promise, or seemed to have lower probabilities for success in comparison with others, were dropped. A series of workshops was initiated to assess the state of the art, to provide insights into problems remaining to be addressed, and to support technology transfer. The Task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding other characteristics associated with high-quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the Task cost goals were not achieved.

  6. Integrated optical MEMS using through-wafer vias and bump-bonding.

    SciTech Connect

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  7. A Wafer-Scale Etching Technique for High Aspect Ratio Implantable MEMS Structures

    PubMed Central

    Bhandari, R; Negi, S; Rieth, L.; Solzbacher, F

    2010-01-01

    Microsystem technology is well suited to batch fabricate microelectrode arrays, such as the Utah electrode array (UEA), intended for recording and stimulating neural tissue. Fabrication of the UEA is primarily based on the use of dicing and wet etching to achieve high aspect ratio (15:1) penetrating electrodes. An important step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Traditional etching processes are performed on a single array, and the etching conditions are not optimized. As a result, the process leads to variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. This report presents a wafer-scale etching method for the UEA. The method offers several advantages, such as substantial reduction in the processing time, higher throughput and lower cost. More importantly, the method increases the geometrical uniformity from electrode to electrode within an array (1.5 0.5 % non-uniformity), and from array to array within a wafer (2 0.3 % non-uniformity). Also, the etching rate of silicon columns, produced by dicing, are studied as a function of temperature, etching time and stirring rate in a nitric acid rich HF-HNO3 solution. These parameters were found to be related to the etching rates over the ranges studied and more-importantly affect the uniformity of the etched silicon columns. An optimum etching condition was established to achieve uniform shape electrode arrays on wafer-scale. PMID:20706618

  8. Rinsing of wafers after wet processing: Simulation and experiments

    NASA Astrophysics Data System (ADS)

    Chiang, Chieh-Chun

    In semiconductor manufacturing, a large amount (50 billion gallons for US semiconductor fabrication plants in 2006) of ultrapure water (UPW) is used to rinse wafers after wet chemical processing to remove ionic contaminants on surfaces. Of great concern are the contaminants left in narrow (tens of nm), high-aspect-ratio (5:1 to 20:1) features (trenches, vias, and contact holes). The International Technology Roadmap for Semiconductors (ITRS) stipulates that ionic contaminant levels be reduced to below ˜ 10 10 atoms/cm2. Understanding the bottlenecks in the rinsing process would enable conservation of rinse water usage. A comprehensive process model has been developed on the COMSOL platform to predict the dynamics of rinsing of narrow structures on patterned SiO 2 substrates initially cleaned with NH4OH. The model considers the effect of various mass-transport mechanisms, including convection and diffusion/dispersion, which occur simultaneously with various surface phenomena, such as adsorption and desorption of impurities. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, have been addressed. Modeling results show that the efficacy of rinsing is strongly influenced by the rate of desorption of adsorbed contaminants, mass transfer of contaminants from the mouth of the feature to the bulk liquid, and the trench aspect ratio. Detection of the end point of rinsing is another way to conserve water used for rinsing after wet processing. The applicability of electrochemical impedance spectroscopy (EIS) to monitor rinsing of Si processed in HF with and without copper contaminant was explored. In the first study, the effect of the nature of surface state (flat band, depletion, or accumulation) of silicon on rinsing rate was investigated. The experimental results show that the state of silicon could affect rinsing kinetics through modulation of ion adsorption. In the second study, silicon was intentionally contaminated by spiking HF with copper ions, cleaned in dilute HCl and then rinsed, and the entire process was followed by continuous impedance measurements. The measured impedance values at different stages have been correlated to the nature of the silicon surface, as characterized by scanning electron microscope (SEM) and inductively coupled plasma mass spectrometry (ICP-MS) methods.

  9. Thermal and power integrity analysis and optimization for high performance VLSI

    NASA Astrophysics Data System (ADS)

    Wang, Ting-Yuan

    The ever-increasing demands for more functionality and higher speed have pushed the VLSI industry towards more aggressive scaling. Since this trend leads to higher current density and power dissipation in power/ground (P/G) network, the voltage fluctuations on the on-chip power distribution system are becoming a crucial factor in determining the performance and the reliability of VLSI designs. A complete picture of the power grid integrity can be obtained only when IR-drop, electromigration (EM), and thermal effect are all considered together. However, traditional P/G network design methodologies aim at minimizing the total routing area subject to EM and IR-drop constraints. Thermal effect is ignored in the design, and can cause thermally-induced performance and reliability issues. Therefore, we propose an algorithm for P/G network design with thermal integrity. The basic idea is to include the thermal effect in optimization process. To consider thermal effect in IR-drop, IR-drop constraint must be temperature dependent. In addition, a new self-consistent constraint is defined and used to replace the EM constraint for the thermal integrity. This self-consistent constraint is based on the idea of finding simultaneous solution of EM and SH effects. In order to have required thermal reliability in P/G network, the objective function is based on minimizing the sum of each wire's weighted sum of average power dissipation and wire area. The idea is that the smaller the routing area, the larger the power dissipation will be in P/G network. This approach addresses the power dissipation and thermal integrity. Due to the thermal integrity design of P/G network, we need to effectively analyze the three-dimensional (3-D) substrate temperature distribution and hot-spot locations. Therefore, we develop an efficient transient thermal simulator, 3D Thermal-ADI, using the ADI method to simulate the 3-D temperature profile. Basically, the ADI method is an alternative solution method which instead of solving the three dimensional problems, solves a succession of three one-dimensional problems. Our simulator is not only unconditionally stable but also has a linear runtime and a linear memory usage. In order to analyze the thermal reliability of P/G network, we develop a SPICE-compatible thermal simulator, 3D Thermal-IEKS, for interconnect reliability analysis. The basic idea is to model the thermal simulation problem as electrical simulation problem. An adaptive approach is used to reduce the problem size and achieve enough accuracy. Then an improved extended Krylov subspace (IEKS) engine, independent of the number of input ports, is used for simulation.

  10. Mask blank defect printability comparison using optical and SEM mask and wafer inspection and bright field actinic mask imaging

    NASA Astrophysics Data System (ADS)

    Mangat, Pawitter; Verduijn, Erik; Wood, Obert R.; Benk, Markus P.; Wojdyla, Antoine; Goldberg, Kenneth A.

    2015-07-01

    Despite significant enhancements in defect detection using optical and e-beam methodology, the smaller length scales and increasing challenges of future technology nodes motivate ongoing research into the need and associated cost of actinic inspection for EUV masks. This paper reports an extensive study of two EUV patterned masks, wherein the mask blank defectivity was characterized using optical (mask and wafer) methods and bright-field mask imaging (using the SHARP actinic microscope) of previously identified blank defects. We find that the bright field actinic imaging tool microscope captures and images many defects that are not seen by the automated optical inspection of patterned masks and printed wafers. In addition, actinic review reveals the impact of multilayer damage and depicts the printability profile which can be used as an added metric to define the patterned mask repair and defect compensation strategies.

  11. A New Thinning Method for Obtaining Less than 100-nm-Thick Si Film on Wafer Bonding

    NASA Astrophysics Data System (ADS)

    Imai, Kazuo

    1991-06-01

    This paper proposes a new wafer thinning method in bonding silicon-on-insulator (SOI) technology. With this new method, thermal oxidation is performed on thin boron-doped Si films after highly selective back-etching to reduce the boron concentration in the film. The boron concentration in the silicon layer on oxide can be decreased more than 2 figures under proper thermal oxidation conditions. A 90-nm-thick silicon layer with 4 1017/cm3 boron concentration was formed on an insulator by this method. Transmission electron microscope (TEM) observation shows that the silicon layer has a highly crystalline quality. It is also found that the reflow of borophosphosilicate glass (BPSG) can effectively fill in the small surface gaps during wafer bonding.

  12. Wafer-level Au-Au bonding in the 350-450 °C temperature range

    NASA Astrophysics Data System (ADS)

    Tofteberg, Hannah R.; Schjølberg-Henriksen, Kari; Fasting, Eivind J.; Moen, Alexander S.; Taklo, Maaike M. V.; Poppe, Erik U.; Simensen, Christian J.

    2014-08-01

    Metal thermocompression bonding is a hermetic wafer-level packaging technology that facilitates vertical integration and shrinks the area used for device sealing. In this paper, Au-Au bonding at 350, 400 and 450 °C has been investigated, bonding wafers with 1 µm Au on top of 200 nm TiW. Test Si laminates with device sealing frames of 100, 200, and 400 µm in width were realized. Bond strengths measured by pull tests ranged from 8 to 102 MPa and showed that the bond strength increased with higher bonding temperatures and decreased with increasing frame width. Effects of eutectic reactions, grain growth in the Au film and stress relaxation causing buckles in the TiW film were most pronounced at 450 °C and negligible at 350 °C. Bond temperature below the Au-Si eutectic temperature 363 °C is recommended.

  13. Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

    NASA Astrophysics Data System (ADS)

    Altan, Hakan

    All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

  14. Formation and combustion characteristics of elephantgrass and energycane wafers

    NASA Astrophysics Data System (ADS)

    Mofleh, Mohamad I.

    Elephantgrass (Pennisetum purpureum Schum.) and energycane (Saccharum Spp.) are two cane type grasses. These are tall-growing perennial bunchgrasses that produce long hardened stems and grow in the tropics and subtropics. Traditionally, they have been used for forage and, in some regions, have been randomly burned on fields or disposed of uselessly. However, these plants have high dry matter yield and, thus, are excellent candidates as energy crops. Elephantgrass and energycane have been used for direct combustion in their loose form in large-scale applications. Several problems, many of which were attributed to their low bulk density, were encountered with using the materials. Consequently, this project was initiated to investigate the formation and combustion characteristics of the two materials in the form of small compact units called wafers. A hydraulic press that applied axial stresses on the material in four different dies was used. A load cell and a displacement transducer were utilized to measure the stresses and material detection. Wafer quality was evaluated using a tumbler built according to the American Society of Agricultural Engineers standards. In addition, a small stove was built to test wafer combustion. Thermocouples were used to measure temperatures during combustion. All the data gathered was transferred to a computer using a data acquisition system. It was found that the stress-deformation and stress-density relationships of elephantgrass and energycane were of exponential nature. Compaction energy required, which was calculated from the area under the force-deformation curves, ranged from 0.1 to 0.3% of their energy content. It was also found that wafer quality (durability) was mainly a function of wafer size and its final (relaxed) density in addition to material stem-to-leaf ratio and its crude protein content. Wafers possessed poor ignition quality but once ignited, they burned satisfactorily. The results indicated that sufficient and uniform combustion air distribution and a stove lining were critical factors in burning these materials. Further, the findings revealed that it may not be recommended to use elephantgrass or energycane in large-scale applications due to their high slagging index. Nonetheless, using them in small-scale applications may be possible. Elephantgrass was generally a better candidate for such an application.

  15. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    NASA Astrophysics Data System (ADS)

    McEwan, Alistair; van Schaik, André

    2003-12-01

    The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a) rate level functions for onset and steady-state response, (b) recovery after masking, (c) additivity, (d) two-component adaptation, (e) phase locking, (f) recovery of spontaneous activity, and (g) computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  16. VLSI Implementation of a Template Subtraction-Based Algorithm for Real-Time Stimulus Artifact Rejection

    PubMed Central

    Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J.; Mohseni, Pedram

    2015-01-01

    This paper presents very-large-scale integrated (VLSI) implementation of an infinite impulse response (IIR) temporal filtering technique for real-time stimulus artifact rejection (SAR) in bidirectional interfacing with the nervous system. The template subtraction-based, IIR-SAR algorithm is implemented on a ?W-level digital signal processing (DSP) unit that initializes its embedded 16b, 4K SRAM with the first recorded stimulus artifact to reduce the operation time in generating an accurate artifact template signal for subtraction. The DSP unit is integrated with spike-recording and microstimulation circuitry to create a functional, standalone, prototype system-on-chip (SoC) fabricated in AMS 0.35?m 2P/4M CMOS. The DSP unit functionality has been validated in benchtop tests using a prerecorded neural dataset from a laboratory rat, as well as in neurobiological experiments with isolated buccal ganglia of an Aplysia californica (a marine mollusk). The SoC can successfully remove mV-range stimulus artifacts with duration of <114.7ms from the contaminated neural data in real time and recover ?V-range extracellular neural spikes that occur on the tail end of the artifacts. The root-mean-square (rms) value of the pre-processed stimulus artifact is reduced on average by a factor of ~2430 post-processing, with DSP unit power consumption of <25?W from 1.5V. PMID:21095990

  17. Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI

    PubMed Central

    Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

    2011-01-01

    We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of high and low-firing activity. Depending on the overall excitability, transitions to the high state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the high state retains a working memory of a stimulus until well after its release. In the latter case, high states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted high states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical high state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons. PMID:22347151

  18. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    NASA Technical Reports Server (NTRS)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  19. Super Buffer: a systolic VLSI graphics engine for real-time raster image generation

    SciTech Connect

    Gharachlorloo, N.

    1985-01-01

    The new Super Buffer family of systems for real time generation of three dimensional, general-purpose, interactive and dynamic raster images is the subject of this thesis. In these systems the conventional 512 x 512 frame buffer is replaced by a 512 x 1 virtual scanline buffer. Image updating, buffering and refreshing are all performed by a single chip Systolic VLSI Raster Graphics Engine. The Engine is composed of an array of identical specialized Pixel Processors which collaborate to break the real time computation barrier by performing several billion Pixel operations per second in order to generate raster images in real time. A basic Super Buffer system has been successfully implemented and tested on a single prototype board connected to an IBM PC-AT. This approach is compared and contrasted to other high performance frame buffer based system architectures. The flexibility and power of the Super Buffer architecture is demonstrated by its ability to execute in real time the computationally intensive hidden surface removal and linear shading algorithms. Furthermore, the basic Super Buffer can be expanded in hardware to handle higher resolution displays and to generate images of high complexity, forming an entire family of systems with the same general architecture.

  20. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    NASA Astrophysics Data System (ADS)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jrgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithms competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.