Sample records for vlsi technology wafers

  1. Restructurable VLSI-a demonstrated wafer-scale technology

    Microsoft Academic Search

    PETER W. WYATT; JACK I. RAFFEL

    1989-01-01

    Restructurable VLSI (RVLSI) is an approach to wafer-scale integration which has been demonstrated by building six different monolithic silicon, wafer-scale chips for signal processing applications. It is based on the implementation of redundancy by laser microwelding on a finished, tested, packaged wafer. The concept of RVLSI is discussed, the chips built to data are reviewed, and some of the major

  2. Comparison of Wafer Scale Integration with VLSI Packaging Approaches

    Microsoft Academic Search

    C. Neugebauer; R. Carlson

    1987-01-01

    A comparison is made of various high-density packaging approaches, including printed wiring board, thick-film hybrids, and wafer scale integration (WSI). Criteria include power dissipation, density, delays, and cost. It is concluded that thin-film hybrids using state-of-the-art VLSI chips have the potential for WSI density and performance. The requirement for fault tolerance, additional levels of metallization, excess power dissipation, process conservatism

  3. The evolution of silicon wafer cleaning technology

    Microsoft Academic Search

    Werner Kern

    1990-01-01

    The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as RCA Standard Clean. This is still the primary method used in the industry. What

  4. Various Applications Of An Automated Wafer Inspection System In VLSI Manufacturing

    NASA Astrophysics Data System (ADS)

    Matsuda, Kimihiro; Takashima, Isamu; Aoki, Yasuo; Araki, Junichi

    1988-01-01

    Although the VLSI products produced in our manufacturing lines are mostly designed with 1 micron geometries, we expect the majority of products will shift to sub-micron design very soon. This article discusses results of our experiments to releaf human operators from the already difficult visual inspection tasks with a fully automated equipment. We have two groups of visual inspection tasks necessary on the VLSI manufacturing floor. One is Engineering Analysis and the other is in-line monitor, or Product Wafer Auditing. The former, Engineering Analysis, demands a variety of different measurements and inspections, such as line width, contact area, multilayer alignment precision and defect density. On the otherhand, Product Wafer Auditing, will need only one or two such functions per mo-nitoring point in the process, but will use the function more extensively, continuously, and repeatedly. In the manufacturing environment, where the ever pressing demand to increase yield is para-mount, it is crucial to reduce defect finding and analysing time. For that purpose, we need higher speed and accuracy for production wafer inspection than can be obtained with human inspectors. In this context, our experience on the KLA-2020, fully automated wafer inspection equipment has proven to be truely beneficial in the area of the following five different cases of evaluation of the KLA-2020, conducted in our plant. Case: 1. Visual inspection of the VLSI production wafer after aluminum dry-etching was studied in comparison with human operators. The result is that not only was the KLA-2020 much more thorough in detecting defects but also was much faster than any of the operators, by far. Case: 2. We applied the KLA-2020 to identify the cause of die, lost at probe test. We traced the killer defect, which was originated from the reticle. KLA-2020 is effective in reticle qualification. Case: 3. We found that the line-width instruments based upon laser scatterology cannot properly measure most of the dense 1 micron geometry of our VLSI devices. However, the KLA-2020 has provided excellent data of such Case: 4. During the course of process development, where the objective was to improve the LW uniformity within a production wafer, we found the efficiency and accuracy of the KLA-2020 were so good that the objective was met successfully in a very short time. In addition, the yield was improved remarkably. Case: 5. There have been no practical and simple methods to measure a small area in a pro-duction VLSI wafer. We will show the experimental results of measuring the area of contact holes in dropouts using the KLA-2020.

  5. A robust production control policy for VLSI wafer fabrication

    Microsoft Academic Search

    SHELDON X. C. LOU; PATRICK W. KAGER

    1989-01-01

    The authors present control policy for shop-level scheduling in a semiconductor wafer fabrication facility. The policy is designed to reduce the work in process in the shop floor and to follow the production plan as closely as possible. It is also robust against random interference such as machine breakdowns. The flow rate control policy is compared with two other approaches

  6. Fault-tolerant wafer-scale architectures for VLSI

    Microsoft Academic Search

    Donald S. Fussell; Peter J. Varman

    1982-01-01

    The basic problem which limits both yields and chip sizes is the fact that circuits created using current design techniques will not function correctly in the presence of even a single flaw of sufficient size anywhere on the chip. In this work we examine the problem of constructing chips up to the size of a wafer which operate correctly despite

  7. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  8. Wafer Inspection Technology For Submicron Devices

    NASA Astrophysics Data System (ADS)

    Okamoto, Kazunori; Yoshitome, Shokichi

    1989-07-01

    As processes advance into production of submicron devices, reducing defect density to an acceptable level is becoming a more difficult task. To deal with this problem, new wafer inspection technologies have been developed. The new systems can inspect dense patterned wafers to identify particles and process defects. An improvement over manual inspection is realized in defect sensitivity, inspection speed, and consistency of results. The technologies available for automatic wafer inspection have different capabilities. Therefore, to take advantage of each technology, the methods for system utilization must be considered. The methods involve identification of killer defects and determining the problem cause and required corrective action. This paper will focus on typical defects found in a submicron manufacturing facility. An evaluation of new wafer inspection technology will be described. Examples will be given to illustrate how inspection technology can be applied to solve problems in a production line.

  9. A wafer-scale 3-D circuit integration technology

    Microsoft Academic Search

    James A. Burns; Brian F. Aull; Chenson K. Chen; Chang-Lee Chen; Craig L. Keast; Jeffrey M. Knecht; V. Suntharalingam; K. Warner; P. W. Wyatt; D.-R. W. Yost

    2006-01-01

    The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.

  10. Wafer-level vacuum/hermetic packaging technologies for MEMS

    NASA Astrophysics Data System (ADS)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  11. Stresa, Italy, 25-27 April 2007 NOVEL BONDING TECHNOLOGIES FOR WAFER-LEVEL TRANSPARENT

    E-print Network

    Boyer, Edmond

    Stresa, Italy, 25-27 April 2007 NOVEL BONDING TECHNOLOGIES FOR WAFER-LEVEL TRANSPARENT PACKAGING costs of most devices. Aligned wafer bonding techniques for Wafer-level packaging (WLP) demonstrates presents well understood wafer bonding and bond alignment technologies as well as high-volume proven

  12. On board processor development for NASA's spaceborne imaging radar with VLSI system-on-chip technology

    Microsoft Academic Search

    Wai-chi Fang; Michael Y. Jin

    2004-01-01

    This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with VLSI system-on-chip technology. Finally, a minimum version of this VLSI on-board processor designed for performance evaluation and for partial demonstration is illustrated.

  13. Influence of wafer fabrication technology on wire bond process

    Microsoft Academic Search

    Chew Pei Yi

    2010-01-01

    Wire bond process is the main area bringing the package into functionality as it plays the main role into connecting between chip and lead frame. Therefore, the main concern in this process is the bond ability and reliability of the process. This paper will mainly discuss on the remaining challenges of wafer fabrication technology towards wire bond process. Therefore, a

  14. Three-dimensional shared memory fabricated using wafer stacking technology

    Microsoft Academic Search

    K. W. Lee; T. Nakamura; T. Ono; Y. Yamada; T. Mizukusa; H. Hashimoto; K. T. Park; H. Kurino; M. Koyanagi

    2000-01-01

    We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the

  15. VLSI technology for smaller, cheaper, faster return link systems

    NASA Technical Reports Server (NTRS)

    Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

    1994-01-01

    Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

  16. GaAs VLSI technology and circuit elements for DSP

    NASA Astrophysics Data System (ADS)

    Mikkelson, James M.

    1990-10-01

    Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

  17. Comparison of the radiation hardness of various VLSI technologies for defense applications

    SciTech Connect

    Gibbon, C.F.

    1985-01-01

    In this review the radiation hardness of various potential very large scale (VLSI) IC technologies is evaluated. IC scaling produces several countervailing trends. Reducing vertical dimensions tends to increase total dose hardness, while reducing lateral feature sizes may increase susceptibility to transient radiation effects. It is concluded that during the next decade at least, silicon complimentary MOS (CMOS), perhaps on an insulating substrate (SOI) will be the technology of choice for VLSI in defense systems.

  18. Optoelectronic-VLSI: photonics integrated with VLSI circuits

    Microsoft Academic Search

    Ashok V. Krishnamoorthy; Keith W. Goossen

    1998-01-01

    Optoelectronic-VLSI (OE-VLSI) technology represents the intimate integration of photonic devices with silicon VLSI electronics. We review the motivations and status of emerging OE-VLSI technologies and examine the performance of OE-VLSI technology versus conventional wire-bonded OE packaging. The results suggest that OE-VLSI integration offers substantial power and speed improvements even when relatively small numbers of photonic devices are driven with commodity

  19. Wafer level embedding technology for 3D wafer level embedded package

    Microsoft Academic Search

    Aditya Kumar; Xia Dingwei; Vasarla Nagendra Sekhar; Sharon Lim; Chin Keng; Gaurav Sharma; Vempati Srinivas Rao; Vaidyanathan Kripesh; John H. Lau; Dim-Lee Kwong

    2009-01-01

    This paper presents the development of wafer level embedding process for a three dimensional (3D) embedded micro wafer level package (EMWLP). Wafer level embedding process was carried out by using compression molding machine and low-cost granular epoxy molding compound (EMC). Various molding process parameters such as molding time and temperature and three EMCs of different CTEs were analyzed to achieve

  20. A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology

    Microsoft Academic Search

    Christopher Cook; John E. Cunningham; A. Hargrove; G. G. Ger; Keith W. Goossen; William Y. Jan; Helen H. Kim; R. Krause; M. Manges; M. Morrissey; M. Perinpanayagam; A. Persaud; George J. Shevchuk; Victor Sinyansky; Ashok V. Krishnamoorthy

    2003-01-01

    We describe the packaging and testing of a two-dimensional array parallel-optics module with 36 channels with each channel operating up to 3.3 Gb\\/s. This represents the first commercial module based on direct integration of vertical-cavity surface-emitting lasers (VCSELs) onto silicon very large scale integration (VLSI) circuits using a hybrid optoelectronic-VLSI technology. The module eliminates wire bonds between the driver\\/receiver chips

  1. Fabricating capacitive micromachined ultrasonic transducers with wafer-bonding technology

    Microsoft Academic Search

    Yongli Huang; A. Sanli Ergun; E. Haeggstrom; Mohammed H. Badi; B. T. Khuri-Yakub

    2003-01-01

    Introduces a new method for fabricating capacitive micromachined ultrasonic transducers (CMUTs) that uses a wafer bonding technique. The transducer membrane and cavity are defined on an SOI (silicon-on-insulator) wafer and on a prime wafer, respectively. Then, using silicon direct bonding in a vacuum environment, the two wafers are bonded together to form a transducer. This new technique, capable of fabricating

  2. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  3. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  4. Micro-machined dielectrically isolated (MMDI) wafer technology [SOI

    Microsoft Academic Search

    W. Cantarini; S. Lizotte; S. Ahmed

    1998-01-01

    This paper describes a new economical alternative to costly bonded silicon-on-insulator (BSOI) wafers in which dielectrically isolated wafers are fabricated from single bulk silicon wafers. Initial processing involves trench etching through a single wafer to a predefined depth using micro-machining tools. The trenches are filled with an insulator to provide lateral dielectric isolation. Standard semiconductor processing is performed. The back

  5. Kerf-free wafering: Technology overview and challenges for thin PV manufacturing

    Microsoft Academic Search

    Francois J. Henley

    2010-01-01

    Eliminating high absorber material loss while allowing thin and ultra-thin crystalline silicon PV has been a “Holy Grail” of the crystalline silicon PV industry for decades. Generally called “kerf-free wafering”, the fundamental approach is to substitute slurry saws with an alternative waste-free wafering technology. Ideally, the technology would also eliminate the difficulty to process thin to ultra-thin wafers inherent to

  6. Interconnection technologies for multichip assemblies (ITMA)-A UK Information Technology Engineering Directorate hybrid wafer scale project

    Microsoft Academic Search

    D. J. Pedder

    1993-01-01

    The Interconnection technology for multichip assemblies (ITMA) project is addressing the application of a silicon-substrate-based multichip module (MCM) technology to the requirements of parallel computing applications in the UK. The program involves activities on MCM design methodology, silicon substrate process technology, device assembly, module packaging technology, the design of VLSI devices specifically for MCM applications, and the implementation of advanced

  7. Innovative imaging technology opens new horizon to wafer inspection for advanced DRAM products

    Microsoft Academic Search

    M. Richter; C. Mata; A. Gratch; C. Fouquet

    2004-01-01

    Automated optical wafer inspection was introduced in the beginning of 90's when wafer fabrication entered the 200 mm wafer and sub-micron processing era in order to perform yield monitoring during ramp-up and volume production. Two technologies, Brightfield (BF) and Darkfield (DF) were adapted by the semiconductor industry. However, their evolution rapidly lagged behind the stringent demand for increased sensitivity at

  8. Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies

    NASA Astrophysics Data System (ADS)

    Michel, J.-C.; Le Denmat, J.-C.; Sungauer, E.; Robert, F.; Yesilada, E.; Armeanu, A.-M.; Entradas, J.; Sturtevant, J. L.; Do, T.; Granik, Y.

    2013-09-01

    Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a consequence, computational lithography solutions are currently under development in order to correct wafer topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer stack. In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC flow for chip scale mask correction is presented with quality and run time penalty analysis.

  9. A low cost wafer-level MEMS packaging technology

    Microsoft Academic Search

    P. Monajemi; F. Ayazi; P. J. Joseph; P. A. Kohl

    2005-01-01

    This paper presents a low-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied to a wide variety of MEMS devices after their fabrication sequence is completed. Our technique utilizes thermal decomposition of a sacrificial polymeric material through a polymer overcoat

  10. 17.5um thin Cu wire bonding for fragile low-K wafer technology

    Microsoft Academic Search

    Teo Chen; Kim Jude

    2010-01-01

    This paper describes the challenges of a 17.5um thin bare Cu wire bonding on aluminum bond pads for a fragile low-k wafer technology, on a BGA package. Previous evaluations have so far focused on 20um and 25um bare Cu wires as a suitable low cost replacement for Au wires. To improve performance, more fragile low-k wafer technology is being developed.

  11. Wafer-level vacuum packaging technology based on selective electroplating

    NASA Astrophysics Data System (ADS)

    Topart, Patrice A.; Leclair, Sebastien; Alain, Christine; Jerominek, Hubert

    2004-01-01

    A novel concept for low-cost, wafer-level packaging of MEMS is proposed and applied to vacuum packaging of INO"s 160x120 pixel uncooled bolometric focal plane arrays, FPAs, based on vanadium oxide thermistor material. A wafer-scale metallic tray composed of several tens of micropackages is electroplated by using the thick resist SU-8 as a micromold. FPA dies and infrared windows are then soldered to the main tray by flip-chip bonding. Contrary to the conventional wafer to wafer bonding approach, assembly and vacuum sealing steps are dissociated. For this purpose, each micropackage is equipped with a pump-out hole for outgassing under vacuum and at elevated temperature prior to vacuum sealing. The process flow for fabrication of micropackages is described. The influence of DC and pulse plating conditions on the stress and properties of deposited nickel packages was investigated. Results on the selective electroplating of indium solder on antireflection-coated IR window wafers and the formation of a solderable layer around the chip are presented.

  12. Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap

    Microsoft Academic Search

    Ashok V. Krishnamoorthy; David A. B. Miller

    1996-01-01

    Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs-AlGaAs multiple-quantum-well

  13. 2236 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 16, NO. 12, DECEMBER 1998 Wafer-Fused Optoelectronics for Switching

    E-print Network

    2236 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 16, NO. 12, DECEMBER 1998 Wafer-Fused Optoelectronics, Senior Member, IEEE, and John E. Bowers, Fellow, IEEE Abstract-- Wafer fusion technique for realization, optical waveguide components, wafer bonding. I. INTRODUCTION MAJOR requirements for optical packet

  14. 1144 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 10, OCTOBER 2007 Wafer-Level Modular Testing of Core-Based SoCs

    E-print Network

    Chakrabarty, Krishnendu

    2007 Wafer-Level Modular Testing of Core-Based SoCs Sudarshan Bahukudumbi, Student Member, IEEECs. To reduce packaging cost and the test cost for pack- aged chips, wafer-level testing (wafer sort) is used constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can

  15. Fast integral rigorous modeling applied to wafer topography effect prediction on 2x nm bulk technologies

    NASA Astrophysics Data System (ADS)

    Michel, J.-C.; Le Denmat, J.-C.; Tishchenko, A.; Jourlin, Y.

    2014-03-01

    Reflection by wafer topography and underlying layers during optical lithography can cause unwanted overexposure in the resist [1]. In most cases, the use of bottom anti reflective coating limits this effect. However, this solution is not always suitable because of process complexity, cost and cycle time penalty, as for ionic implantation lithography process in 28nm bulk technology. As a consequence, computational lithography solutions are currently under development to simulate and correct wafer topographical effects [2], [3]. For ionic implantation source drain (SD) photolithography step, wafer topography influences resulting in implant pattern variation are various: active silicon areas, Poly patterns, Shallow Trench Isolation (STI) and topographical transitions between these areas. In 28nm bulk SD process step, the large number of wafer stack variations involved in implant pattern modulation implies a complex modeling of optical proximity effects. Furthermore, those topography effects are expected to increase with wafer stack complexity through technology node downscaling evolution. In this context, rigorous simulation can bring significant value for wafer topography modeling evolution in R and D process development environment. Unfortunately, classical rigorous simulation engines are rapidly run time and memory limited with pattern complexity for multiple under layer wafer topography simulation. A presentation of a fast rigorous Maxwell's equation solving algorithm integrated into a photolithography proximity effects simulation flow is detailed in this paper. Accuracy, run time and memory consumption of this fast rigorous modeling engine is presented through the simulation of wafer topography effects during ionic implantation SD lithography step in 28nm bulk technology. Also, run time and memory consumption comparison is shown between presented fast rigorous modeling and classical rigorous RCWA method through simulation of design of interest. Finally, integration opportunity of such fast rigorous modeling method into OPC flow is discussed in this paper.

  16. 3D micro-optical lens scanner made by multi-wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Bargiel, S.; Gorecki, C.; Bara?ski, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frömel, J.

    2013-03-01

    We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

  17. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon, E-mail: dadembyora@mosfet.t.u-tokyo.ac.jp, E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); JST-CREST, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Yokoyama, Masafumi; Nakane, Ryosho [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Li, Jian; Kao, Yung-Chung [IntelliEPI, Inc., 1250 E. Collins Blvd., Richardson, Texas 75081 (United States)

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300?mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700?cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  18. Inertial sensor technology using DRIE and wafer bonding with connecting capability

    Microsoft Academic Search

    Kei Ishihara; Chi-Fan Yung; A. A. Ayon; Martin A. Schmidt

    1999-01-01

    A novel device structure utilizing deep reactive ion etching (DRIE) technology and aligned wafer bonding was developed. In this structure, an interconnecting scheme for electrical signal routing with signal crossovers is realized. Also, the `footing effect' and the `bowing effect,' which are inherent in DRIE processes, were investigated in detail. A mask layout strategy for solving the footing effect was

  19. Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Shi, Fang Frank

    Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

  20. Wafer-Level Transfer Technologies for PZT-Based RF MEMS Switches

    Microsoft Academic Search

    Roland Guerre; Ute Drechsler; Debabrata Bhattacharyya; Pekka Rantakari; Richard Stutz; Robert V. Wright; Zlatoljub D. Milosavljevic; Tauno Vaha-Heikkila; Paul B. Kirby; Michel Despont

    2010-01-01

    We report on wafer-level transfer technologies to integrate PZT-based radio frequency (RF) microelectromechanical-systems switches on CMOS. Such heterogeneous integration can overcome the incompatibility of PZT material with back-end-of-the-line (BEOL) CMOS technology. The PZT stack and the transfer process have been optimized to avoid degradation of the PZT actuators during the transfer. In particular, we have optimized the seed layer for

  1. Product assurance technology for custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

    1985-01-01

    The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

  2. High-voltage MOS transistors compatible with CMOS VLSI technology

    NASA Astrophysics Data System (ADS)

    Podmiotko, Wlodzimierz

    1992-08-01

    In this paper high-voltage MOS transistors structures fabricated using a standard CMOS technology and a special design technique are presented. The design, characterization, and modeling of n-MOS, with the breakdown voltage of 50 V, and p-MOS, with the breakdown voltage of 130 V, fabricated using a standard 3 micrometers CMOS process are discussed. In addition, the possibility of high-voltage buffer circuit realization which is composed of n-MOS and p-MOS transistors, operating with the supply system USS equals 0, UDD equals 5 V, UE equals - 40 V, self-isolated from low-voltage components is demonstrated.

  3. The reverse blocking IGBT for matrix converter with ultra-thin wafer technology

    Microsoft Academic Search

    M. Takei; T. Naito; K. Ueno

    2003-01-01

    An isolation type vertical 600V-50A IGBT with reverse blocking capability (RB-IGBT) has been developed for the first time. Ultra-thin wafer technology combined with deep boron diffusion technique results in a great improvement on trade-off performance. RB-IGBT can be used as a bi-directional switch by anti-parallel connection with another RB-IGBT. These bi-directional switches realize a high efficiency matrix converter.

  4. A novel fabrication technology for anti-reflex wafer-level vacuum packaged microscanning mirrors

    NASA Astrophysics Data System (ADS)

    Oldsen, M.; Hofmann, U.; Quenzer, H. J.; Janes, J.; Stolte, C.; Gruber, K.; Ites, M.; Sörensen, F.; Wagner, B.

    2008-02-01

    The use of microscanning mirrors in mobile laser projection systems demands for robust fabrication technologies. Dust, change in humidity and temperature can only be tolerated if the fragile devices are enclosed in a hermetic package. A novel fabrication process is presented based on two 30 micron thick epitaxially deposited silicon layers and a buried interconnection layer. This technology allows the fabrication of stacked combdrives for electrostatic mirror actuation and lateral feedthroughs needed for hermetic encapsulation with standard wafer bonding processes. High display resolution requires large scan angles of the mirror plate. Therefore, a fabrication technology for structured glass wafers is presented to provide deep cavities for large mirror plate movements. A solution for effective laser spot reflex suppression is presented based on a static tilt of the mirror plate in relation to the glass cover wafer during eutectic bonding. By doing so, the reflex generated at the glass surfaces is shifted out of the image area. The cavity pressure of packaged devices has been measured showing the necessity of a getter layer in order to provide cavity pressures below 1 mbar. The performance of a packaged device with integrated getter layer has been evaluated. A driving amplitude of only 6 V is needed to achieve scan angles of above 50 deg. White light interferometric measurements showed excellent planarity of the mirror plate with a radius of curvature of about 18 m.

  5. Wafer topography modeling for ionic implantation mask correction dedicated to 2x nm FDSOI technologies

    NASA Astrophysics Data System (ADS)

    Michel, Jean-Christophe; Le Denmat, Jean-Christophe; Sungauer, Elodie; Robert, Frédéric; Yesilada, Emek; Armeanu, Ana-Maria; Entradas, Jorge; Sturtevant, John L.; Do, Thuy; Granik, Yuri

    2013-04-01

    Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist [1]. This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technology node and below at the ionic implantation process. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but increases process complexity and adds cost and cycle time penalty. As a consequence, an OPC based solution is today under evaluation to cope with stack effects involved in ionic implantation patterning [2] [3]. For the source drain (SD) ionic implantation process step on 28nm Fully Depleted Silicon-on-Insulator (FDSOI) technology, active silicon areas, poly silicon patterns, Shallow Trench Isolation (STI), Silicon-on-Insulator (SOI) areas and the transitions between these different regions result in significant SD implant pattern critical dimension variations. The large number of stack variations involved in these effects implies a complex modeling to simulate pattern degradations. This paper deals with the characterization of stack effects on 28nm node using SOI substrates. The large number of measurements allows to highlight all individual and combined stack effects. A new modeling flow has been developed in order to generate wafer stack aware OPC model. The accuracy and the prediction of the model is presented in this paper.

  6. 1.5 ?m to 0.87 ?m optical upconversion using wafer fusion technology

    NASA Astrophysics Data System (ADS)

    Luo, H.; Ban, D.; Liu, H. C.; Springthorpe, A. J.; Wasilewski, Z. R.; Buchanan, M.; Glew, R.

    2004-05-01

    Wafer fusion is an important processing tool for heterogenous integration of different materials regardless of their lattice constants. It removes the limitation of conventional epitaxial growth techniques and introduces a design parameter for achieving high performance semiconductor devices. In this article, we propose and demonstrate a 1.5 ?m to 0.87 ?m optical upconversion device based on wafer fusion technology. The device consists of an In0.53Ga0.47As (InGaAs) p-i-n photodetector and an AlGaAs/GaAs light-emitting diode (LED) integrated with wafer fusion. Incoming 1.5 ?m light is absorbed by the InGaAs photodetector and generates a photocurrent. The resultant photocurrent drives the GaAs LED, which emits radiation at 0.87 ?m. An internal quantum efficiency of 20% and an external quantum efficiency of 0.27% was obtained at room temperature. The results show the potential of the upconversion device in near-infrared imaging applications.

  7. VLSI neuroprocessors

    NASA Technical Reports Server (NTRS)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional techniques and enables multiple assignments, (many to many), not achievable with standard statistical approaches. Tactical movement planning (finding the best path from A to B) is accomplished with a digital two-dimensional concurrent processor array. By exploiting the natural parallel decomposition of the problem in silicon, a four order of magnitude speed-up over optimized software approaches has been demonstrated.

  8. Abstract--Novel technologies like substrate transfer technology can introduce severe topography on otherwise flat silicon wafers.

    E-print Network

    Technische Universiteit Delft

    on otherwise flat silicon wafers. Since optical lithography is usually performed on ultra flat wafers, the alignment system is not optimized for high topography wafers. In this work, an experimental procedure is presented to measure the alignment offset of an ASML PAS5000/50 waferstepper on high topography wafers

  9. High performance VLSI for space and commercial applications

    Microsoft Academic Search

    G. K. Maki; H. C. Shaw; K. Q. Chen

    1996-01-01

    High performance VLSI is a key electronic technology required to advance science and commercial space missions. This paper illustrates several such NASA applications which require special purpose VLSI. In addition to being able to solve unique scientific problems, specialized VLSI can provide breakthrough technology for new commercial products. For example, the basic technology used to solve a key problem for

  10. Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si\\/low-k CMOS technology

    Microsoft Academic Search

    P. R. Morrow; C.-M. Park; S. Ramanathan; M. J. Kobrinsky; M. Harmes

    2006-01-01

    The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si\\/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETs and 4-MB SRAMs were bonded face-to-face using copper pads with size ranging between 5 ?m×5 ?m and 6 ?m×40 ?m. The top wafers were thinned to different thicknesses in the

  11. Plate-like structure health monitoring based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers

    NASA Astrophysics Data System (ADS)

    Liu, Zenghua; Zhao, Jichen; He, Cunfu; Wu, Bin

    2008-11-01

    Piezoelectric ceramic wafers are applied for the excitation and detection of ultrasonic guided waves to determine the health state of plate-like structures. Two PZT wafers, whose diameter is 11mm and thickness is 0.4mm respectively, are bonded permanently on the surface of a 1mm thick aluminum plate. One of these wafers is actuated by sinusoidal tone burst at various frequencies ranging from 100kHz to 500kHz, the other one is used as a receiver for acquiring ultrasonic guided wave signals. According to the amplitudes and shapes of these received signals, guided wave modes and their proper frequency range by using these wafers are determined. For the improvement of the signal-to-noise ratio, the Daubechies wavelet of order 40 is used for signal denoising as the mother wavelet. Furthermore, the detection of an artificial cylindrical through-hole defect is achieved by using S0 at 300kHz. Experimental results show that it is feasible and effective to detect defects in plate-like structures based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers.

  12. Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing

    NASA Astrophysics Data System (ADS)

    Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

    2005-09-01

    The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore the capability of the tool for characterizing multiple geometric parameters associated with the manufacturing process that are important to the yield and performance of advanced bottle DRAM devices.

  13. Multimedia systems play a central part in many human activities. Due to the significant advances in the VLSI technology, there is an

    E-print Network

    Pedram, Massoud

    Abstract Multimedia systems play a central part in many human activities. Due to the significant advances in the VLSI technology, there is an increasing demand for portable multimedia appliances capable a steady move from stand- alone (or desktop) multimedia to deeply distributed multimedia systems. Whereas

  14. Application of a new laser scanning pattern wafer inspection tool to leading edge memory and logic applications at Infineon Technologies

    Microsoft Academic Search

    T. Reuter; U. Bohmler; S. Steck; M. McLaren; Siqun Xiao; R. Howland Pinto

    1999-01-01

    A new patterned wafer laser-based inspection tool has been introduced to the market place, incorporating double darkfield laser scanning technology. Developed from a well-known production-proven platform, the new system is intended to provide the sensitivity required for 0.18 ?m design rules, with extendibility to 0.13 ?m. The inspection technology combines low angle laser illumination with dual darkfield scattered light collection

  15. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  16. Ultra-high heat flux cooling characteristics of cryogenic micro-solid nitrogen particles and its application to semiconductor wafer cleaning technology

    NASA Astrophysics Data System (ADS)

    Ishimoto, Jun; Oh, U.; Guanghan, Zhao; Koike, Tomoki; Ochiai, Naoya

    2014-01-01

    The ultra-high heat flux cooling characteristics and impingement behavior of cryogenic micro-solid nitrogen (SN2) particles in relation to a heated wafer substrate were investigated for application to next generation semiconductor wafer cleaning technology. The fundamental characteristics of cooling heat transfer and photoresist removal-cleaning performance using micro-solid nitrogen particulate spray impinging on a heated substrate were numerically investigated and experimentally measured by a new type of integrated computational-experimental technique. This study contributes not only advanced cryogenic cooling technology for high thermal emission devices, but also to the field of nano device engineering including the semiconductor wafer cleaning technology.

  17. Study on the use of VLSI ASIC technology for generic power system computer relay architectures

    E-print Network

    Faulkner, Kenneth Ray

    1994-01-01

    this form of noise. The geometry and terinination impedances will effect the severity of the 11 noise. SPICE has been used to model the performance degradation due to cross-talk in PCBs. [13] Due to the much smaller inductances involved in VLSI, this form... for this implementation [8]. Figure 3 Simple Sample/Hold Circuit [10] While sigma-delta modulators for analog/digital conversion are common, Olivier and Dijkstra maintain that classical sigma-delta modulators are not ideal for signals that are multiplexed into the A...

  18. VLSI design automation assistant: learning to walk

    Microsoft Academic Search

    T. J. Kowalski; D. E. Thomas

    1983-01-01

    This paper describes an approach to VLSI design synthesis using both knowledge-based expert systems and data and control flow analysis. The authors are concerned with design synthesis as it proceeds from an algorithmic description of a VLSI system to a list of technology-independent registers, operators, data paths, and control signals. This paper discusses the development of the design automation assistant

  19. Performance optimization of VLSI interconnect layout

    Microsoft Academic Search

    Jason Cong; Lei He; Cheng-kok Koh; Patrick H. Madden

    1996-01-01

    This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design un- der the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver\\/gate delay models of various degrees of accuracy and efficiency

  20. A LOW COST WAFER-LEVEL MEMS PACKAGING TECHNOLOGY Pejman Monajemi, Paul J. Joseph*

    E-print Network

    Ayazi, Farrokh

    thermal decomposition of a sacrificial polymeric material through a polymer overcoat cap, and can-on-insulator resonators, and thick silicon gyroscopes and accelerometers are presented. I. INTRODUCTION Wafer sacrificial material, Unity 2000 (Promerus, LLC) [9,10], through a spin-coated solid polymer overcoat, Avatrel

  1. Single-Mask, Flip-Bonded Titanium-On-Glass (FBTOG) Technology for Wafer-Level Batch Fabrication of Suspended High-Aspect-Ratio Bulk Titanium Microstructures

    Microsoft Academic Search

    Y. Zhang; G. Zhao; Q. Shu; Y. Tian; W. Li; J. Chen

    2009-01-01

    A Flip-Bonded Titanium-On-Glass (FBTOG) technology, which combines titanium Inductively-Coupled-Plasma (ICP) deep etching and adhesive wafer bonding technique, was developed to fabricate suspended in-plane high-aspect-ratio bulk titanium microstructures at wafer level. 25?m thick suspended structures with a trench aspect ratio of about 10 are demonstrated. A 2200?m-long comb-drive actuated bulk titanium lateral relay showed a contact resistance of 2.3? at a

  2. Free-standing CVD diamond wafers for thermal management by d.c. arc jet technology

    Microsoft Academic Search

    K. J Gray; H Windischmann

    1999-01-01

    Because of the unfavorable mechanical properties of diamond, the source and type of stresses present must be identified and controlled at every stage of the CVD diamond deposition process in order to develop a high-yield, large-wafer-scale fabrication process. In this paper, we report on the types of defect and stress encountered in free-standing CVD diamond films deposited by d.c. arc

  3. Advances in production methods in VLSI and ULSI technology using isolated-chamber sputter deposition of Al 1% Si films

    Microsoft Academic Search

    Y. K. Ahn; C. S. Oh; W. J. Hwang; J. W. Koh; Y. W. Song; G. S. Cho; C. G. Ko; D. J. Harra; Y. K. Kim; J. van Gogh; C. H. Shin

    1990-01-01

    Sputtering process optimization is described as related to steady-state production of VLSI and ULSI devices using isolated deposition modules in a production environment. Improvements in step coverage for Al-1%-Si, obtained over VLSI and ULSI level topology typical of 1-Mb to 16-Mb semiconductor devices, are described, and data are presented. Techniques for improving the average step coverage and the worst-case step

  4. A High Aspect-Ratio Silicon Substrate-ViaTechnology and Applications: Through-Wafer Interconnects for Power and Ground and Faraday Cages for SOC Isolation

    E-print Network

    del Alamo, Jesús A.

    technology can also be exploited to reduce crosstalk in RF circuits and improve subsystem isolation in RFA High Aspect-Ratio Silicon Substrate-ViaTechnology and Applications: Through-Wafer Interconnects for Power and Ground and Faraday Cages for SOC Isolation Joyce H. Wu, Jesds A. del Alamo, and Keith A

  5. MIT Microsystems Technology LaboratoriesMIT Microsystems Technology LaboratoriesDavid White, Duane Boning and Aaron GowerDavid White, Duane Boning and Aaron Gower Characterization of Endpoint and Wafer LevelCharacterization of Endpoint and Wafer Level

    E-print Network

    Boning, Duane S.

    Boning and Aaron GowerDavid White, Duane Boning and Aaron Gower Characterization of Endpoint and Wafer LevelCharacterization of Endpoint and Wafer Level NonNon--Uniformity using InUniformity using In and Aaron Gower Outline of PresentationOutline of Presentation ·· Overview: Wafer Scale Endpoint Uniformity

  6. Analysis and optimization of VLSI Clock Distribution Networks for skew variability reduction 

    E-print Network

    Rajaram, Anand K.

    2004-11-15

    As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution ...

  7. Toward 300 mm wafer-scalable high-performance polycrystalline chemical vapor deposited graphene transistors.

    PubMed

    Rahimi, Somayyeh; Tao, Li; Chowdhury, Sk Fahad; Park, Saungeun; Jouvray, Alex; Buttress, Simon; Rupesinghe, Nalin; Teo, Ken; Akinwande, Deji

    2014-10-28

    The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26,000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ? 74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ? 40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available. PMID:25198884

  8. Low temperature full wafer adhesive bonding of structured wafers

    Microsoft Academic Search

    F. Niklaus; H. Andersson; P. Enoksson; G. Stemme

    2001-01-01

    In this paper, we present a technology for void free low temperature full wafer adhesive bonding of structured wafers. Benzocyclobutene (BCB) is used as the intermediate bonding material. BCB bonds well with various materials and does not release significant amounts of by-products during the curing process. Thus void-free bond interfaces can be achieved. Cured BCB coatings have an excellent resistance

  9. Wafer scale nano-membranes supported on a silicon microsieve using thin-film transfer technology

    NASA Astrophysics Data System (ADS)

    Unnikrishnan, Sandeep; Jansen, Henri; Berenschot, Erwin; Elwenspoek, Miko

    2008-06-01

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independent of the thin film, which is later transferred onto it by fusion bonding, thus providing flexibility in design and processing steps. Using this thin-film transfer technique, nano-membranes down to 50 nm thickness are fabricated. The fabrication of different kinds of membranes made of inorganic, metallic and polymer materials is presented here. Apart from dense nano-membranes, perforated membranes are fabricated using this modular approach. One of the main areas of interest for such membranes is in fluidics, where the low thickness and high strength of the supported nano-membranes are a big advantage.

  10. Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review

    Microsoft Academic Search

    Sang Hwui Lee; Kuan-Neng Chen; James Jian-Qiang Lu

    2011-01-01

    This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an im- portant manufacturing technique for advanced microelectronics and microelectromechanical systems, including 3-D integrated circuits, advanced wafer-level packaging, and microfluidics. Commercially available alignment tools provide prebonding wafer-to-wafer misalignment tolerances on the order of 0.25 µm. However, better alignment accuracy is required for increasing demands

  11. Fault Emulation for Dependability Evaluation of VLSI Systems

    Microsoft Academic Search

    David De Andrés; Juan Carlos Ruiz; Daniel Gil; Pedro J. Gil

    2008-01-01

    Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the

  12. Silicon TSV interposers for photonics and VLSI packaging

    NASA Astrophysics Data System (ADS)

    Vodrahalli, N.; Li, C. Y.; Kosenko, V.

    2011-02-01

    Miniaturization, higher performance, and higher bandwidth needs of the electronic industry continue to drive technology innovations through increased levels of integration. Through Silicon Via (TSV) technology along with flip chip technology provides significant improvements over the traditional technologies for packaging VLSI circuits. Silicon Interposers built using TSVs and embedded capacitors provide solutions to the next generation needs of VLSI Packaging. TSV Si interposers also provide a paltform for integrating photonic elements like the laser diodes and optical fibers for next generation high bandwidth VLSI packaging. The presentation describes (i) the TSV technologies developed, (ii) implementation of Si TSV interposer with embedded capacitors for VLSI packaging, and (iii) development of Si TSV interposer for integration of photonics and VLSI subsystems. Reliability results of interposers with embedded capacitors are also presented.

  13. Customizable VLSI artificial neural network chips based on a novel technology

    SciTech Connect

    Fu, C. Y.; Law, B.; Chapline, G. [Lawrence Livermore National Lab., CA (United States); Swenson, D. [Naval Air Warfare Center, China Lake, CA (United States)

    1993-09-14

    The human cerebral cortex contains approximately 10{sup 11} neurons and 10{sup 14} synapses. It thus seems logical that any technology intended to mimic human capabilities should have the ability to fabricate a very large number of neurons and even larger numbers of synapses. This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems.

  14. APPLIED PHYSICS REVIEWSFOCUSED REVIEW Adhesive wafer bonding

    E-print Network

    Salama, Khaled

    APPLIED PHYSICS REVIEWS­FOCUSED REVIEW Adhesive wafer bonding F. Niklausa Microsystem Technology 9 February 2006 Wafer bonding with intermediate polymer adhesives is an important fabrication-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive

  15. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  16. Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction

    Microsoft Academic Search

    Zhuo Feng; Guo Yu; Peng Li

    2007-01-01

    Parameterized circuit models are desired at various VLSI design stages to account for the increasing process-induced performance variations. However, the large number of process variation sources encountered in modern VLSI technologies often lead to overly complex parameterized models whose generation as well as application is computationally expensive. In this paper, we address this challenge by proposing a general VLSI parameter

  17. Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding

    E-print Network

    Spearing, S. Mark

    Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

  18. Wafer to wafer overlay control algorithm implementation based on statistics

    NASA Astrophysics Data System (ADS)

    Lee, Byeong Soo; Kang, Young Seog; Kong, Jeong Heung; Hwang, Hyun Woo; Song, Myeong Gyu

    2015-03-01

    For mass production of DRAM device, a stable and effective overlay control becomes more and more important as DRAM design rule shrinks. Existent technologies were already applied to overcome this situation. Nevertheless, we are still suffered from tight overlay margin and forced to move from lot-based to wafer-based overlay control. However, the wafer-based control method requires a huge amount of measurement resource. In this paper, we present the insight for the wafer-based overlay correction with optimal measurement resource which is suitable for mass production. The experiment which is the wafer-based overlay correction by several statistical analyses carried out for 2X nm node DRAM. Among them, linear regression is a strong candidate for wafer-based overlay control, which improved up to 0.8 nm of maximum overlay.

  19. A novel technology for fabricating customizable VLSI artificial neural network chips

    SciTech Connect

    Fu, C.Y.; Law, B.; Chapline, G. [Lawrence Livermore National Lab., CA (United States); Swenson, D. [Naval Air Warfare Center, China Lake, CA (United States)

    1992-02-05

    This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems. These neural networks are programmed using precision laser cutting and deposition. The fast turnaround of laser-based customization allows us to explore different neural network architectures and to rapidly program the synaptic weights. Our customizable chip allows us to expand an artificial network laterally and vertically. This flexibility permits us to build very large neural network systems.

  20. System-on-Wafer: 2-D and 3-D Technologies for Heterogeneous Systems

    Microsoft Academic Search

    Jean-Charles Souriau; Nicolas Sillon; Jean Brun; Hervé Boutry; Thierry Hilt; David Henry; Gilles Poupon

    2011-01-01

    System integration, performance, cost and enhanced product functionality form the major driving forces behind contemporary innovations in packaging. The need for minia- turization has led to new architectures which combine a whole range of different technologies. The ultimate miniaturization goal is to incorporate all of the elements necessary to build the system in the same package. This approach of system-in-package

  1. Atomically Flat Silicon Surface and Silicon\\/Insulator Interface Formation Technologies for (100) Surface Orientation Large-Diameter Wafers Introducing High Performance and Low-Noise Metal–Insulator–Silicon FETs

    Microsoft Academic Search

    Rihito Kuroda; Tomoyuki Suwa; Akinobu Teramoto; Rui Hasebe; Shigetoshi Sugawa; Tadahiro Ohmi

    2009-01-01

    Technology to atomically flatten the silicon surface on (100) orientation large-diameter wafer and the formation technology of an atomically flat insulator film\\/silicon interface are developed in this paper. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200-mm-diameter wafers by annealing in pure argon ambience at 1200degC for 30 min. Atomically flat surfaces with

  2. Design automation for wafer scale integration

    SciTech Connect

    Donlan, B.J.

    1986-01-01

    Wafer scale integration (WSI) is a technique for implementing large digital systems on a single wafer. This thesis describes a system of design automation tools developed to aid in the implementation of wafer scale integrated systems. An overview of wafer scale integration is given with fabrication details and yield considerations discussed. The Wafer architectural Design Language (WDL) used to describe and specify a system architecture to the development system is introduced along with a compiler that translates the high level WDL description into net lists and other internal data bases. Interactive placement tools used to map the system architecture onto the functional die sites on a wafer are described. A very fast line probe router was developed to perform the custom wafer level routing need to personalize each wafer. Router data structures, algorithms, techniques, and results are discussed in detail. Sample wafer scale architectures and the result of their WSI implementations are shown. Also presented is the Wafer Transmission Module (WTM) a packaging technology related to wafer scale integration.

  3. VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.

    PubMed

    Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip

    2014-01-01

    Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (?1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology. PMID:24628497

  4. Layout optimization in ultra deep submicron VLSI design 

    E-print Network

    Wu, Di

    2006-08-16

    As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several ...

  5. Algorithmic techniques for nanometer VLSI design and manufacturing closure 

    E-print Network

    Hu, Shiyan

    2008-10-10

    As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip and power density. Imperfections due to process, voltage and temperature...

  6. IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY, VOL. 9, NO. 2, MARCH 2001 381 Multivariable Feedback Relevant System Identification of a Wafer Stepper

    E-print Network

    Van den Hof, Paul

    Feedback Relevant System Identification of a Wafer Stepper System Raymond A. de Callafon and Paul M. J. Van of a positioning mechanism present in a wafer stepper. The positioning mechanism in a wafer stepper is used in chip manufacturing processes for accurate posi- tioning of the silicon wafer on which the chips are to be produced

  7. VLSI layout of a pipelined multiplier

    Microsoft Academic Search

    B. Shirazi; Pradipto Mukherjee

    1988-01-01

    The proposed multiplier views the operations as a logical one, without using addition or counting. Such a novel view provides grounds for a high pipeline throughput. The authors discuss the algorithm and then the cell design, cell placement, and a routing scheme in the VLSI layout of the proposed multiplier using CMOS technology. Then they compare their design against a

  8. Security Challenges During VLSI Test David Hely

    E-print Network

    Tomkins, Andrew

    Security Challenges During VLSI Test David H´ely LCIS Grenoble Institute of Technology Valence be breached through testing security breaches. In this paper we review testing security problems, focusing their characteristics. I. INTRODUCTION Integrated circuit testing has emerged in recent years as a new security problem

  9. Silicon Wafer Epitaxy

    NSDL National Science Digital Library

    This Quicktime animation shows an optional process for creating silicon epitaxial wafers. The animations shows a trichlorosilane gas being injected which creates a monocrystaline film atop the preexisting wafer. This is the seventh animation in a series of how silicon wafers are created. The previous animation showing silicon wafer polishing can be seen here.The next and final animation in this sequence about silicon wafer laser inspection can be seen here.

  10. In-Situ Optical Wafer Temperature Measurement

    NASA Astrophysics Data System (ADS)

    Adams, Bruce; Schietinger, Chuck

    2003-09-01

    The need for increasingly tighter process control is eminently apparent as semiconductor device dimensions become smaller and wafers larger. Today "Thermal Budgets" are shrinking and ramp rates are increasing throughout wafer processing. Wafer temperature is perhaps the most universally critical process variable in front-end integrated circuits (IC) manufacturing. The use of pyrometry and optical lightpipes continues to gain widespread acceptance as the standard temperature control method in many processes. Lightpipes are used for controlling temperature in chemical vapor deposition (CVD), rapid thermal processing (RTP), epitaxial film growth (EPI) and physical vapor deposition (PVD). Optical thermometry offers numerous advantages over other forms of wafer temperature measurement. This paper presents the current strengths and limitations in optical wafer temperature measurement. Many factors continue to drive the measurement technology. As IC junctions become shallower, thermal budget concerns drive process temperatures down. Processing time and ramp rates continue to shorten in particular for implant anneals. Increasingly, process control requires complete thermal histories of wafers throughout IC manufacturing. These factors and new materials (copper and low-? dielectrics) push tool manufactures and pyrometer vendors toward lower temperatures while still requiring high sensitivity, and accuracy. The accuracy of most in-situ optical temperature measurement continues to be dominated by uncertainty in wafer emissivity. Factors that limit accuracy, e.g., from wafer to wafer and from tool to tool, and advances in the technology are discussed.

  11. Detection of electromigration in VLSI metalizations layers by low-frequency noise measurements

    Microsoft Academic Search

    W. Yang; Z. Clik-Butler; H. H. Hoang; W. R. Hunter

    1989-01-01

    A fast, nondestructive, wafer-level method of detecting and characterizing electromigration in VLSI interconnections is presented. Low-frequency (LF) noise measurements have been used to predict lifetimes of aluminum metallization layers. The correlation between mechanisms causing these LF fluctuations and electromigration was investigated. It was found that the activation energies measured using LF noise techniques correspond closely to those for electromigration mechanisms.

  12. Modeling of defect propagation\\/growth for in-line defect inspection optimization in VLSI fabrication

    Microsoft Academic Search

    Xiaolei Lis; A. Strojwas; M. Reddy; L. Milor; Y. T. Lin

    1997-01-01

    Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material and the underlying IC topography. A rigorous 2D topography simulator METROPOLE, has been developed to allow the prediction and

  13. Restructurable VLSI program

    NASA Astrophysics Data System (ADS)

    Oleary, G. C.

    1985-03-01

    This report describes work performed on the Restructurable VLSI Program sponsored by the information Processing Techniques Office of the Defense Advanced Research Projects Agency during the period 1 October 1984 through 31 March 1985.

  14. Restructurable VLSI program

    NASA Astrophysics Data System (ADS)

    Blankenship, P. E.

    1982-10-01

    This report describes work on the Reconstructable VLSI Research Program sponsored by the Information Processing Techniques Office of the Defense Advanced Research Projects Agency during the semiannual period 1 October 1981 through 31 March 1982.

  15. Restructurable VLSI program

    SciTech Connect

    Blankenship, P.E.

    1982-03-01

    This report describes work on the Reconstructable VLSI Research Program sponsored by the Information Processing Techniques Office of the Defense Advanced Research Projects Agency during the semiannual period 1 October 1981 through 31 March 1982.

  16. Performance comparison between optoelectronic and VLSI multistage interconnection networks

    Microsoft Academic Search

    Fouad E. Kiamilev; Philippe Marchand; Ashok V. Krishnamoorthy; Sadik C. Esener; Sing H. Lee

    1991-01-01

    The performance characteristics of optoelectronic and VLSI multistage interconnection networks are compared. The bases of the comparison include speed, bandwidth, power consumption, and footprint area. The communication network used in the comparison is a synchronous packet-switched multistage interconnection network built from 2×2 bit-serial switching elements. CMOS technology was used in the VLSI implementation, and it is assumed that the entire

  17. Integrating Through-Wafer Interconnects With Active Devices and Circuits

    Microsoft Academic Search

    Jim Jozwiak; Richard G. Southwick; III; Vaughn N. Johnson; William B. Knowlton; Amy J. Moll

    2008-01-01

    Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside

  18. NASA VLSI 2007 Ghai, Mohanty &

    E-print Network

    Mohanty, Saraju P.

    NASA VLSI 2007 Ghai, Mohanty & Kougianos 1 A 45nm Flash Analog to Digital Converter for Low Voltage dhruva@unt.edu #12;NASA VLSI 2007 Ghai, Mohanty & Kougianos 2 Outline Introduction and Motivation and Future Works #12;NASA VLSI 2007 Ghai, Mohanty & Kougianos 3 Introduction and Motivation ADCs

  19. Multiwire slurry wafering demonstrations

    Microsoft Academic Search

    C. P. Chen

    1978-01-01

    Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m\\/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of

  20. Scheduling semiconductor wafer fabrication

    Microsoft Academic Search

    LAWRENCE M. WEIN

    1988-01-01

    The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

  1. Silicon Wafer Polishing

    NSDL National Science Digital Library

    This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

  2. Wafer Level Chip Scale Packaging

    Microsoft Academic Search

    Michael Töpper

    \\u000a Wafer Level Packaging (WLP) based on redistribution is the key technology which is evolving to System in Package (SiP) and\\u000a Heterogeneous Integration (HI) by 3-D packaging using Through Silicon Vias (TSV). Materials and process technologies are key\\u000a for a reliable WLP. It is not only the choice for the right polymer or metal but the interfaces could be even more

  3. Silicon Wafer Lapping

    NSDL National Science Digital Library

    This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

  4. Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

    Microsoft Academic Search

    Massoud Pedram; Shahin Nazarian

    2006-01-01

    The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections.

  5. Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits

    Microsoft Academic Search

    Atul Maheshwari; Israel Koren; Wayne Burleson

    2003-01-01

    Transient faults in VLSI circuits could lead to disastrousconsequences. With technology scaling, circuitsarebecomingincreasinglyvulnerabletotransientfaults. Thispaperspresentsanaccurateand e-cient method to estimate fault-sensitivity of VLSI circuits. Using a binary counter and an RC5 encryption implementation as examples, this paper shows that by performing a limited amount of randomsimulations,faultsensitivitycanbeestimatedaccuratelyatareasonablylowcomputational cost. Thismethodisthenusedtoshowthatthecombinationoftwocircuitleveltechniquescanmake circuits more fault-tolerant than using these techniques individually.

  6. Analog VLSI Implementation of Artificial Neural Networks with Supervised On-Chip Learning

    Microsoft Academic Search

    Maurizio Valle

    2002-01-01

    Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and\\/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities

  7. Wafer level chip scale packaging (WL-CSP): an overview

    Microsoft Academic Search

    Philip Garrou

    2000-01-01

    Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when

  8. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    None

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  9. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  10. 30-40GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

    Microsoft Academic Search

    Frank Ellinger; Lucio Carlo Rodoni; Gion Sialm; Christian Kromer; G. von Buren; M. L. Schmatz; C. Menolfi; T. Toifl; T. Morf; M. Kossel; H. Jackel

    2004-01-01

    In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS technology. All impedance matching, bias, and filter elements are implemented on the

  11. Reliable VLSI sequential controllers

    Microsoft Academic Search

    Sterling R. Whitaker; Gary K. Maki; Manjunath Shamanna

    1991-01-01

    A VLSI architecture for synchronous sequential controllers is resented that has attractive qualities for roducing reliable circuits. In these circuits, one hardware implementation can realize any flow table with a maximum of 2n internal states and m inputs. A real time fault detection means is resented along with a strategy for verifying the correctness of the checking hardware. This self-check

  12. Image quality and wafer level optics

    NASA Astrophysics Data System (ADS)

    Dagan, Y.; Humpston, G.

    2010-05-01

    Increasing demand from consumers to integrate camera modules into electronic devices, such as cell phones, has driven the cost of camera modules down very rapidly. Now that most cell phones include at least one camera, consumers are starting to ask for better image quality - without compromising on the cost. Wafer level optics has emerged over the past few years as an innovative technology enabling simultaneous manufacturing of thousands of lenses, at the wafer level. Using reflow-compatible materials to manufacture these lenses permits a reduction in the cost and size of camera module, thus answering the market demand for lowering the cost. But what about image quality? The author will present image quality analysis that was conducted for both VGA and megapixel camera resolutions. Comparison between conventional camera modules and wafer level camera modules shows wafer level technology brings equivalent, if not better, image quality performance compared to conventional camera modules.

  13. Semiconductor Wafer Bonding

    Microsoft Academic Search

    U. Gosele; Q.-Y. Tong

    1998-01-01

    When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical

  14. Ablation and cleaning of wafer surface by excimer laser

    Microsoft Academic Search

    Yong-Kee Kim; Dae-Jin Kim; Je-Kil Ryu; Sung-Sik Pak

    2001-01-01

    The importance of surface cleaning is an essential factor in VLSI technology, flat panel display, and data storage devices. The results of laser cleaning technology were studied using KrF excimer laser (248 nm) irradiation in cleanroom environment. The applied energy density was 200 - 800 mJ\\/cm2 at a repetition rate of 10 - 40 Hz with various focused beam widths.

  15. Verification of VLSI designs

    NASA Technical Reports Server (NTRS)

    Windley, P. J.

    1991-01-01

    In this paper we explore the specification and verification of VLSI designs. The paper focuses on abstract specification and verification of functionality using mathematical logic as opposed to low-level boolean equivalence verification such as that done using BDD's and Model Checking. Specification and verification, sometimes called formal methods, is one tool for increasing computer dependability in the face of an exponentially increasing testing effort.

  16. Optical receivers for optoelectronic VLSI

    Microsoft Academic Search

    Ted K. Woodward; Ashok V. Krishnamoorthy; Anthony L. Lentine; Leo M. F. Chirovsky

    1996-01-01

    We describe our work on the design and testing of optical receivers for use in optoelectronic VLSI. The local nature of the optoelectronic VLSI system permits novel receiver designs, incorporating multiple optical beams and\\/or synchronous operation, while the requirement of realizing large numbers of receivers on a single chip severely constrains area and power consumption. We describe four different receiver

  17. Wafer characteristics via reflectometry

    SciTech Connect

    Sopori, Bhushan L. (Denver, CO)

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  18. Firehose Architectures for Free-Space Optically Interconnected VLSI Circuits

    Microsoft Academic Search

    Ashok V. Krishnamoorthy; David A. B. Miller

    1997-01-01

    Abstract Free-space optical interconnects will soon be able ,to provide ,input\\/output bandwidths ,to a VLSI chip in excess of a terabit per second. The successful application of this technology to parallel distributed processing systems depends ,on the ,need for high-bandwidth interconnects and

  19. Fast scientific computation in CMOS VLSI shared-memory multiprocessors

    Microsoft Academic Search

    B. K. Bose; P. M. Hansen; C. Lee; D. A. Patterson

    1988-01-01

    The authors present design considerations for fast and efficient scientific computation in CMOS VLSI in general, and shared memory multiprocessors in particular, using SPUR as a case study. Algorithmic and technological tradeoffs for fast floating-point arithmetic are presented, together with design issues in tightly-coupled coprocessor interfaces. SPUR simulations indicate that basic arithmetic operations are three to ten times faster than

  20. Carbon Nanotubes for VLSI: Interconnect and Transistor Applications

    Microsoft Academic Search

    Yuji Awano; Shintaro Sato; Mizuhisa Nihei; Tadashi Sakai; Yutaka Ohno; Takashi Mizutani

    2010-01-01

    Carbon nanotubes (CNTs) offer unique properties such as the highest current density, ballistic transport, ultrahigh thermal conductivity, and extremely high mechanical strength. Because of these remarkable properties, they have been expected for use as wiring materials and as alternate channel materials for extending complementary metal-oxide-semiconductor (CMOS) performance in future very large scale integration (VLSI) technologies. In this paper, we report

  1. High-speed parallel CRC circuits in VLSI

    Microsoft Academic Search

    Tong-Bi Pei; Charles Zukowski

    1992-01-01

    The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should

  2. A unified single-phase clocking scheme for VLSI systems

    Microsoft Academic Search

    MORTEZA AFGHAHI; CHRISTER SVENSSON

    1990-01-01

    Two of the main consequences of advances in VLSI technologies are increased cost of design and wiring. In CMOS synchronous systems, this cost is partly due to tedious synchronization of different clock phases and routing of these clock signals. Here, a single-phase clocking scheme that makes the design very compact and simple is described. It is shown that this scheme

  3. Titanic: a VLSI based content addressable parallel array processor

    SciTech Connect

    Weems, C.; Levitan, S.; Foster, C.

    1982-01-01

    A design is presented for a content addressable parallel array processor (CAPAP) which is both practical and feasible. Its practicality stems from an extensive program of research into real applications of content addressability and parallelism. The feasibility of the design stems from development under a set of conservative engineering constraints tied to limitations of VLSI technology. 1 ref.

  4. From Wafer to Package

    NSDL National Science Digital Library

    This website includes an animation of finished wafer to packaged integrated Circuits. Objective: Describe the wafer to packaged device process steps. This simulation is from Module 075 of the Process & Equipment III Cluster of the MATEC Module Library (MML). You will find the animation under the heading "Process & Equipment III." To view other clusters or for more information about the MML visit http://matec.org/ps/library3/process_I.shtmlKey

  5. Stable wafer-carrier system

    SciTech Connect

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  6. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  7. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  8. Mixed voltage VLSI design

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  9. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  10. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  11. Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors

    E-print Network

    Zhou, Chongwu

    Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications compatibility. Here in this paper, we report our progress on wafer-scale processing of separated nanotube thin-film transistors (SN-TFTs) for display applications, including key technology components such as wafer

  12. Modeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen H. Garofalinia)

    E-print Network

    Garofalini, Stephen H.

    Modeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen for publication 31 December 2000 The role of moisture in hydrophilic wafer bonding was modeled using molecular Institute of Physics. DOI: 10.1063/1.1351538 I. INTRODUCTION Wafer bonding technology takes advantage

  13. Wafer-to-wafer bonding for microstructure formation

    Microsoft Academic Search

    MARTIN A. SCHMIDT

    1998-01-01

    Wafer-to-wafer bonding processes for microstructure fabrication are categorized and described. These processes have an impact in packaging and structure design. Processes are categorized into direct bonds, anodic bonds, and bonds with intermediate layers. Representative devices using wafer-to-wafer bonding are presented. Processes and methods for characterization of a range of bonding methods are discussed. Opportunities for continued development are outlined

  14. Improvement of depth of focus control using wafer geometry

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sangmin; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Veeraraghavan, Sathish; Kim, JH; Awasthi, Amartya; Byeon, Jungho; Mueller, Dieter; Sinha, Jaydeep

    2015-03-01

    For several decades, the semiconductor industry has been controlling site flatness of the starting wafer material by defining tight specs on industry-standard site flatness metrics such as SFQR (Site Frontsurface-referenced least sQuares/Range) and ESFQR (Edge Site Frontsurface-referenced least sQuares/Range) that scale with technology nodes. The need for controlling site flatness of the starting material stems from previous research that shows that site flatness directly impacts lithography defocus. The wafer flatness variation changes significantly due to wafer processing downstream such as CMP, etch, and film deposition. Hence, for 2X nm and smaller technology nodes with very stringent focus process windows, it is critical to control wafer flatness variations at critical steps along the semiconductor process flow. In this paper, the capability of an interferometer-based patterned wafer metrology tool to predict lithography defocus is validated by comparison to scanner leveling data. The patterned wafer metrology tool is used to characterize the impact of near-edge flatness changes on the critical dimension (CD) of the contact holes due to different edge CMP process conditions. The results of the characterization illustrate how a site flatness specification or threshold can be developed for critical patterning steps. The paper also illustrates how the patterned wafer metrology tool can be used to identify processes causing site flatness variations. Finally, the site flatness variation at these processes can be monitored using the pattern wafer metrology tool to detect process drifts and excursion before patterning.

  15. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  16. Medical Device Wafer Singulation

    Microsoft Academic Search

    A. Teng; F. Wilhelmsen

    2007-01-01

    Singulation can be the most damaging step in electronic manufacturing where individual dice are freed from a brittle silicon wafer. So much torque and force is applied to the silicon during this process that if precautionary steps are not taken, the freed die may exhibit low strength due to chipping damage. For medical devices, this is particularly a problem because

  17. Fine grinding of silicon wafers

    Microsoft Academic Search

    Z. J Pei; Alan Strasbaugh

    2001-01-01

    Silicon wafers are used for the production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. As one of such processes, surface grinding of silicon wafers has attracted attention among various investigators and a limited number of articles can be found in the literature. However, no published articles are available regarding fine grinding of

  18. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  19. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam [1366 Technologies] [1366 Technologies

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

  20. Quality procedures for VLSI/VHSIC (Very Large Scale Integrated and Very High Speed Integrated Circuits) type devices

    NASA Astrophysics Data System (ADS)

    Cohen, S.

    1985-11-01

    Procedures for microcircuit screening and qualification to ensure the reliability and uniformity of VLSI/VHSIC devices were prepared. The use of Process Control Monitors (PCM) and Reliability Evaluation Modules (REM) were incorporated in the procedures. In addition, recommended guidelines for the evaluation of Computer-Aided-Manufacturing (CAM) facilities were generated in this study. A proposed replacement was provided for existing Method 5007 to MIL-STD-883, Wafer Acceptance Procedure which incorporates reliability screening, process quality evaluation, and electrical parameter testing of each wafer in a lot.

  1. Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits 

    E-print Network

    Lu, Xiang

    2006-04-12

    Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this dissertation, we study three challenging issues in delay test: fault modeling, ...

  2. Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng, Ion Mandoiu, Qinke Wang, Xu Xu, and Alex Z. Zelikovsky

    E-print Network

    Zelikovsky, Alexander

    Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng, Ion Mandoiu, Qinke Wang, Xu@cs.gsu.edu ABSTRACT Multi-project Wafers (MPW) are an efficient way to share the rising costs of mask tooling between and wafer dicing problems under the prevalent side- to-side wafer dicing technology. Our contributions

  3. VLSI high speed packet processor

    NASA Technical Reports Server (NTRS)

    Grebowsky, Gerald J.; Dominy, Carol T.

    1988-01-01

    The Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a packet processor card utilizing semicustom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multichannel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the packet processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semicustom VLSI logic.

  4. Fabrication technologies for three-dimensional integrated circuits

    Microsoft Academic Search

    Rafael Reif; Andy Fan; Kuan-Neng Chen; Shamik Das

    2002-01-01

    The MIT approach to 3D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: (a) structural integrity of the Cu-Cu bond; (b) Cu-Cu contact electrical characteristics; and (c) process flow efficiency

  5. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 ?m after thinning down to the nominal thickness of 75 ?m and 50 ?m. The measurement precision is better than 2 um.

  6. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny [Axcelis Technologies, Inc. 108 Cherry Hill Drive, Beverly, MA 01915 (United States)

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  7. Stanford Telecom VLSI design of a convolutional decoder

    Microsoft Academic Search

    H. A. Bustamante; I. Kang; C. Nguyen; R. E. Peile

    1989-01-01

    The authors describe the novel hardware and speed-efficient architectural features of a recent Stanford Telecom VLSI implementation of a 20-Mb\\/s convolutional decoder using 1.5-?m CMOS technology. The chip offers a selection of convolutional codes, including the (2,1) K=7 code commonly used in satellite communications, high-rate punctured versions of the code, and a (2,1) K=6 code included for requirements of backward

  8. Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization by Exploring Wafer-to-Wafer Correlation

    E-print Network

    Li, Xin

    Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization by Exploring Wafer-to-Wafer In this paper, we propose a new technique, referred to as Multi- Wafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Towards this goal, a novel Bayesian

  9. Hindawi Publishing Corporation VLSI Design

    E-print Network

    Paris-Sud XI, Université de

    Design (ESLD) has been introduced in [1] as a solution to decrease the time to market using highHindawi Publishing Corporation VLSI Design Volume 2012, Article ID 298396, 14 pages doi:10 the original work is properly cited. In this paper, we introduce the Reconfigurable Video Coding (RVC) standard

  10. VLSI Assist For a Multiprocessor

    Microsoft Academic Search

    Bob Beck; Bob Kasten; Shreekant S. Thakkar

    1987-01-01

    Multiprocessors have long been of interest to computer community. They provide the potential for accelerating applications through parallelism and increased throughput for large multi-user system. Three factors have limited the commercial success of multiprocessor systems; entry cost, range of performance, and ease of application. Advances in very large scale integration (VLSI) and in computer aided design (CAD) have removed these

  11. VLSI mixed signal processing system

    NASA Astrophysics Data System (ADS)

    Alvarez, A.; Premkumar, A. B.

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  12. VLSI mixed signal processing system

    NASA Technical Reports Server (NTRS)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  13. Wafer-level radiation testing for hardness assurance

    Microsoft Academic Search

    M. R. Shaneyfelt; K. L. Hughes; J. R. Schwank; F. W. Sexton; D. M. Fleetwood; P. S. Winokur; E. W. Enlow

    1991-01-01

    To implement the qualified manufacturers list (QML) approach to hardness assurance in a practical and cost-effective manner, one must identify technology parameters that affect radiation hardness and bring them under statistical process control. To aid this effort, the authors have developed a wafer-level test system to map test-structure and IC response across a wafer. This system permits current-voltage and charge-pumping

  14. Stress measurement of thin wafer using reflection grating method

    Microsoft Academic Search

    Chi Seng Ng; Anand K. Asundi

    2010-01-01

    Flatness\\/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature\\/flatness is thus necessary to ensure reliability of device

  15. Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs

    E-print Network

    Chakrabarty, Krishnendu

    Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs Sudarshan Bahukudumbi.kacprowicz@intel.com Abstract--Wafer-level test during burn-in (WLTBI) has re- cently emerged as a promising technique to reduce result in high cost [1], [5]. Wafer level burn-in (WLBI) has recently emerged as an enabling technology

  16. Streaming and removal forces due to second-order sound field during megasonic cleaning of silicon wafers

    E-print Network

    Deymier, Pierre

    wafers P. A. Deymiera) Department of Materials Science and Engineering, University of Arizona, Tucson/fluid interface for two systems of importance in the technology of megasonic cleaning of silicon wafers. The first and a viscous fluid, namely water. The second system accounts for the finite thickness of silicon wafers

  17. Design and test of an optoelectronic-VLSI chip with 540-element receiver-transmitter arrays using differential optical signaling

    Microsoft Academic Search

    Michael B. Venditti; Emmanuelle Laprise; Julien Faucher; Pierre-Olivier Laprise; J. E. A. Lugo; D. V. Plant

    2003-01-01

    We have constructed an optoelectronic very-large-scale integration (OE-VLSI) chip with a 540-element receiver and transmitter array. Differential optical signaling was used in conjunction with a fully differential electrical architecture for the receiver and transmitter circuits. The chip was partitioned into multiple functional channels to demonstrate different chip-to-chip communication functions appropriate for applications of OE-VLSI technology. Wide optical input-output busses were

  18. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  19. Calibration wafer for temperature measurements in RTP tools

    NASA Astrophysics Data System (ADS)

    Kreider, K. G.; DeWitt, D. P.; Tsai, B. K.; Lovas, F. J.; Allen, D. W.

    1998-11-01

    Rapid thermal processing (RTP) is a key technology that is used to produce integrated circuits at lower cost and reduced thermal budgets. One of the limiting factors in expanding the use of RTP is the accuracy of temperature measurements of the wafer during processing. We are developing a wafer for calibrating radiometric temperature measurements in RTP tools. The calibration wafer incorporates thin-film thermocouples with platinum/palladium (Pt/Pd) wire thermocouples welded to thin-film pads at the periphery of the 200 mm wafers. We have reduced the uncertainty of the temperature measurements up to 1200 K with this system. This has been accomplished by reducing the uncertainty due to the thermocouple itself and due to reduction of heat transfer near the junction.We report results of NIST calibrations of radiometers using Pt/Pd wire thermocouples welded to the thin films on the wafer and of calibrated type K thermocouples. The thin-film thermocouples were sputter deposited from high purity Pt, Pd and Rh. These thin-film thermocouples were calibrated by comparison with Pt/Pd wire thermocouples in a specially designed test cell at temperatures up to 1150 K. Radiometric temperature measurements were made on the calibration wafer in the NIST RTP sensor test bed, using a commercial radiometer, and compared to those obtained from the thermocouple measurements. A model is presented to account for errors in the radiometric measurements due to stray radiation from the heating lamps, reflection of wafer emission from the chamber walls, and wafer emissivity. The calibrated type K thermocouples indicated temperature measurements within 4 K of both the Rh/Pt and Pt/Pd thermocouples on the 200 mm calibration wafer between 1000 K and 1150 K. The Pt/Pd thin films proved less durable than the Rh/Pt thin films and the limitations of these systems are discussed.

  20. A second generation 50 Mbps VLSI level zero processing system prototype

    NASA Technical Reports Server (NTRS)

    Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

    1994-01-01

    Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

  1. Wafer-Based Nanostructure Manufacturing for Integrated Nanooptic Devices

    NASA Astrophysics Data System (ADS)

    Wang, Jian Jim; Chen, Lei; Tai, Stephen; Deng, Xuegong; Sciortino, Paul F.; Deng, Jiandong; Liu, Feng

    2005-02-01

    The authors have developed a nanomanufacturing platform based on wafer-level nanoreplication with mold and nanopattern transfer by nanolithography. The nanoreplication process, which is based on imprinting a single-layer spin-coated ultraviolet (UV)-curable resist, achieved good nanopatterning fidelity and on-wafer uniformity with high throughput. Some manufacturing issues of the nanoreplication process, such as the impact of wafer and mold surface particles on nanoreplication yield, are also discussed. Nano-optic devices, such as,quarter-wave plates and polarizers, were manufactured with the nanomanufacturing platform. An average wafer-level optical performance yield of 86% was achieved. The developed technology is applied for high-throughput and low-cost manufacturing nanostructure-based optical devices and integrated optical devices.

  2. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  3. PARALLEL IMPLEMENTATION OF VLSI HED CIRCUIT SIMULATION

    E-print Network

    Silc, Jurij

    14 PARALLEL IMPLEMENTATION OF VLSI HED CIRCUIT SIMULATION INFORMATICA 2/91 Keywords: circuit, India Junj Sile Marjan Spegel Jozef Stefan Institute, Ljubljana, Slovenia The importance of circuit simulation in the design of VLSI circuits has channelised research work in the direction of finding methods

  4. Mask registration and wafer overlay

    NASA Astrophysics Data System (ADS)

    Lee, Chulseung; Bang, Changjin; Kim, Myoungsoo; Kang, Hyosang; Lee, Dohwa; Jeong, Woonjae; Lim, Ok-Sung; Yoon, Seunghoon; Jung, Jaekang; Laske, Frank; Parisoli, Lidia; Roeth, Klaus-Dieter; Robinson, John C.; Jug, Sven; Izikson, Pavel; Dinu, Berta; Widmann, Amir; Choi, DongSub

    2010-03-01

    Overlay continues to be one of the key challenges for lithography in advanced semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. Some low k1 techniques, such as Double Exposure and Double Patterning also add additional loss of the overlay margin due to the fact that the single layer pattern is created based on more than 1 exposure. Therefore, the overlay between 2 exposures requires very tight overlay specification. Mask registration is one of the major contributors to wafer overlay, especially field related overlay. We investigated mask registration and wafer overlay by co-analyzing the mask data and the wafer overlay data. To achieve the accurate cohesive results, we introduced the combined metrology mark which can be used for both mask registration measurement as well as for wafer overlay measurement. Coincidence of both metrology marks make it possible to subtract mask signature from wafer overlay without compromising the accuracy due to the physical distance between measurement marks, if we use 2 different marks for both metrologies. Therefore, it is possible to extract pure scanner related signatures, and to analyze the scanner related signatures in details to in order to enable root cause analysis and ultimately drive higher wafer yield. We determined the exact mask registration error in order to decompose wafer overlay into mask, scanner, process and metrology. We also studied the impact of pellicle mounting by comparison of mask registration measurement pre-pellicle mounting and post-pellicle mounting in this investigation.

  5. Plasma-assisted InP-to-Si low temperature wafer bonding

    Microsoft Academic Search

    Donato Pasquariello; Klas Hjort

    2002-01-01

    The applicability of wafer bonding as a tool to integrate the dissimilar material system InP-to-Si is presented and discussed with recent examples of InP-based optoelectronic devices on Si. From there, the lowering of annealing temperature in wafer bonding by plasma-assisted bonding is the essence of this review paper. Lower annealing temperatures would further launch wafer bonding as a competitive technology

  6. Self-checking VLSI reduced instruction set computers

    SciTech Connect

    Lo, Jien-Chung.

    1989-01-01

    The reduced instruction set computer (RISC) is the architecture that dominates today's very large scale integrated (VLSI) processor designs. As the VLSI technology advances, the complexity of a VLSI processor makes design and testing of a VLSI processor very difficult. The self-checking processor design may help to solve these problems, since a self-checking processor can be used as a basic component in a fault-tolerant computer system for the end-user and it can simplify the testing complexity for the manufacturer. In this dissertation, several techniques, that enhance the efficiency of a self-checking processor, are presented. First, a very flexible new design scheme for TSC Berger code checker is given. This design can achieve a faster speed with moderate increase in hardware. A novel scheme to designing a self-checking arithmetic and logic unit (ALU) is also presented. Currently, the only design that can be applied to a self-checking processor design is the two-rail encoded ALU, which needs twice the hardware requirement. The novel scheme uses the Berger code to encode the ALU with the check prediction technique. Theorems and design for Berger check prediction ALU are presented. With The Bergen check prediction ALU, the entire data path can be encoded in a Berger code. This, in turns, reduces the number of checkers in the data path and the hardware requirement. An example design of self-checking RISC processor, called SCRISC, is presented. The SCRISC is designed based on the Berger check prediction ALU. Also, the self-checking issues, such as opcode binary assignments, interfacing and applications to fault-tolerant computer systems, are discussed.

  7. Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

    NASA Astrophysics Data System (ADS)

    Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

    2006-09-01

    A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

  8. Spinner For Etching Of Semiconductor Wafers

    NASA Technical Reports Server (NTRS)

    Lombardi, Frank

    1989-01-01

    Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

  9. Wafer-Level Thermocompression Bonds

    E-print Network

    Tsau, Christine H.

    Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding without the application of an electric field or complicated pre-bond cleaning procedure. The presence of a ductile ...

  10. 3-D INTEGRATION USING WAFER BONDING J.-Q. L *, A. KUMAR *, Y. KWON *, E.T. EISENBRAUN **, R.P. KRAFT *, J.F. McDONALD *, R.J.

    E-print Network

    Salama, Khaled

    3-D INTEGRATION USING WAFER BONDING J.-Q. LÜ *, A. KUMAR *, Y. KWON *, E.T. EISENBRAUN **, R at Albany, Albany, NY 12203 ABSTRACT Use of wafer bonding technology is a promising approach to 3-D system integration. This paper describes a specific approach, incorporating wafer alignment and wafer

  11. Constant fan-in digital neural networks are VLSI-optimal

    SciTech Connect

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  12. The VLSI design of error-trellis syndrome decoding for convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

    1985-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  13. The VLSI design of an error-trellis syndrome decoder for certain convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

    1986-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  14. The triangle processor and normal vector shader: a VLSI system for high performance graphics

    Microsoft Academic Search

    Michael Deering; Stephanie Winner; Bic Schediwy; Chris Duffy; Neil Hunt

    1988-01-01

    Current affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated. Massively parallel VLSI system have the potential to bypass this bottleneck, but

  15. Twist wafer-bonding: A new technology that enables the monolithic integration of all III-V compounds for (opto) electronic devices

    Microsoft Academic Search

    Ejike Felix Ejeckam

    1997-01-01

    Silicon has perhaps, more than any other single element in the periodic table, played a critical role in shaping the information and technological age for which the 20th century will be remembered. Innovative technological applications designed to enhance every facet of our lives have vastly exceeded the predictions of our forebears. These advances have been predicated on the intrinsic merits

  16. Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

    NASA Astrophysics Data System (ADS)

    Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

    2015-04-01

    In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on–off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10?13–10?11 µm2/Hz for n-type and 10?12–10?10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

  17. VLSI Processor For Vector Quantization

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  18. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  19. VLSI Array processors

    Microsoft Academic Search

    S. Kung

    1985-01-01

    High speed signal processing depends critically on parallel processor technology. In most applications, general-purpose parallel computers cannot offer satisfactory real-time processing speed due to severe system overhead. Therefore, for real-time digital signal processing (DSP) systems, special-purpose array processors have become the only appealing alternative. In designing or using such array Processors, most signal processing algorithms share the critical attributes of

  20. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  1. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    NASA Astrophysics Data System (ADS)

    Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

    2014-08-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  2. Parallel VLSI Circuit Analysis and Optimization

    E-print Network

    Ye, Xiaoji

    2012-02-14

    The prevalence of multi-core processors in recent years has introduced new opportunities and challenges to Electronic Design Automation (EDA) research and development. In this dissertation, a few parallel Very Large Scale Integration (VLSI) circuit...

  3. Reconfigurable VLSI architecture for a database processor

    SciTech Connect

    Oflazer, K.

    1983-01-01

    This work brings together the processing potential offered by regularly structured VLSI processing units and the architecture of a database processor-the relational associative processor (RAP). The main motivations are to integrate a RAP cell processor on a few VLSI chips and improve performance by employing procedures exploiting these VLSI chips and the system level reconfigurability of processing resources. The resulting VLSI database processor consists of parallel processing cells that can be reconfigured into a large processor to execute the hard operations of projection and semijoin efficiently. It is shown that such a configuration can provide 2 to 3 orders of magnitude of performance improvement over previous implementations of the RAP system in the execution of such operations. 27 refs.

  4. Application of network coding for VLSI routing

    E-print Network

    Nemade, Nikhil Pandit

    2009-05-15

    This thesis studies the applications of the network coding technique for intercon- nect optimization and improving the routability of Very-large-scale integration (VLSI) designs. The goal of the routing process is to connect the required sets...

  5. Software Structuring Principles for VLSI CAD

    E-print Network

    Katzenelson, Jacob

    1987-12-01

    A frustrating aspect of the frequent changes to large VLSI CAD systems is that so little of the old available programs can be reused. It takes too much time and effort to find the reusable pieces and recast them for ...

  6. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L. (Denver, CO)

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  7. The VLSI complexity of Boolean functions

    Microsoft Academic Search

    Mark R. Kramer; Jan Van Leeuwen

    1983-01-01

    It is well-known that all Boolean functions of n variables can be computed by a logic circuit with O(2n\\/n) gates (Lupanov's theorem) and that there exist Boolean functions of n variables which require logic circuits of this size (Shannon's theorem). We present corresponding results for Boolean functions computed by VLSI circuits, using Thompson's model of a VLSI chip. We prove

  8. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R. (Berkeley, CA)

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  9. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  10. Abstract--Dual-gate junction field-effect transistors (JFETs) are integrated in a substrate transfer process called back-wafer

    E-print Network

    Technische Universiteit Delft

    transfer process called back-wafer contacted silicon-on-glass (SOG) technology. The silicon-on-BOX (buried-oxide) layer of an SOI wafer is transferred to glass and the JFET top- and bottom-gates are contacted-end applications where the increased cost of these wafers is justified by the improved performance offered by SOI

  11. On the use of wafer positional and spatial pattern analysis to identify process marginality and to de-convolute counterintuitive experimental results

    Microsoft Academic Search

    Greg Klein; Laurence Kohler; Joseph Wiseman; Brian Dunham; Anh-Thu Tran; Stacie Brown; Masaki Shingo; I. Burki

    2007-01-01

    The use of wafer randomization and positional analysis in manufacturing is ubiquitous and well established. Wafer electrical and yield data can be traced back to specific operations in the manufacturing process with the help of wafer sequencing records. Tight process windows or complex process technologies may however require that the statistical parameter versus sequence signal be combined with other variables

  12. VLSI circuits and systems for microphotonic applications

    NASA Astrophysics Data System (ADS)

    Lachowicz, S.; Rassau, A.; Kim, C.; Lee, S.-M.

    2005-12-01

    This paper describes various VLSI systems for microphotonic applications. The first project investigates an optimum phase design implementing a multi phase Opto-ULSI processor for multi-function capable optical networks. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering (BS) Opto-ULSI processor (OUP) for integrated intelligent photonic system (IIPS), while investigating the optimal phase characteristics and developing compensation for the nonlinearity of liquid crystal. The second part provides an insight into realisation of a novel 3-D configurable chip based on "sea-of-pixels" architecture, which is highly suitable for applications in multimedia systems as well as for computation of coefficients for generation of holograms required in optical switches. The paper explores strategies for implementation of distributed primitives for arithmetic processing. This entails optimisation of basic cells that would allow using these primitives as part of a 3-D "sea-of-pixel" configurable processing array. The concept of 3-D Soft-Chip Technology (SCT) entails integration of "Soft-Processing Circuits" with "Soft-Configurable Circuits", which effectively manipulates hardware primitives through vertical integration of control and data. Thus the notion of 3-D Soft-Chip emerges as a new design paradigm for content-rich multimedia, telecommunication and photonic-based networking system applications. Combined with the effective manipulation of configurable hardware arithmetic primitives, highly efficient and powerful soft configurable processing systems can be realized.

  13. Inductive fault analysis of VLSI circuits

    SciTech Connect

    Ferguson, F.J.

    1987-01-01

    Inductive fault analysis (IFA) is a systematic method for determining the realistic faults likely to occur in a VLSI circuit. This method takes into account the circuit's fabrication technology, fabrication defect statistics, and physical layout. This inductive approach of characterizing faults, by drawing conclusions based on analyzing the particulars of low-level fault-inducing mechanisms, departs from the traditional scenario of simply assuming a convenient high-level fault model. For a given circuit, the IFA procedure extracts a comprehensive list of circuit-level faults and ranks them according to their relative likelihood of occurrence. These ranked fault lists can be used to validate the traditional stuck-at fault model, assess the true fault coverage of traditional test sets, facilitate more-effective test generation, and support yield-optimization techniques. A software program automating the IFA procedure, called FXT, was implemented. Several circuits from a commercial standard cell library were analyzed. Based on the extracted fault lists for these circuits, a number of interesting observations can be made. With the availability of the IFA method and the FXT tool, a number of very interesting and promising research tasks can be pursued.

  14. Wafer scale packaging for a MEMS video scanner

    NASA Astrophysics Data System (ADS)

    Helsel, Mark P.; Barger, Jon; Wine, David W.; Osborn, Thor D.

    2001-04-01

    Miniaturized scanners have proven their usefulness in a host of applications including video display, bar code reading, image capture, laser printing and optical switching. In order for these applications to reach fruition, however, the MEMS scanner component must be packaged in a manner that is compatible with the volume manufacturing capabilities of the technology. This paper describes a process that was developed to package an SVGA resolution (800 X 600) biaxial video scanner. The scanner is designed for a head mounted display product, targeted to the medical and industrial markets. The scanner is driven magnetically on one axis and capacitively on the other axis. The first level wafer scale package described here incorporates the capacitive drive electrodes into the mounting substrate. The substrate wafer and the device wafer are then bonded using a glass frit sealing technique. Finally, the scanner and substrate are hermetically sealed into a metal can at reduced pressure.

  15. The 1991 3rd NASA Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Maki, Gary K.

    1991-01-01

    Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

  16. Optical Interconnects for Neural and Reconfigurable VLSI Architectures

    E-print Network

    Jahns, Jürgen

    Optical Interconnects for Neural and Reconfigurable VLSI Architectures DIETMAR FEY, WERNER ERHARD show for the example of neural and reconfigurable VLSI archi- tectures that fine-grain architectures fulfill these requirements. An OE-VLSI circuit realization based on multiple quantum-well mod- ulators

  17. Application of a wafer development process to mask making

    NASA Astrophysics Data System (ADS)

    Lee, Gaston; Berger, Celine; Burgel, Christian; Feicke, Axel; Cantrell, Rusty; Tschinkl, Martin

    2005-06-01

    Recently, the design of integrated circuits has become more and more complicated due to higher circuit densities. In particular for logic applications, the design is no longer uniform but combines different kinds of circuits into one mask layout resulting in stringent criteria for both wafer and photomask manufacturing. Photomask CD uniformity control and defectivity are two key criteria in manufacturing today"s high-end reticles, and they are both strongly impacted by the mask developing process. A new photomask develop tool (ACT-M) designed by Tokyo Electron Limited (TEL) has been installed at the Advanced Mask Technology Center (AMTC) in Dresden, Germany. This ACT-M develop tool is equipped with a standard NLD nozzle as well as an SH nozzle which are both widely used in wafer developing applications. The AMTC and TEL used the ACT-M develop tool to adapt wafer puddle develop technology to photomask manufacturing, in an attempt to capture the same optimum CD control enjoyed by the wafer industry. In this study we used the ACT-M develop tool to examine CD uniformity, local loading and defect control on P-CAR and N-CAR photomasks exposed with 50keV e-beam pattern generators. Results with both nozzle types are reported. CD uniformity, loading, and defectivity results were sufficient to meet 65-nm technology node requirements with these nozzles and tailored made develop recipes for photomask processing.

  18. MAPPER alignment sensor evaluation on process wafers

    NASA Astrophysics Data System (ADS)

    Vergeer, N.; Lattard, L.; de Boer, G.; Couweleers, F.; Dave, D.; Pradelles, J.; Bustos, J.

    2013-03-01

    MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3? std) of alignment mark readings can be achieved while being robust against various process steps.

  19. Artificial Cognitive Systems: From VLSI Networks of Spiking Neurons to Neuromorphic Cognition

    Microsoft Academic Search

    Giacomo Indiveri; Elisabetta Chicca; Rodney J. Douglas

    2009-01-01

    Abstract Neuromorphic engineering {(NE)} is an emerging research field that has been attempting to identify neural types of computational\\u000aprinciples, by implementing biophysically realistic models of neural systems in Very Large Scale Integration {(VLSI)} technology.\\u000aRemarkable progress has been made recently, and complex artificial neural sensory-motor systems can be built using this technology.\\u000aToday, however, {NE} stands before a large

  20. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  1. On-wafer seamless integration of GaN and Si (100) electronics

    E-print Network

    Chung, Jinwook

    The high thermal stability of nitride semiconductors allows for the on-wafer integration of (001)Si CMOS electronics and electronic devices based on these semiconductors. This paper describes the technology developed at ...

  2. NREL Core Program; Session: Wafer Silicon (Presentation)

    SciTech Connect

    Wang, Q.

    2008-04-01

    This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

  3. Silicon Wafer Processing Dr. Seth P. Bates

    E-print Network

    Colton, Jonathan S.

    Silicon Wafer Processing Dr. Seth P. Bates Applied Materials Summer, 2000 Objective To provide from blank silicon wafers. Goals The Transfer Plan provides a curriculum covering the process of manufacturing integrated circuits from the silicon wafer blanks, using the equipment manufactured by Applied

  4. A radix-8 wafer scale FFT processor

    Microsoft Academic Search

    Earl E. Swartzlander Jr.; Vijay K. Jain; Hiroomi Hikawa

    1992-01-01

    Wafer Scale Integration promises radical improvements in the performance of digital signal processing systems. This paper describes the design of a radix-8 systolic (pipeline) fast Fourier transform processor for implementation with wafer scale integration. By the use of the radix-8 FFT butterfly wafer that is currently under development, continuous data rates of 160 MSPS are anticipated for FFTs of up

  5. Sea of Leads (SoL) ultrahigh density wafer-level chip input\\/output interconnections for gigascale integration (GSI)

    Microsoft Academic Search

    Muhannad S. Bakir; Hollie A. Reed; Hiren D. Thacker; Chirag S. Patel; Paul A. Kohl; Kevin P. Martin; James D. Meindl

    2003-01-01

    Sea of Leads (SoL) is an ultrahigh density (>104\\/cm2) compliant chip input\\/output (I\\/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I\\/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of

  6. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  7. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Astrophysics Data System (ADS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-02-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  8. Design Technologies for Low Power VLSI

    Microsoft Academic Search

    Massoud Pedram

    1997-01-01

    Low power has emerged as a principal theme in today's electronics indus- try. The need for low power has caused a major paradigm shift where power dis- sipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power cir- cuits and systems. It describes the many issues facing designers

  9. Wafer based mask characterization for double patterning lithography

    NASA Astrophysics Data System (ADS)

    de Kruif, Robert; Bubke, Karsten; Janssen, Gert-Jan; van der Heijden, Eddy; Fochler, Jörg; Dusa, Mircea; Peters, Jan Hendrik; de Haas, Paul; Connolly, Brid

    2008-04-01

    Double Patterning Technology (DPT) is considered the most acceptable solution for 32nm node lithography. Apart from the obvious drawbacks of additional exposure and processing steps and therefore reduced throughput, DPT possesses a number of additional technical challenges. This relates to exposure tool capability, the actual applied process in the wafer fab but also to mask performance. This paper will focus on the latter. We will report on the performance of a two-reticle set based on a design developed to study the impact of mask global and local placement errors on a DPT dual line process. For 32 nm node lithography using DPT a reticle to reticle overlay contribution target of <= 1.5nm has been proposed. Reticle based measurements have shown that this proposed target can be met for standard overlay features and dedicated DPT features. In this paper we will present experimental intra field overlay wafer data resulting from the earlier mentioned reticle set. The reticles contain a 13x19 array of modules comprising various standard overlay features such as ASML overlay gratings and bar-in-bar overlay targets. Furthermore the modules contain split 40nm half pitch DPT features. The reticles have been exposed on an ASML XT:1700i on several wafers in multiple fields. Reticle to reticle overlay contribution has been studied in resist (double exposure) and using the IMEC dual line process (DPT). We will show that the reticle to reticle overlay contribution on the wafer is smaller than 1.5nm (1x). We will compare the wafer data with the reticle data, study the correlation and show that reticle to reticle overlay contribution based single mask registration measurements can be used to qualify the reticle to reticle overlay contribution on wafer.

  10. Proceedings of the 21st International VLSI Multilevel Interconnect Conference (VMIC), Sept.29-Oct.2, Waikoloa, HI, pp. 393-398, 2004.

    E-print Network

    Interconnections for Nanometer Scale VLSI Technologies Navin Srivastava and Kaustav Banerjee Department of copper vias/contacts fails to meet ITRS cur- rent density requirements beyond the 45 nm technology node are analyzed in comparison with copper and proc- ess technology requirements are laid out that would make

  11. Low temperature wafer direct bonding

    Microsoft Academic Search

    Qin-Yi Tong; Giho Cha; Roman Gafiteanu; Ulrich Gosele

    1994-01-01

    A pronounced increase of interface energy of room temperature bonded hydrophilic Si\\/Si, Si\\/SiO2, and SiO2\\/SiO 2 wafers after storage in air at room temperature, 150°C for 10-400 h has been observed. The increased number of OH groups due to a reaction between water and the strained oxide and\\/or silicon at the interface at temperatures below 110°C and the formation of

  12. Wafer Inspection in the Photolithography Process

    NSDL National Science Digital Library

    This is a description for a learning module from Maricopa Advanced Technology Education Center. This PDF describes the module; access may be purchased by visiting the MATEC website. In this module, your learners begin to master the sensitive after develop inspection (ADI) methods that follow photolithography. MATEC describes macro- and micro-inspection techniques and distinguishes qualitative (inspection) from quantitative (metrology) methods. The chief focus is on teaching learners to examine wafers under an optical microscope; a simulated microscope is also provided in a computer-based training (CBT) format. The module covers edge bead inspection and provides extensive practice in flash boundary inspection, including evaluating Nikon crosses, overlay boxes, scanning electronic microscope features, resolution bars, Verniers, and product identification numbers.

  13. Local bipolar-transistor gain measurement for VLSI devices

    NASA Astrophysics Data System (ADS)

    Bonnaud, O.; Chante, J. P.

    1981-08-01

    A method is proposed for measuring the gain of a bipolar transistor region as small as possible. The measurement then allows the evaluation particularly of the effect of the emitter-base junction edge and the technology-process influence of VLSI-technology devices. The technique consists in the generation of charge carriers in the transistor base layer by a focused laser beam in order to bias the device in as small a region as possible. To reduce the size of the conducting area, a transversal reverse base current is forced through the base layer resistance in order to pinch in the emitter current in the illuminated region. Transistor gain is deduced from small signal measurements. A model associated with this technique is developed, and this is in agreement with the first experimental results.

  14. Wafer CD variation for random units of track and polarization

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

    2012-03-01

    After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

  15. Wafer bonding for three dimensional (3D) integration

    NASA Astrophysics Data System (ADS)

    Kwon, Yongchai

    2003-10-01

    Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 · Gtip · t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400°C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400°C. Thermal cycling performed at a temperature 450°C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

  16. Use of polyimides in VLSI fabrication

    NASA Astrophysics Data System (ADS)

    Wilson, A. M.

    The functional requirements of overcoats and multilevel insulators for very large scale integrated circuits (VLSI) are outlined. The moisture barrier properties of polyimide films are reviewed. Polyimide performance vs plasma enhanced chemically vapor deposited (CVD) silicon nitride overcoats are compared. The topological and via forming advantages of polyimides vs plasma enhanced CVD silicon oxide as a multilevel insulator are cited. The temperature and voltage field induced electronic charge transport and trapping at oxide interfaces is cited as the most serious limitation to the use of polyimides as multilevel insulators on VLSI chips.

  17. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  18. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2010-03-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  19. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2009-12-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  20. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOEpatents

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  1. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  2. A VLSI implementation and evaluation of a Signed Bit-Sequential Binary Multiplier 

    E-print Network

    McCullin, James Edward

    1982-01-01

    ) is described in this thesis. The SBSMX algorithm is investigated in order to first develop a system block diagram, and eventually an NMOS circuit design capable of implementing the signed multiplication in existing VLSI technology. New modular design... is that of modularization. Effective use of this technique is important in the design of modern complex integrated circuits, and will therefore play an important role in choosing the final circuit design. The second phase in the design cycle is that of implementation...

  3. A 16-channel analog VLSI processor for bionic ears and speech-recognition front ends

    Microsoft Academic Search

    Michael W. Baker; T. K.-T. Lu; C. D. Salthouse; J.-J. Sit; S. Zhak; R. Sarpeshkar

    2003-01-01

    We describe a 470 ?W 16-channel analog VLSI processor for bionic ears (cochlear implants) and portable speech-recognition front ends. The power consumption of the processor is kept at low levels through the use of subthreshold CMOS technology. Each channel is composed of a programmable bandpass filter, an envelope detector, and a logarithmic dual-slope analog-to-digital converter that currently operate over 51

  4. Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

    Microsoft Academic Search

    Fariborz Assaderaghi; Dennis Sinitsky; Stephen A. Parke; Jeffrey Bokor; Ping K. Ko; Chenming Hu

    1997-01-01

    In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (Vt) drops

  5. Wafer-Level Packaging of Micromechanical Resonators

    Microsoft Academic Search

    Paul Jayachandran Joseph; Pejman Monajemi; Farrokh Ayazi; Paul A. Kohl

    2007-01-01

    An approach to low-cost, wafer-level packaging of microelectromechanical systems (MEMS), e.g., microresonators, is reported. The process does not require wafer-to-wafer bonding and can be applied to a wide range of MEMS devices. A sacrificial polymer-placeholder is first patterned on top of the MEMS component of interest, followed by overcoating with a low dielectric constant polymer overcoat. The sacrificial polymer decomposes

  6. An all digital VLSI tactile array sensor

    Microsoft Academic Search

    M. Raibert

    1984-01-01

    This paper describes a new VLSI tactile array sensor that was designed for use on the fingers of a robot manipulator. The photolithographic methods used in fabricating the microelectronics were also used to build an array of mechanical structures on top of an integrated circuit. When covered with a suitable elastic material, the mechanical structures, notch-shaped windows in the protective

  7. VLSI array synthesis for polynomial GCD computation

    Microsoft Academic Search

    Yongjin Jeong; Wayne Burleson

    1993-01-01

    Polynomial GCD (greatest common divisor) finding is an important problem in algebraic computation, especially in decoding error correcting codes. The authors show a new systolic array structure for the polynomial GCD problem using a systematic array synthesis technique. The VLSI implementation of the array structure is area-efficient and achieves maximum throughput with pipelining. The dependency graph (DG) of the Euclid

  8. Power consumption estimation in CMOS VLSI chips

    Microsoft Academic Search

    Dake Liu; Christer Svensson

    1994-01-01

    Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom

  9. VLSI system design for automotive control

    Microsoft Academic Search

    Andreas Laudenbach; Manfred Glesner

    1992-01-01

    Presents a novel VLSI approach for combustion engine control. The approach is based on a real-time solution of a thermodynamical differential equation. The control system calculates an optimum ignition point by fast measurement and real-time processing of signals as temperature, pressure, and volume of the combustion chamber. The required computational power cannot be met with standard signal processors. The design

  10. VLSI System Design for automotive Control

    Microsoft Academic Search

    A. Laudenbach; M. Glesner

    1991-01-01

    This paper presents a novel VLSI approach for combustion engine control. The approach is based on a real time solution of a thermodynamical differential equation. The control system calculates an optimum ignition point by fast measurement and real time processing of signals as temperature, pressure and volume of the combustion chamber. The required computational power cannot be met with standard

  11. VLSI binary multiplier using residue number systems

    Microsoft Academic Search

    F. Barsi; A. Di Cola

    1982-01-01

    The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted

  12. Modeling concepts for VLSI CAD objects

    Microsoft Academic Search

    Don S. Batory; Won Kim

    1985-01-01

    VLSI CAD applications deal with design objects that have an interface description and an implementation description. Versions of design objects have a common interface but differ in their implementations. A molecular object is a modeling construct which enables a database entity to be represented by two sets of heterogeneous records, one set describes the object's interface and the other describes

  13. Electro-optic techniques for VLSI interconnect

    NASA Astrophysics Data System (ADS)

    Neff, J. A.

    1985-03-01

    A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

  14. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  15. A method to maintain wafer alignment precision during adhesive wafer bonding

    Microsoft Academic Search

    Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

    2003-01-01

    In this paper, a novel method is presented that prevents aligned wafers from shifting relative to each other during adhesive bonding. The attainable pre-bond wafer alignment accuracy on commercially available bonding equipment is typically 2–5?m. However, in adhesive wafer bonding, the intermediate adhesive material must exist in a liquid-like state to wet the wafer surfaces and thereby achieve bonding. When

  16. New Results in the Use of Piezoelectric Wafer Active Sensors for Structural Health Monitoring

    Microsoft Academic Search

    Victor Giurgiutiu

    Piezoelectric-wafer active sensors (PWAS) are small, inexpensive, non-invasive, elastic wave generators\\/receptors that can be easily affixed to a structure. Piezoelectric-wafer active sensors are wide- band non-resonant devices. They can be wired into sensor arrays and connected to data concentrators and wireless communicators. However, the development of PWAS technology is not yet complete, and a number of issues have still to

  17. Stress free wafer bonded GaAs-on-Si photonic devices and circuits

    Microsoft Academic Search

    Y.-H. Lo; Y. Xiong; Y. Zhou; Z. H. Zhu; A. A. Allerman; T. Hargett; R. Sieg; K. D. Choquette

    1999-01-01

    The integration of photonic devices with silicon circuitry has been proposed as an enabling technology for the next generation optical transceivers, router interconnect fabrics, and local area network (LAN) switches. One prevalent hybrid integration technique, wafer fusion bonding, involves fusing two wafers with different lattice constants under high pressure and elevated temperature, such as 700°C for GaAs\\/Si in contaminant-free environments.

  18. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

  19. Stress measurement of thin wafer using reflection grating method

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand K.

    2010-08-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this research, the system is calibrated with reference to stress measurement equipment from KLA-Tencor. Some initial results based on a joint project with Infineon Technologies are re-examined. The stress distribution of the wafers are derived with the aid of Stoney's equation. Finally, the results from our proposed system are compared and contrasted with data obtained from KLA-Tencor equipment.

  20. JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 4, AUGUST 2011 885 Wafer-to-Wafer Alignment for Three-Dimensional

    E-print Network

    Salama, Khaled

    JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 4, AUGUST 2011 885 Wafer-to-Wafer Alignment-Qiang Lu, Fellow, IEEE Abstract--This paper presents a review of the wafer-to-wafer alignment used for 3-D and microelectromechanical systems, including 3-D integrated circuits, advanced wafer-level packaging, and microfluidics

  1. On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs Mottaqiallah Taouil1

    E-print Network

    Kuzmanov, Georgi

    On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs Mottaqiallah Taouil1 Said, and lower power consumption compared to planar ICs. Fabricating these 3D-SICs using Wafer-to- Wafer (W2W) stacking has several advantages including: high throughput, thin wafer and small die handling, and high TSV

  2. On Optimizing Test Cost for Wafer-to-Wafer 3D-Stacked ICs Mottaqiallah Taouil Said Hamdioui

    E-print Network

    Kuzmanov, Georgi

    On Optimizing Test Cost for Wafer-to-Wafer 3D-Stacked ICs Mottaqiallah Taouil Said Hamdioui to manufacture such 3D-SICs. Wafer-to-Wafer (W2W) stacking seems the most favorable approach when high manufacturing throughput, thinned wafers and small die handling is required. However, efficient and optimal test

  3. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    PubMed

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 ?m CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 ?W per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data. PMID:23852175

  4. Cascaded VLSI Chips Help Neural Network To Learn

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  5. Architecture for VLSI design of Reed-Solomon encoders

    NASA Technical Reports Server (NTRS)

    Liu, K. Y.

    1981-01-01

    The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

  6. Wafer scale architecture for an FFT processor

    Microsoft Academic Search

    V. K. Jain; H. A. Nienhaus; D. L. Landis; S. Al-Arian; C. E. Alvarez

    1989-01-01

    A description is given of research on a WSI FFT processor. Attention is focused on the design methodology, architecture, and sparing strategy and restructuring. The basic cells utilized are the MSA and the coefficient ROM. The wafer thus has only two types of cell, making the algorithm highly suitable for restructable wafer-scale integration (WSI) design. The restructuring algorithm is discussed

  7. Designing a mechanism to cleave silicon wafers

    E-print Network

    Figueroa, Victor, 1982-

    2004-01-01

    A device was designed and manufactured to precisely cleave silicon wafers. Two vacuum chucks were designed to support a 150 mm diameter silicon wafer and cleave it by providing a pure moment at a pre-etched v-notch while ...

  8. Methane production using resin-wafer electrodeionization

    DOEpatents

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  9. VLSI implementation of a functional neural network

    Microsoft Academic Search

    Dimokritos A. Panagiotopoulos; Sanjeev K. Singh; Robert W. Newcomb

    1997-01-01

    The VLSI implementation of a two-hidden layer discretized functional artificial neural network (FANN) has been demonstrated. A chip-set has been defined that implements the FANN, while it allows for expandability in the number of its inputs and outputs, as well as the number of neurons and connections in each hidden layer. Use of current-mode circuitry has resulted in compact multiplication

  10. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    NASA Technical Reports Server (NTRS)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  11. Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI

    E-print Network

    Manohar, Rajit

    Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI Rajit Manohar and Clinton VLSI archi- tecture for fast and efficient simulation of wireless networks. The approach is inspired component-based simulation architectures (for instance, see [3, 14]). Wireless ad hoc networks present

  12. CSCE 6933/5933 Advanced Topics in VLSI Systems

    E-print Network

    Mohanty, Saraju P.

    of inverters, - delay of each inverterpt f Advanced Topics in VLSI Systems 9 #12;Ring Oscillator Accuracy Physical design is done only 2 times in the proposed design flow. Advanced Topics in VLSI Systems 8 #12;Ring Oscillator: 45nm CMOS Design pNt f 2 1 Where - frequency of oscillations, N - number

  13. Distributed Object Oriented Data Structures and Algorithms for VLSI CAD

    E-print Network

    Chandy, John A.

    Distributed Object Oriented Data Structures and Algorithms for VLSI CAD John A. Chandy , Steven 61801, USA£ Sierra Vista Research, 236 N Santa Cruz Avenue, Los Gatos, CA 95030, USA Abstract. ProperCAD. This paper discusses the use of such distributed data structures in the context of a partic- ular VLSI CAD

  14. RICE UNIVERSITY An Integrated CAD Framework Linking VLSI

    E-print Network

    Cavallaro, Joseph R.

    the printed layout will match the designed mask for a par- ticular set of process parameters. The designer canRICE UNIVERSITY An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators;An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators Chaitali Sengupta

  15. Selecting Colors for Representing VLSI Layout Giordano Bruno Beretta

    E-print Network

    Beretta, Giordano

    . Additional Keywords and Phrases: functional colors, IC layout, printing Xerox Corporation XEROX Palo AltoSelecting Colors for Representing VLSI Layout Giordano Bruno Beretta #12;#12;Selecting Colors for Representing VLSI Layout Giordano Bruno Beretta EDL·88·7 December 1988 [P88·00226j © Copyright 1988 Xerox

  16. Advanced getter solutions at wafer level to assure high reliability to the last generations MEMS

    Microsoft Academic Search

    M. Moraja; M. Amiotti

    2003-01-01

    The success of MEMS technology is related to the long term reliability and low cost of the final device. The wafer level package is a key technology to assure both long term stability and low cost. In an hermetically sealed MEMS, the degradation of the vacuum or inert atmosphere affect the working conditions of the devices, especially where moving parts

  17. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices

    NASA Astrophysics Data System (ADS)

    Kim, Dae Jong; Yoo, Hyung Won; Kim, Chul Hong; Lee, Hak Kwon; Kim, Sung Su; Bae, Koon Ho; Spielberg, Hedvi; Lee, Yun Ho; Levi, Shimon; Bustan, Yariv; Rozentsvige, Moshe

    2010-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

  18. VLSI Architectures For Syntactic Image Analysis

    NASA Astrophysics Data System (ADS)

    Chiang, Y. P.; Fu, K. S.

    1984-01-01

    Earley's algorithm has been commonly used for the parsing of general context-free languages and error-correcting parsing in syntactic pattern recognition. The time complexity for parsing is 0(n3). In this paper we present a parallel Earley's recognition algorithm in terms of "x*" operation. By restricting the input context-free grammar to be X-free, we are able to implement this parallel algorithm on a triangular shape VLSI array. This system has an efficient way of moving data to the right place at the right time. Simulation results show that this system can recognize a string with length n in 2n+1 system time. We also present an error-correcting recognition algorithm. The parallel error-correcting recognition algorithm has also been im-plemented on a triangular VLSI array. This array recognizes an erroneous string length n in time 2n+1 and gives the correct error count. Applications of the proposed VLSI architectures to image analysis are illus-trated by examples.

  19. Algorithms for VLSI routing. [Very Large Scale Integration, semiconductor chip design

    SciTech Connect

    Zhou, Dian.

    1990-01-01

    This thesis considers the problems arising from VLSI routing design. Algorithms are proposed for solving both global and local routing problems. For routing multiterminal nets in the gate array and sea-of-gates technologies, the author presents a global router which upper bounds the global density of the routing by 2s*, where s* is the span of the nets. For standard cell technology, he presents a global router which achieves the optimal horizontal density while upper bounding the vertical density by 2s*. The parallel implementations of the proposed global routing algorithms are presented.

  20. Wafer inspection as alternative approach to mask defect qualification

    NASA Astrophysics Data System (ADS)

    Holfeld, Christian; Katzwinkel, Frank; Seifert, Uwe; Mothes, Andreas; Peters, Jan Hendrik

    2007-10-01

    Defect inspection is one of the major challenges in the manufacturing process of photomasks. The absence of any printing defect on patterned mask is an ultimate requirement for the mask shop, and an increasing effort is spent in order to detect and subsequently eliminate these defects. Current DUV inspection tools use wavelengths five times or more larger than the critical defect size on advanced photomasks. This makes the inspectability of high-end mask patterns (including strong OPC and small SRAF's) and sufficient defect sensitivity a real challenge. The paper evaluates the feasibility of inspecting the printed wafer as an alternative way for the high-sensitivity defect inspection of photomasks. Defects originating in the mask can efficiently be filtered as repeated defects in the various dies on wafer. Using a programmed-defect mask of 65-nm technology, a reliable detection of the printing defects was achieved with an optimized inspection process. These defects could successfully be traced back to the photomask in a semi-automated process in order to enable a following repair step. This study shows that wafer inspection is able to provide a full defect qualification of advanced photomasks with the specific advantage of assessing the actual printability of arbitrary defects.

  1. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    SciTech Connect

    Emanuel Sachs

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the wafer. In addition, it was found to be suitable for growing very large crystals. The equipment used was simple and inexpensive to operate. Reasonable solar cells were fabricated on re-crystallized material.

  2. A bulk silicon dissolved wafer process for microelectromechanical devices

    Microsoft Academic Search

    Yogesh B. Gianchandani; Khalil Najafi

    1992-01-01

    A single-sided bulk silicon dissolved wafer process that has been used to fabricate several different micromechanical structures is described. It involves the simultaneous processing of a glass wafer and a silicon wafer, which are eventually bonded together electrostatically. The silicon wafer is then dissolved to leave heavily boron doped devices attached to the glass substrate. Overhanging features can be fabricated

  3. Development of a monolithic, multi-MEMS microsystem on a chip demonstrating iMEMS{trademark} VLSI technology. R and D status report number 10, January 1--March 31, 1996

    SciTech Connect

    NONE

    1996-04-17

    This quarter saw the first silicon from the iMEMS{reg_sign} test chip, with complete circuits and beam structures. The wafers looked fine cosmetically and the circuits functioned as designed, but the beams suffered an anomaly that the authors have never seen before. Diagnostic work is under way to sort out the root cause, and other wafers are coming out this quarter to see if it was a one-time anomaly. Work on the process-development front has slowed because of the construction of a dedicated fabrication line for the last-generation process. With the current robust market place for ADI`s business, the existing fabrication line has been operating at 100% capacity. On the device front, great progress has been made by both Berkeley and ADI in the area of gyroscopes. Measurements of close to a degree per second or better have been made for gyros of all three axes and of both single- (linear) and double- (rotary) axis devices. In addition, ADI has designed a gyro that can be packaged in air that very well might meet some of the low-precision needs. Accelerometers of several new formats have been designed and several have been implemented in silicon. First samples of the ADXL 181 designed especially for the fuzing, safe and arming application have been assembled and are in characterization by ADI and others. In addition, 2-axis, Z-axis and digital output designs have been demonstrated. A 3-axis micro-watt accelerometer has been designed and is in fabrication. A 2-axis design for tilt applications is also nearing silicon realization. This portfolio of linear accelerometers, and even angular versions of the same provide, an arsenal of capability for specialized needs as they arise in both commercial and military applications.

  4. Detection of Metal Contamination on Silicon Wafer Backside and Edge by New TXRF Methods

    NASA Astrophysics Data System (ADS)

    Kohno, Hiroshi; Yamagami, Motoyuki; Formica, Joseph; Shen, Liyong

    2009-09-01

    In conventional 200 mm wafer processing, backside defects are not considered to be of much concern because they are obscured by wafer backside topography. However, in current 300 mm wafer processing where both sides of a wafer are polished, backside defects require more consideration. In the beginning, backside defect inspection examined particle contamination because particle contamination adversely influences the depth of field in lithography. Recently, metal contamination is of concern because backside metal contamination causes cross-contamination in a process line, and backside metals easily transfer to the front surface. As the industry strives to yield more devices from the area around the wafer edge, edge exclusion requirements have also become more important. The current International Technology Roadmap for Semiconductors [1] requires a 2 mm edge exclusion. Therefore, metal contamination must be controlled to less than 2 mm from the edge because metal contamination easily diffuses in silicon wafers. To meet these current semiconductor processing requirements, newly developed zero edge exclusion TXRF (ZEE-TXRF) and backside measurement TXRF (BAC-TXRF) are effective metrology methods.

  5. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  6. Everything Wafers: A Guide to Semiconductor Substrates

    NSDL National Science Digital Library

    This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

  7. Wafer Backside Anisotropic Wet Etching of Silicon

    NSDL National Science Digital Library

    This animation, created by Southwest Center for Microsystems Education (SCME), illustrates how the "wafer backside anisotropic wet etching of silicon is used to form the pressure sensor chamber." Further information and resources can be found on the SCME website.

  8. A Novel Bonding Method for Ionic Wafers

    Microsoft Academic Search

    M. M. R. Howlader; Tadatomo Suga; Moon J. Kim

    2007-01-01

    A novel method for bonding sapphire, quartz, and glass wafers with silicon using the modified surface activated bonding (SAB) method is described. In this method, the mating surfaces were cleaned and simultaneously coated with nano-adhesion Fe layers using a low energy argon ion beam. The optical images show that the entire area of the 4-in wafers of LiNbO3\\/Si was bonded.

  9. Effects of wafer thermostability and wafer-holding materials on optical loss in GaAs annealing

    E-print Network

    Byer, Robert L.

    Effects of wafer thermostability and wafer-holding materials on optical loss in GaAs annealing Y. S for publication 13 February 1998 A periodic structure of bonded GaAs wafers has been proposed for quasi lead to unacceptably high optical losses. When commercial semi-insulating GaAs wafers were bonded

  10. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  11. Porous solid ion exchange wafer for immobilizing biomolecules

    SciTech Connect

    Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  12. Three-Dimensional Electro-Thermal Modeling of Thin Film Micro-Refrigerators for Site-Specific Cooling of VLSI ICs

    E-print Network

    -refrigerator integrated onto a chip. The model takes into account of the Peltier cooling and heating, Joule heating-Specific Cooling of VLSI ICs Je-Hyoung Park, Sung-Mo Kang, Yan Zhang, Kazuhiko Fukutani, Ali Shakouri Dept of "hot spots" is an important issue. Recently, a cooling technology based on heterostructure integrated

  13. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 4, DECEMBER 1998 707 Algorithm-Based Low-Power Transform Coding

    E-print Network

    Liu, K. J. Ray

    , and K. J. Ray Liu, Senior Member, IEEE Abstract--In most low-power VLSI designs, the supply voltage processing. I. INTRODUCTION DUE to the limited power-supply capability of current battery technology the power consumption. However, a speed penalty is suffered for the devices (operators) as the supply

  14. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

  15. Continuous-valued probabilistic behavior in a VLSI generative model.

    PubMed

    Chen, Hsin; Fleury, Patrice C D; Murray, Alan F

    2006-05-01

    This paper presents the VLSI implementation of the continuous restricted Boltzmann machine (CRBM), a probabilistic generative model that is able to model continuous-valued data with a simple and hardware-amenable training algorithm. The full CRBM system consists of stochastic neurons whose continuous-valued probabilistic behavior is mediated by injected noise. Integrating on-chip training circuits, the full CRBM system provides a platform for exploring computation with continuous-valued probabilistic behavior in VLSI. The VLSI CRBM's ability both to model and to regenerate continuous-valued data distributions is examined and limitations on its performance are highlighted and discussed. PMID:16722178

  16. Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems

    Microsoft Academic Search

    Pascal Andreas Meinerzhagen; Onur Andiç; Jürg Treichler; Andreas Peter Burg

    2011-01-01

    This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-compatible gain-cell-based dynamic memories. A memory macro in 90-nm CMOS technology including multilevel write and read circuits is proposed and analyzed

  17. Design and characterization of analog VLSI neural network modules

    SciTech Connect

    Gowda, S.M.; Sheu, B.J.; Choi, Joongho (Univ. of Southern California, Los Angeles (United States)); Hwang, Changgyu (Samsung Electronics Co., Kiheung-Eup (Korea, Republic of)); Cable, J.S. (TRW Inc., Redondo Beach, CA (United States))

    1993-03-01

    High-speed computational capabilities of artificial neural networks can be used to solve many complex pattern recognition and image processing problems in science and engineering applications. These networks are implemented in VLSI technologies as regular arrays of analog or digital circuit cells. Although neural networks inherently contain some degree of fault tolerance, a significant percentage of possible processing defects can result in failure of the network. In order to assure the quality and reliability of neural networks, a systematic method to test large arrays of analog, digital, or mixed-signal circuit components that constitute these networks is necessary. A detailed testing procedure for such networks, consisting of a parametric test and a behavioral test, is described. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2-[mu]m double-polysilicon CMOS technologies are presented to demonstrate the testing procedure.

  18. Funding Sources VLSI CAD Laboratory

    E-print Network

    California at San Diego, University of

    accurate results approximate results Layout density modeling: SRAM (left) and NAND2 (right) 3D-IC processes, multiple exposures are needed to print critical chip layers: layout and mask design have new (DFM) Technology Roadmap (ITRS) Adaptive and Resilient Circuits 3D Integrated Circuit Design IC

  19. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  20. Thermal Behavior of Large-Diameter Silicon Wafers during High-Temperature Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Yokoyama, Ichiro; Kang, Kitaek; Takahashi, Nobuaki

    2002-07-01

    Thermal behavior of 200-mm- and 300-mm-diameter Si (100) wafers during high-temperature rapid thermal processing (RTP) in a single wafer furnace (SWF) is investigated as a function of temperature, pressure, process time, wafer handling method and speed. Significant elastic wafer shape deformation was observed during wafer temperature ramp-up. Slip generation was frequently observed in wafers processed above 1050°C. Size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in reducing defect generation during RTP at the given process conditions. Highly reproducible, slip-free RTP results were achieved in 200-mm- and 300-mm-diameter Si (100) wafers processed at 1100°C by optimizing the wafer handling method and speed.

  1. An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization

    E-print Network

    Huang, Yi-Le

    2012-02-14

    Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common method for handling multi...

  2. Circuits for high-performance low-power VLSI logic

    E-print Network

    Ma, Albert

    2006-01-01

    The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and ...

  3. Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation 

    E-print Network

    Wang, Shiwei

    2014-11-27

    This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a ...

  4. What Can SFF CAD Learn from the VLSI CAD Revolution?

    E-print Network

    McMains, Sara

    What Can SFF CAD Learn from the VLSI CAD Revolution? Carlo H. S'equin and Sara McMains CS Division of this interface between designers and fabricators. For many applications, the performance of the digital logic

  5. Semiconducting wafer form shaping with an electric discharge machine

    NASA Astrophysics Data System (ADS)

    Yang, Yu-Tung

    1988-09-01

    Gallium can be used as a temporary glue for semiconducting wafer mounting. The good electric contact between the electrode, the gallium layer, and the semiconducting wafer makes the spark cutting and the semiconducting wafer form shaping much easier. After wafer spark cutting, the residual gallium can be easily removed by a cotton swab from the surface of the wafer in warm isopropyl alcohol (IPA). Also, in this report, improved circuitry of the electric discharge machine for easy and economical construction is described. Gallium arsenide wafers have been form shaped by the present method.

  6. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  7. Slip-Free Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-06-01

    Defect generation phenomena in Si wafers during atmospheric pressure rapid thermal processing (RTP) in a single wafer furnace (SWF) are investigated as a function of temperature, process time, wafer handling method and speed. The size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in controlling defect generation during RTP under given process conditions. Highly reproducible slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100°C for 60 s (up to 5 times) by optimizing the wafer handling method and speed.

  8. Neural algorithms on VLSI concurrent architectures

    SciTech Connect

    Caviglia, D.D.; Bisio, G.M.; Parodi, G.

    1988-09-01

    The research concerns the study of neural algorithms for developing CAD tools with A.I. features in VLSI design activities. In this paper the focus is on optimization problems such as partitioning, placement and routing. These problems require massive computational power to be solved (NP-complete problems) and the standard approach is usually based on euristic techniques. Neural algorithms can be represented by a circuital model. This kind of representation can be easily mapped in a real circuit, which, however, features limited flexibility with respect to the variety of problems. In this sense the simulation of the neural circuit, by mapping it on a digital VLSI concurrent architecture seems to be preferrable; in addition this solution offers a wider choice with regard to algorithms characteristics (e.g. transfer curve of neural elements, reconfigurability of interconnections, etc.). The implementation with programmable components, such as transputers, allows an indirect mapping of the algorithm (one transputer for N neurons) accordingly to the dimension and the characteristics of the problem. In this way the neural algorithm described by the circuit is reduced to the algorithm that simulates the network behavior. The convergence properties of that formulation are studied with respect to the characteristics of the neural element transfer curve.

  9. On-wafer calibration techniques for giga-hertz CMOS measurements

    Microsoft Academic Search

    Troels Emil Kolding; Fredrik Bajers Vej

    1999-01-01

    This paper presents five different methods for performing on-wafer calibration of RF CMOS measurements. All methods are compatible with standard CMOS technology. A comparison of method performance up to 12 GHz is made with measurements on RF CMOS devices. The results verify that substrate and metallization losses must be considered to obtain high accuracy. Fixture design issues are discussed and

  10. Wafer-level MEMS packaging via thermally released metal-organic membranes

    Microsoft Academic Search

    Pejman Monajemi; Paul J. Joseph; Paul A. Kohl; Farrokh Ayazi

    2006-01-01

    This paper reports on the design, implementation and characterization of wafer-level packaging technology for a wide range of microelectromechanical system (MEMS) devices. The encapsulation technique is based on thermal decomposition of a sacrificial polymer through a polymer overcoat to form a released thin-film organic membrane with scalable height on top of the active part of the MEMS. Hermiticity and vacuum

  11. Conformance of ECD wafer bumping to future demands on CSP, 3D integration, and MEMS

    Microsoft Academic Search

    L. Dietrich; M. Toepper; O. Ehrmann; H. Reichl

    2006-01-01

    A bumping technique which is based on electrochemical deposition (ECD) of various metals and metal alloys on wafer level will be presented and characterized in this paper. The machining of the single process steps principally origins from front-end technology widely using standard equipment, but mainly differing in structure sizes and layer thicknesses. Photosensitive polymers have been coated to repassivate the

  12. Wafer focusing measurement of optical lithography system based on Hartmann-Shack wavefront testing

    NASA Astrophysics Data System (ADS)

    Zhu, Xianchang; Hu, Song; Zhao, Lixin

    2015-03-01

    To improve the focusing measurement precision of wafer in optical lithography instrument (OLI), a method based on Hartmann-Shack (HS) testing principle is introduced. Defocus of wafer is immediately detected by measuring the image change between plane and spherical wavefront. As defocus is measured by every sub-lens of microlens array (MLA), serials of defocus position are calculated at single shot of CCD sensor. Choose the average in this measurement the outstanding advantage of this technology is the high accuracy and efficiency. With an experiment to validate the feasibility, the accuracy of focusing measurement is indicated as 20 nm.

  13. Development of an architectural design tool for 3-D VLSI sensors

    E-print Network

    Tyrrell, Brian (Brian Matthew)

    2004-01-01

    Three dimensional integration schemes for VLSI have the potential for enabling the development of new high-performance architectures for applications such as focal plane sensors. Due to the high costs involved in 3-D VLSI ...

  14. Effect of wafer geometry on lithography chucking processes

    NASA Astrophysics Data System (ADS)

    Turner, Kevin T.; Sinha, Jaydeep K.

    2015-03-01

    Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

  15. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  16. In-line failure analysis on productive wafers with dual-beam SEM/FIB systems

    NASA Astrophysics Data System (ADS)

    Weiland, Rainer; Boit, Christian; Dawes, Nick; Dziesiaty, Andreas; Demm, Ernst; Ebersberger, Bernd; Frey, Lothar; Geyer, Stefan; Hirsch, Alexander; Lehrer, Christoph; Meis, Peter; Kamolz, Matthias; Lezec, Henri; Rettenmaier, Hans; Tittes, Wolfgang; Treichler, Rolf; Zimmermann, Harald

    2001-04-01

    Modern dual beam SEM/FIB tools will allow physical failure analysis on productive wafers in the cleanroom if contamination of wafer and production equipment can be controlled. In this study we show that the risks of Ga- diffusion and -desorption as well as heavy metal contamination can be overcome. The reentry of analyzed wafers into the production flow results in lower overall costs and a dramatically shortened feedback loop to production engineers, leading to reduced down times of production tools etc. Most FIB-applications (i.e. highlight etch of cross sections) can be processed with appropriate gas chemistry. Ion Beam deposition of an insulating material to refill the crater created by the sputtering process is also investigated. If either resolution is not sufficient or more complex analyses have to be applied a sample lift-out technique was developed making it obsolete to sacrifice wafers also in these cases. The fixed sample can be analyzed off-line with all PFA- methods, even plasma etching or lift-off in HF is possible. The benefits of this quantum leap for physical failure analysis are reduction of wafer costs and the possibility to reduce analysis cycle time as well as the number of learning cycles in technology development.

  17. Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer

    SciTech Connect

    Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

    1999-09-07

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

  18. Integratible process for fabrication of fluidic microduct networks on a single wafer

    NASA Astrophysics Data System (ADS)

    Matzke, Carolyn M.; Ashby, Carol I. H.; Bridges, Monica M.; Griego, Leonardo; Wong, C. Channy

    1999-08-01

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 mm, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectric materials.

  19. A bioinspired collision detection algorithm for VLSI implementation

    NASA Astrophysics Data System (ADS)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  20. Automated routing method for VLSI with three interconnection layers

    SciTech Connect

    Lee, C.H.

    1986-01-01

    Recently, to the extent allowed by the fabricating technology, approaches have been made to develop an automated router for the multi-layer IC layout design. This thesis examines the VLSI routing problem where three layers are available for interconnection. The author investigates the routing problem in three stages: global routing, power/ground routing, and channel routing. The global routing for the three-interconnection layer model is not much different from that of the two layer model. The global routing problem is studied for two cases: gate array and general cell layout. In the three-layer grid model, power/ground wires keep the direction-per-layer scheme as signal net wires. However, the power/ground routing is further constrained by the width of wires and the layers they are laid on. The major result presented in this dissertation is an algorithm for a channel routing problem. Given a rectangular channel with terminals on top and bottom sides, the algorithm will find a three-layer channel routing that minimizes the channel width and the wire length. Experimental results show that the router is close to optimal.

  1. Geometry control of recrystallized silicon wafers for solar applications

    E-print Network

    Ruggiero, Christopher W

    2009-01-01

    The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

  2. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  3. Sub-imaging Techniques For 3D-Interconnects On Bonded Wafer Pairs

    NASA Astrophysics Data System (ADS)

    Kong, Lay Wai; Krueger, Peter; Zschech, Ehrenfried; Rudack, Andrew C.; Arkalgud, Sitaram; Diebold, Alain C.

    2010-11-01

    The semiconductor industry's ability to follow Moore's law to continue to increase the number of components on integrated circuits is increasingly difficult. One way to improve the product performance even at decreased footprint is the use of 3D interconnects which stacks multiple chips in a single package. This new technology for connecting chips overcomes some of the limitations of 2D interconnects. For example, 3D interconnects significantly reduce interconnect delay and improve clock distribution. At the same time that research into 3D technology such as Through Silicon Vias (TSVs) is advancing quickly, the microscopy techniques used in the evaluation of TSV must also advance in capability. Void inspection after copper plating, defect detection and overlay measurements after wafer bonding are challenging. Microscopy techniques for which silicon is opaque such as scanning acoustic microscope (SAM) and confocal infrared microscope (IR) are capable of inspecting the interface between bonded wafer pairs, while high resolution X-Ray techniques are used to detect voids in TSVs. Initial work was done to determine the limitation of these techniques. Four pairs of bonded wafers were prepared at different thicknesses (100, 200, 300 and 400 ?m) to evaluate the effects of wafer thinning using acoustic and infrared microscopy techniques. SAM was able to resolve the 20 ?m alignment structure with 300 MHz transducer on 300 mm wafer pair, while IR has sub-micron resolution for all bonded wafers. This paper discusses the current status of SAM, IR microscopy and XRM in terms of their application to process metrology for 3D interconnects.

  4. A reconfigurable neuromorphic VLSI multi-chip system applied to visual motion computation

    Microsoft Academic Search

    Giacomo Indiveri; Adrian M. Whatley; Jorg Kramer

    1999-01-01

    We present a multi-chip neuromorphic system in which an address event representation is used for inter-chip communication. The system comprises an analog VLSI transient imager with adaptive photoreceptors, an analog VLSI motion receiver chip and a prototyping communication infrastructure which allows for programmability of connections between the elements on the two chips. We describe the properties of the two VLSI

  5. A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

    1986-01-01

    A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

  6. An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs

    E-print Network

    Thornton, Mitchell

    An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs with a Proposal demands on these placement and routing algorithms than on VLSI or PCB layouts. However, many of the existing techniques and algorithms for VLSI and PCB placement and routing are well­suited for use in MCMs

  7. Advanced laser mask repair in the current wafer foundry environment

    NASA Astrophysics Data System (ADS)

    Robinson, Tod; Yi, Daniel; LeClaire, Jeff; White, Roy; Bozak, Ron; Archuletta, Mike

    2010-09-01

    Contrary to the prior assumptions of its technical demise, deep UV (DUV) femtosecond pulsed laser repair of photomasks is continuing to mature and improve as a technology. Similar to the optical enhancements that allow for 193 nm wavelength light to continue being used down to the 32, or even in some cases 22 nm, node, the process regimes for this type of laser repair continue to expand as new processes are discovered. This work reviews the qualification of repair performance for production at a major wafer foundry site. In addition advances are shown in the area of through-pellicle repair (TRP) process development. These advances include the preferential (versus surrounding reference mask structures) removal of soft defects and the capability to remove or manipulate particles on top of a flat absorber region with no detectable removal of the absorber. These developments will further demonstrate the progressive decoupling of the laser repair spot size from the minimum technology node for laser repair.

  8. Low-temperature full wafer adhesive bonding

    Microsoft Academic Search

    Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

    2001-01-01

    We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 µm and 18 µm. The tested polymer materials were benzocyclobutene (BCB)

  9. Wafer Bonded Subwavelength Metallo-Dielectric Laser

    E-print Network

    Fainman, Yeshaiahu

    . Date of current version June 28, 2011. This work was supported by the Defense Advanced Research Projects Agency, the National Science Foundation (NSF), the NSF Center for Integrated Access Networks Wafer Bonded Metallo-Dielectric Laser #12;reported by a few research groups [4]­[9], but integration

  10. Decoupling bulk- and surface-limited lifetimes in thin kerfless silicon wafers using spectrally resolved transient absorption pump-probe spectroscopy and computer simulations

    E-print Network

    Siah, Sin Cheng

    2013-01-01

    One of the key technological objectives to further decrease the cost of silicon (Si) PV and enable manufacturing of crystalline silicon is to improve the quality of thin, kerfless Si wafers to monocrystalline equivalent. ...

  11. Defect detection in patterned wafers using multichannel Scanning Electron Microscope

    E-print Network

    Cohen, Israel

    Defect detection in patterned wafers using multichannel Scanning Electron Microscope Maria Zontak using Scanning Electron Microscope (SEM) images. A wafer is irradiated with a focused beam of electrons s t r a c t Recent computational methods of wafer defect detection often inspect Scanning Electron

  12. NEW OR IMPRO VED DEVICES. DIRECT STEPPING ON WAFERS

    E-print Network

    Paris-Sud XI, Université de

    667 NEW OR IMPRO VED DEVICES. DIRECT STEPPING ON WAFERS P. PARRENS and P. TIGREAT (*) CEA-CENG LETI parameters such as wafer reflectivity, numerical aperture of the lens, spatial coherence of illumination. - Direct stepping on wafers has become a well-known and accepted technique after many recent publications

  13. Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models

    E-print Network

    Makris, Yiorgos

    Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models Nathan Kupp, Ke) are collected to monitor the health-of-line and to make wafer scrap decisions preceding final test. These measurements are typically sampled spatially across the surface of the wafer from between-die scribe line sites

  14. Enhanced Design Flow and Optimizations for Multi-Project Wafers

    E-print Network

    Zelikovsky, Alexander

    1 Enhanced Design Flow and Optimizations for Multi-Project Wafers Andrew B. Kahng Ion I. Mandoiu Xu and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW of mask tooling among up to tens of designs. However, MPW reticle floorplanning and wafer dicing introduce

  15. Automatic Clustering of Wafer Spatial Signatures Wangyang Zhang

    E-print Network

    Li, Xin

    1 Automatic Clustering of Wafer Spatial Signatures Wangyang Zhang 1 , Xin Li 1 , Sharad Saxena 2 of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically capture wafer spatial signatures by a small number

  16. MECHANICAL STRENGTH OF SILICON WAFERS AND ITS MODELLING

    Microsoft Academic Search

    G. Coletti; C. J. J. Tool; L. J. Geerligs

    Mechanical strength measurements of multicrystall ine Si wafers are carried out with a ring -on-ring test geometry. This geometry is very sensitive to the surface of the wafers rather than the edge. The measurements reveal the great importance of the saw damage on the mechanical stability of as-cut as well as textured wafers. The initial surface defects make a big

  17. Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)

    SciTech Connect

    Rupnowski, P.; Sopori, B.

    2008-05-01

    A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

  18. Automated reticle inspection data analysis for wafer fabs

    Microsoft Academic Search

    Derek Summers; Gong Chen; Bryan Reese; Trent Hutchinson; Marcus Liesching; Hai Ying; Russell Dover

    2008-01-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the

  19. Automated reticle inspection data analysis for wafer fabs

    Microsoft Academic Search

    Derek Summers; Gong Chen; Bryan Reese; Trent Hutchinson; Marcus Liesching; Hai Ying; Russell Dover

    2009-01-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the

  20. Analog VLSI system for active drag reduction

    SciTech Connect

    Gupta, B.; Goodman, R.; Jiang, F.; Tai, Y.C. [California Inst. of Technology, Pasadena, CA (United States)] [California Inst. of Technology, Pasadena, CA (United States); Tung, S.; Ho, C.M. [Univ. of California, Los Angeles, CA (United States)] [Univ. of California, Los Angeles, CA (United States)

    1996-10-01

    In today`s cost-conscious air transportation industry, fuel costs are a substantial economic concern. Drag reduction is an important way to reduce costs. Even a 5% reduction in drag translates into estimated savings of millions of dollars in fuel costs. Drawing inspiration from the structure of shark skin, the authors are building a system to reduce drag along a surface. Our analog VLSI system interfaces with microfabricated, constant-temperature shear stress sensors. It detects regions of high shear stress and outputs a control signal to activate a microactuator. We are in the process of verifying the actual drag reduction by controlling microactuators in wind tunnel experiments. We are encouraged that an approach similar to one that biology employs provides a very useful contribution to the problem of drag reduction. 9 refs., 21 figs.

  1. Implementation of optical interconnections for VLSI

    NASA Technical Reports Server (NTRS)

    Wu, Wennie H.; Bergman, Larry A.; Johnston, Alan R.; Guest, Clark C.; Esener, Sadik C.

    1987-01-01

    This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: (1) the holographic optical element (HOE), (2) the laser sources, (3) the detectors and associated circuits forming an optically addressed gate, and (4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 x 20 microns has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity, and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five holograms.

  2. PLA realizations for VLSI state machines

    NASA Technical Reports Server (NTRS)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  3. Synthesis algorithm of VLSI multipliers for ASIC

    NASA Technical Reports Server (NTRS)

    Chua, O. H.; Eldin, A. G.

    1993-01-01

    Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

  4. Laser diodes integrated with butt-jointed spotsize converter fabricated on 2-in wafer

    Microsoft Academic Search

    Masato Wada; Hiroshi Okamoto; Kenji Kishi; Yoshiaki Kadota; M. Qkamoto; Yasuhiro Kondo; Yoshihisa Sakai; Hiromi Oohashi; Yasumasa Suzaki; Yuichi Tohmori; Masashi Nakao; Yoshio Itaya; Mitsuo Yamamoto

    1997-01-01

    Laser diodes integrated with spotsize converters by butt-joint technology combined with selective area metal organic vapor phase epitaxial (MOVPE) growth have been successfully fabricated. Satisfactory uniformity, reproducibility (>99%) and tolerance for low threshold current, a narrow emitted beam, and low optical coupling loss to fiber (<-2.4 dB) are obtained by using 2-in full wafer fabrication technology in the experimental fabrication.

  5. Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force

    Microsoft Academic Search

    Minoru Sudou; Hidekuni Takao; Kazuaki Sawada; Makoto Ishida

    2007-01-01

    This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of

  6. Observation of silicon wafer emissivity in rapid thermal processing chambers for pyrometric temperature monitoring

    Microsoft Academic Search

    J. Nulman; S. Antonio; W. Blonigan

    1990-01-01

    The emissivity of silicon wafers in a rapid thermal processing chamber has been measured as a function of the wafer temperature. Wafers with different surface roughness and layers have been studied. For transparent wafers, both sides of the wafer affect the emissivity. This emissivity is not only affected by surface roughness, but also by the layers deposited on the wafer.

  7. Product assurance technology efforts: Technical accomplishments

    NASA Technical Reports Server (NTRS)

    1985-01-01

    Product assurance technology topics addressed include: wafer acceptance procedures, test chips, test structures, test chip methodology, fault models, and the Combined Release and Radiation Effects Satellite test chip.

  8. Wafer-scale fabrication of nanoapertures using corner lithography

    NASA Astrophysics Data System (ADS)

    Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

    2013-07-01

    Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated—based on a theoretical foundation including a statistical analysis—with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures.

  9. Wafer-scale fabrication of nanoapertures using corner lithography.

    PubMed

    Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

    2013-07-19

    Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated--based on a theoretical foundation including a statistical analysis--with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures. PMID:23792365

  10. Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing

    Microsoft Academic Search

    Shao-Chung Hsu; Chen-Fu Chien

    2007-01-01

    Semiconductor manufacturing involves lengthy and complex processes, and hence is capital intensive. Companies compete with each other by continuously employing new technologies, increasing yield, and reducing costs. Yield improvement is increasingly important as advanced fabrication technologies are complicated and interrelated. In particular, wafer bin maps (WBM) that present specific failure patterns provide crucial information to track the process problems in

  11. Sensors and Achcators A, 43 (1994) 22X29 223 Low-temperature silicon wafer-to-wafer bonding using gold at

    E-print Network

    Grigoriev, Alexei

    1994-01-01

    Sensors and Achcators A, 43 (1994) 22X29 223 Low-temperature silicon wafer-to-wafer bonding using and actuator systems of high complexity bemme commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated

  12. Wafer surface pre-treatment study for micro bubble free of lithography process

    NASA Astrophysics Data System (ADS)

    Yang, Xiaosong; Zhu, XiaoZheng; Cai, Spencer

    2014-04-01

    Photo resist micro bubble and void defect is reported as a typical and very puzzle defect type in photo lithography process, it becomes more and more significantly and severely with the IC technology drive towards 2× node. Introduced in this paper, we have studied the mechanism of photo resist micro bubble at different in-coming wafer surface condition and tested a series of pre treatment optimization method to resolve photo resist micro bubble defect on different wafer substrate, including in the standard flat and smooth wafer surface and also in special wafer surface with high density line/space micro-structure substrate as is in logic process FinFET tri-gate structure and Nor type flash memory cell area Floating Gate/ONO/Control Gate structure. As is discovered in our paper, in general flat and smooth wafer surface, the photo resist micro bubble is formed during resist RRC coating process (resist reduction coating) and will easy lead to Si concave defect after etch; while in the high density line/space micro-structure substrate as FinFET tri-gate, the photo resist void defect is always formed after lithography pattern formation and will final cause the gate line broken after the etching process or localized over dose effect at Ion IMP layers. The 2nd type of photo resist micro bubble is much more complicated and hard to be eliminated. We try to figure out the interfacial mechanism between different type of photo resist (ArF, KrF and I-line) and pre-wet solvent by systematic methods and DOE splits. And finally, we succeeded to dig out the best solution to eliminate the micro bubble defect in different wafer surface condition and implement in the photolithography process.

  13. Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

    NASA Astrophysics Data System (ADS)

    Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

    2004-08-01

    The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

  14. Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process

    NASA Astrophysics Data System (ADS)

    Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

    2013-09-01

    Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements™) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

  15. Experimental investigation of three-dimensional interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Ku, Yi-sha; Chang, Po-Yi; Shen, Chris

    2012-10-01

    The use and enhancement of a semi-automated wafer characterization tool, a dual channel capacitive sensor module, is demonstrated by implementing a new measurement algorithm for metallization process control. This tool is capable of measuring the deposited metal film thickness induced bow and warpage in a full wafer surface scan. The nondestructive solution can measure Cu metal film thickness with a total measurement uncertainty of 0.18 ?m (1?). The stress conversion map can be obtained based on the modified Stoney's formula and the capacitance-displacement technique. A wafer thinning process was also performed to characterize the warpage/bow of 8-in. wafers, which continues to increase as wafer thicknesses are reduced from 725 to 300 ?m. There was a linear relationship between the wafer warpage and bow and the square of the inverse of the thickness. Metrology results from actual 3-D interconnect processing wafers are presented.

  16. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    PubMed

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits. PMID:19086836

  17. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  18. Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

    NASA Astrophysics Data System (ADS)

    Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

    2015-03-01

    We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

  19. Comparison of On-Wafer Calibrations

    Microsoft Academic Search

    Dylan F. Williams; Roger B. Marks; Andrew Davidson

    1991-01-01

    A powerful new verification technique determines the measurement accuracy of scattering parameter calibrations. The technique determines the relative reference impedance, reference plane offset, and the worst-case measurement deviations of any calibration from a benchmark calibration. The technique is applied to several popular on-wafer scattering parameter calibrations, and the deviations between those calibrations and the thru-reflect line calibration are quantified.

  20. Lateral field emission diodes using SIMOX wafer

    Microsoft Academic Search

    Jung-Hyeon Park; Hyung-Il Lee; Heung-Sik Tae; Jeung-Soo Huh; Jung-Hee Lee

    1997-01-01

    Lateral field emission diodes were fabricated by using separation by implantation of oxygen (SIMOX) wafer and their current-voltage characteristics (I-V) were analyzed. Applying conventional photolithography and local oxidation of silicon (LOGOS) process, we fabricated single-crystalline lateral silicon field emitters with very sharp cathode and anode tips and very short cathode to anode spacing ranging from 0.3 to 0.8 ?m as

  1. Characterization of semiconductor surface-emitting laser wafers

    SciTech Connect

    Gourley, P.L.; Vawter, G.A.; Brennan, T.M.; Hammons, B.E.

    1990-01-01

    The development of epitaxial semiconductor surface-emitting lasers has begun in recent years. These lasers are ultra-short (few {mu}m) Fabry-Perot resonators comprising epitaxial multilayer semiconductor mirrors and quantum well active regions. The resonators are single crystals grown along the lasing axis by molecular beam epitaxy (MBE) or chemical vapor deposition (CVD). They offer significant advances over conventional cleaved, edge-emitting lasers for creating lasers with single elements of 2 dimensional arrays, low beam divergence, engineered active regions, single longitudinal modes, and improved temperature characteristics. To realize the high potential of these new laser structures, techniques for characterizing the laser wafer after growth and between fabrication steps must be developed. In this paper we discuss several optical techniques that we have developed for this emerging surface-emitting laser technology.

  2. On testing VLSI chips for the big Viterbi decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.

    1989-01-01

    A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

  3. On testing VLSI chips for the big Viterbi decoder

    NASA Astrophysics Data System (ADS)

    Hsu, I. S.

    1989-02-01

    A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

  4. Advanced Modelling of Silicon Wafer Solar Cells

    NASA Astrophysics Data System (ADS)

    Peters, Marius; Fajun, Ma; Siyu, Guo; Hoex, Bram; Blaesi, Benedikt; Glunz, Stefan; Aberle, Armin; Luther, Joachim

    2012-10-01

    Modelling of solar cells today is general practice in research and widely-used in industry. Established modelling software is typically limited to one dimension and/or to small scales. Additionally, novel effects, like, e.g., the use of diffractive structures or luminescent materials, are not established. In this paper we discuss how the combination of different modelling techniques can be used to overcome these limitations. In this context two examples are presented. The first example concerns the combination of the open source simulation software PC1D with circuit modelling to investigate the effect of local shunts on the global characteristics of a silicon wafer solar cell. For the investigated example (4.5 cm2 cell area) we find that a local point shunt reduces the solar cell efficiency by 4% relative. The second example concerns the modelling of diffractive gratings for thin silicon wafer solar cells. For this purpose, we use the rigorous coupled wave analysis to simulate Sentaurus technical computer-aided design (TCAD) is combined with the rigorous coupled wave analysis, a method to solve Maxwell's equations for periodic structures. Here we show that a grating can be used to improve the absorption in a thin silicon wafer solar cell considerably.

  5. Propagation of resist heating mask error to wafer level

    NASA Astrophysics Data System (ADS)

    Babin, S. V.; Karklin, Linard

    2006-10-01

    As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the mask error budget - the resist heating CD error. In simulation of exposure using a stepper, variable MEEF was considered.

  6. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

  7. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  8. A multi coding technique to reduce transition activity in VLSI circuits

    NASA Astrophysics Data System (ADS)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  9. A radial basis function neurocomputer implemented with analog VLSI circuits

    NASA Technical Reports Server (NTRS)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  10. Combinatorial limit to the computing power of VLSI circuits

    SciTech Connect

    Vuillemin, J.

    1983-03-01

    The author introduces a property of Boolean functions, called transitivity, which consists of integer, polynomial, and matrix products as well as of many interesting related computational problems. The area of any circuit computing a transitive function grows quadratically with the circuit's maximum data rate, expressed in bits s/sup -1/. This result provides a precise analytic expression of an area-time tradeoff for a wide class of VLSI circuits. Furthermore, this tradeoff is achievable. One has thus matching (to within a constant multiplicative factor) upper and lower complexity bounds for the three above products, in the VLSI circuits computational model. 15 references.

  11. NASA Space Engineering Research Center for VLSI systems design

    NASA Technical Reports Server (NTRS)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  12. Incremental placement and routing of VLSI macrocells

    SciTech Connect

    Ozeki, T.

    1989-01-01

    This dissertation proposes a strategy to automatically position and interconnect a set of rectangular VLSI macrocell blocks by using an integrated set of incremental algorithms. The set of tools is subdivided into three major modules - design manager, floor planner (ExPlan), and global router (MAP). Design manager is used as an interface between the database and the user to simplify the user's task of cell library management by a use of simple command language. ExPlan is used to generate a transformation matrix of given cell list and netlist by best first heuristic search mechanism. The resulting floorplan provides coordinate and orientation of each cell in the cell list with sufficient channel dimension between cells for all nets to be successfully connected and total net lengths minimized. Absolute placement and routing is performed by MAP to create a layout which minimizes overall area by incrementally compacting channels. Each rectangular channel is partitioned such that they can be routed in a predetermined sequence to eliminate the usage of a switchbox router. MAP has capability to route nets with multiple terminals as well as perform connections on standard cells. The final routed result is automatically checked against the netlist for verifying the connectivity of all nets.

  13. Performance optimization of digital VLSI circuits

    SciTech Connect

    Marple, D.P.

    1987-01-01

    Designers of digital VLSI circuits have virtually no computer tools available for the optimization of circuit performance. Instead, a designer relies extensively on circuit-analysis tools, such as circuit simulation (SPICE) and/or critical-delay-path analysis. A circuit-analysis approach to digital design is very labor-intensive and seldom produces a circuit with optimum area/delay or power/delay trade off. The goal of this research is to provide a synthesis approach to the design of digital circuits by finding the sizes of transistors that optimize circuits by finding the sizes of transistors that optimize circuit performance (delay, area, power). Solutions are found that are optimum for all possible delay paths of a given circuit and not for just a single path. The approach of this research is to formulate the problem of area/delay or power/delay optimization as a nonlinear program. Conditions for optimality are then established using graph theory and Kuhn-Tucker conditions. Finally, the use of augmented-Lagrangian and projected-Lagrangian algorithms are reviewed for the solution of the nonlinear programs. Two computer programs, PLATO and COP, were developed by the author to optimize CMOS PLA's (PLATO) and general CMOS circuits (COP). These tools provably find the globally optimum transistor sizes for a given circuit. Results are presented for PLA's and small- to medium-sized cells.

  14. Investigation of intrinsic gettering for germanium doped Czochralski silicon wafer

    NASA Astrophysics Data System (ADS)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Wang, Weiyan; Zeng, Yuheng; Que, Duanlin

    2007-06-01

    The intrinsic gettering (IG) effects in a germanium-doped Czochralski (GCz) silicon wafer have been investigated through a processing simulation of dynamic random access memory making and an evaluation on IG capability for copper contamination. It has been suggested that both the good quality defect-free denuded zones (DZs) and the high-density bulk microdefect (BMD) regions could be generated in GCz silicon wafer during device fabrication. Meanwhile, it was also indicated that the tiny oxygen precipitates were hardly presented in DZs of silicon wafer with the germanium doping. Furthermore, it was found in GCz silicon wafer that the BMDs were higher in density but smaller in size in contrast to that in conventional Cz silicon wafer. Promoted IG capability for metallic contamination was therefore induced in the germanium-doped Cz silicon wafer. A mechanism of the germanium doping on oxygen precipitation in Cz silicon was discussed, which was based on the hypothesis of germanium-related complexes.

  15. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  16. Resonance ultrasonic vibrations for crack detection in photovoltaic silicon wafers

    Microsoft Academic Search

    W. Dallas; O. Polupan; S. Ostapenko

    2007-01-01

    The resonance ultrasonic vibrations (RUV) technique is adapted for non-destructive crack detection in full-size silicon wafers for solar cells. The RUV methodology relies on deviation of the frequency response curve of a wafer, ultrasonically stimulated via vacuum coupled piezoelectric transducer, with a periphery crack versus regular non-cracked wafers as detected by a periphery mounted acoustic probe. Crack detection is illustrated

  17. Automatic saw-mark detection in multicrystalline solar wafer images

    Microsoft Academic Search

    Wei-Chen Li; Du-Ming Tsai

    2011-01-01

    This paper presents a method of automatic defect inspection for the photovoltaic industry, with a special focus on multicrystalline solar wafers. It presents a machine vision-based scheme to automatically detect saw-mark defects in solar wafer surfaces. A saw-mark defect is a severe flaw that occurs when a silicon ingot is cut into wafers. Early detection of saw-mark defects in the

  18. A four-step method for de-embedding gigahertz on-wafer CMOS measurements

    Microsoft Academic Search

    Troels Emil Kolding

    2000-01-01

    In this paper, a de-embedding method is proposed for conducting accurate on-wafer device measurements in the gigahertz range. The method addresses issues of substrate coupling and contact effects and is therefore suitable for measurements with lossy technologies such as CMOS. The method assumes a probe-tip two-port calibration performed with well-known techniques and impedance substrates. By employing a physical interpretation of

  19. MEMS Vertical Probe Cards With Ultra Densely Arrayed Metal Probes for Wafer-Level IC Testing

    Microsoft Academic Search

    Fei Wang; Rong Cheng; Xinxin Li

    2009-01-01

    We have developed a MEMS probe-card technology for wafer-level testing ICs with 1-D line-arrayed or 2-D area-arrayed dense pads layouts. With a novel metal MEMS fabrication technique, an area-arrayed tip matrix is realized with an ultradense tip pitch of 90 mum times196 mum for testing 2-D pad layout, and a 50-mum minimum pitch is also achieved in line-arrayed probe cards

  20. Design and optimization of thermo-mechanical reliability in wafer level packaging

    Microsoft Academic Search

    X. J. Fan; B. Varia; Q. Han

    2010-01-01

    In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design\\/material selection, polymer-cored ball application, and PCB design\\/material selection are studied. The investigation focuses on four different WLP technologies: standard

  1. Development of wafer-scale cooling\\/heating thermoelectric arrays using thin-film superlattice devices

    Microsoft Academic Search

    R. Alley; K. Coonley; P. Addepalli; E. Siivola; M. Mantini; R. Venkatasubramanian

    2002-01-01

    Thin-film superlattice thermoelectric material was used to fabricate 2-inch wafer scale thermoelectric module arrays. These arrays employ a promising thermoelectric device technology that exhibits a significant enhancement in the thermoelectric device figure of merit (ZT) at 300 K, cooling\\/heating power densities in excess of 100 Watts\\/cm2, and response times significantly faster than bulk devices. To power and characterize these devices,

  2. A large area MOS-GTO with wafer-repair technique

    Microsoft Academic Search

    M. Stoisiek; M. Beyer; W. Kiffe; H.-J. Schultz; H. Schmid; H. Schwarzbauer; R. Stengl; P. Turkes; D. Theis

    1987-01-01

    Turn-off thyristors with MOS-controlled emitter-base shorts (MOS-GTOs) are fabricated by using IC technology. Therefore, the device area is limited to about 1 cm2. However, typical power devices for currents >100 amps need to have areas well above this value. We now succeeded in realizing a MOS-GTO of 3 cm diameter by applying a laboratory type wafer repair technique. Processing failures,

  3. VLSI Lab Tutorial 3 Virtuoso Layout Editing Introduction

    E-print Network

    Mahmoodi, Hamid

    tutorial is to guide you through the design process in creating a custom IC layout for your CMOS inverter design. The layout represents masks used in wafer fabs to fabricate a die on a silicon wafer, which be able to: - Create a mask layout of the CMOS inverter that you have designed earlier. - Check that your

  4. A generic architecture for wafer-scale neuromorphic systems

    SciTech Connect

    Raffel, J.I.; Mann, J.R.; Berger, R.; Soares, A.M.; Gilbert, S.L. (MIT, Lexington, MA (USA); Spectrix Corp., Evanston, IL (USA))

    1989-01-01

    The massive parallelism and high fan-out characteristics of neural networks impose interconnection requirements that are too extreme for IC-implementation; wafer-scale integration, however, interconnects many circuits on a wafer, thereby eliminating wirebonds, package pins, and external printed-circuit wiring. A generic wafer-scale device for neural networks has been devised which employs multiplying D/A converters for programmable synapses and operational amplifiers for summing nodes. Upon fabrication of each such wafer, laser cuts and links may be used to both define network connectivity and furnish defect-avoidance for the improvement of production yields. 7 refs.

  5. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M. (Antioch, CA)

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  6. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  7. Micro-miniature gas chromatograph column disposed in silicon wafers

    SciTech Connect

    Yu, C.M.

    2000-05-30

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  8. Wafer Signature Analysis of IDDQ Test Data Sagar S. Sabade D. M. H. Walker

    E-print Network

    Walker, Duncan M. "Hank"

    Wafer Signature Analysis of IDDQ Test Data Sagar S. Sabade D. M. H. Walker Department of Computer. The concept of wafer signature is proposed. A wafer signature is obtained by sorting all IDDQ readings on a wafer for a vector. A break or jump in the wafer signature is considered to indicate defective chips

  9. Electrooptic shutter devices utilizing PLZT ceramic wafers

    SciTech Connect

    Thornton, A.L.

    1981-01-01

    Optical transparency was achieved in lead zirconate-titanate ferroelectric ceramics by substituting moderate amounts of the element lanthanum (8 to 12%) for lead. These compositions exhibit the quadratic (Kerr) electrooptic effect. The excellent optical qualities of these materials (designated PLZT) has permitted the practical utilization of their electrooptic properties in a number of devices. All of these devices utilize the classic Kerr cell arrangement. A PLZT wafer with optical axis oriented at 45/sup 0/ with respect to the axes of polarization is sandwiched between crossed polarizers. Application of an electric field via an interdigital array of electrodes on opposing wafer surfaces forces the PLZT material into a tetragonal state with the resulting induced birefringence proportional to the square of the applied electric field. Hence, the electrooptic wafer provides a retardation of light so that a component is passed by the second crossed polarizer to achieve an ON or open state. Maximum transmission is achieved when the retardation is half-wave. Shutter devices developed by Sandia and those in continuing development are described with respect to operational characteristics and physical configuration. The devices range in size from very small apertures of 50 ..mu..m x 2 mm with center-to-center repeat dimensions of 125 ..mu..m - to very large - apertures of 15.2 cm in single pieces and mosaics with apertures of 15.2 cm x 20.3 cm. Major efforts have centered on shutter development for the protection of aircrew from eye-damaging weapon effects. Other devices are also described which: provide eye protection for welders, protect vidicon tubes, function as page composers for holographic memories serve as large aperture photographic shutters, provide stereoscopic three-dimensional TV displays, and serve as data links in a fiber-optic transmission path.

  10. Autonomous vehicle guidance using analog VLSI neuromorphic sensors

    E-print Network

    Autonomous vehicle guidance using analog VLSI neuromorphic sensors Giacomo Indiveri and Paul step towards the design of a fully autonomous vehicle that will safely navigate using only inputs from of compact low-power autonomous systems. We describe such a system, consisting of a mobile robot equipped

  11. A Low-Power Analog VLSI Visual Collision Detector

    Microsoft Academic Search

    Reid R. Harrison

    2003-01-01

    We have designed and tested a single-chip analog VLSI sensor that detects imminent collisions by measuring radially expansive optic flow. The design of the chip is based on a model proposed to explain leg-extension behavior in flies during landing approaches. A new elementary motion detector (EMD) circuit was developed to measure optic flow. This EMD circuit models the bandpass nature

  12. CSCE 6933/5933 Advanced Topics in VLSI Systems

    E-print Network

    Mohanty, Saraju P.

    . Advanced Topics in VLSI Systems #12;2 Scaling Trends and Effects: Summary · Scaling improves Transistor in Nanoscale Transistors: NMOS Vs PMOS Perspective", in Proceedings of the 20th IEEE International Conference and also gives a qualitative idea of the driving capacity of a Nano-CMOS transistor. Advanced Topics

  13. "Seeing" in the Dark: Neuromorphic VLSI Modeling of Bat Echolocation

    E-print Network

    Horiuchi, Timothy K.

    "Seeing" in the Dark: Neuromorphic VLSI Modeling of Bat Echolocation IEEE SIGNAL PROCESSING and Ranging, which includes echolocation. It is most com- monly associated with underwater sens- ing an airborne echolocation system, bats have incredible aerial agility, flying in complete darkness through

  14. Architectures and VLSI Implementations of the AES-Proposal Rijndael

    Microsoft Academic Search

    Nicolas Sklavos; Odysseas G. Koufopavlou

    2002-01-01

    Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit\\/sec. It performs efficiently in

  15. A weighted reduced connectivity matrix partitioning algorithm [VLSI design

    Microsoft Academic Search

    Weibiao Zhang; Ruili Zhang; M. Hassoun

    2000-01-01

    M-way partitioning algorithms have many important applications in VLSI design. A heuristic Reduced Connectivity Matrix Partitioning (RCMP) algorithm can handle m-way partitioning with good time and space complexity. In this paper, we introduce a weighted RCMP (WRCMP) algorithm, which incorporates area constraints with performance objectives at the same time in order to extend the capability of RCMP. A program has

  16. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  17. Macromodeling and Optimization of Digital MOS VLSI Circuits

    Microsoft Academic Search

    Mark Douglas Matson; Lance A. Glasser

    1986-01-01

    Power consumption and signal delay are crucial to the design of high-performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based

  18. The on-chip parallelism of VLSI circuits

    Microsoft Academic Search

    M. L. Bailey

    1989-01-01

    Simulation is a bottleneck in VLSI circuit design. Not only are there many simulation runs throughout the design cycle, but each run can take hours or days to complete. One often suggested means of speeding up event-driven simulation is to use multiple processors to exploit the natural parallelism present in the circuit, that is to partition the circuit among multiple

  19. VLSI architecture for fast 2D discrete orthonormal wavelet transform

    Microsoft Academic Search

    Henry Y. H. Chuang; Ling Chen

    1995-01-01

    The discrete wavelet transform (DWT) provides a new method for signal\\/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a signal or an image into localized contributions for multiscale analysis. In this paper, we present a parallel pipelined VLSI array architecture for 2D dyadic separable DWT. The

  20. A VLSI implementation of the continuous wavelet transform

    Microsoft Academic Search

    R. Timothy Edwards; C. Cauwenberghs

    1996-01-01

    We have designed and fabricated a VLSI circuit which performs a continuous wavelet transform on a one-dimensional (e.g., sound) input in real time. This implementation uses oversampling techniques and simple switched capacitor filters to achieve good signal quality in a system which is small and consumes little power. Measurement results that validate correct operation of wavelet decomposition are included

  1. AN ANALOG VLSI CIRCUIT IMPLEMENTING AN ORTHOGONAL CONTINUOUS WAVELET TRANSFORM

    E-print Network

    Harris, John G.

    AN ANALOG VLSI CIRCUIT IMPLEMENTING AN ORTHOGONAL CONTINUOUS WAVELET TRANSFORM Dongwei Chen John G structure originally developed by Lee [4]. 1. Introduction The Continuous Wavelet Transform (CWT) has been-orthogonal wavelets [a] [3]. The present, system performs a continuous-scale or- thogonal multiresolution analysis

  2. Modeling Selective Attention Using a Neuromorphic Analog VLSI Device

    Microsoft Academic Search

    Giacomo Indiveri

    2000-01-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits.

  3. Yield analysis of 2D hexagonal VLSI\\/WSI arrays

    Microsoft Academic Search

    Afzel Noore; S. Cambam

    1991-01-01

    This paper proposes techniques for determining the yield of redundant 2D hexagonal VLSI and WSI arrays. Such arrays are very useful in parallel processing, distributed processing and systolic array applications. Redundancy is implemented at the interstitial spaces of the array structure and reconfiguration is performed locally in order to keep the interconnections short and simple. The first reconfiguration strategy models

  4. Analog VLSI signal processing: Why, where, and how?

    Microsoft Academic Search

    Eric A. Vittoz

    1994-01-01

    Analog VLSI signal processing is most effective when precision is not required, and is therefore an ideal solution for the implementation of perception systems. The possibility to choose the physical variable that represents each signal allows all the features of the transistor to be exploited opportunistically to implement very dense time- and amplitude-continuous processing cells. This paper describes a simple

  5. Analog VLSI signal processing: Why, where, and how?

    Microsoft Academic Search

    Eric A. Vittoz

    1994-01-01

    Analog VLSI signal processing is most effective when precision is not required, and is therefore an ideal solution for the implementation of perception systems. The possibility to choose the physical variable that represents each signal allows all the features of the transistor to be exploited opportunistically to implement very dense time- and amplitude- continuous processing cells. This paper describes a

  6. Photonic VLSI for On-Chip Computing Architectures

    Microsoft Academic Search

    Alyssa Apsel; Tao Yin; Anand Mohan Pappu

    In this paper, we demonstrate the feasibility of using on-chip optoelectronics within VLSI systems to address a wide range of signal distribution issues by examining the following fundamental question: how can we transmit information from one source to many destinations while minimizing propagation delay, skew, jitter, and noise in a way that is compatible with low-cost manufacturing and CMOS circuits?

  7. Decentralized Fault-Tolerant Clock Pulse Generation in VLSI Chips

    E-print Network

    Szmolyan, Peter

    Decentralized Fault-Tolerant Clock Pulse Generation in VLSI Chips The invention offers a solution for various problems associated with the steady increase of clock rates of chips. It offers a fault of faults; · self generation of clock pulses. Instead of globally distributing the clock produced

  8. ASAP-a 2D DFT VLSI processor and architecture

    Microsoft Academic Search

    Jonathon D. Mellott; Michael Lewis; Fred Taylor; P. Coffield

    1996-01-01

    In this paper we examine the use of a recent innovation, called the logarithmic residue number system or LRNS, as an alternative to conventional DSP processors for implementing multiply-accumulate (MAC) operations. ASAP is a custom VLSI multiprocessor chip based on the LRNS. The fabricated ASAP device is capable of achieving MAC bandwidth-area ratios far greater than a conventional processor. The

  9. Electron Beam Tester Integrated into a VLSI Tester

    Microsoft Academic Search

    Hironobu Niijima; Yasuo Tokunaga; Shouichi Koshizuka; Kazuo Yakuwa; Péter Fazekas; Mathias Sturm; Hans-peter Feuerbaum

    1988-01-01

    An integrated EB (electron-beam) testing system is constructed for precise failure analysis and reduction of total testing time, coupling a VLSI tester and an EB tester. Unique features of the system are briefly described, together with its system configuration and functions. The close connection of LSI testing and EB testing environments is further continued. It is planned to improve the

  10. A reconfigurable and fault-tolerant VLSI multiprocessor array

    Microsoft Academic Search

    Israel Koren

    1981-01-01

    Multiprocessor arrays have the property of regularity, enabling a low-cost VLSI implementation. However, multiprocessor systems with a fixed structure tend to be error prone and restricted to specialized applications, which makes them less attractive to the semiconductor industry. Consequently, reconfigurability and fault-tolerance are desirable features of a multiprocessor array. A multiprocessor array with a flexible structure can be adapted to

  11. VLSI\\/PCB placement with obstacles based on sequence pair

    Microsoft Academic Search

    Hiroshi Murata; Kunihiro Fujiyoshi; Mineo Kaneko

    1998-01-01

    In a typical very large scale integration\\/printed circuit board (VLSI\\/PCB) design, some modules are preplaced in advance, and the other modules are requested to be placed without overlap with each other and with these preplaced modules. The presence of such obstacles introduces inconsistency to a coding scheme, called sequence pair, which has been proposed for an obstacle free placement problem.

  12. Carafe: an inductive fault analysis tool for CMOS VLSI circuits

    Microsoft Academic Search

    Alvin Jee; F. Joel Ferguson

    1993-01-01

    Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults in CMOS circuits. As a result, tests based on traditional fault models may not detect all the faults that occur in the circuit. This paper discusses the Carafe software package which determines which faults are likely to occur in a circuit

  13. Realistic statistical worst-case simulations of VLSI circuits

    Microsoft Academic Search

    Michael Bolt; Marc Rocchi; Jan Engel

    1991-01-01

    A simple and cost-effective method for evaluating the parametric product manufacturability of VLSI circuits is presented. The method, named gradient analysis, enables designers to predict the standard deviation of the circuit performance from measured or specified design parameter variations. This method, with a minimum extra design cost, avoids the overdesign associated with the traditional prediction of the worst-case performance of

  14. A VLSI architecture of color model-based tonsillitis detection

    Microsoft Academic Search

    Pranithan Phensadsaeng; Werapon Chiracharit; Kosin Chamnongthai

    2009-01-01

    Tonsillitis disease is the cause of heart attack and pneumonia. It is also a sign of suspected symptom of heart disease. To improve data transfer rates, this paper proposes VLSI architecture by using color model for early-state tonsillitis detection. In this method, input image is divided into 9 blocks. Each block has 3times3 window which send color data and pixel

  15. CSCE 6933/5933 Advanced Topics in VLSI Systems

    E-print Network

    Mohanty, Saraju P.

    Topics in VLSI Systems 1 Lecture 6: Sigma-Delta Modulator and Evaluation of SPICE NOTE: The figures, text Contribution · High level Design of Sigma-Delta Modulator · Design of Individual Components · Comparative view of Sigma-Delta modulation is done using Verilog-A in Cadence and design of individual components (Diff

  16. SPIDER -- A CAD System for Modeling VLSI Metallization Patterns

    Microsoft Academic Search

    Joseph E. Hall; Dale E. Hocevar; Ping Yang; Michael J. Mcgraw

    1987-01-01

    A system of CAD programs, called SPIDER, for ensuring adequate current-carrying capacity in VLSI circuits has been developed. The approach is hierarchical, and it automates and simplifies many of the tasks previously performed by the circuit designer. The system converts transient current waveforms into dc electromigration equivalent values, and includes an algorithm for determining the line width adjustments necessary for

  17. Algorithms for routing and testing routability of planar VLSI layouts

    Microsoft Academic Search

    Charles E. Leiserson; F. Miller Maley

    1985-01-01

    This paper studies the problem of routing wires in a grid among features on one layer of a VLSI chip, when a sketch of the layer is given. A sketch specifies the positions of features and the topology of the interconnecting wires. We give polynomial-time algorithms that (1) determine the routability of a sketch, and (2) produce a routing of

  18. Goalie: A Space Efficient System for VLSI Artwork Analysis

    Microsoft Academic Search

    Thomas Szymanski; Christopher Van Wyk

    1985-01-01

    Advances in VLSI have resulted in more and more complex circuitry, fueling the need for programs that analyze IC mask artwork. This article describes Goalie, an artwork analysis system, by explaining the algorithms used to support circuit extraction, Boolean geometric operations, connectivity analysis, capacitance measurement and design checking. Tests on several systems have shown that Goalie runs at least as

  19. Power Optimization in VLSI Layout: A Massoud Pedram

    E-print Network

    Pedram, Massoud

    Power Optimization in VLSI Layout: A Survey Massoud Pedram Department of EE-Systems University View, CA-94043 Abstract This paper presents a survey of layout techniques for designing low power, and thus the #12;2 Power Minimization in IC Design: Principles and Applications die temperature. Heat

  20. A special purpose silicon compiler for designing supercomputing VLSI systems

    NASA Technical Reports Server (NTRS)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  1. VLSI Implementation of Low Power Reconfigurable MIMO Detector 

    E-print Network

    Dash, Rajballav

    2009-12-02

    2.3 Analysis Criteria for VLSI Implementation ......................................... 21 2.4 Discussion of Implementation/Simulation Methodology ..................... 23 3. FPGA IMPLEMENTATION OF RECONFIGURABLE MIMO DETECTOR . 25 3.1 Fixed... Table 3.2 FPGA Implementation Results .......................................................... 35 Table 4.1 Comparison of Performance with Existing Architectures ................. 49 Table 4.3 ASIC Implementation Details...

  2. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  3. Use of direct wafer bonding of silicon for fabricating solar cell structures with vertical p-n junctions

    Microsoft Academic Search

    V. B. Voronkov; E. G. Guk; V. A. Kozlov; M. Z. Shvarts; V. B. Shuman

    1998-01-01

    A technology based on ion implantation and the direct wafer bonding of p\\u000a +-p-n\\u000a + structures has been developed for multijunction silicon solar cells. The internal quantum efficiency of such structures is\\u000a close to unity in the wavelength range 350–900 nm.

  4. Microsystems and wafer processes for volume production of highly reliable fiber optic components for telecom and datacom-application

    Microsoft Academic Search

    H. L. Althaus; W. Gramann; K. Panzer

    1998-01-01

    In realizing an efficient volume production of highly reliable active fiberoptic components the microsystem-technique was one of the most important factors. Micro-mechanical methods allow large scale fabrication of micro optical silicon lenses with methods, machines and materials using standard semiconductor wafer technology. With micromechanical processes, such as anodic bonding of optical components and special solder bonding techniques, it is possible

  5. Ultra-Low Noise HEMT Device Models: Application of On-Wafer Cryogenic Noise Analysis and Improved Parameter Extraction Techniques

    NASA Technical Reports Server (NTRS)

    Bautista, J. J.; Hamai, M.; Nishimoto, M.; Laskar, J.; Szydlik, P.; Lai, R.

    1995-01-01

    Significant advances in the development of HEMT technology have resulted in high performance cryogenic low noise amplifiers whose noise temperatures are within an order of magnitude of the quantum noise limit. Key to the identification of optimum HEMT structures at cryogenic temperatures is the development of on-wafer noise and device parameter extraction techniques. Techniques and results are described.

  6. Layout controlled one-step dry etch and release of MEMS using deep RIE on SOI wafer

    Microsoft Academic Search

    Liu Haobing; Franck Chollet

    2006-01-01

    Deep reactive ion etching (DRIE) of silicon on insulator (SOI) wafer has become a popular method to build microelectromechanical systems (MEMS) because it is versatile and simple. However when the devices using this technology become large in size or have compliant beams, the stiction occurring during the HF wet release is a serious problem. We have observed that some structure

  7. An embedded vision system based on an analog VLSI vision sensor [robot vision applications

    Microsoft Academic Search

    Vlatko Becanovic; Stefan Kubina; Alan A. Stocker

    2005-01-01

    We present a novel programmable miniature vision module. The module combines an analog VLSI (aVLSI) vision sensor with a digital post-processor (MPC555). The aVLSI sensor provides gray-scale image data as well as smooth optical flow estimates. The particular computational architecture (analog and parallel) of the sensor allows efficient real-time estimation of the smooth optical flow field. The MPC555 controls the

  8. Parallel Logic Level simulation of VLSI Circuits In this paper, we study parallel logic level simulation of combinational VLSI Boolean

    E-print Network

    Cong, Jason "Jingsheng"

    Parallel Logic Level simulation of VLSI Circuits Abstract In this paper, we study parallel logic evaluated the impact on parallel circuit simulation of different number of partitions with different. Few staticstics have been published to exploit the parallelism and analyze performance in circuit

  9. High density circuit technology, part 1

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

  10. Wafer-level optical interconnection network layout

    NASA Astrophysics Data System (ADS)

    Hornak, Lawrence A.; Tewksbury, Stuart K.; Weidman, Timothy W.; Kwock, Elizabeth W.

    1990-08-01

    Two important issues will greatly influence the success of mapping optical interconnections into future waferlevel distributed computing systems: (1), the scalability of active optical devices with cointegration along side ULSI components, and (2), the scalability of optical networks and components to the wafer level. If these criteria can be met, planar integrated and free-space optics can potentially provide a very high performance communication network within the multi-wafer environment. With the predominantly planar geometry and processing of waferlevel circuits, process compatible integrated planar optical interconnections are especially attractive for providing network passive connectivity. As with their electrical counterparts, spatial, as well as time division multiplexing of optical interconnections is desirable, given that layout and area constraints are not too severe. Therefore here, emphasis is shifted away from the individual behavior of traditional long distance lightwave single mode waveguides towards the collective system behaviour (i.e. density, coupling, layout, etc.) of large dense arrays of multimode optical waveguides. In this paper, initial experimental optical coupling results are presented for arrays of multimode polysilyne polymer waveguides, both for straight configurations and for arrays with radial right angle bend layouts.

  11. Wafer-level filling of microfabricated atomic vapor cells based on thin-film deposition and photolysis of cesium azide

    SciTech Connect

    Liew, Li-Anne; Moreland, John; Gerginov, Vladislav [Electromagnetics Division, National Institute of Standards and Technology, Boulder, Colorado 80305 (United States); Time and Frequency Division, National Institute of Standards and Technology, Boulder, Colorado 80305 (United States)

    2007-03-12

    The thin-film deposition and photodecomposition of cesium azide are demonstrated and used to fill arrays of miniaturized atomic resonance cells with cesium and nitrogen buffer gas for chip-scale atomic-based instruments. Arrays of silicon cells are batch fabricated on wafers into which cesium azide is deposited by vacuum thermal evaporation. After vacuum sealing, the cells are irradiated with ultraviolet radiation, causing the azide to photodissociate into pure cesium and nitrogen in situ. This technology integrates the vapor-cell fabrication and filling procedures into one continuous and wafer-level parallel process, and results in cells that are optically transparent and chemically pure.

  12. Impact of VLSI/VHSIC on satellite on-board signal processing

    NASA Technical Reports Server (NTRS)

    Aanstoos, J. V.; Ruedger, W. H.; Snyder, W. E.; Kelly, W. L.

    1981-01-01

    Forecasted improvements in IC fabrication techniques, such as the use of X-ray lithography, are expected to yield submicron circuit feature sizes within the decade of the 1980s. As dimensions decrease, reliability, cost, speed, power consumption and density improvements will be realized which have a significant impact on the capabilities of onboard spacecraft signal processing functions. This will in turn result in increases of the intelligence that may be deployed on spaceborne remote sensing platforms. Among programs oriented toward such goals are the silicon-based Very High Speed Integrated Circuit (VHSIC) researches sponsored by the U.S. Department of Defense, and efforts toward the development of GaAs devices which will compete with silicon VLSI technology for future applications. GaAs has an electron mobility which is five to six times that of silicon, and promises commensurate computation speed increases under low field conditions.

  13. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    NASA Astrophysics Data System (ADS)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2015-02-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  14. Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm

    E-print Network

    Wladyslaw Szczesniak

    2008-01-07

    This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.

  15. Wafer-Scale Fabrication of Plasmonic Crystals from Patterned Silicon Templates Prepared by Nanosphere Lithography

    E-print Network

    Wafer-Scale Fabrication of Plasmonic Crystals from Patterned Silicon Templates Prepared Supporting Information ABSTRACT: By combining nanosphere lithography with template stripping, silicon wafers then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic

  16. 75 FR 76952 - Grant of Authority for Subzone Status; Lam Research Corporation (Wafer Fabrication Equipment...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-12-10

    ...Subzone Status; Lam Research Corporation (Wafer Fabrication Equipment) Fremont, Newark...establish a special-purpose subzone at the wafer fabrication equipment manufacturing and...to the manufacturing and distribution of wafer fabrication equipment at the...

  17. High density circuit technology, part 3

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations.

  18. Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence

    E-print Network

    it is convenient to texture monocrystalline silicon wafers with a (100) surface orientation through alkaline etchImaging crystal orientations in multicrystalline silicon wafers via photoluminescence H. C. Sio, Z crystallization of amorphous silicon: Controlled nanosecond studies in the dynamic transmission electron

  19. A Model for the Silicon Wafer Bonding Process

    Microsoft Academic Search

    R. Stengl; T. Tan; U. Gösele

    1989-01-01

    The bonding speed (or contact wave velocity) of silicon and fused quartz wafers has been measured as a function of temperature. The results show that the bonding process stops to operate at temperatures above 90°C and 320°C for fused quartz and bare silicon wafers, respectively. By comparing our results to infrared spectra obtained from silica gel we develop a tentative

  20. Shock performance study of solder joints in wafer level packages

    Microsoft Academic Search

    Amarinder Singh Ranouta; Xuejun Fan; Qiang Han

    2009-01-01

    In this paper, an integrated testing, finite element modeling and failure analysis approach for drop test reliability of wafer level packages is developed to examine the shock performance of large array wafer level packages. For standard JEDEC drop test, it has been found that corner component group (group A) failed first for 12 times 12 array packages. This is different

  1. Effects of Wafer Emissivity on Rapid Thermal Processing Temperature Measurement

    NASA Astrophysics Data System (ADS)

    Chen, D. H.; DeWitt, D. P.; Tsai, B. K.; Kreider, K. G.; Kimes, W. A.

    2003-09-01

    Lightpipe radiation thermometers (LPRTs) are widely used to measure wafer temperatures in rapid thermal processing (RTP) tools. To use blackbody-calibrated LPRTs to infer the wafer temperature, it is necessary to build a model to predict the effective emissivity accounting for the wafer and chamber radiative properties as well as geometrical features of the chamber. The uncertainty associated with model-corrected temperatures can be investigated using test wafers instrumented with thin-film thermocouples (TFTCs) on which the LPRT target spot has been coated with films of different emissivity. A finite-element model of the wafer-chamber arrangement was used to investigate the effects of Pt spot (?s = 0.25) and Au spot (?s = 0.05) on the temperature distribution of test wafers with spectral emissivities of 0.65 and 0.84. The effects of the shield reflectivity and the cool lightpipe (LP) tip on the wafer temperature were evaluated. A radiance analysis method was developed, and a comparison of model-based predictions with experimental observations was made on a 200 mm diameter wafer in the NIST RTP test bed. The temperature rises caused by the low-emissivity spot were predicted and the cooling effect of the LP tip was determined. The results of the study are important for developing the model-based corrections for temperature measurements and related uncertainties using LPRTs in semiconductor thermal processes.

  2. Dispatching in an integrated circuit wafer fabrication line

    Microsoft Academic Search

    Pravin K. Johri

    1989-01-01

    Wafer Fabrication has been described as the most complicated manufacturing environment existing today. This paper describes a method used to dispatch lots in one of AT&T's Wafer Fabrication Clean Rooms. The objective is to minimize idle time on important facilities in the clean room. For each lot in the clean room, the method indicates the slack time the lot can

  3. Wafer-level microfluidic cooling interconnects for GSI

    Microsoft Academic Search

    Bing Dang; Paul Joseph; Muhannad Bakir; Todd Spencer; Paul Kohl; James Meindl

    2005-01-01

    We present a novel CMOS compatible approach to fabricate on-chip microfluidic cooling channels using a spin-on sacrificial polymer material at wafer level. Deep trenches (>100 ?m) etched into the backside of an IC wafer were successfully filled up by a single spin coating step with a high viscosity sacrificial polymer. A porous overcoat material allows the decomposition of the polymer

  4. Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint

    SciTech Connect

    Rupnowski, P.; Sopori, B.

    2008-05-01

    This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

  5. Effect of mechanical surface damage on Silicon wafer strength

    Microsoft Academic Search

    Daisuke Echizenya; Hiroo Sakamoto; Katsuhiko Sasaki

    2011-01-01

    Solar power generation using polycrystalline silicon wafers has been rapidly growing in recent years. As a result, it is required to understand the strength characteristics of polycrystalline silicon wafers in order to enhance their quality. Scratches and material defects should be taken into consideration when strength characteristics of polycrystalline silicon are evaluated, since it is a brittle material. In this

  6. QUANTIFYING SURFACE DAMAGE BY MEASURING MECHANICAL STRENGTH OF SILICON WAFERS

    Microsoft Academic Search

    G. Coletti; C. J. J. Tool; L. J. Geerligs

    Ring on ring test geometry reveals the great importance of the saw damage on the mechanical stability of as-cut and textured wafers. The initial surface defects make big and unexpected differences in the strength after a standard industrial acid etch. The measuring technique is very sensitive to the surface of the wafers rather than the edge. The influence of bulk

  7. Wafer fab conversion through theory of constraint project management techniques

    Microsoft Academic Search

    J. Fritz; J. Benjamin; R. Rerick

    1999-01-01

    Summary form only given. The drive for manufacturing on larger diameter wafers has been strong for the past few years and is projected to continue. Although the benefits of running production on larger diameter wafers has long been established throughout the industry, the capital investment to start a 300 mm or 200 mm fab from scratch can be difficult to

  8. Wafer Probe Station, Low Noise Amplifiers, and Wideband Feed Developments

    E-print Network

    Weinreb, Sander

    Wafer Probe Station, Low Noise Amplifiers, and Wideband Feed Developments S. Weinreb, A. Akgiray-ridge flared horn wideband feeds #12;Wafer Fabrication of LNA's and Other Radiometer Components 20-Sep-2011 of Millions Field Environment Phased- Array Feeds 0.7-1.8 15K/50K 300K 800,000 Noise SKA Mid 15m Dishes 0

  9. Hermetic wafer bonding based on rapid thermal processing , Liwei Lin

    E-print Network

    Lin, Liwei

    Hermetic wafer bonding based on rapid thermal processing Mu Chiao* , Liwei Lin Berkeley Sensor 94720-1740, USA Abstract Hermetic wafer bonding based on rapid thermal processing (RTP) has been are accomplished when the aluminum bonding solder is 150 mm wide and 4.5 mm thick. Furthermore, it is found

  10. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S. (Los Alamos, NM)

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  11. Thermal modeling of a wafer in a rapid thermal processor

    Microsoft Academic Search

    Jean-Marie Dilhac; Nicolas Nolhier; Christian Ganibal; Christine Zanchi

    1995-01-01

    A model, using geometric optics, has been developed to calculate the illumination of a wafer inside a rapid thermal processor. The main parameters of the model are: the processing chamber geometry, the lamp number and location, the reflector characteristics, and the wafer temperature. Each incident light component, i.e., direct or reflected, is identified, its contribution to the illumination of the

  12. Height Inspection of Wafer Bumps Without Explicit 3-D Reconstruction

    Microsoft Academic Search

    Mei Dong; Ronald Chung; Edmund Y. Lam; Kenneth S. M. Fung

    2010-01-01

    Die bonding in the semiconductor industry requires placement of solder bumps not on PCBs but on wafers. Such wafer bumps, which are much miniaturized from their counterparts on printed circuit boards (PCBs), require their heights meet rigid specifications. Yet the small size, the lack of texture, and the mirror-like nature of the bump surface make the inspection task a challenge.

  13. Microstructure of AuSn Wafer Bonding for RF-MEMS Packaging

    Microsoft Academic Search

    Jian Cai; Qian Wang; Xiaogang Li; Woonbae Kim; Shuidi Wang; Junsik Hwang; Changyoul Moon

    2005-01-01

    RF-MEMS is one of the most potential applications for MEMS products. Eutectic solder wafer bonding is one of the attractive methods for RF-MEMS wafer level packaging. A process of gold-tin hermetical wafer bonding was developed in SAIT, Korean. Different UBM systems and thin films of gold-tin were deposited on cap wafer, RF-MEMS device wafer and substrate wafer (if needed). The

  14. [4] H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, AddisonWesley, 1990, pp. 81133. [5] K. D. Boese, J. Cong, A. B. Kahng, K. S. Leung and D. Zhou, ``On HighSpeed VLSI Interconnects

    E-print Network

    Kahng, Andrew B.

    ­133. [5] K. D. Boese, J. Cong, A. B. Kahng, K. S. Leung and D. Zhou, ``On High­Speed VLSI Interconnects. Wrege, ``Mixed Spanning Trees'', Proc. Great Lakes Symp. on VLSI, March 1993, pp. 62­66. [22] S. Sutanthavibul and E. Shragowitz, ``Adaptive Timing­Driven Layout for High Speed VLSI'', Proc. ACM/IEEE Design

  15. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  16. Wafer-level Au-Au bonding in the 350-450 °C temperature range

    NASA Astrophysics Data System (ADS)

    Tofteberg, Hannah R.; Schjølberg-Henriksen, Kari; Fasting, Eivind J.; Moen, Alexander S.; Taklo, Maaike M. V.; Poppe, Erik U.; Simensen, Christian J.

    2014-08-01

    Metal thermocompression bonding is a hermetic wafer-level packaging technology that facilitates vertical integration and shrinks the area used for device sealing. In this paper, Au-Au bonding at 350, 400 and 450 °C has been investigated, bonding wafers with 1 µm Au on top of 200 nm TiW. Test Si laminates with device sealing frames of 100, 200, and 400 µm in width were realized. Bond strengths measured by pull tests ranged from 8 to 102 MPa and showed that the bond strength increased with higher bonding temperatures and decreased with increasing frame width. Effects of eutectic reactions, grain growth in the Au film and stress relaxation causing buckles in the TiW film were most pronounced at 450 °C and negligible at 350 °C. Bond temperature below the Au-Si eutectic temperature 363 °C is recommended.

  17. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  18. A TECHNOLOGY FOR MONOLITHIC INTEGRATION OF COMMERCIAL MESFET VLSI ELECTRONICS

    E-print Network

    Shenoy, Krishna V.

    , K.V. Shenoy, and C.G. Fonstad, Jr. Department of Electrical Engineering and Computer Science DATAWRITE DATA VHI VRTD vLo StorageNode Voltage Figure 1: Schematic of an RTD/EFET SRAM cell. 1 shows a schematic of our memory cell. For demonstration purposes we have chosen a two tran- sistor

  19. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    ERIC Educational Resources Information Center

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  20. Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip Matthias Fugger, Ulrich Schmid, Gottfried Fuchs

    E-print Network

    Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip Matthias F¨ugger, Ulrich Schmid to synchronous clocking in VLSI Systems-on-Chip and similar applications. Keywords: Fault-tolerant distributed algorithms, VLSI Systems-on-Chip, fault-tolerant tick generation, clock synchronization. Number of Pages: 20

  1. 78 FR 23472 - Amendments to Existing Validated End-User Authorizations: CSMC Technologies Corporation in the...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-04-19

    ...Specifically, BIS removes Wuxi CR Semiconductor Wafers and Chips Co., Ltd. from CSMC's list...of the merger of Wuxi CR Semiconductor Wafers & Chips Co., Ltd. and CSMC Technologies...214061, China. Wuxi CR Semiconductor, Wafers and Chips Co., Ltd., 14 Liangxi...

  2. A Sharp methodology for VLSI layout

    NASA Astrophysics Data System (ADS)

    Bapat, Shekhar

    1993-01-01

    The layout problem for VLSI circuits is recognized as a very difficult problem and has been traditionally decomposed into the several seemingly independent sub-problems of placement, global routing, and detailed routing. Although this structure achieves a reduction in programming complexity, it is also typically accompanied by a reduction in solution quality. Most current placement research recognizes that the separation is artificial, and that the placement and routing problems should be solved ideally in tandem. We propose a new interconnection model, Sharp and an associated partitioning algorithm. The Sharp interconnection model uses a partitioning shape that roughly resembles the musical sharp 'number sign' and makes extensive use of pre-computed rectilinear Steiner trees. The model is designed to generate strategic routing information along with the partitioning results. Additionally, the Sharp model also generates estimates of the routing congestion. We also propose the Sharp layout heuristic that solves the layout problem in its entirety. The Sharp layout heuristic makes extensive use of the Sharp partitioning model. The use of precomputed Steiner tree forms enables the method to model accurately net characteristics. For example, the Steiner tree forms can model both the length of the net and more importantly its route. In fact, the tree forms are also appropriate for modeling the timing delays of nets. The Sharp heuristic works to minimize both the total layout area by minimizing total net length (thus reducing the total wiring area), and the congestion imbalances in the various channels (thus reducing the unused or wasted channel area). Our heuristic uses circuit element movements amongst the different partitioning blocks and selection of alternate minimal Steiner tree forms to achieve this goal. The objective function for the algorithm can be modified readily to include other important circuit constraints like propagation delays. The layout technique first computes a very high-level approximation of the layout solution (i.e., the positions of the circuit elements and the associated net routes). The approximate solution is alternately refined, objective function. The technique creates well defined sub-problems and offers intermediary steps that can be solved in parallel, as well as a parallel mechanism to merge the sub-problem solutions.

  3. Recent technological trends and their impact on system design

    Microsoft Academic Search

    Pratap Pattnaik

    2007-01-01

    Over the past two decades, significant advancements in VLSI technologies (e.g. Moore's Law), Network Bandwidth, and Disk storage capacity have fueled an unprecedented integration of information technologies into the global economy. These advances have enabled the I\\/T (information technology) community to develop and deploy containerized and composable software stacks, while providing adequate performance to the end users. This model of

  4. Piezoresistive stress sensors on (110) silicon wafers

    NASA Technical Reports Server (NTRS)

    Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

    1992-01-01

    Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

  5. Capacitive micromachined ultrasonic transducers with through-wafer interconnects

    NASA Astrophysics Data System (ADS)

    Zhuang, Xuefeng

    Capacitive micromachined ultrasonic transducer (CMUT) is a promising candidate for making ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with through-wafer interconnects, a CMUT array can be directly integrated with a front-end integrated circuit (IC) to achieve compact packaging and to mitigate the effects of the parasitic capacitance from the connection cables. Through-wafer via is the existing interconnect scheme for CMUT arrays, and many other types of micro-electro-mechanical system (MEMS) devices. However, to date, no successful through-wafer via fabrication technique compatible with the wafer-bonding method of making CMUT arrays has been demonstrated. The through-wafer via fabrication steps degrade the surface conditions of the wafer, reduce the radius of curvature, thus making it difficult to bond. This work focuses on new through-wafer interconnect techniques that are compatible with common MEMS fabrication techniques, including both surface-micromachining and direct wafer-to-wafer fusion bonding. In this dissertation, first, a through-wafer via interconnect technique with improved characteristics is presented. Then, two implementations of through-wafer trench isolation are demonstrated. The through-wafer trench methods differ from the through-wafer vias in that the electrical conduction is through the bulk silicon instead of the conductor in the vias. In the first implementation, a carrier wafer is used to provide mechanical support; in the second, mechanical support is provided by a silicon frame structure embedded inside the isolation trenches. Both implementations reduce fabrication complexity compared to the through-wafer via process, and result in low series resistance and small parasitic capacitance. Two-dimensional CMUT arrays incorporating trench-isolated interconnects show high output pressure (2.9 MPa), wide bandwidth (95%), small pulse-echo amplitude variation (sigma = 6.6% of the mean amplitude), and excellent element yield (100% in 16x16-element array). Volumetric ultrasound imaging was demonstrated by flip-chip bonding one of the fabricated 2D arrays to a custom-designed IC. An important added benefit of the trench-isolated interconnect is the capability to realize flexible arrays. A flexible 2D CMUT array is demonstrated by filling the trenches with polydimethylsiloxane (PDMS). The results presented in this dissertation show that through-wafer trench-isolation is a viable solution for providing electrical interconnects to CMUT elements. These techniques are potentially useful for providing through-wafer interconnects to many other types of MEMS sensors and actuators because of their post-process nature. The results also show that 2D CMUT arrays fabricated using wafer-bonding deliver good performance.

  6. Effects of design, structure and material on thermal-mechanical reliability of large array wafer level packages

    Microsoft Academic Search

    Bhavesh Varia; Xuejun Fan; Qiang Han

    2009-01-01

    In this paper, thermo-mechanical reliability of a variety of state-of-art wafer level packaging (WLP) technologies is studied from a structural design point of view. Various WLP technologies, such as Ball on I\\/O with and without redistribution layer (RDL), Ball on Polymer with and without under bump metallurgy (UBM) process, and encapsulated Copper Post WLPs, are investigated for their structural characteristics

  7. Noise-margin limitations on gallium-arsenide VLSI

    NASA Technical Reports Server (NTRS)

    Long, Stephen I.; Sundaram, Mani

    1988-01-01

    Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

  8. Design of Reconfigurable Optical Interconnects Employing Opto-VLSI Processors

    Microsoft Academic Search

    Roger Jeffery; Kamal Alameh; Mikhail Vasiliev

    2005-01-01

    We investigate the design and performance of a reconfigurable optical interconnect structure based on vertical-cavity surface-emitting lasers (VCSEL), Opto-VLSI processors and photodetector arrays. We optimise a proof-of-concept 3-VCSEL-element structure that eliminates crosstalk caused by unwanted diffracted optical beams and show that a bit error role (BER) of 10'17 is feasible at 3.2 Gbps for each channel.

  9. Scanners for visualizing activity of analog VLSI circuitry

    Microsoft Academic Search

    Carver A. Mead; Tobias Delbrück

    1991-01-01

    This paper tutorially describes mixed digital-analog serial multiplexers (scanners) that we use to visualize the activity of one- and two-dimensional arrays of analog VLSI elements. These scanners range from simple one-dimensional devices designed to scan a one-dimensional array onto an oscilloscope, to complete video scanners with integrated sync and blank computation and on-chip video amplifiers. We discuss practical details of

  10. Drift chamber tracking with a VLSI neural network

    SciTech Connect

    Lindsey, C.S.; Denby, B.; Haggerty, H. [Fermi National Accelerator Lab., Batavia, IL (United States); Johns, K. [Arizona Univ., Tucson, AZ (United States). Dept. of Physics

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We`ll briefly discuss possible applications in high energy physics detector triggers.

  11. A new VLSI design for Viterbi decoder based on ASIP

    Microsoft Academic Search

    Zhiqiang Yi; Yuanxin Xu; Yun Li; Kuang Wang

    2002-01-01

    Trellis Code Modulation (TCM) has been widely used because it can obtain 2.55?7.37 dB coding gain without bandwidth expansion or reduction of the effective information rates. Since Viterbi decoder plays an important role in the realization of HDTV system, we conduct the research and development on integration of Viterbi decoder. This paper proposes a new VLSI design of Viterbi decoder

  12. VLSI-implementation issues of turbo trellis-coded modulation

    Microsoft Academic Search

    Frank Kienle; Gerd Kreiselmaier; Norbert Wehn

    2003-01-01

    Turbo trellis-coded modulation (TTCM) is a very promising approach for future communication systems. It combines the advantages of channel coding with multilevel signals and the powerful turbo-codes concept. In this paper we consider VLSI implementation aspects of TTCM. We show that techniques, known from binary turbo-decoders, can be applied to TTCM to reduce the implementation complexity significantly. In detail we

  13. System Integration of the VLSI-PLM Chip

    Microsoft Academic Search

    Linda G. Bushnell; Vason P. Srini; Lau T. Nguyen

    1990-01-01

    The design and building of an interface system for the VLSI-PLM (Prolog Machine) chip, a high-performance CMOS processor for executing Prolog, are described. The interface system plugs into a Sun 3\\/160 host. Two versions of this system have been designed: a wire-wrapped board and a printed circuit board. First, the design and simulations were done using Mentor Graphics computer aided

  14. ASAP-a 2D DFT VLSI processor and architecture

    Microsoft Academic Search

    J. D. Mellott; Michael Lewis; Fred Taylor; P. Coffield

    1996-01-01

    We examine the use of an innovation, called the logarithmic residue number system or LRNS, as an alternative to conventional DSP processors for implementing multiply-accumulate (MAC) operations. The Athena Sensor Arithmetic Processor (ASAP) is a custom VLSI multiprocessor chip based on the LRNS. The fabricated ASAP device is an LRNS “vector-processor on a chip” capable of achieving MAC bandwidth-area ratios

  15. A Nanosensor Array-Based VLSI Gas Discriminator

    Microsoft Academic Search

    Kevin M. Irick; Wei Xu; Narayanan Vijaykrishnan; Mary Jane Irwin

    2005-01-01

    Chemiresistive nanowires can be organized as cross-reactive sensor arrays to mimic the human olfactory system in terms of sensing and discriminating various gases and odors. This paper presents a single chip gas discrimination system that integrates a cross-reactive array of chemiresistive nanosensors with an underlying VLSI pattern classifier to accurately and efficiently identify the gas\\/odor to which the system is

  16. Drift chamber tracking with a VLSI neural network

    SciTech Connect

    Lindsey, C.S.; Denby, B.; Haggerty, H. (Fermi National Accelerator Lab., Batavia, IL (United States)); Johns, K. (Arizona Univ., Tucson, AZ (United States). Dept. of Physics)

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers.

  17. Computing perspectives: the rise of the VLSI processor

    Microsoft Academic Search

    Maurice V. Wilkes

    1990-01-01

    Around 1970 Intel discovered it could put 2,000 transistors—or perhaps a few more—on a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), an event which had been long heralded, but had been seemingly slow to come. At the time, it went almost unnoticed in the computer industry. This was partly

  18. An Efficient Parallel VLSI Video\\/Communication Controller 1

    Microsoft Academic Search

    G. Konstantoulakis; G. Korinthios; G. Lykakis; D. Reisis; G. Synnefakis

    This paper presents a parallel VLSI architecture specifically designed to support emerging video\\/data communication\\/multiplexing applications as a video\\/communication controller. Using a shared memory with efficient interconnection the design can accommodate either a processing system as a peripheral which can store data and perform specific operations on these, or a switching system as a buffer with real time processing and multiplexing

  19. A Framework for Solving VLSI Graph Layout Problems

    Microsoft Academic Search

    Sandeep N. Bhatt; Frank Thomson Leighton

    1984-01-01

    This paper introduces a new divide-and-conquer framework for VLSI graph layout.Universally close upper and lower bounds are obtained for important cost functions such aslayout area and propagation delay. The framework is also effectively used to design regular andconfigurable layouts, to assemble large networks of processors using restructurable chips, andto configure networks around faulty processors. It is also shown how good

  20. VLSI designs for redundant binary-coded decimal addition

    Microsoft Academic Search

    B. Shirazi; D. Y. Y. Yun; C. N. Zhang

    1988-01-01

    A binary-coded decimal system provides rapid binary-decimal conversion. However, BCD arithmetic operations are often slow and require complex hardware. One can eliminate the need for carry propagation and thus improve performance of BCD operations by using a redundant binary-coded decimal (RBCD) system. The VLSI design of an RBCD adder is introduced. The design consists of two small PLAs and two

  1. A digital color CCD imaging system using custom VLSI circuits

    Microsoft Academic Search

    K. A. Parulski; L. J. D'Luna; R. H. Hibbard

    1989-01-01

    The authors describe a prototype digital imaging system that can be configured as a single-sensor video camera or a film-to-video converter. The system includes a CCD (charge-coupled device) image sensor with a 3G color filter pattern, two full-custom CMOS digital video signal processing chips, and a custom electronically programmable sequencer chip. The CMOS VLSI digital circuits offer real-time operation while

  2. VLSI implementation of high-speed SHA256

    Microsoft Academic Search

    Ling Bai; Shuguo Li

    2009-01-01

    To accelerate the speed of iterative computation for the existing SHA-256 algorithm, using 7-3-2 array compressor is proposed to reduce the critical path delay in this paper. The frequency of the proposed scheme is 1.7 times higher than other VLSI implementations under the same process. In addition, the paper designs a new universal architecture for implementing SHA-2 algorithms. The design

  3. Parallel algorithms and VLSI architectures for stack filtering using Fibonacci p-codes

    Microsoft Academic Search

    David Z. Gevorkian; K. O. Egiazarian; S. S. Agaian; J. T. Astola; O. Vainio

    1995-01-01

    A parallel decompositional algorithm and VLSI architecture is proposed for computation of the output of a stack filter over a single window of input samples using Fibonacci p-codes. For a subclass of positive Boolean functions, a more efficient parallel algorithm and VLSI architecture for running stack filtering is also presented. The area-time complexities of the proposed designs are estimated

  4. Thermal Modeling, Analysis and Management in VLSI Circuits: Principles and Methods

    E-print Network

    Pedram, Massoud

    1 Thermal Modeling, Analysis and Management in VLSI Circuits: Principles and Methods Massoud Pedram have made thermal effects one of the most important concerns of VLSI designers. The increasing. Recent data shows that more than 50% of all IC failures are related to thermal issues. This article

  5. Object oriented Lisp implementation of the CHEOPS VLSI floor planning and routing system

    Microsoft Academic Search

    Christian Masson; Remy Escassut; Denis Barbier; Daniel Winer; Gregory Chevallier

    1991-01-01

    This paper presents the architecture and capabilities of the CHEOPS Floor Planning and Routing System for macrocell VLSI design, which was implemented in Le_Lisp ( @ from INRIA) using Object Oriented Programming. CHEOPS is a highly interactive system providing an integrated set of facilities allowing VLSI designers to cover all steps from initial floorplan evaluation down to final chip composition

  6. An O(n log m) algorithm for VLSI design rule checking

    Microsoft Academic Search

    Charles R. Bonapace; Chi-yuan Lo

    1992-01-01

    The authors describe a new variant of the segment tree approach for VLSI design rule checking. The best known algorithms to date for flat VLSI design rule checking require O(n log n ) expected time and O(?n) space, where n is the total number of edges on a mask layer of the chip. The expectation is with respect to a

  7. A NEW TEST METRIC AND A NEW SCAN ARCHITECTURE FOR EFFICIENT VLSI TESTING

    E-print Network

    Stanford University

    A NEW TEST METRIC AND A NEW SCAN ARCHITECTURE FOR EFFICIENT VLSI TESTING A DISSERTATION SUBMITTED. To overcome the difficulty and cost of VLSI testing, we need to search for better testing techniques. Chip testing can be classified into two categories: production testing and characterization testing

  8. LOW POWER REAL TIME ELECTRONIC NEURON VLSI DESIGN USING SUBTHRESHOLD TECHNIQUE

    E-print Network

    Ayers, Joseph

    LOW POWER REAL TIME ELECTRONIC NEURON VLSI DESIGN USING SUBTHRESHOLD TECHNIQUE Young Jun Lee a VLSI electronic neuron circuit that imple- ments Hindmarsh and Rose neuron model. Magnitude and time neuron can be modulated dynamically by varying the input voltage level. The circuit is designed using 0

  9. Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in VLSI Circuits

    E-print Network

    Dey, Sujit

    12.5 190 Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in VLSI insertion" methodology protect the sequential elements in digital circuits against various noise effects in today's VLSI chip design due to interferences from multiple noise sources as well as radiation

  10. 42 BIBLIOGRAPHY [Seitz 84] C.L. Seitz, Concurrent VLSI Architectures, IEEE Transactions

    E-print Network

    42 BIBLIOGRAPHY [Seitz 84] C.L. Seitz, Concurrent VLSI Architectures, IEEE Transactions­Passing Concurrent Computers, IEEE Computer, pp. 9--24, August 1988. [Dally 87] W.J. Dally, A VLSI Architecture, Deadlock­Free Message Routing in Mul­ tiprocessor Interconnection Networks, IEEE Transactions on Computers

  11. Abstract--This paper describes the development of visualization aids for VLSI Computer-Aided Design

    E-print Network

    Nestor, John A.

    that of software algorithm animation, but greater emphasis is placed on the relationship of the algorithms is to adapt ideas from software visualization and algorithm animation [5], [6] to aid students, designers--Visualization, Animation, VLSI CAD, Design Automation, Placement, Routing. I. INTRODUCTION HE ongoing revolution in VLSI

  12. Delta-sigma cellular automata for analog VLSI random vector generation

    Microsoft Academic Search

    Gert Cauwenberghs

    1999-01-01

    We present a class of analog cellular automata for parallel analog random vector generation, including theory on the randomness properties, scalable parallel very large scale integration (VLSI) architectures, and experimental results from an analog VLSI prototype with 64 channels. Linear congruential coupling between cells produces parallel channels of uniformly distributed random analog values, with statistics that are uncorrelated both across

  13. A Reconfigurable Neuromorphic VLSI Multi-Chip System Applied to Visual Motion Computation

    E-print Network

    A Reconfigurable Neuromorphic VLSI Multi-Chip System Applied to Visual Motion Computation Giacomo¨urich [giacomojamwjkramer]@ini.phys.ethz.ch Abstract We present a multi-chip neuromorphic system in which an Address Event Representation is used for inter-chip com- munication. The system comprises an analog VLSI transient imager

  14. Las Vegas is better than determinism in VLSI and distributed computing (Extended Abstract)

    Microsoft Academic Search

    Kurt Mehlhorn; Erik Meineche Schmidt

    1982-01-01

    In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean

  15. A Memory Aware Behavioral Synthesis Tool for Real-Time VLSI Circuits

    E-print Network

    Paris-Sud XI, Université de

    A Memory Aware Behavioral Synthesis Tool for Real-Time VLSI Circuits Gwenol´e Corre, Eric Senn the mem- ory architecture and the memory mapping in the Behav- ioral Synthesis of Real-Time VLSI circuits. We formalize the memory mapping as a set of constraints for the syn- thesis, and defined a Memory

  16. VLSI Implementation of Digital Signal Processing Algorithms for MIMO/SISO

    E-print Network

    Gulak, P. Glenn

    VLSI Implementation of Digital Signal Processing Algorithms for MIMO/SISO Systems by Mahdi Shabany Department of Electrical and Computer Engineering University of Toronto c Copyright by Mahdi Shabany 2009 #12;VLSI Implementation of Digital Signal Processing Algorithms for MIMO/SISO Systems Mahdi Shabany Doctor

  17. Ulnar Impaction Syndrome: Ulnar Shortening vs. Arthroscopic Wafer Procedure

    PubMed Central

    Smet, Luc De; Vandenberghe, Lore; Degreef, Ilse

    2014-01-01

    The outcome of ulnar shortenings was compared with that of arthroscopic wafer resections for ulnar impaction (or abutment) syndrome in patients with a positive ulnar variance. The outcome was measured by DASH score, visual analog scale for pain, and working incapacity. The mean DASH score in the ulnar shortening group was 26; in the wafer group it was 36. The VAS scores were respectively 4.4 and 4.6. The working incapacity was 7?months in the ulnar shortening group and 6.1 months in the wafer group. The differences between the two groups were not statistically significant. PMID:25032075

  18. Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards. [Very Large Scale Integration (VLSI)

    SciTech Connect

    Pin, F.G.; Watanabe, Y.

    1992-01-01

    This paper discusses the sensor-based driving of a car in a-priori unknown environments using human-like'' reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver's aid using the new fuzzy inferencing VLSI hardware and human-like'' reasoning schemes.

  19. Development of thin edgeless silicon pixel sensors on epitaxial wafers

    NASA Astrophysics Data System (ADS)

    Boscardin, M.; Bosisio, L.; Contin, G.; Giacomini, G.; Manzari, V.; Orzan, G.; Rashevskaya, I.; Ronchin, S.; Zorzi, N.

    2014-09-01

    The paper reports on the development of novel p-on-n thin edgeless planar pixel sensors, compatible with ALICE front-end electronics, fabricated by FBK on epitaxial material. The focus of the activity is the minimization of the material budget required for hybrid pixel detectors. This goal has been addressed in two different stages. In the first one, planar pixel detectors fabricated on epitaxial wafers have been thinned and bonded to the readout chips. The second stage is described by the present paper: the `active edge' concept has been studied for the reduction of the dead area at the periphery of the devices. An overview of the key technological steps and of the electrical characterization of the fabricated sensors is given. In addition, the preliminary results on the static behavior of test sensors after neutron irradiation at different fluences (up to 2.5 × 1015 1 MeV-neq/cm2) are reported. The results demonstrate that these kinds of devices are a viable solution for the reduction of the material budget while maintaining the typical electrical characteristics expected from radiation silicon sensors.

  20. Low-energy silicon-on-insulator ion implanted gratings for optical wafer scale testing

    NASA Astrophysics Data System (ADS)

    Loiacono, Renzo; Reed, Graham T.; Mashanovich, Goran Z.; Gwilliam, Russell M.; Lulli, Giorgio; Feldesh, Ran; Jones, Richard

    2011-01-01

    Silicon photonics shows tremendous potential for the development of the next generation of ultra fast telecommunication, tera-scale computing, and integrated sensing applications. One of the challenges that must be addressed when integrating a "photonic layer" onto a silicon microelectronic circuit is the development of a wafer scale optical testing technique, similar to that employed today in integrated electronics industrial manufacturing. This represents a critical step for the advancement of silicon photonics to large scale production technology with reduced costs. In this work we propose the fabrication and testing of ion implanted gratings in sub micrometer SOI waveguides, which could be applied to the implementation of optical wafer scale testing strategies. An extinction ratio of over 25dB has been demonstrated for ion implanted Bragg gratings fabricated by low energy implants in submicron SOI rib waveguides with lengths up to 1mm. Furthermore, the possibility of employing the proposed implanted gratings for an optical wafer scale testing scheme is discussed in this work.

  1. Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

    NASA Astrophysics Data System (ADS)

    Goto, Tetsuya; Kuroda, Rihito; Akagawa, Naoya; Suwa, Tomoyuki; Teramoto, Akinobu; Li, Xiang; Obara, Toshiki; Kimoto, Daiki; Sugawa, Shigetoshi; Ohmi, Tadahiro; Kamata, Yutaka; Kumagai, Yuki; Shibusawa, Katsuhiko

    2015-04-01

    By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate–source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

  2. Innovative through-silicon-via formation approach for wafer-level packaging applications

    NASA Astrophysics Data System (ADS)

    Tang, Chao Wei; Tsu Young, Hong; Li, Kuan Ming

    2012-04-01

    Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system-in-packaging and wafer-level packaging applications. Among several available TSV formation methods, Bosch deep reactive ion etching (DRIE) is widely used because it enables the fabrication of TSVs with almost any diameter, from the submicrometer level to hundreds of micrometers. However, the high cost of Bosch DRIE makes it uneconomical for industrial production. We present a novel wafer-level TSV formation approach that is effective and cost-efficient. The proposed method integrates a diode-pumped solid-state ultraviolet nanosecond pulsed laser and rapid wet chemical etching. The former is effective in drilling through 400 µm thick silicon wafers and the latter is used for removing the unwanted heat-affected zone, recast layer and debris left after drilling. Experimental results demonstrate that the combined approach effectively eliminates the unwanted material formed by nanosecond laser pulses. Furthermore, this approach has a significant cost advantage over Bosch DRIE. In summary, the proposed approach affords superior TSV quality, higher TSV throughput and lower cost of process ownership than Bosch DRIE. These advantages could provide the necessary impetus for rapid commercialization of the several high-density fabrication methodologies that depend on TSVs.

  3. Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

    NASA Technical Reports Server (NTRS)

    Aanstoos, J. V.; Snyder, W. E.

    1981-01-01

    Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

  4. Residual Stress Analysis in Thin Device Wafer Using Piezoresistive Stress Sensor

    Microsoft Academic Search

    Aditya Kumar; Xiaowu Zhang; Qing Xin Zhang; Ming Chinq Jong; Guanbo Huang; Lee Wen Sheng Vincent; Vaidyanathan Kripesh; Charles Lee; John H. Lau; Dim Lee Kwong; Venky Sundaram; Rao R. Tummula; Georg Meyer-Berg

    2011-01-01

    In this paper, piezoresistive stress sensors have been used to analyze the residual stress in thin device wafers. For the analysis, device wafers having piezoresistive stress sensors were fabricated. The stress sensors were then calibrated to determine the piezoresistive coefficients. The analysis of residual stress in device wafers was carried out after thinning the device wafers to three different thicknesses

  5. USING VARIATION DECOMPOSITION ANALYSIS TO DETERMINE THE EFFECT OF PROCESS ON WAFER AND DIELEVEL UNIFORMITY IN

    E-print Network

    Boning, Duane S.

    USING VARIATION DECOMPOSITION ANALYSIS TO DETERMINE THE EFFECT OF PROCESS ON WAFER­ AND DIE an understanding of the trade­offs in wafer and die­level uniformity, and their interaction, as functions the measured variation into wafer, die, wafer­die interaction and residual components, we have determined

  6. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  7. Due-date based scheduling and control policies in a multiproduct semiconductor wafer fabrication facility

    Microsoft Academic Search

    Yeong-Dae Kim; Jung-Ug Kim; Seung-Kil Lim; Hong-Bae Jun

    1998-01-01

    This paper focuses on lot release control and scheduling problems in a semiconductor wafer fab producing multiple products that have different due dates and different process flows. For lot release control, it is necessary to determine the type of a wafer lot and the time to release wafers into the wafer fab, while it is necessary to determine sequences of

  8. System Validation of ASML wafer stepper System Validation IN4387 Group 2

    E-print Network

    Mousavi, Mohammad

    System Validation of ASML wafer stepper System Validation IN4387 Group 2 A. Delawari (anton;1 Introduction For the next generation of the wafer stepper, ultraviolet light is used to project the desired layout onto the wafer surface. Due to the absorption of ultraviolet light by the atmosphere, the wafer

  9. A study of defects on EUV masks using blank inspection, patterned mask inspection, and wafer inspection

    E-print Network

    A study of defects on EUV masks using blank inspection, patterned mask inspection, and wafer wafer inspection. The printable blank defect density excluding particles and patterns is 0.63/cm2 . Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection

  10. Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas

    E-print Network

    Kushner, Mark

    Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas Natalia Y the edge of the wafer and wafer terminating structures, such as focus rings. The intended purpose of these structures is to make the reactant fluxes uniform to the edge of the wafer and so prevent a larger than

  11. Zinc Oxide Nanowires Low-Temperature Wafer-Scale Production of

    E-print Network

    Yang, Peidong

    Zinc Oxide Nanowires Low-Temperature Wafer-Scale Production of ZnO Nanowire Arrays** Lori E. Greene aqueous conditions. We present data for arrays on four-inch (ca. 10 cm) silicon wafers and two) wafer to form a 50­200-nm thick film of crystal seeds. Between coatings, the wafer was annealed at 1508C

  12. Wafer-Scale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing

    E-print Network

    Boning, Duane S.

    1 Wafer-Scale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing Dennis Oumaa of the die location on the wafer, thus a combined wafer/die pattern dependent polish- ing model is required stage modeling methodology which accounts for both wafer-scale variation and within-die pattern

  13. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic Hyun S. Kima)

    E-print Network

    Eom, Chang Beom

    layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers hasBonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits Hyun S. Kima April 2004; accepted 28 July 2004) We report a method for bonding silicon-on-insulator wafers onto glass

  14. Micromachining of a fiber-to-waveguide coupler using grayscale lithography and through-wafer etch

    NASA Astrophysics Data System (ADS)

    Dillon, Thomas; Zablocki, Mathew; Shi, Shouyan; Murakowski, Janusz; Prather, Dennis

    2008-02-01

    For some time, the micro-optics and photonics fields have relied on fabrication processes and technology borrowed from the well-established silicon integrated circuit industry. However, new fabrication methodologies must be developed for greater flexibility in the machining of micro-optic devices. To this end, we have explored grayscale lithography as an enabler for the realization of such devices. This process delivers the ability to sculpt materials arbitrarily in three dimensions, thus providing the flexibility to realize optical surfaces to shape, transform, and redirect the propagation of light efficiently. This has opened the door for new classes of optical devices. As such, we present a fiber-to-waveguide coupling structure utilizing a smoothly contoured lensing surface in the device layer of a silicon-on insulator (SOI) wafer, fabricated using grayscale lithography. The structure collects light incident normally to the wafer from a singlemode optical fiber plugged through the back surface and turns the light into the plane of the device layer, focusing it into a single-mode waveguide. The basis of operation is total internal reflection, and the device therefore has the potential advantages of providing a large bandwidth, low polarization sensitivity, high efficiency, and small footprint. The structure was optimized with a simulated annealing algorithm in conjunction with two-dimensional finite-difference time-domain (FDTD) simulation accelerated on the graphics processing unit (GPU), and achieves a theoretical efficiency of approximately seventy percent, including losses due to Fresnel reflection from the oxide/silicon interface. Initial fabrication results validate the principle of operation. We discuss the grayscale fabrication process as well as the through-wafer etch for mechanical stabilization and alignment of the optical fiber to the coupling structure. Refinement of the through-wafer etch process for high etch rate and appropriate sidewall taper are addressed.

  15. Fabrication of a mechanically aligned single-wafer MEMS turbine with turbocharger

    NASA Astrophysics Data System (ADS)

    Pelekies, S. O.; Schuhmann, T.; Gardner, W. G.; Camacho, A.; Protz, J. M.

    2010-10-01

    We describe the fabrication of a turbocharged, microelectromechanical system (MEMS) turbine. The turbine will be part of a standalone power unit and includes extra layers to connect the turbine to a generator. The project goal is to demonstrate the successful combination of several features, namely: silicon fusion bonding (SFB), a micro turbocharger [2], two rotors, mechanical alignment between two wafers [1], and the use of only one 5" silicon wafer. The dimension of the actual turbine casing will be 14mm. The turbine rotor will have a diameter of 8mm. Given these dimensions, MEMS processes are an adequate way to fabricate the device, but it will be necessary to stack up seven different layers to build the turbine, as it is not possible to construct it out of one thick wafer. SFB will be used for bonding because it permits the great precision necessary for high quality alignment. Yet a more precise alignment will be necessary between the layers that contain the turbine rotor, to decrease imbalance and guarantee operation at a very high rpm. To achieve these tight tolerances, a mechanical alignment feature announced by Liudi Jiang [1] is used. The alignment accuracy is expected to be around 200nm. Despite the fact that the turbine consists of multiple layers, it will be fabricated on only one silicon-on-insulator (SOI) wafer. As a result, all layers are exposed to the same process flow. The fabrication process includes MEMS technology as photolithography, nine deep reactive ion etching (DRIE) steps, and six SFB operations. A total of 14 masks are necessary for the fabrication.

  16. 9nm node wafer defect inspection using visible light

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

    2014-04-01

    Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

  17. Embedded Ultrasonics NDE with Piezoelectric Wafer Active Sensors

    Microsoft Academic Search

    Victor Giurgiutiu

    2003-01-01

    The use of piezoelectric wafer active sensors (PWAS) for embedded ultrasonic nondestructive evaluation (NDE) is described. PWAS structure and principle of operation are presented. The interaction between PWAS and ultrasonic Lamb waves is modeled and analyzed, and excitation \\

  18. New LEEPL technology

    NASA Astrophysics Data System (ADS)

    Utsumi, Takao

    2014-10-01

    A new concept of semiconductor lithography is presented. The new technology is tentatively called as New LEEPL since it is an outgrowth of LEEPL which has been developed around 2002. However the new system is completely different from LEEPL. Instead of a single membrane mask used in LEEPL, we use "mask wafer" where mask patterns are made on a wafer by NIL at corresponding positions of chip patterns of chip wafer. The mask patterns on mask wafer have parallel struts structure of 2 division complementary mask (2-DCMPS) Gold (or Si ) dots of thickness of ~50?m are made on the surface of struts and scribing region for equalizing the temperature of mask wafer and chip wafer. Without these contact dots the temperature difference of ~0.5 K will be generated by full power of 1000?A at 2KV. Both mask wafer and chip wafer are cramped together and kept united throughout the processes. The overlay errors between mask patterns and corresponding chip patterns are measured optically. The error map data are fed to 10 e-beam column array to correct the overlay placement errors. Each column does not have main scanning deflector but has tiny deflector only for beam-tilt operation to correct errors. It can deliver 100?A without space charge blur and thus the resolution of L/S pattern of 10nm range can be achieved at resist thickness of 20nm. The e-beam exposure over the mask is performed by the stage motion. Since mask wafer does not have thermal distortion, the thin membrane's distortion alone will affect the image placement accuracy. In order to obtain less than 1nm distortion of the membrane, the size of 2-DCPS must be smaller 0.7mm.

  19. High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production

    SciTech Connect

    Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

  20. Silicon Wafer Bonding by Modified Surface Activated Bonding Methods

    Microsoft Academic Search

    Chenxi Wang; E. Higurashi; T. Suga

    2007-01-01

    8-inch Si-Si wafer bonding at room temperature is performed by means of two modified surface activated bonding (SAB) methods respectively, namely the SAB with nano-adhesion layer and sequential plasma activated bonding (SPAB). And post-annealing processes in atmospheric air utilized do not aim to improve the bonding strength, but to investigate void formation if the bonded wafers heated in subsequent heated